Semiconductor structure manufacturing method, semiconductor structure and semiconductor integrated device

Abstract

The embodiment of the present application provides a method for manufacturing a semiconductor structure, a semiconductor structure and a semiconductor integrated device, the method for manufacturing the semiconductor structure comprising: providing a substrate; the substrate comprising a device area and a non-device area; wherein corresponding ion-doped areas are respectively formed in the device area and the non-device area; the ion-doped area formed in the device area and the ion-doped area formed in the non-device area are formed in the same process based on the same mask; a metal gate structure is formed on the surface of the ion-doped area in the device area; a gate contact structure is formed on the side of the metal gate structure away from the substrate, and a resistive contact structure is formed corresponding to the non-device area; wherein the gate contact structure is in contact with the surface of the metal gate structure away from the substrate; and the resistive contact structure is in direct contact with the ion-doped area in the non-device area. Through the embodiment of the present application, the additional process steps and masks added for manufacturing resistors are reduced, and the manufacturing process of resistors in the system-level chip is simplified.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor manufacturing technology, and specifically to a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor integrated device. Background Art

[0002] System-on-Chip (SoC) has been widely used in many fields such as consumer electronics, communication equipment, automotive electronics, and medical equipment due to its advantages of low power consumption, high performance, and easy integration. The core of the system-on-chip is to integrate multiple functional modules including logic circuits, memory, analog circuits, and mixed signal circuits on the same chip. This highly integrated design not only improves the overall performance of the chip, but also significantly reduces the size and power consumption of the system, meeting the strict requirements of modern electronic products for miniaturization and low power consumption.

[0003] Resistors are key components of analog circuits and mixed-signal circuits, and play an important role in voltage division, current limiting, and signal filtering. However, in the existing system-level chip process, it is often necessary to add multiple process steps and masks to form a resistor structure after the manufacture of integrated circuit components such as transistors. In other words, the existing resistor manufacturing process is relatively complicated. Summary of the invention

[0004] In view of this, multiple embodiments of the present application provide a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor integrated device to simplify the manufacturing process of resistors in a system-on-chip.

[0005] In one aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; the substrate comprising a device area and a non-device area; wherein corresponding ion-doped areas are formed in the device area and in the non-device area, respectively; the ion-doped area formed in the device area and the ion-doped area formed in the non-device area are formed in the same process based on the same mask; a metal gate structure is formed on the surface of the ion-doped area in the device area; a gate contact structure is formed on a side of the metal gate structure away from the substrate, and a resistive contact structure is formed corresponding to the non-device area; wherein the gate contact structure is in contact with a surface of the metal gate structure away from the substrate; and the resistive contact structure is in direct contact with the ion-doped area in the non-device area.

[0006] Optionally, the step of forming a metal gate structure on the surface of the ion-doped region in the device region includes: forming corresponding dummy gate structures on the surface of the device region and the surface of the non-device region, respectively; wherein the dummy gate structure formed on the surface of the device region and the dummy gate structure formed on the surface of the non-device region are formed in the same process based on the same mask; the dummy gate structure includes a dummy gate, a gate dielectric layer and a gate sidewall; a dummy gate silicide layer is formed on the surface of the dummy gate on the surface of the non-device region; the dummy gate on the surface of the device region is removed to form a metal gate; wherein, in the process of removing the dummy gate on the surface of the device region, the dummy gate silicide layer is removed, and the dummy gate on the surface of the non-device region is retained under the blocking effect of the dummy gate silicide layer.

[0007] Optionally, the ion doped region formed in the device region includes a heavily doped region; the method further includes: forming a heavily doped region silicide layer on the surface of the heavily doped region; wherein the heavily doped region silicide layer and the pseudo gate silicide layer are formed in the same process based on the same mask.

[0008] Optionally, before the step of forming a gate contact structure on a side of the metal gate structure away from the substrate and forming a resistive contact structure corresponding to the non-device area, the method further includes: forming an interlayer dielectric layer on the surface of the substrate; wherein a distance from the interlayer dielectric layer away from the substrate surface to the substrate is not less than a distance from the metal gate structure away from the substrate surface to the substrate; etching and removing a portion of the interlayer dielectric layer, forming a gate interlayer dielectric layer opening corresponding to the metal gate and a resistive interlayer dielectric layer opening corresponding to a dummy gate formed on the surface of the non-device area in the interlayer dielectric layer, so that the metal gate and the dummy gate are exposed; and selectively removing the dummy gate and the gate dielectric layer formed on the surface of the non-device area by an etching process, so that the ion-doped area in the non-device area is exposed.

[0009] Optionally, in the step of selectively removing the dummy gate and the gate dielectric layer formed on the surface of the non-device area by an etching process to expose the ion-doped area in the non-device area, the etching selectivity ratio of the material of the dummy gate and the material of the metal gate falls within the range of 18:1 to 22:1.

[0010] In another aspect, an embodiment of the present application provides a semiconductor structure, comprising: a substrate; the substrate comprising a device area and a non-device area; wherein corresponding ion-doped areas are formed in the device area and in the non-device area, respectively; the ion-doped area formed in the device area and the ion-doped area formed in the non-device area are formed in the same process based on the same mask; a metal gate structure formed on the surface of the device area; a gate contact structure formed on a side of the metal gate structure away from the substrate; wherein the gate contact structure is in contact with the surface of the metal gate structure away from the substrate; a resistive contact structure formed corresponding to the non-device area; the resistive contact structure is in direct contact with the ion-doped area in the non-device area.

[0011] Optionally, the ion-doped region includes an N-type doped well region and a P-type doped well region; an isolation structure is formed between the N-type doped well region and the P-type doped well region in the device region; no isolation structure is formed between the N-type doped well region and the P-type doped well region in the non-device region; an N-type threshold voltage adjustment region is formed in the N-type doped well region; and a P-type threshold voltage adjustment region is formed in the P-type doped well region.

[0012] Optionally, the resistive contact structure contacts the ion-doped region in the non-device region to form a resistive structure; and the resistivity of the resistive structure falls within a range of 40Ω / sq to 120Ω / sq.

[0013] Optionally, the semiconductor structure also includes: an interlayer dielectric layer formed on the surface of the substrate; wherein the interlayer dielectric layer has a gate interlayer dielectric layer opening corresponding to the metal gate structure; the gate contact structure contacts the surface of the metal gate structure away from the substrate through the gate interlayer dielectric layer opening; the interlayer dielectric layer has a resistive interlayer dielectric layer opening corresponding to the ion-doped region in the non-device region; and the resistive contact structure contacts the ion-doped region in the non-device region through the resistive interlayer dielectric layer opening.

[0014] In yet another aspect, an embodiment of the present application provides a semiconductor integrated device, which includes a semiconductor structure manufactured according to the method for manufacturing a semiconductor structure as described in the above embodiment or a semiconductor structure as described in the above embodiment.

[0015] In multiple embodiments of the present application, a substrate including a device area and a non-device area is provided, wherein corresponding ion-doped areas are respectively formed in the device and in the non-device area, the ion-doped area formed in the device area and the ion-doped area formed in the non-device area are formed in the same process based on the same mask, and then a metal gate structure is formed on the surface of the ion-doped area in the device area, and a gate contact structure in contact with the surface of the metal gate structure away from the substrate is formed on the side of the metal gate structure away from the substrate, and a resistor contact structure in direct contact with the ion-doped area in the non-device area is formed in the corresponding non-device area. The unexpected effects achieved include: since the ion-doped area in the device area and the ion-doped area in the non-device area are formed in the same process based on the same mask, and the direct contact between the resistor contact structure and the ion-doped area in the non-device area will produce a higher contact resistance, that is, the resistor contact structure contacts the ion-doped area in the non-device area to form a high-resistance resistor structure, so that the process steps and masks for manufacturing transistors can be used to realize the manufacturing of transistors and resistors, reducing the additional process steps and masks added for manufacturing resistors, and simplifying the resistor manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for describing the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic diagram of the relative position relationship between the titanium nitride resistor and other structures of the semiconductor integrated device provided for related technology.

[0018] Figure 2 Microscopic image of a semiconductor integrated device including a titanium nitride resistor provided for related art.

[0019] Figure 3 A schematic diagram of the relative position relationship between polysilicon resistors and other structures of semiconductor integrated devices provided for related technologies.

[0020] Figure 4 A schematic flow chart of a method for manufacturing a semiconductor structure provided for one embodiment of the present application.

[0021] Figure 5 A schematic structural diagram of a substrate provided for one embodiment of the present application.

[0022] Figure 6 A schematic diagram of forming a doped well region in a substrate is provided for one embodiment of the present application.

[0023] Figure 7A schematic structural diagram of a substrate provided for one embodiment of the present application.

[0024] Figure 8 A schematic diagram of a process for forming a metal gate structure on the surface of an ion-doped region in a device region is provided for one embodiment of the present application.

[0025] Fig. 9 A schematic diagram of forming corresponding dummy gate structures on the surfaces of a device region and a non-device region respectively, provided for one embodiment of the present application.

[0026] Fig.10 A schematic diagram of forming a dummy gate silicide layer on a dummy gate surface of a non-device region surface is provided for one embodiment of the present application.

[0027] Fig.11 A schematic diagram of removing a dummy gate from the surface of a device region provided in accordance with an embodiment of the present application.

[0028] Fig.12 A schematic diagram of forming a metal gate on the surface of a device region is provided for one embodiment of the present application.

[0029] Fig.13 A schematic diagram of forming an interlayer dielectric layer on a substrate surface is provided for one embodiment of the present application.

[0030] Fig.14 A schematic diagram of forming a gate interlayer dielectric layer opening and a resistor interlayer dielectric layer opening in an interlayer dielectric layer is provided for one embodiment of the present application.

[0031] Fig.15 A schematic diagram of removing a dummy gate in a non-device region and a gate dielectric layer in a non-device region provided for one embodiment of the present application.

[0032] Fig.16 A schematic structural diagram of a semiconductor structure provided for one embodiment of the present application.

[0033] Fig.17 Microscope imaging of a gate contact structure and a resistor contact structure provided for one embodiment of the present application.

[0034] Structure number description

[0035] 101, semiconductor substrate; 102, intermetallic dielectric layer; 103, titanium nitride resistor; 104, polysilicon resistor; 200, substrate; 201, substrate; 202, buffer layer; 203, deep doped well; 204, isolation structure; 210, device area; 211, N-type doped well area in device area; 212, P-type doped well area in device area; 213, N-type threshold voltage adjustment area in device area; 214, P-type threshold voltage adjustment area in device area; 215, N-type heavily doped area; 216, P-type heavily doped area; 220, non-device area; 221, N-type doped well area in non-device area; 222, P-type doped well area in non-device area; 223, N-type threshold voltage adjustment area in non-device area; 224, P-type threshold voltage adjustment area in non-device area Adjustment area; 300, substrate; 310, device area pseudo gate structure; 311, device area pseudo gate; 312, device area gate sidewall; 313, device area gate dielectric layer; 314, heavily doped area silicide layer; 315, metal gate; 320, non-device area pseudo gate structure; 321, non-device area pseudo gate; 321', non-device area pseudo gate after silicide reaction; 322, non-device area gate sidewall; 323, non-device area gate dielectric layer; 324, pseudo gate silicide layer; 330, metal gate structure; 340, interlayer dielectric layer; 341, gate interlayer dielectric layer opening; 342, resistor interlayer dielectric layer opening; 350, gate contact structure; 360, resistor contact structure; 400, semiconductor structure. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0037] The drawings provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the shape, quantity and proportion of each component may be changed, and the layout of the components may also be more complicated.

[0038] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "center", etc., indicate the orientation or position relationship based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application, and does not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features.

[0039] As system-level chips continue to develop in the direction of miniaturization, the process nodes for manufacturing system-level chips continue to shrink, which puts higher requirements on the integration of system-level chips. By integrating more functional modules within a limited chip area, the overall performance of the chip is improved, and the power consumption and cost of chip manufacturing are reduced.

[0040] Among the multiple functional modules integrated in the system-level chip, resistors, especially high-resistance resistors, are integrated in most system-level chips for realizing different functions because they play a key role in voltage division, current limitation, signal filtering, and input impedance matching of amplifiers or sensors. Therefore, the manufacturing process of resistors has an important impact on the overall manufacturing process of the system-level chip.

[0041] In the related art, resistors in a system-on-chip are usually made of titanium nitride (TiN) or polycrystalline silicon (Poly Si) materials.

[0042] See also Figure 1 and Figure 2 The titanium nitride resistor 103 is usually formed on a side of the intermetallic dielectric layer 102 away from the semiconductor substrate 101, wherein a shallow trench isolation structure is formed in the semiconductor substrate 101. The manufacturing process of the titanium nitride resistor 103 includes: first, forming a titanium nitride film on the surface of the intermetallic dielectric layer 102 by a vapor deposition process, and then patterning the titanium nitride film by using a mask corresponding to the titanium nitride resistor 103.

[0043] See also Figure 3 The polysilicon resistor 104 is usually formed on the surface of the semiconductor substrate 101, wherein a shallow trench isolation structure is formed in the semiconductor substrate 101. The manufacturing process of the polysilicon resistor 104 includes: first, depositing a polysilicon film on the surface of the semiconductor substrate 101, and then doping and patterning the polysilicon film using a mask corresponding to the polysilicon resistor 104.

[0044] From the manufacturing process of the titanium nitride resistor and the polysilicon resistor mentioned above, it can be seen that no matter which material is used to manufacture the resistor, the manufacturing process is relatively complicated. In the process of manufacturing system-level chips, it is necessary to add multiple additional masks and process steps to manufacture resistors after completing the manufacture of integrated circuit components such as MOS tubes (Metal Oxide Semiconductor Field Effect Transistor), which increases the manufacturing cost and prolongs the production cycle. In addition, the complex manufacturing process may also introduce more process variables, increase the difficulty of controlling the process accuracy, and thus have an adverse effect on the overall production yield and performance consistency of the system-level chip.

[0045] Therefore, it is necessary to provide a method for manufacturing a semiconductor structure, by providing a substrate including a device area and a non-device area, wherein corresponding ion-doped areas are formed in the device and the non-device area respectively, the ion-doped area formed in the device area and the ion-doped area formed in the non-device area are formed in the same process based on the same mask, then a metal gate structure is formed on the surface of the ion-doped area in the device area, and then a gate contact structure is formed on the side of the metal gate structure away from the substrate to contact the surface of the metal gate structure away from the substrate, and a resistor contact structure is formed in the corresponding non-device area to directly contact the ion-doped area in the non-device area. Since the ion-doped area in the device area and the ion-doped area in the non-device area are formed in the same process based on the same mask, and the resistor contact structure is in direct contact with the ion-doped area in the non-device area, a higher contact resistance will be generated. The contact resistance can realize the design function of high-resistance resistors in system-level chips, so that the process steps and masks of MOS tube manufacturing can be used to realize the manufacturing of MOS tubes and resistors, so as to reduce the additional process steps and masks added for manufacturing resistors, simplify the resistor manufacturing process, reduce the manufacturing cost of resistors, and improve the overall production efficiency and production yield of the system-level chip.

[0046] See also Figure 4 An embodiment of the present application provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure may include steps S110, S120, and S130.

[0047] S110: providing a substrate.

[0048] In this embodiment, the base may be formed by performing multiple ion implantations on the substrate.

[0049] See also Figure 5In this embodiment, the substrate 200 can be used as a basis for forming system-level chip components such as MOS tubes and resistors. Specifically, the substrate 200 can include a base 201 , a buffer layer 202 , a deep doped well 203 and an isolation structure 204 .

[0050] In this embodiment, the material of the substrate 201 may be a semiconductor material, an insulating material, a conductor material or any combination thereof. For example, the material of the substrate 201 may be silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), etc. Considering the performance stability, manufacturing process and manufacturing cost of the system-level chip, P-type silicon (P+ Silicon) with a high doping concentration is selected as the material of the substrate 201.

[0051] In some embodiments, the material of the substrate 201 may also be N-type silicon (N+ Silicon) with a high doping concentration.

[0052] In this embodiment, after the material of the substrate 201 is determined, the following process steps may be performed on the substrate 201 to obtain the substrate 200 .

[0053] First, a device region 210 and a non-device region 220 may be defined in the substrate 201. The device region 210 may be used to form a MOS transistor, and the non-device region 220 may be used to form a high resistance (High R) resistor.

[0054] Subsequently, isolation structures 204 may be formed in the device region 210 and between the device region 210 and the non-device region 220. For example, the isolation structure 204 may be a shallow trench isolation (STI) structure for reducing leakage.

[0055] After the isolation structure 204 is formed, a buffer layer 202 may be formed on the surface of the substrate 201. Specifically, the buffer layer 202 may be used to reduce the damage to the surface of the substrate 201 caused by the subsequent ion implantation process. The buffer layer 202 may be formed by oxidizing the surface of the substrate 201 through a dry oxidation process or a wet oxidation process, and the material of the buffer layer 202 may be silicon dioxide (SiO2).

[0056] After the buffer layer 202 is formed, ion implantation may be performed on the substrate 201 to form a deep doped well 203 on a side of the substrate 201 away from the buffer layer 202. Specifically, the doping type of the deep doped well 203 is different from the doping type of the substrate 201. When the doping type of the substrate 201 is P-type, the doping type of the deep doped well 203 may be N-type; when the doping type of the substrate 201 is N-type, the doping type of the deep doped well 203 may be P-type.

[0057] See also Figure 6 In order to improve the manufacturing process integration of the system-level chip, the process steps and masks for forming the MOS transistor in the device area 210 can be used to form the MOS transistor in the device area 210 and form the high resistance resistor in the non-device area 220. Therefore, after obtaining the substrate 200, the same ion implantation process can be performed on the device area 210 and the non-device area 220 of the substrate 201 using the same mask, so that corresponding ion doping regions are formed in the device area 210 and the non-device area 220 respectively.

[0058] In this embodiment, the ion implantation process may include an N-type doped well region implantation sub-process and a P-type doped well region implantation sub-process. Specifically, the process of performing the N-type doped well region implantation sub-process may be: performing N-type doped well region ion implantation based on a mask corresponding to the formation of the N-type doped well region, thereby forming a device region N-type doped well region (N-Well, NW) 211 for manufacturing PMOS (Positive MOS) in the device region 210, and forming a non-device region N-type doped well region 221 in the non-device region 220. Since the device region N-type doped well region 211 and the non-device region N-type doped well region 221 are formed in the same sub-process, the process parameters such as ion implantation energy and ion implantation concentration used to form the two regions are the same. The process of performing the P-type doped well region implantation sub-process is similar to the process of performing the N-type doped well region implantation sub-process, and will not be repeated here. After the P-type doped well region implantation sub-process is completed, a device region P-type doped well region (P-Well, PW) 212 for manufacturing NMOS (Negative MOS) is formed in the device region 210 , and a non-device region P-type doped well region 222 is formed in the non-device region 220 .

[0059] Accordingly, in this embodiment, the ion-doped region may include an N-type doped well region and a P-type doped well region. In order to reduce current leakage between MOS tubes and reduce parasitic capacitance, an isolation structure 204 may be formed between the device region N-type doped well region 211 and the device region P-type doped well region 212 in the device region in the device region 210. In the non-device region 220, there is no direct current path between the non-device region N-type doped well region 221 and the non-device region P-type doped well region 222. In order to improve chip integration and chip area utilization, no isolation structure 204 is formed between the non-device region N-type doped well region 221 and the non-device region P-type doped well region 222.

[0060] In some embodiments, to improve the performance and reliability of the system-level chip and reduce cross-coupling, an isolation structure 204 may be formed between the non-device region N-type doped well region 221 and the non-device region P-type doped well region 222 in the non-device region 220 .

[0061] See also Figure 7. In the related art, since resistors can only be manufactured based on titanium nitride and polysilicon, the resistivity of the manufactured resistors can only vary within a small range, which makes it difficult to meet the manufacturing requirements of system-level chips. Therefore, in order to expand the range of resistivity variation and adjust the threshold voltage of the MOS tube, in some embodiments, the ion implantation process may also include an N-type threshold voltage adjustment area implantation sub-process and a P-type threshold voltage adjustment area implantation sub-process. The execution process of the threshold voltage adjustment area implantation sub-process is similar to the execution process of the doped well area implantation sub-process in the above-mentioned embodiment, and will not be repeated here.

[0062] Correspondingly, in the present embodiment, the ion doped region may further include an N-type threshold voltage adjustment region and a P-type threshold voltage adjustment region. Specifically, in the device region 210, a device region N-type threshold voltage adjustment region 213 may be formed in the device region N-type doped well region 211, and a device region P-type threshold voltage adjustment region 214 may be formed in the device region P-type doped well region 212. In the non-device region 220, a non-device region N-type threshold voltage adjustment region 223 may be formed in the non-device region N-type doped well region 221, and a non-device region P-type threshold voltage adjustment region 224 may be formed in the non-device region P-type doped well region 222.

[0063] After performing the doping well region implantation sub-process and the threshold voltage adjustment region implantation sub-process on the substrate 200 , the base 300 is obtained.

[0064] S120: forming a metal gate structure on the surface of the ion-doped region in the device region.

[0065] To simplify the manufacturing process of resistors, in the process of manufacturing the metal gate structures of PMOS and NMOS in the device area using the last gate process, a metal gate structure can be formed in the device area, and a dummy gate structure can be formed in the non-device area, so as to reduce the number of masks and process steps required in the subsequent formation of the resistor contact structure.

[0066] See also Figure 8 In this embodiment, step S120 may include sub-steps S121, S122 and S123.

[0067] S121: forming corresponding dummy gate structures on the surface of the device region and the surface of the non-device region respectively.

[0068] See also Fig. 9. In this embodiment, the dummy gate structure may include a dummy gate, a gate dielectric layer and a gate sidewall. Among them, the material of the dummy gate may be polysilicon. The material of the gate dielectric layer may be a high dielectric constant material, for example, hafnium dioxide (HfO2). The material of the gate sidewall may be silicon nitride. Specifically, in the device area dummy gate structure 310 formed on the surface of the device area 210, the device area dummy gate 311 may be used to determine the position where the subsequent metal gate 315 is formed, the device area gate sidewall 312 may be used to protect the gate, and the device area gate dielectric layer 313 may be used to increase the drive current, reduce the leakage current and improve the threshold voltage control. In the non-device area dummy gate structure 320 formed on the surface of the non-device area 220, the non-device area dummy gate 321 may be used to determine the position where the subsequent resistive contact structure contacts the non-device area 220, and the non-device area gate sidewall 322 may be used as a mask in the subsequent process of forming the resistive contact structure.

[0069] To further simplify the manufacturing process of the resistor, in this embodiment, the dummy gate structure formed on the surface of the device area 210 and the dummy gate structure formed on the surface of the non-device area 220 can be formed in the same process based on the same mask. Specifically, the following process steps can be performed on the substrate 300 to form the device area dummy gate structure 310 and the non-device area dummy gate structure 320.

[0070] First, a gate dielectric material layer and a dummy gate material layer may be deposited in sequence on the surface of the substrate 300 .

[0071] Subsequently, the same mask can be used to perform photolithography and etching on the pseudo gate material layer and the gate dielectric material layer on the surface of the device area 210 and the surface of the non-device area 220 to obtain a device area pseudo gate 311 formed on the surface of the ion-doped area in the device area 210, a device area gate dielectric layer 313, and a non-device area pseudo gate 321 and a non-device area gate dielectric layer 323 formed on the surface of the ion-doped area in the non-device area 220.

[0072] Next, a gate spacer material layer covering the device region dummy gate 311 and the non-device region dummy gate 321 may be deposited on the surface of the substrate 300 .

[0073] Finally, the same mask can be used to etch the gate sidewall material layer on the surface of the device area 210 and the surface of the non-device area 220 to obtain a device area gate sidewall 312 formed on the side of the device area pseudo gate 311 and the side of the device area gate dielectric layer 313, and a non-device area gate sidewall 322 formed on the side of the non-device area pseudo gate 321 and the side of the non-device area gate dielectric layer 323.

[0074] See also Fig.10In this embodiment, after obtaining the device region dummy gate structure 310 and the non-device region dummy gate structure 320, ion implantation may be performed again on the device region 210 to form an N-type heavily doped region 215 for forming a PMOS source and drain in the device region N-type doped well region 211, and to form a P-type heavily doped region 216 for forming an NMOS source and drain in the device region P-type doped well region 212.

[0075] S122: forming a dummy gate silicide layer on the surface of the dummy gate on the surface of the non-device region.

[0076] In the related art, in order to reduce the contact resistance between the source-drain contact structure and the source-drain of the MOS tube, a silicide layer needs to be formed on the surface of the heavily doped region used to form the source-drain of the MOS tube, while the pseudo gate in the device area needs to be removed in the subsequent process, and no silicide layer needs to be formed on its surface. In order to reduce the number of masks and process steps that increase the manufacturing resistance, a silicide layer can be formed on the surface of the heavily doped region and the surface of the pseudo gate in the non-device area based on the same mask and the same process step, so that when the pseudo gate in the device area is removed, the silicide layer formed on the surface of the pseudo gate in the non-device area is used to protect the pseudo gate in the non-device area.

[0077] In order to reduce the number of masks added in the manufacturing process of the resistor, in this embodiment, a self-aligned silicidation (Salicide) process can be used to form a heavily doped region silicide layer 314 on the surface of the heavily doped region, and a dummy gate silicide layer 324 can be formed on the surface of the non-device region dummy gate 321. Specifically, a heavily doped region silicide layer 314 is formed on the surface of both the N-type heavily doped region 215 and the P-type heavily doped region 216. The extension direction of the non-device region dummy gate 321 is used as the height direction of the non-device region dummy gate 321. Since part of the polysilicon in the non-device region dummy gate 321 is converted into a silicide layer through a silicidation reaction, the height of the non-device region dummy gate 321' along the height direction after the silicidation reaction is less than the height of the non-device region dummy gate 321 along the height direction.

[0078] S123: removing the dummy gate on the surface of the device region to form a metal gate.

[0079] See also Fig.11 In this embodiment, only the device region pseudo gate 311 in the device region pseudo gate structure 310 may be removed, and the device region gate sidewall 312 and the device region gate dielectric layer 313 may be retained. Specifically, in the process of removing the device region pseudo gate 311, the device region pseudo gate 311 and the pseudo gate silicide layer 324 may be removed by controlling the etching selectivity of polysilicon and silicide, while the non-device region pseudo gate 321' after the silicide reaction is retained.

[0080] See also Fig.12In this embodiment, after removing the device region dummy gate 311, metal may be filled into the opening formed by removing the device region dummy gate 311 to form a metal gate 315. Specifically, the metal gate 315 may be formed using a self-aligned metal gate (SAMG) process to reduce the process steps required to define the position of the metal gate 315. The metal gate 315, the device region gate sidewall 312, and the device region gate dielectric layer 313 form a metal gate structure 330.

[0081] See also Figures 13 to 15 In order to achieve electrical isolation between different conductive layers, reduce parasitic effects, and improve the reliability and performance of the system-on-chip, in some embodiments, before the step of forming a gate contact structure on the side of the metal gate structure away from the substrate and forming a resistive contact structure corresponding to the non-device area, the method for manufacturing the semiconductor structure may further include: forming an interlayer dielectric layer 340 on the surface of the substrate 300; etching and removing a portion of the interlayer dielectric layer 340, forming a gate interlayer dielectric layer opening 341 corresponding to the metal gate 315 and a resistive interlayer dielectric layer opening 342 corresponding to the dummy gate formed on the surface of the non-device area 220, that is, the non-device area dummy gate 321' after the silicidation reaction, in the interlayer dielectric layer 340, so that the metal gate 315 and the non-device area dummy gate 321' after the silicidation reaction are exposed; selectively removing the dummy gate and the gate dielectric layer formed on the surface of the non-device area 220, that is, the non-device area dummy gate 321' after the silicidation reaction and the non-device area gate dielectric layer 323 by an etching process, so that the ion doping area in the non-device area 220 is exposed.

[0082] In this embodiment, the material of the interlayer dielectric layer 340 may be an oxide, for example, silicon dioxide. To enhance the electrical isolation effect, the distance from the interlayer dielectric layer 340 away from the surface of the substrate 300 to the substrate 300 is not less than the distance from the metal gate structure 330 away from the surface of the substrate 300 to the substrate 300, that is, the interlayer dielectric layer 340 may cover the metal gate 315 and the pseudo gate 321' in the non-device region after the silicidation reaction. Specifically, in order for the interlayer dielectric layer 340 to continue to play an electrical isolation role in the subsequent process of forming the contact structure, the distance from the interlayer dielectric layer 340 away from the surface of the substrate 300 to the substrate 300 may be greater than the distance from the metal gate structure 330 away from the surface of the substrate 300 to the substrate 300.

[0083] Since the position of the metal gate 315 relative to the substrate 300 is the position of the device area pseudo gate 311 relative to the substrate 300, and the non-device area pseudo gate 321 and the device area pseudo gate 311 are formed based on the same mask, therefore, in this embodiment, the gate interlayer dielectric layer opening 341 and the resistor interlayer dielectric layer opening 342 can be formed by etching based on the same mask.

[0084] In order to reduce the damage to the metal gate 315 during the process of removing the dummy gate 321' in the non-device area after the silicidation reaction, in the present embodiment, in the step of selectively removing the dummy gate and the gate dielectric layer formed on the surface of the non-device area 220 by using an etching process to expose the ion-doped area in the non-device area 220, the etching selectivity ratio of the material of the dummy gate 321' in the non-device area after the silicidation reaction and the material of the metal gate 315 can fall within the range of 18:1 to 22:1. Specifically, in the process of selectively removing the dummy gate 321' in the non-device area after the silicidation reaction and the gate dielectric layer 323 in the non-device area, the etching stop can be controlled by the etching time. Since the etching rate of the material of the dummy gate 321' in the non-device area after the silicidation reaction is greater than the etching rate of the material of the metal gate 315, it can be achieved that the damage to the metal gate 315 is small when the dummy gate 321' in the non-device area after the silicidation reaction and the gate dielectric layer 323 in the non-device area are completely removed. For example, the etching selection ratio between the material of the non-device region dummy gate 321 ′ after the silicidation reaction and the material of the metal gate 315 may be 18:1, 20:1, or 22:1.

[0085] S130: forming a gate contact structure on a side of the metal gate structure away from the substrate, and forming a resistive contact structure corresponding to the non-device area.

[0086] See also Fig.16 In order to simplify the manufacturing process of the high-resistance resistor, the manufacturing process of the gate contact structure 350 can be used to form a gate contact structure 350 that contacts the surface of the metal gate 315 away from the substrate 300, and to form a resistor contact structure 360 ​​that directly contacts the ion-doped region in the non-device area 220. Since a Schottky contact is formed between the resistor contact structure 360 ​​and the ion-doped region in the non-device area 220, a large contact resistance is provided, so that the design function of the high-resistance resistor can be realized by using the large contact resistance.

[0087] In order to reduce the damage to the metal gate 315 caused by the contact between the contact metal and the metal gate 315, in this embodiment, the gate contact structure 350 may include a gate contact metal and a contact isolation layer. Specifically, the material of the contact isolation layer may be titanium (Ti) and titanium nitride (TiN), and the material of the gate contact metal may be tungsten (W).

[0088] Please also read Fig.16 and Fig.17 In this embodiment, the extension direction of the gate contact structure 350 is used as the height direction of the gate contact structure 350 and the resistive contact structure 360. Since the resistive contact structure 360 ​​is in direct contact with the ion-doped region in the non-device region 220, the height of the resistive contact structure 360 ​​along the height direction is greater than the height of the gate contact structure 350 along the height direction.

[0089] Since the contact resistance between the resistive contact structure 360 ​​and the ion-doped region in the non-device area 220 is relatively large, in the present embodiment, the resistive contact structure 360 ​​contacts the ion-doped region in the non-device area 220 to form a resistive structure with a relatively large resistance value. Specifically, since there are two ion-doped regions in the non-device area 220, and the doping types and doping concentrations of the two ion-doped regions are different, the resistivity variation range of the resistive structure is expanded. The resistivity of the resistive structure can fall within the range of 40Ω / sq~120Ω / sq. For example, the resistivity of the high-resistance resistor structure can be 40Ω / sq, 60Ω / sq, 80Ω / sq, 100Ω / sq, 120Ω / sq.

[0090] Please continue reading Fig.16 An embodiment of the present application provides a semiconductor structure 400 . The semiconductor structure 400 may include a substrate, a metal gate structure formed on the surface of a device region 210 , a gate contact structure 350 formed on a side of the metal gate structure away from the substrate, and a resistive contact structure 360 ​​formed corresponding to the non-device region 220 .

[0091] In this embodiment, the substrate may include a device region 210 and a non-device region 220. Specifically, corresponding ion-doped regions may be formed in the device region 210 and in the non-device region 220. The ion-doped region formed in the device region 210 and the ion-doped region formed in the non-device region 220 may be formed in the same process based on the same mask.

[0092] In this embodiment, the gate contact structure 350 contacts the surface of the metal gate 315 away from the substrate. The resistive contact structure 360 ​​directly contacts the ion-doped region in the non-device region 220 .

[0093] In this embodiment, the ion-doped region may include an N-type doped well region and a P-type doped well region. Specifically, in the device region 210, an isolation structure 204 may be formed between the device region N-type doped well region 211 and the device region P-type doped well region 212. In the non-device region 220, no isolation structure 204 is formed between the non-device region N-type doped well region 221 and the non-device region P-type doped well region 222. A device region N-type threshold voltage adjustment region 213 may be formed in the device region N-type doped well region 211, and a device region P-type threshold voltage adjustment region 214 may be formed in the device region P-type doped well region 212. A non-device region N-type threshold voltage adjustment region 223 may be formed in the non-device region N-type doped well region 221, and a non-device region P-type threshold voltage adjustment region 224 may be formed in the non-device region P-type doped well region 222.

[0094] In this embodiment, the resistive contact structure 360 ​​contacts the ion-doped region in the non-device region 220 to form a resistive structure. The resistivity of the resistive structure may fall within the range of 40Ω / sq to 120Ω / sq. For example, the resistivity of the resistive structure may be 40Ω / sq, 60Ω / sq, 80Ω / sq, 100Ω / sq, or 120Ω / sq.

[0095] In this embodiment, the semiconductor structure 400 may further include an interlayer dielectric layer 340 formed on the surface of the substrate.

[0096] In this embodiment, the interlayer dielectric layer 340 may have a gate interlayer dielectric layer opening corresponding to the metal gate structure 330, and the gate contact structure 350 may contact the surface of the metal gate 315 away from the substrate through the gate interlayer dielectric layer opening. The interlayer dielectric layer 340 may have a resistive interlayer dielectric layer opening corresponding to the ion-doped region in the non-device region 220, and the resistive contact structure 360 ​​may contact the ion-doped region in the non-device region 220 through the resistive interlayer dielectric layer opening.

[0097] The technical effects of the semiconductor structure described in the above embodiment can be explained by referring to other embodiments of the present application, and will not be repeated here.

[0098] In an embodiment of the present application, a substrate including a device area and a non-device area is provided, wherein corresponding ion-doped areas are respectively formed in the device and in the non-device area, the ion-doped area formed in the device area and the ion-doped area formed in the non-device area are formed in the same process based on the same mask, and then a metal gate structure is formed on the surface of the ion-doped area in the device area, and then a gate contact structure is formed on the side of the metal gate structure away from the substrate to contact the surface of the metal gate structure away from the substrate, and a resistor contact structure is formed in the corresponding non-device area to directly contact the ion-doped area in the non-device area. The unexpected effects achieved include: since the ion-doped area in the device area and the ion-doped area in the non-device area are formed in the same process based on the same mask, and the direct contact of the resistor contact structure with the ion-doped area in the non-device area will produce a higher contact resistance, that is, the resistor contact structure contacts the ion-doped area in the non-device area to form a high-resistance resistor structure, so that the process steps and masks for manufacturing MOS tubes can be used to realize the manufacturing of MOS tubes and resistors, reducing the additional process steps and masks added for manufacturing resistors, and simplifying the resistor manufacturing process. In addition, since there are two ion-doped regions with different doping types and doping concentrations in the non-device region, the range of resistivity variation of the high-resistance resistor structure is expanded.

[0099] An embodiment of the present application provides a semiconductor integrated device, which may include the semiconductor structure described in the above embodiment, or may include a semiconductor structure manufactured by the method for manufacturing the semiconductor structure described in the above embodiment.

[0100] Regarding the technical effects of the semiconductor integrated device described in the above embodiment, reference can be made to other embodiments of the present application for comparative explanation and no further details will be given here.

[0101] It should be understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, rather than to limit the scope of this application.

[0102] It can be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0103] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0104] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application are the same as the meanings generally understood by those skilled in the art of the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms "a kind of", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include majority forms, unless the context clearly indicates other meanings.

[0105] In several embodiments provided in this application, it should be understood that the disclosed semiconductor structure and semiconductor integrated device can be implemented in other ways. For example, the embodiments of the semiconductor structure and semiconductor integrated device described above are merely illustrative.

[0106] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; The substrate comprises a device region and a non-device region; wherein corresponding ion-doped regions are formed in the device region and the non-device region respectively; the ion-doped region formed in the device region and the ion-doped region formed in the non-device region are formed in the same process based on the same mask; A metal gate structure is formed on the surface of the ion-doped region in the device region; wherein the step of forming the metal gate structure on the surface of the ion-doped region in the device region comprises: forming corresponding dummy gate structures on the surface of the device region and the surface of the non-device region respectively; wherein the dummy gate structure formed on the surface of the device region and the dummy gate structure formed on the surface of the non-device region are formed in the same process based on the same mask; the dummy gate structure comprises a dummy gate, a gate dielectric layer and a gate sidewall; a dummy gate silicide layer is formed on the surface of the dummy gate on the surface of the non-device region; the dummy gate on the surface of the device region is removed to form a metal gate; wherein, in the process of removing the dummy gate on the surface of the device region, the dummy gate silicide layer is removed, and the dummy gate on the surface of the non-device region is retained under the blocking effect of the dummy gate silicide layer; A gate contact structure is formed on a side of the metal gate structure away from the substrate, and a resistive contact structure is formed corresponding to the non-device area; wherein the gate contact structure is in contact with a surface of the metal gate structure away from the substrate; and the resistive contact structure is in direct contact with an ion-doped area in the non-device area.

2. The method according to claim 1, characterized in that The ion doped region formed in the device region includes a heavily doped region; the method further includes: A heavily doped region silicide layer is formed on the surface of the heavily doped region; wherein the heavily doped region silicide layer and the dummy gate silicide layer are formed in the same process based on the same mask.

3. The method according to claim 1, characterized in that Before the step of forming a gate contact structure on a side of the metal gate structure away from the substrate and forming a resistive contact structure corresponding to the non-device area, the method further includes: An interlayer dielectric layer is formed on the surface of the substrate; wherein the distance between the interlayer dielectric layer and the substrate away from the substrate surface is not less than the distance between the metal gate structure and the substrate away from the substrate surface; Etching and removing a portion of the interlayer dielectric layer, forming a gate interlayer dielectric layer opening corresponding to the metal gate and a resistor interlayer dielectric layer opening corresponding to the dummy gate formed on the surface of the non-device area in the interlayer dielectric layer, so that the metal gate and the dummy gate are exposed; The dummy gate and the gate dielectric layer formed on the surface of the non-device area are selectively removed by an etching process, so that the ion-doped area in the non-device area is exposed.

4. The method according to claim 3, characterized in that In the step of selectively removing the dummy gate and the gate dielectric layer formed on the surface of the non-device area by an etching process to expose the ion-doped area in the non-device area, the etching selectivity ratio of the material of the dummy gate and the material of the metal gate falls within the range of 18:1 to 22:

1.

5. A semiconductor structure, characterized in that: The semiconductor structure is manufactured according to the method for manufacturing a semiconductor structure according to any one of claims 1 to 4; the semiconductor structure comprises: A substrate; the substrate comprises a device region and a non-device region; wherein corresponding ion-doped regions are formed in the device region and the non-device region, respectively; the ion-doped region formed in the device region and the ion-doped region formed in the non-device region are formed in the same process based on the same mask; A metal gate structure formed on a surface of the device region; A gate contact structure formed on a side of the metal gate structure away from the substrate; wherein the gate contact structure is in contact with a surface of the metal gate structure away from the substrate; A resistive contact structure is formed corresponding to the non-device area; the resistive contact structure is in direct contact with the ion-doped area in the non-device area.

6. The semiconductor structure according to claim 5, characterized in that: The ion-doped region includes an N-type doped well region and a P-type doped well region; an isolation structure is formed between the N-type doped well region and the P-type doped well region in the device region; no isolation structure is formed between the N-type doped well region and the P-type doped well region in the non-device region; an N-type threshold voltage adjustment region is formed in the N-type doped well region; and a P-type threshold voltage adjustment region is formed in the P-type doped well region.

7. The semiconductor structure according to claim 5, characterized in that: The resistive contact structure contacts the ion-doped region in the non-device region to form a resistive structure; and the resistivity of the resistive structure falls within a range of 40Ω / sq to 120Ω / sq.

8. The semiconductor structure according to claim 5, characterized in that: Also includes: An interlayer dielectric layer is formed on the surface of the substrate; wherein the interlayer dielectric layer has a gate interlayer dielectric layer opening corresponding to the metal gate structure; the gate contact structure contacts the surface of the metal gate structure away from the substrate through the gate interlayer dielectric layer opening; the interlayer dielectric layer has a resistive interlayer dielectric layer opening corresponding to the ion-doped region in the non-device region; the resistive contact structure contacts the ion-doped region in the non-device region through the resistive interlayer dielectric layer opening.

9. A semiconductor integrated device, characterized in that: The semiconductor integrated device comprises the semiconductor structure as claimed in any one of claims 5 to 8.

Images