Semiconductor device and method for manufacturing semiconductor device

Abstract

This application discloses a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes: a semiconductor layer; a drain-well region located in the semiconductor layer; a drain region located in the drain-well region; a first source-well region and a second source-well region located on opposite sides of the drain region; a first source region located in the first source-well region; a second source region located in the second source-well region; a first source-well contact region located within the first source region and extending into the first source-well region; a second source-well contact region located within the second source region and extending into the second source-well region; a first gate cell extending from the first source-well region to the drain region; a second gate cell extending from the second source-well region to the drain region; a first portion of the first source electrode making ohmic contact with the first source region, and a second portion making ohmic contact with the first source-well contact region; a first portion of the second source electrode making ohmic contact with the second source region, and a second portion making ohmic contact with the second source-well contact region. By providing a semiconductor device in which the source electrode simultaneously contacts the source region and the source-well contact region, the operating performance is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more particularly to a semiconductor device and a method for manufacturing the semiconductor device. Background Technology

[0002] In power management technology, a MOSFET controlled by a protected circuit is typically connected in series in the circuit for charge and discharge protection. To meet the charging speed requirements during power supply charging, the on-resistance of the MOSFET needs to be as low as possible. Existing methods to reduce on-resistance include reducing cell size, thinning the chip, and increasing substrate density. However, smaller cell size and thinner chip mean reduced mechanical strength, which increases the risk of damage to the switching transistor during manufacturing and use. Secondly, while a high substrate density can reduce on-resistance, it may also lead to an increase in leakage current, thereby affecting the energy efficiency and stability of the MOSFET. Summary of the Invention

[0003] This application provides a semiconductor device and a method for manufacturing the semiconductor device, aiming to solve the problem of performance degradation in other aspects caused by reducing the on-resistance of a MOSFET in the prior art.

[0004] This application provides a semiconductor device, comprising: a semiconductor layer having a first doping type; a drain well region having a second doping type and located within the semiconductor layer; a drain region having a second doping type and located within the drain well region; a first source well region and a second source well region having a first doping type and located on opposite sides of the drain region; a first source region having a second doping type and located within the first source well region; a second source region having a second doping type and located within the second source well region; a first source well contact region having a first doping type, located within the first source well region and extending to the first source well region; a second source well contact region having a first doping type, located within the second source well region and extending to the second source well region; and a first gate cell located on the semiconductor layer, extending from the first source well region to the drain region. The first source-well region extends to cover a portion of the first source-well region and a portion of the drain region; the second gate cell is located on the semiconductor layer, extending from the second source-well region to the drain region, covering a portion of the second source-well region and a portion of the drain region; the first source electrode has a first portion and a second portion, the first portion of the first source electrode being located above the first source region and forming an ohmic contact with the first source region, and the second portion of the first source electrode being located above the first source-well contact region and forming an ohmic contact with the first source-well contact region; and the second source electrode has a first portion and a second portion, the first portion of the second source electrode being located above the second source region and forming an ohmic contact with the second source region, and the second portion of the second source electrode being located above the second source-well contact region and forming an ohmic contact with the second source-well contact region.

[0005] This application provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor layer of a first doping type; forming a drain region of a second doping type within the semiconductor layer; forming a drain region of the second doping type within the drain region; forming a first source-well region and a second source-well region of the first doping type symmetrically arranged on both sides of the drain region; forming a first gate cell and a second gate cell; simultaneously forming a first source region and a second source region by ion implantation, wherein the first source region is in the first source-well region and the second source region is in the second source-well region; forming a first source aperture region and a second source aperture region, wherein the first source aperture region exposes a portion of the first source-well contact region and a portion of the first source region, and the second source aperture region exposes a portion of the second source-well contact region and a portion of the second source region; and forming the first source-well contact region and the second source-well contact region by ion implantation of the first doping type within the first source region and the second source region.

[0006] This application provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor layer of a first doping type; forming a drain region of a second doping type within the semiconductor layer; forming a drain region of the second doping type within the drain region; forming a first source-well region and a second source-well region of the first doping type symmetrically disposed on both sides of the drain region; forming a first gate cell and a second gate cell; simultaneously forming a first source region and a second source region by ion implantation, wherein the first source region is in the first source-well region and the second source region is in the second source-well region; forming a first source-well contact region and a second source-well contact region by ion implantation of the first doping type in the first source region and the second source region according to a source-well contact region mask; and forming a first source aperture region and a second source aperture region according to an aperture region mask, wherein the first source aperture region exposes a portion of the first source region and a portion or all of the first source-well contact region, and the second source aperture region exposes a portion of the second source region and a portion or all of the second source-well contact region.

[0007] Through one or more embodiments of the above embodiments in this application, at least the following technical effects can be achieved: This application provides a semiconductor MOS device in which the source electrode is in contact with both the source region and the source-well contact region. The larger contact area between the source electrode and the source region can reduce the MOS resistance. At the same time, the contact between the source electrode and the source-well contact region of this semiconductor device avoids the situation in the prior art where the source electrode and the source cannot make effective contact, resulting in parasitic diodes and the MOS transistor not working properly. Attached Figure Description

[0008] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0009] Figure 1 A schematic diagram of the circuit structure of an existing battery protection system is shown.

[0010] Figure 2A top view of a semiconductor device according to an embodiment of this application is shown;

[0011] Figure 3 It shows Figure 2 The example shown is a cross-sectional view of a semiconductor device along the A-A' direction;

[0012] Figure 4 It shows Figure 2 The example shown is a cross-sectional view of a semiconductor device along the B-B' direction;

[0013] Figure 5 A schematic diagram of a semiconductor layer according to an embodiment of this application is shown;

[0014] Figure 6 A schematic diagram is shown after forming a leak trap region according to an embodiment of this application;

[0015] Figure 7 A schematic diagram showing the formation of an isolation region according to an embodiment of this application is shown;

[0016] Figure 8 A schematic diagram showing the formation of a drain region, a first source-well region, and a second source-well region according to an embodiment of this application is provided.

[0017] Figure 9 This diagram shows a schematic diagram after forming a first dielectric layer and a polysilicon layer according to an embodiment of this application;

[0018] Figure 10 A schematic diagram showing the formation of a first gate cell, a second gate cell, a first source region, and a second source region according to an embodiment of this application is provided.

[0019] Figure 11 The following diagram illustrates the formation of a second dielectric layer according to an embodiment of this application. Figure 10 A schematic diagram of the structure shown;

[0020] Figure 12 A schematic diagram is shown after forming a first source-sink contact region and a second source-sink contact region according to an embodiment of this application;

[0021] Figure 13 A superimposed schematic diagram of an aperture region mask and a source-well contact region mask according to an embodiment of this application is shown.

[0022] The meanings of the reference numerals in the attached figures are as follows:

[0023] 201 Semiconductor Layer

[0024] 202 First Dielectric Layer

[0025] 203 Leakage Trap Region

[0026] 204a First Source Trap Region

[0027] 204b Second Source Trap Region

[0028] 205 Quarantine Zone

[0029] 206 polycrystalline silicon layer

[0030] 2061 First gate unit

[0031] 2062 Second gate unit

[0032] 207a First Source Region

[0033] 207b Second Source Region

[0034] 208 Leakage Zone

[0035] 209 Second dielectric layer

[0036] 210a First Source Opening Region

[0037] 210b Second Source Opening Region

[0038] 211a First source trap contact region

[0039] 211b Second source trap contact region

[0040] 212a First Source Electrode

[0041] 212b Second Source Electrode

[0042] 213 Electrostatic withstand voltage area

[0043] 303 Electrostatic Protection Zone Mask

[0044] 304a First N-type Doped Region

[0045] 304b second N-type doped region

[0046] 305 First protective contact window

[0047] 306 Second protective contact window

[0048] 307 First Electrostatic Protection Electrode

[0049] 308 Second electrostatic protection electrode

[0050] 401 First Opening

[0051] 402 Second Opening

[0052] 403 Third Opening

[0053] 404 Fourth opening

[0054] 405 Fifth Opening

[0055] 501 Opening Area Mask

[0056] 502 Source-Sink Contact Area Mask Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0058] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0059] In the description of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances. In this embodiment, the simulated display screen touch unit is connected to the head tracking unit to obtain the movement path of the sensing cursor in the display device.

[0060] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0061] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0062] To facilitate understanding of the semiconductor devices in the embodiments of this application, the application scenarios of the semiconductor devices provided in the embodiments of this application are first described. The semiconductor devices provided in the embodiments of this application can be applied to battery management and charging protection systems of portable electronic devices such as smartphones, smartwatches, and tablets, or they can also be applied to different scenarios such as protection current conversion systems and power ICs. Figure 1 In the power protection circuit shown, the power protection chip mainly monitors and controls the charging and discharging state of the battery to prevent abnormal situations such as overcharging, over-discharging, and overcurrent. The battery 1 supplies power to the external circuit 4. The power protection chip is located between the battery 1 and the external circuit 4. The power protection chip has a first input terminal and a second input terminal to provide control signals to control the conduction of two MOS transistor structures 3.

[0063] Figure 2 A top view of a semiconductor device according to an embodiment of this application is shown. The semiconductor device includes a device region and an electrostatic discharge (ESD) protection zone, which are schematically divided according to the function of the semiconductor structure formed on various portions of the substrate. In practical applications, the semiconductor device can be formed on a single, continuous substrate. This substrate can be a single-crystal silicon substrate or an epitaxial substrate. The substrate material can be silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, and can be a compound semiconductor, alloy semiconductor, or a combination of the above materials. Figure 2In the illustrated embodiment, for ease of understanding, a first source electrode 212a and a first source-well contact region 211a and a first source region 207a directly contacting the first source electrode 212a are shown, wherein the first source-well contact regions 211a are spaced apart along the long side of the first source electrode 212a in the first source region 207a. Figure 2 In the first source region 207a, a portion of the first source well contact region 211a directly contacts the first source electrode 212a and forms an effective ohmic contact. Figure 2 The area ratio and shape of the first source well contact region 211a and the first source region 207a in the figure are only schematic representations and do not represent the area ratio and shape of the first source well contact region 211a and the first source region 207a in actual applications.

[0064] Figure 3 It shows Figure 2 Cross-sectional view of a semiconductor device along the A-A' direction. Figure 4 It shows along Figure 2 A cross-sectional view of a semiconductor device along the B-B' direction. Figure 2-4 In the illustrated embodiment, the semiconductor device employs a single-crystal silicon substrate, which includes:

[0065] Semiconductor layer 201 has a first doping type;

[0066] Drain well region 203, having a second doping type, is located within semiconductor layer 201;

[0067] Drain region 208, having a second doping type, is located within drain trap region 203;

[0068] The first source-well region 204a and the second source-well region 204b have a first doping type and are located on both sides of the drain region 208, respectively.

[0069] The first source region 207a has a second doping type and is located within the first source-well region 204a;

[0070] The second source region 207b has a second doping type and is located within the second source-well region 204b;

[0071] The first source-well contact region 211a has a first doping type, is located within the first source region 207a and extends into the first source-well region 204a.

[0072] The second source-well contact region 211b, having a first doping type, is located within the second source region 207b and extends into the second source-well region 204b.

[0073] The first gate cell 2061 is located on the semiconductor layer 201, extending from the first source-well region 204a to the drain region 208, covering a portion of the first source-well region 204a and a portion of the drain region 208.

[0074] The second gate cell 2062 is located on the semiconductor layer 201, extending from the second source-well region 204b to the drain region 208, covering a portion of the second source-well region 204b and a portion of the drain region 208.

[0075] The first source electrode 212a has a first portion and a second portion. The first portion of the first source electrode 212a is located above the first source region 207a and forms an ohmic contact with the first source region 207a. The second portion of the first source electrode 212a is located above the first source-well contact region 211a and forms an ohmic contact with the first source-well contact region 211a.

[0076] The second source electrode 212b has a first part and a second part. The first part of the second source electrode 212b is located above the second source region 207b and forms an ohmic contact with the second source region 207b. The second part of the second source electrode 212b is located above the second source well contact region 211b and forms an ohmic contact with the second source well contact region 211b.

[0077] exist Figure 3-4 In the illustrated embodiment, the semiconductor device further includes an isolation region 205, which is located above the drain region 208. The first gate cell 2061 and the second gate cell 2062 also cover a portion of the isolation region 205. It should be noted that... Figure 3 In the illustrated embodiment, isolation region 205 can improve the drain electric field distribution of the first field-effect transistor M1 and the second field-effect transistor M2, but in some embodiments, the semiconductor device may not include isolation region 205.

[0078] exist Figure 3-4 In the illustrated embodiment, the semiconductor device includes two common-drain metal-oxide-semiconductor field-effect transistors (FETs), which are referred to as the first FET M1 and the second FET M2 for ease of understanding. The first FET M1 and the second FET M2 have a common drain on the isolation region 205 (not shown in the figure, hereinafter referred to as the common drain), and the first FET M1 and the second FET M2 are arranged symmetrically along the center line of the isolation region 205.

[0079] The first source region 207a serves as the source of the first field-effect transistor M1, and the first gate cell 2061 serves as the gate of the first field-effect transistor M1. The first gate cell 2061 receives a control signal and controls the conduction and turn-off of the first field-effect transistor M1 based on the control signal. The first source region 207a is disposed on the upper surface of the first source-well region 204a, and one surface of the first source region 207a is exposed outside the first source-well region 204a. This surface serves as the connection surface of the first source region 207a for connecting other metal layers or interconnect metals (not shown in the figure).

[0080] exist Figure 3 In the illustrated embodiment, a first source-well contact region 211a is provided on the surface of the first source region 207a, which is connected to the first source electrode 212a. A second source-well contact region 211b is provided on the surface of the second source region 207b, which is connected to the second source electrode 212b. The ion implantation dose of the first source-well contact region 211a is greater than that of the first source region 207a, and the ion implantation dose of the second source-well contact region 211b is greater than that of the second source region 207b. In this embodiment, by increasing the area of ​​the ohmic contact between the first source region 207a and the first source electrode 212a, the electrical connection between the first source region 207a and the first source electrode 212a is improved. Similarly, by increasing the area of ​​the ohmic contact between the second source region 207b and the second source electrode 212b, the electrical connection between the second source region 207b and the second source electrode 212b is improved.

[0081] The second field-effect transistor M2 is completely symmetrical to the first field-effect transistor M1, and has the same structure and working principle. The second field-effect transistor M2 can be understood by referring to the principle description of the first field-effect transistor M1. The structure and principle of the second field-effect transistor M2 will not be described in detail here.

[0082] exist Figure 2 In the embodiment shown, the first source-well region 204a, the drain region 208, and the second source-well region 204b are arranged sequentially along the short side of the first source electrode. The number of first source-well contact regions 211a is N. The N first source-well contact regions 211a are arranged at intervals along the long side of the first source electrode in the first source region 207a, where N is a positive integer ≥1.

[0083] In some embodiments, in the short side direction of the first source electrode, the width of the first source-well contact region 211a may be less than or equal to the width of the first source region 207a. Figure 2The diagram illustrates a case where the width of the first source-well contact region 211a is less than the width of the first source region 207a. It should be noted that in some embodiments, the width of the first source-well contact region 211a may be equal to the width of the first source region 207a. Similarly, the width of the second source-well contact region 211b may be equal to or less than the width of the second source region 207b.

[0084] exist Figure 3-4 In the illustrated embodiment, the first gate cell 2061 includes a first portion and a second portion, wherein the first portion is formed using a first dielectric layer 202 on the semiconductor layer 201, and the second portion is formed using a polysilicon layer 206 on the first dielectric layer 202. The second gate cell 2062 also includes a first portion and a second portion, wherein the first portion is formed using the first dielectric layer 202 on the semiconductor layer 201, and the second portion is formed using a polysilicon layer 206 on the first dielectric layer 202, wherein the polysilicon layer 206 has a first doping type. The first dielectric layer 202 serves as a gate oxide layer to isolate the polysilicon layer 206 from the semiconductor layer 201.

[0085] exist Figure 2-4 In the illustrated embodiment, the first source electrode 212a penetrates the second dielectric layer 209, is located above and electrically connected to the first source-well contact region 211a, and is also located above and electrically connected to the first source region 207a. The second source electrode 212b penetrates the second dielectric layer 209, is located above and electrically connected to the second source-well contact region 211b, and is also located above and electrically connected to the second source region 207b. The first source electrode 212a includes a first source metal filled within the first source aperture region 210a, wherein the first source aperture region 210a and the first source-well contact region 211a are formed according to different photomasks. The first source aperture region 210a is first formed by photolithography based on the aperture region photomask, and then the first source-well contact region 211a is formed by ion implantation based on the source-well contact region photomask. The second source electrode 212b includes a second source metal filled within the second source aperture region 210b, wherein the second source aperture region 210b and the second source well contact region 211b are formed according to different photomasks. First, the second source aperture region 210b is formed by photolithography based on the aperture region photomask, and then the second source well contact region 211b is formed by ion implantation based on the source well contact region photomask.

[0086] like Figure 2-4 As shown, the semiconductor device provided in this application also includes an electrostatic discharge (ESD) protection device, which includes:

[0087] The first dielectric layer 202 is disposed on the semiconductor layer 201;

[0088] A polysilicon layer 206 is disposed on the first dielectric layer 202;

[0089] The polysilicon layer 206 includes a first N-type doped region 304a and a second N-type doped region 304b, wherein a P-type doped region lies between the first N-type doped region 304a and the second N-type doped region 304b. Figure 2-4 In the illustrated embodiment, the first N-type doped region 304a, the P-type doped region 206 between the first N-type doped region 304a and the second N-type doped region 304b, and the second N-type doped region 304b constitute an NPN structure for electrostatic protection of the gate of the first transistor M1. It should be noted that... Figure 2-4 The NPN structure shown is merely an example. In some embodiments, there may be multiple N-type doped regions and multiple P-type doped regions, forming an NPNPN structure or an NPNPNPN structure, depending on the voltage withstand requirements of the application.

[0090] exist Figure 2-4 In the illustrated embodiment, the P-type doped region 206, the first gate unit 2061, and the second gate unit 2062 are formed simultaneously. The first N-type doped region 304a, the second N-type doped region 304b, the first source region 207a, and the second source region 207b are formed simultaneously using the same mask.

[0091] exist Figure 2-4 In the illustrated embodiment, the semiconductor device further includes a first electrostatic discharge (ESD) electrode 307 and a second ESD electrode 308. The first ESD electrode 307 penetrates the second dielectric layer 209, is located above and electrically connected to the first N-type doped region 304a. The second ESD electrode 308 penetrates the second dielectric layer 209, is located above and electrically connected to the second N-type doped region 304b. The first ESD electrode 307 is electrically connected to the first gate cell 2061, and the second ESD electrode 308 is electrically connected to the first source electrode 212a, providing ESD protection for the first field-effect transistor M1. The connection direction of the ESD electrodes is not limited; for example, the first ESD electrode 307 can be electrically connected to the first source electrode 212a, and the second ESD electrode 308 can be electrically connected to the first gate cell 2061.

[0092] In some embodiments, the semiconductor device may further include a third electrostatic discharge (ESD) electrode and a fourth ESD electrode, which are electrically connected to the second source electrode 212b and the second gate unit 2062, respectively, to provide ESD protection for the second field-effect transistor M2.

[0093] exist Figure 2-4 In the embodiment shown, the sheet resistance of the first doped semiconductor layer 201 is 5 to 30 Ohm / sq.

[0094] exist Figure 2-4 In the illustrated embodiment, the first doping type is P-type doping, and the second doping type is N-type doping.

[0095] exist Figure 2-4 In the illustrated embodiment, the semiconductor device further includes an electrostatic discharge (ESD) withstand region 213, which is formed simultaneously with the isolation region 205 using the same process, thereby increasing the isolation capability between the drain region 203 and the P-type doped region 206.

[0096] In some embodiments, the isolation region 205 and the electrostatic discharge (ESD) withstand region 213 are manufactured using an STI process or a LOCOS process. For example, an isolation region 205 can be formed by creating a trench on the surface of the semiconductor layer 201 and filling the trench with silicon oxide material.

[0097] This application provides a laterally diffused metal-oxide-semiconductor (MOS) with a common-drain design between the two field-effect transistors (FETs), saving chip area and allowing more MOS devices to be accommodated per unit chip area. This reduces the on-resistance per unit area, thereby improving chip performance. Simultaneously, because the cross-sectional area of ​​the source electrode is much larger than that of the source-well contact region, simultaneous contact between the source electrode and both the source and source-well contact regions is achieved. The larger contact area between the source electrode and the source region reduces the resistance of the MOS device. Furthermore, the large contact area between the source electrode and the source-well contact region avoids the parasitic diode problem caused by the lack of short-circuiting between the source and source-well contact regions in existing technologies. Similarly, in the electrostatic discharge (ESD) protection device, the contact area between the first N-type doped region and the second N-type doped region and the ESD protection electrode is also large, resulting in better ohmic contact performance.

[0098] This application also provides a method for manufacturing a semiconductor device, the semiconductor device including a device region and an electrostatic protection zone, the manufacturing method including steps S101 to S109.

[0099] Step S101: Provide a semiconductor layer 201 of the first doping type.

[0100] Step S102: Form a drain well region 203 with a second doping type within the semiconductor layer 201.

[0101] Step S103: Form a second-doped drain region 208 within the drain trap region 203.

[0102] Step S104: A first source-well region 204a and a second source-well region 204b of the first doped type are formed symmetrically on both sides of the drain region 208.

[0103] Step S105: Form the first gate cell 2061 and the second gate cell 2062.

[0104] Step S106: Ion implantation is used to simultaneously form a first source region 207a and a second source region 207b, wherein the first source region 207a is in the first source-well region 204a and the second source region 207b is in the second source-well region 204b.

[0105] Step S107: Form a first source aperture region 210a and a second source aperture region 210b according to the aperture region mask, wherein the first source aperture region 210a exposes a part of the first source region 207a, and the second source aperture region 210b exposes a part of the second source region 207b.

[0106] Step S108: Based on the source-well contact region mask, first doping type ions are implanted into the first source region 207a and the second source region 207b to form the first source-well contact region 211a and the second source-well contact region 211b.

[0107] Please refer to the following. Figures 5 to 12 The manufacturing method of a semiconductor integrated circuit is described using an example in which the first doping type is P-type doping and the second doping type is N-type doping.

[0108] Figure 5 A schematic diagram of a semiconductor layer 201 according to an embodiment of the present application is shown. In some embodiments, the semiconductor layer 201 is doped by an ion implantation process to form a P-type doped semiconductor layer 201.

[0109] Figure 6 This diagram illustrates the formation of a drain trap region 203 according to an embodiment of this application. The drain trap region 203 is formed by doping a portion of the semiconductor layer 201 using an ion implantation process. The drain trap region 203 has a different doping type than the semiconductor layer 201. In some embodiments, the N-type ion implantation dose of the drain trap region 203 is 1e. 12 ~5e 13 / cm 3 The doping concentration of the drain well region 203 is greater than that of other parts of the semiconductor layer 201. In one embodiment, the drain well region 203 can be formed by an epitaxial process.

[0110] Figure 7 The diagram shows a schematic of the formation of isolation region 205 and electrostatic discharge (ESD) region 213 according to an embodiment of this application. Isolation region 205 and ESD region 213 are formed by STI process or LOCOS process. The material of isolation region 205 is silicon oxide. It should be noted that the process flow for forming isolation region 205 can be omitted in some embodiments.

[0111] Figure 8The diagram shows a drain region 208, a first source-well region 204a, and a second source-well region 204b formed according to an embodiment of this application. Since the isolation region 205 is relatively thin, an N-type doped drain region 208 can be formed around the isolation region 205 by ion implantation. At the same time, a P-type doped first source-well region 204a and a second source-well region 204b are formed on both sides of the isolation region 205 (drain region 208) by ion implantation. The two are symmetrical to each other and spaced apart from the drain region 208.

[0112] Figure 9 A schematic diagram is shown after forming a first dielectric layer 202 and a polysilicon layer 206 according to an embodiment of this application. After forming the polysilicon layer 206, the polysilicon layer 206 is doped to obtain a P-type doped polysilicon layer 206, which is used to form a first gate cell 2061, a second gate cell 2062, and a P-type doped region.

[0113] Figure 10 This diagram illustrates the formation of a first gate cell 2061, a second gate cell 2062, a first source region 207a, and a second source region 207b according to an embodiment of this application. After removing a portion of the first dielectric layer 202 and the polysilicon layer 206, a first opening 401 is formed exposing the first source-well region 204a, a second opening 402 exposes the drain region 208, and a third opening 403 exposes the second source-well region 204b. The dielectric layer and the first-doped polysilicon layer 206 between the first opening 401 and the second opening 402 are configured as the first gate cell 2061, and the dielectric layer and the first-doped polysilicon layer 206 between the second opening 402 and the third opening 403 are configured as the second gate cell 2062. Ion implantation is performed through the first opening 401 to form the N-type doped first source region 207a, and ion implantation is performed through the third opening 403 to form the N-type doped second source region 207b. In one embodiment, the N-type ion implantation dose of the first source region 207a and the second source region 207b is 1e 15 / cm 2 Order of magnitude. Simultaneously, while forming the first N-type doped source region 207a and the second source region 207b through ion implantation, N-type ions are implanted into the polysilicon layer 206 to form the first N-type doped region 304a and the second N-type doped region 304b.

[0114] Figure 11 The following diagram illustrates the formation of the second dielectric layer 209 according to an embodiment of this application. Figure 10 The diagram shows a schematic of the structure. The second dielectric layer 209 completely covers the surface of the semiconductor layer 201, the first gate cell 2061, and the second gate cell 2062.

[0115] Figure 12A schematic diagram is shown after the formation of the first source-well contact region 211a and the second source-well contact region 211b according to an embodiment of this application. First, a first source aperture region 210a exposing a portion of the first source region 207a and a second source aperture region 210b exposing a portion of the second source region 207b are formed on the second dielectric layer 209.

[0116] Figure 13 A superimposed schematic diagram of an aperture region mask 501 and a source-well contact region mask 502 according to an embodiment of this application is shown. In one embodiment, a first source aperture region 210a, a second source aperture region 210b, a first protective contact window 305, and a second protective contact window 306 are first formed based on the aperture region mask 501, wherein a portion of the first source aperture region 210a is exposed, and a portion of the second source aperture region 210b is exposed. Then, a first source-well contact region 211a and a second source-well contact region 211b are formed in the first and second source regions using ion implantation of a first doping type based on the source-well contact region mask 502. In one embodiment, the first source-well contact region 211a is formed by ion implantation through the first source aperture region 210a, and the second source-well contact region 211b is formed by ion implantation through the second source aperture region 210b based on the source-well contact region mask 502.

[0117] In some embodiments, the P-type ion implantation dose for forming the first source-well contact region 211a and the second source-well contact region 211b is 1e 15 / cm 2 -1e 16 / cm 2 Between orders of magnitude.

[0118] In some embodiments, the width ratio of the first source aperture region 210a to the width ratio of the first source region 207a is in the range of 0.1:1 to 1:1. The first source-well contact region 211a formed by the contact window having this width ratio enables good contact performance and current transmission efficiency between the first source region 207a and the source electrode. The same applies to the second source-well contact region 211b, which will not be described in detail here.

[0119] After forming a first source well contact region 211a of the first doped type through the first source opening region 210a and forming a second source well contact region 211b of the first doped type through the second source opening region 210b, the above method further includes filling the first source opening region 210a with a first source metal to form a first source electrode 212a and filling the second source opening region 210b with a second source metal to form a second source electrode 212b. Figure 2-4 A schematic diagram is shown after the formation of the first source electrode 212a and the second source electrode 212b according to an embodiment of this application.

[0120] For the manufacture of electrostatic discharge protection devices, after step 105, the above-mentioned semiconductor device manufacturing method further includes: forming an electrostatic discharge protection mask 303 on the surface of the polysilicon layer 206 of the electrostatic discharge protection area, removing a portion of the electrostatic discharge protection mask 303, and forming a fourth opening 404 and a fifth opening 405.

[0121] Figure 10 This diagram illustrates a portion of the electrostatic discharge protection zone mask 303 after removal according to an embodiment of this application. After removing this portion of the electrostatic discharge protection zone mask 303, forming a fourth opening 404 and a fifth opening 405, ion implantation is performed simultaneously to form a first source region 207a and a second source region 207b. Ion implantation is then performed through the fourth opening 404 to form a first N-type doped region 304a, and through the fifth opening 405 to form a second N-type doped region 304b. Both the first and second N-type doped regions 304a and 304b are N-type doped. The N-type ion implantation dose of the first and second N-type doped regions 304a and 304b is 1e. 15 / cm 2 Order of magnitude. After forming the first N-type doped region 304a and the second N-type doped region 304b, the entire electrostatic protection zone mask 303 is removed.

[0122] Figure 11 A schematic diagram is shown after the formation of the second dielectric layer 209 according to an embodiment of this application. Figure 12 The diagram illustrates the formation of a first protective contact window 305 and a second protective contact window 306 according to an embodiment of this application. The first protective contact window 305 exposes a first N-type doped region 304a, and the second protective contact window 306 exposes a second N-type doped region 304b, formed using a second dielectric layer 209. In some embodiments, in a first direction, the width ratio of the first protective contact window 305 to the width ratio of the first N-type doped region 304a is in the range of 0.2:1 to 1:1. A suitable width ratio can improve the protection effect and reliability of the device. Figure 3-4A schematic diagram is shown after the formation of the first electrostatic discharge (ESD) protection electrode 307 and the second ESD protection electrode 308 according to an embodiment of this application. The first protective contact window 305 is filled with a metallic material to form the first ESD protection electrode 307, and the second protective contact window 306 is filled with a metallic material to form the second ESD protection electrode 308. It should be noted that, in one embodiment, while forming the source-well contact region mask 502, an ESD protection zone mask covering the first protective contact window 305 and the second protective contact window 306 is simultaneously formed in the ESD protection zone. Therefore, when the first source-well contact region 211a and the second source-well contact region 211b are formed by ion implantation, the first N-type doped region 304a and the second N-type doped region 304b exposed through the first protective contact window 305 and the second protective contact window 306 are not affected by P-type doping.

[0123] This application also provides a method for manufacturing a semiconductor device, the semiconductor device including a device region and an electrostatic protection zone, the manufacturing method including steps S201 to S209.

[0124] Step S201: Provide a semiconductor layer of the first doping type;

[0125] Step S202: Form a drain well region with a second doping type within the semiconductor layer;

[0126] Step S203: Form a second-doped drain region within the drain trap region;

[0127] Step S204: A first source-well region and a second source-well region of the first doped type are symmetrically arranged on both sides of the drain region;

[0128] Step S205: Form the first gate cell and the second gate cell;

[0129] Step S206: Ion implantation is used to simultaneously form a first source region and a second source region, wherein the first source region is in the first source-well region and the second source region is in the second source-well region;

[0130] Step S207: Based on the source-well contact region mask, ions of the first doping type are implanted into the first and second source regions to form the first and second source regions; and

[0131] Step S208: Form a first source aperture region and a second source aperture region according to the aperture region mask, wherein the first source aperture region exposes a part of the first source region and a part or all of the first source well contact region, and the second source aperture region exposes a part of the second source region and a part or all of the second source well contact region.

[0132] In one embodiment, the first source well contact region further extends to the first source well region, and the second source well contact region further extends to the second source well region.

[0133] The above embodiments can be applied to a power protection system, such as... Figure 1 As shown, the power protection system includes an input positive terminal B+, an input negative terminal B-, an output positive terminal P+, an output negative terminal P-, a first resistor R1, a first capacitor C1, a power protection chip 2, and the aforementioned semiconductor device 3.

[0134] The positive input terminal B+ is coupled to the positive terminal of the power supply, the negative input terminal B- is coupled to the negative terminal of the power supply, the positive output terminal P+ is coupled to the positive terminal of the external circuit and also coupled to the positive input terminal, and the negative output terminal P- is coupled to the negative terminal of the external circuit 4. The first resistor R1 has a first end and a second end, wherein the first end is coupled to the positive input terminal B+. The first capacitor C1 has a first end and a second end, wherein the first end is coupled to the second end of the first resistor R1, and the second end is coupled to the negative input terminal B-. The power protection chip 2 has an input terminal, a first output terminal, and a second output terminal, wherein the input terminal is coupled to the second end of the first resistor R1. The first gate cell 2061 of the semiconductor device is coupled to the first output terminal of the power protection chip 2, and the second gate cell 2062 is coupled to the second output terminal of the power protection chip 2. The first source-well contact region 211a of the semiconductor device 3 is coupled to the negative input terminal B- through the first source electrode 212a, and the second source-well contact region 211b of the semiconductor device is coupled to the negative output terminal P- through the second source electrode 212b. When the control signal of the power protection chip turns off transistors M1 and / or M2 in the semiconductor device, the power supply loop to the external circuit is cut off.

[0135] like Figure 1 As shown, the NPN structure formed between the first electrostatic discharge (ESD) electrode and the second ESD electrode can be regarded as a pair of positively coupled diodes. The negative electrode of one diode is coupled to the first gate cell through the first ESD electrode, and the negative electrode of the other diode is coupled to the first source electrode through the second ESD electrode, which is used to provide ESD protection for the gate of the first transistor M1.

[0136] In the above steps, the specific steps of the deposition process used to form each layer can be designed according to actual needs, and this application embodiment does not impose specific limitations on this. The specific steps of the etching process used to remove each layer can also be designed according to actual needs, and this application embodiment does not impose specific limitations on this. The specific steps of doping each layer can also be designed according to actual needs, wherein the number of doped regions and the doping concentration and dopant ions of each doped region can be determined according to actual needs.

[0137] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0138] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. However, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor layer, having a first type of doping; A drain trap region, having a second doping type, is located within the semiconductor layer; The drain region, having a second doping type, is located within the drain trap region; The first source-well region and the second source-well region have a first doping type and are located on both sides of the drain region, respectively. The first source region, having a second doping type, is located within the first source-well region; The second source region, having a second doping type, is located within the second source-well region; The first source-well contact region has a first doping type, is located within the first source region and extends into the first source-well region; The second source-well contact region has a first doping type, is located within the second source region and extends into the second source-well region; The first gate cell is located on the semiconductor layer, extending from the first source-well region to the drain region, and covering a portion of the first source-well region and a portion of the drain region; The second gate cell is located on the semiconductor layer, extends from the second source-well region to the drain region, and covers a portion of the second source-well region and a portion of the drain region; The first source electrode has a first part and a second part. The first part of the first source electrode is located above the first source region and forms an ohmic contact with the first source region. The second part of the first source electrode is located above the first source well contact region and forms an ohmic contact with the first source well contact region. The first source well contact regions are spaced apart in the first source region along the long side direction of the first source electrode. and The second source electrode has a first part and a second part. The first part of the second source electrode is located above the second source region and forms an ohmic contact with the second source region. The second part of the second source electrode is located above the second source-well contact region and forms an ohmic contact with the second source-well contact region.

2. The semiconductor device as claimed in claim 1, characterized in that, It also includes an isolation zone, which is located above the leak zone.

3. The semiconductor device of claim 2, wherein the first gate cell and the second gate cell further cover a portion of the isolation region.

4. The semiconductor device of claim 1, wherein the doping concentration of the first source-well contact region is greater than the doping concentration of the first source region.

5. The semiconductor device of claim 1, wherein the first source electrode comprises a first source metal filled within a first source aperture region, wherein the first source aperture region and the first source well contact region are formed by photolithography using different photomasks.

6. The semiconductor device of claim 1, wherein the first source aperture region is first formed by photolithography and then the first source well contact region is formed by ion implantation.

7. The semiconductor device as claimed in claim 1, characterized in that, It also includes an electrostatic discharge (ESD) protection device, which includes: A first dielectric layer is disposed on the semiconductor layer; A polycrystalline silicon layer is disposed on the first dielectric layer; The polycrystalline silicon layer includes a first N-type doped region and a second N-type doped region, wherein a P-type doped region is located between the first N-type doped region and the second N-type doped region.

8. The semiconductor device of claim 7, wherein the P-type doped region, the first gate unit, and the second gate unit are formed simultaneously.

9. The semiconductor device of claim 7, wherein the first N-type doped region, the second N-type doped region, the first source region, and the second source region are formed simultaneously.

10. The semiconductor device as claimed in claim 7, characterized in that, Also includes: The first electrostatic protection electrode is located above the first N-type doped region and is electrically connected to the first N-type doped region. as well as The second electrostatic protection electrode is located above the second N-type doped region and is electrically connected to the second N-type doped region.

11. The semiconductor device as claimed in claim 2, characterized in that, It also includes an electrostatic discharge (ESD) protection device, which includes: The electrostatic discharge (ESD) withstand region is located within the semiconductor layer, and the ESD withstand region and the isolation region are formed simultaneously. The first dielectric layer is located on the electrostatic withstand voltage region; A polycrystalline silicon layer is disposed on the first dielectric layer; The polycrystalline silicon layer includes a first N-type doped region and a second N-type doped region, wherein a P-type doped region is located between the first N-type doped region and the second N-type doped region.

12. The semiconductor device of claim 1, wherein the first doping type is P-type doping and the second doping type is N-type doping.

13. A method for manufacturing a semiconductor device, characterized in that, include: Provide a semiconductor layer of the first doping type; A drain well region with a second doping type is formed within the semiconductor layer; A second-doped drain region is formed within the drain trap region; A first source-well region and a second source-well region of the first doping type are symmetrically arranged on both sides of the drain region; Forming the first gate unit and the second gate unit; Ion implantation is used to simultaneously form a first source region and a second source region, wherein the first source region is in a first source-well region and the second source region is in a second source-well region; A first source aperture region and a second source aperture region are formed according to the aperture region mask, wherein a portion of the first source aperture region is exposed and a portion of the second source aperture region is exposed. as well as According to the source-well contact region mask, ion implantation of the first doping type is used to form the first source region and the second source region to form the first source-well contact region and the second source region. The first source-well contact regions are arranged at intervals along the long side direction of the first source opening region in the first source region.

14. The manufacturing method as described in claim 13, characterized in that, Also includes: An isolation region is formed above the drain region, wherein the isolation region is formed by an STI process or a LOCOS process.

15. The manufacturing method of claim 13, wherein ion implantation is performed on the polysilicon of the electrostatic protection zone while forming the first source region and the second source region to form the first N-type doped region and the second N-type doped region.

16. The manufacturing method of claim 13, wherein the first source-well contact region further extends into the first source-well region, and the second source-well contact region further extends into the second source-well region.

17. A method for manufacturing a semiconductor device, characterized in that, include: Provide a semiconductor layer of the first doping type; A drain well region with a second doping type is formed within the semiconductor layer; A second-doped drain region is formed within the drain trap region; A first source-well region and a second source-well region of the first doping type are symmetrically arranged on both sides of the drain region; Forming the first gate unit and the second gate unit; Ion implantation is used to simultaneously form a first source region and a second source region, wherein the first source region is in a first source-well region and the second source region is in a second source-well region; Based on the source-well contact region mask, ions of a first doping type are implanted into the first and second source regions to form the first and second source regions; and A first source aperture region and a second source aperture region are formed according to the aperture region mask, wherein the first source aperture region exposes a part of the first source region and part or all of the first source well contact region, and the second source aperture region exposes a part of the second source region and part or all of the second source well contact region, and the first source well contact regions are arranged at intervals along the long side direction of the first source aperture region in the first source region.

18. The manufacturing method of claim 17, wherein the first source-well contact region further extends into the first source-well region, and the second source-well contact region further extends into the second source-well region.

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