A large scale addressable critical path test circuit

Abstract

The application discloses a large-scale addressable critical path test circuit, which comprises an excitation circuit for generating an input signal VIN and a power supply VDD; a row addressing circuit and a column addressing circuit for receiving a row address and a column address respectively, and controlling a switch circuit according to the received address signals to select a to-be-tested path from a plurality of to-be-tested paths, apply the input signal VIN to an input end of the to-be-tested path, and apply the power supply VDD to the to-be-tested path to supply power for the to-be-tested path; and a TDC module connected to each to-be-tested path for detecting a delay time required for the input signal VIN to propagate in the corresponding to-be-tested path; and a sensing circuit connected to each to-be-tested path for detecting actual power supply voltages VDD of the to-be-tested paths respectively SENSE In the application, the sensing circuit is used to sense the VDD voltage drop of the to-be-tested unit, and the actual working voltage of the circuit can be accurately detected.

Description

Technical Field

[0001] This invention relates to the field of semiconductor wafer testing technology, and more specifically to a large-scale addressable critical path test circuit. Background Technology

[0002] As CMOS technology nodes continue to shrink, random fluctuations in process technology and unreliability during circuit operation lead to increasingly significant variations in propagation delays along the critical path. Critical path time margin design needs to ensure that the circuit continues to function correctly even under worst-case combinations of process variations, temperature hotspots, and power supply voltage uncertainties, while minimizing design margins and circuit power consumption.

[0003] When designing the time margin of a circuit, accurate estimation of the true critical path is necessary to ensure high reliability. Monitoring the impact of random process variations on critical path delays, as well as changes in the critical path during circuit operation, requires a fast, accurate, large-scale testing technique to provide sufficient data support for monitoring random variations and operational states. Summary of the Invention

[0004] In view of the above-mentioned defects and shortcomings of the existing technology, the present invention provides a large-scale addressable critical path test circuit, which aims to realize the performance measurement of large-scale critical paths (including propagation delay, leakage current, power consumption, etc.), and can also achieve higher area utilization and accuracy.

[0005] To achieve the above objectives, the present invention provides a large-scale addressable critical path test circuit, comprising:

[0006] The excitation circuit is used to generate the input signal VIN and the power supply VDD;

[0007] The row addressing circuit and column addressing circuit are used to receive the row address and column address respectively, and control the switching circuit according to the received address signal to select the path to be tested from multiple paths to be tested, apply the input signal VIN to the input terminal of the path to be tested, and apply the power supply VDD to the path to be tested to supply power to the path to be tested.

[0008] Each path under test is connected to a TDC module, which is used to detect the delay time required for the input signal VIN to propagate in the corresponding path under test.

[0009] The sensing circuit is connected to each path under test and is used to detect the actual supply voltage VDD of each path under test. SENSE .

[0010] A further improvement of the present invention is that the path to be tested is the signal transmission path in the circuit.

[0011] A further improvement of the present invention is that: the multiple paths to be tested are divided into several groups, and any two groups of paths to be tested include circuit units of different levels or different types.

[0012] A further improvement of the present invention is that the types of the circuit units include inverters, NAND gates, NOR gates, etc.

[0013] A further improvement of the present invention is that each of the paths under test is integrated on a single wafer, which is provided with a power supply PAD and an input signal PAD, respectively used to receive the power supply VDD and the input signal VIN generated by the excitation circuit.

[0014] A further improvement of the present invention is that the switching circuits are all implemented by a combination of transmission gates and pull-down transistors.

[0015] A further improvement of the present invention is that: the TDC module converts the delay time into a digital signal Q<1:N> in the form of a temperature code; the output terminal of each TDC module is connected to a transmission gate, and the output terminal of each transmission gate is connected to an encoding circuit; the encoding circuit converts the digital signal Q<1:N> output by the TDC module into a binary signal S<1:A>.

[0016] The advantages of this invention are as follows:

[0017] 1) In this invention, all paths under test share a single VIN and VDD PAD, which can significantly increase the number of tests per unit area.

[0018] 2) This invention provides a circuit that allows for large-scale testing of different paths and supports efficient monitoring of critical paths.

[0019] 3) In this invention, a sensing circuit is used to sense the VDD voltage drop of the unit under test, which can accurately detect the actual operating voltage of the circuit and ensure the accurate analysis of subsequent test data. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the large-scale addressable critical path test circuit of the present invention;

[0021] Figure 2 This is a schematic diagram of the sensing circuit in this invention;

[0022] Figure 3 This is a schematic diagram of the transmission gate in the switching circuit of the present invention;

[0023] Figure 4 This is a connection diagram of the TDC module in this invention;

[0024] Figure 5 This is a schematic diagram of the TDC module in this invention;

[0025] Figure 6 This is a schematic diagram of the output circuit associated with the TDC module in this invention. Detailed Implementation

[0026] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0027] Some exemplary embodiments of the invention have been described for illustrative purposes. It should be understood that the invention may be implemented in other ways not specifically shown in the accompanying drawings.

[0028] This invention provides a large-scale addressable critical path test circuit, mainly composed of an addressing circuit, a switching circuit, an excitation circuit, a sensing circuit, a test array, and a time-to-digital (TDC) circuit. Considering that propagation delay, as a time quantity, cannot be directly output, a TDC circuit is needed to convert the time quantity into a digital quantity for output. Specifically:

[0029] Addressing circuits include row addressing circuits and column addressing circuits. Figure 1 As shown, in this embodiment, both the row address and column address are 4 bits. The row and column addresses are RA[0:3] and CA[0:3], respectively, which are converted into 16-bit R[0:15] and C[0:15] by a decoder, thus enabling the testing of 16×16=256 paths.

[0030] The excitation circuit generates the input signal VIN and the power supply VDD. Row-addressing and column-addressing circuits are connected to the switching circuit. Additionally, the switching circuit is connected to the two outputs of the excitation circuit. The row-addressing and column-addressing circuits control the switching circuit to select the path to be tested from the array of multiple paths under test (DUTs), apply the input signal VIN to the input terminal of that DUT, and apply the power supply VDD to the DUT to supply power. In this way, the power supply VDD and the input signal of the DUT can be specified simultaneously, enabling more comprehensive multi-dimensional testing of the DUT.

[0031] like Figure 1 , Figure 2 As shown, each path under test is connected to a sensing circuit to sense the actual power supply voltage VDD of each path under test.SENSE The input signal VIN is input to the inverter, i.e., the gate terminal of the MOSFET. The gate current is extremely small, and the voltage drop from the transmission gate in the switching circuit is negligible. VDD is connected to the source terminals of the PMOS transistors of each inverter in the path under test. The current is relatively large, and the voltage drop from the transmission gate needs to be considered. Therefore, a sensing circuit is set up, i.e., a transmission gate is connected to the VDD terminal to obtain the signal VDD. SENSE .

[0032] The array under test (DUT) comprises multiple test paths. In this embodiment, each test path is an inverter chain, and the DUT includes 256 test paths, divided into 8 groups of 32 test paths each. Within these 8 groups, any two groups of test paths have inverter chains with different numbers of inverter stages. In this embodiment, the 8 groups of inverter chains have 14, 20, 26, 32, 38, 44, 50, and 56 stages, respectively. Using test paths with different stages ensures diversity in the test paths. It is important to note that inverter chain groups with different stages have different propagation delays. When setting the number of bits in the TDC module's output signal, the maximum delay needs to be estimated to ensure accurate output.

[0033] Each of the paths under test is integrated on a single wafer, which is equipped with a power supply PAD and an input signal PAD, used to receive the power supply VDD and input signal VIN generated by the excitation circuit, respectively. Multiplexing a single power supply PAD and input signal PAD for each path under test can effectively improve chip area utilization. In this embodiment, multiplexing is achieved through addressing circuits and switching circuits.

[0034] like Figure 3 As shown, the switching circuit is implemented using a combination of a transmission gate and a pull-down transistor. When Address[N] = 1, the pull-down transistor is closed, the transmission gate is open, and V... OUT =V IN Otherwise, the pull-down transistor is on, V OUT =0. In the addressing circuit, R[0:15] and C[0:15] can generate 256 signals, corresponding to the VIN and VDD signals of the excitation circuit, and can generate 256 sets of VIN[N] and VDD[N], which uniquely correspond to the row and column addresses. When the address signal is given, only one set of transmission gates in the switching circuit is controlled to be turned on.

[0035] like Figure 4 As shown, the propagation delay of the path under test is output in digital form and shares a common set of output ports. Applying a VIN signal to the input of the inverter chain yields VOUT0, and the delay times of the two are compared. However, the test equipment cannot directly obtain the time quantity; the circuit needs to convert the time quantity into an electrical quantity for output. Using a TDC circuit, inputting VIN and VOUT0 will output the time difference in binary code.

[0036] like Figure 5 As shown, this example uses a TDC based on the vernier delay line principle, consisting of two delay lines with slightly different delay times. The start (precursor) signal is fed to the delay line with the larger delay, i.e., the slow delay line, while the stop (lag) signal is fed to the fast delay line. During the measurement process, the stop signal propagates relatively quickly and eventually catches up with the start signal after passing through a certain number of delay units. Therefore, the resolution of this TDC is the delay difference r = τ between the unit delays in the slow and fast lines. s -τ f The conversion range is the product of the series N and the resolution r.

[0037] The inputs and outputs of the inverter chain are connected to TDC as the preamble and hysteresis signals, respectively, resulting in Q<1:N>. Assuming that at stage M, the hysteresis signal catches up with the preamble signal, then the output of Q<1:M-1> is low. <m:n>Since the output is high, the number M of low levels in Q<1:N> can be used to determine the delay time T. DELAY = r × M. However, when there are many levels, directly outputting Q<1:N> will occupy too many pads, so it is necessary to convert the N-bit temperature code into... Bit( The binary code S<1:A> (rounded up) can effectively reduce the number of PADs.

[0038] like Figure 6 As shown, the outputs of multiple inverter chains are connected together through a transmission gate. If V OUT If the capacitors are directly connected together, the load driven by the inverter will have an excessively large capacitance, resulting in incomplete charging and discharging of the capacitor, which will cause V to... OUT The waveform is severely distorted; the transmission gates are also controlled by the addressing circuit. Digital signals are not affected by charging and discharging time, therefore they need to be converted into digital signals Q<1:N> and isolated via a TDC. Each inverter under test is chained together with a TDC, connected via transmission gates, and the address signal is consistent with the switching circuit. An encoder is then connected to convert Q<1:N> into binary code S<1:A>, further reducing the number of PADs required.

[0039] The output data is used to monitor process effects and changes in the critical path during operation, providing feedback for further adjustments to the circuit's operating state. Delay data is fed back to the control unit, enabling dynamic adjustment of the circuit's operating voltage and frequency. If an increase in critical path delay is detected, it may be necessary to increase the voltage or decrease the operating frequency to ensure circuit stability and reliability. Conversely, if the critical path delay decreases, the voltage can be decreased or the frequency increased to improve energy efficiency and performance. Simultaneously, continuous monitoring of the critical path's performance is required to ensure stable circuit operation under adjusted voltage and frequency.

[0040] The core of this invention lies in improving the integration of the test circuit by sharing the signal ports of all units under test, and outputting the signal in digital form. Other alternatives include changing the number of paths under test, changing the number of parallel test arrays, changing the number of row and column address bits, changing the specific structure of the path, changing the principle and structure of the TDC circuit, changing the structure of the switching circuit, changing the bit width of the delayed output digital signal, and changing the delayed signal feedback method, all of which do not exceed the protection scope of this invention.

[0041] The key aspect of this invention lies in the testing of large-scale path propagation delays, monitoring the impact of process on the critical path and its changes during operation, while simultaneously outputting the delay in digital form to provide feedback for further adjustments to the circuit's operating state. The large-scale test circuit utilizes a switching circuit module to share the power signal for all paths under test, improving area utilization during rapid and accurate testing of different paths. Therefore, the intended protection lies in the design that employs a shared power signal for all paths and outputs it digitally when performing large-scale critical path testing using addressing methods.

[0042] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.< / m:n>

Claims

1. A large-scale addressable critical path test circuit, characterized in that... include: The excitation circuit is used to generate the input signal VIN and the power supply VDD; The row addressing circuit and column addressing circuit are used to receive the row address and column address respectively, and control the switching circuit according to the received address signal to select the path to be tested from multiple paths to be tested, apply the input signal VIN to the input terminal of the path to be tested, and apply the power supply VDD to the path to be tested to supply power to the path to be tested. Each path under test is connected to a TDC module, which is used to detect the delay time required for the input signal VIN to propagate in the corresponding path under test. The sensing circuit is connected to each path under test and is used to detect the actual supply voltage VDD of each path under test. SENSE ; The path to be tested is the signal transmission path in the circuit; Each of the paths under test is integrated on a single wafer, which is provided with a power supply PAD and an input signal PAD, used to receive the power supply VDD and the input signal VIN generated by the excitation circuit, respectively. Each path under test reuses a single power supply PAD and input signal PAD, which is achieved through the addressing circuit and the switching circuit; the propagation delay of each path under test is output in digital form and shares a set of output ports. The TDC module converts the delay time into a digital signal Q<1:N> in the form of a temperature code; the output terminal of each TDC module is connected to a transmission gate, and the output terminal of each transmission gate is connected to an encoding circuit; the encoding circuit converts the digital signal Q<1:N> output by the TDC module into a binary signal S<1:A>.

2. The large-scale addressable critical path test circuit according to claim 1, characterized in that: Multiple paths under test are divided into several groups, and any two groups of paths under test include circuit units of different levels or different types.

3. The large-scale addressable critical path test circuit according to claim 2, characterized in that: The types of circuit units include inverters, NAND gates, and NOR gates.

4. The large-scale addressable critical path test circuit according to claim 1, characterized in that: The switching circuits are all implemented by a combination of transmission gates and pull-down transistors.

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