An LDO circuit with dynamic load compensation

Abstract

The application discloses a kind of LDO circuits with dynamic load compensation, it is related to power management technical field, and its technical solution main point is: including error amplifier, power tube M1, feedback circuit and dynamic load compensation circuit;Power tube M1 is P-type field effect transistor;Feedback circuit detects output voltage, and output voltage is fed back to error amplifier;Dynamic load compensation circuit is connected the drain of power tube M1, for sensing the change of output voltage VOUT, and according to the change of output voltage VOUT the drive current I0 of the drain output of power tube M1 is adjusted.The application is dynamically adjusted to the output current of power tube by dynamic load compensation circuit, and then adjusts output voltage, and when dynamic load compensation circuit can effectively reduce current load in transient response simulation output voltage recovery response time when transient change, so as to enable LDO circuit stable and efficient operation.

Description

Technical Field

[0001] This invention relates to the field of power management technology, and more specifically, to an LDO circuit with dynamic load compensation. Background Technology

[0002] In modern electronic systems, a stable and high-quality power supply is crucial for the normal operation of various circuits. Low-dropout linear regulators (LDOs), as a commonly used power management chip, are widely used in many fields, such as microprocessors, analog circuits, and radio frequency circuits in mobile devices, communication equipment, and consumer electronics.

[0003] As electronic devices become increasingly functional and perform better, higher demands are placed on the transient response performance of power supplies. Traditional LDO circuits have significant limitations when faced with rapid changes in load current. When the load current suddenly increases, the output voltage often experiences a significant sag due to the inherent characteristics of the LDO's internal circuitry. This is because, at the moment of load current change, the LDO's power delivery capability cannot keep up with the new load demand, causing the output voltage to drop instantaneously. For example, when a mobile phone processor instantly switches from a low-power mode to a high-load operating mode, a traditional LDO power supply may cause the processor's supply voltage to drop instantly, affecting processor performance and potentially leading to a brief system crash or malfunction.

[0004] Conversely, when the load current decreases sharply, the output voltage is prone to overshoot. This voltage instability can damage sensitive electronic components, affecting the reliability and lifespan of the circuit. In some high-precision analog or radio frequency circuits, even small voltage fluctuations can lead to signal distortion, increased noise, and other problems, severely impacting the performance of the entire system.

[0005] Furthermore, traditional LDO compensation circuit designs are typically based on specific load conditions and frequency ranges, making them poorly adaptable to complex and ever-changing real-world application scenarios. When the load current changes rapidly, their compensation mechanisms cannot adjust quickly and effectively, further exacerbating transient response problems. Moreover, as electronic devices move towards miniaturization and low power consumption, LDO circuits need to address transient response issues without increasing power consumption and chip area to meet the stringent power stability requirements of increasingly complex electronic systems. A stable power supply is crucial for the operation of modern electronic devices. Low-dropout linear regulators (LDOs) have emerged to play a key role in power management. Summary of the Invention

[0006] The purpose of this invention is to provide an LDO circuit with dynamic load compensation to solve problems such as insufficient transient response performance, output voltage fluctuation, and limitations in compensation circuit design in the prior art.

[0007] The above-mentioned technical objective of the present invention is achieved through the following technical solution: an LDO circuit with dynamic load compensation, comprising an error amplifier, a power transistor M1, a feedback circuit, and a dynamic load compensation circuit;

[0008] The power transistor M1 is a P-type field-effect transistor; the feedback circuit detects the output voltage and feeds it back to the error amplifier; the dynamic load compensation circuit is connected to the drain of the power transistor M1 to sense changes in the output voltage VOUT and adjusts the drive current I0 output from the drain of the power transistor M1 according to the changes in the output voltage VOUT, so as to improve the rate of change of the output voltage VOUT.

[0009] The present invention is further configured such that: the dynamic load compensation circuit includes a sensing circuit and a preloading circuit;

[0010] The sensing circuit is used to sense the current of the power transistor M1;

[0011] The preload circuit generates a preload current based on the current induced by the power transistor M1, and adjusts the preload current according to the change in the output voltage VOUT, thereby adjusting the drive current.

[0012] The present invention is further configured such that: the sensing circuit includes a power transistor M2, the power transistor M2 is a P-type field-effect transistor, the gate of the power transistor M2 is connected to the gate of the power transistor M1, and the channel lengths of the power transistors M1 and M2 are the same, L; and the width W of the power transistor M1 is K1 times the width W of the power transistor M2, the width-to-length ratio of the NMOS transistor M6 is K2 times the width-to-length ratio of the NMOS transistor M5, the width-to-length ratio of the NMOS transistor M4 is K3 times the width-to-length ratio of the NMOS transistor M3, wherein K1, K2, and K3 > 10, the source of the power transistor M2 is used to input the power supply voltage VDD, and the drain of the power transistor M2 is connected to the preload circuit.

[0013] The present invention is further configured such that: the preloading circuit includes NMOS transistors M3, M4, M5, and M6 and capacitor C1, wherein:

[0014] The drain of NMOS transistor M5 is connected to the drain of power transistor M2, and the source of NMOS transistor M5 is connected to the drain of NMOS transistor M3.

[0015] The drain of NMOS transistor M6 is connected to the drain of power transistor M1, the source of NMOS transistor M6 is connected to the drain of NMOS transistor M4, and the gate of NMOS transistor M6 is connected to the gate of NMOS transistor M5. The gates of NMOS transistor M6 and NMOS transistor M5 are connected at point VB, which is the bias control point.

[0016] The present invention is further configured such that when the load decreases, the output voltage VOUT increases, and the voltage difference is coupled to the gates of NMOS transistors M3 and M4 via capacitor C1, thereby increasing the gate voltage of NMOS transistor M4 and increasing the current flowing through NMOS transistor M4, so as to reduce the output voltage VOUT.

[0017] The present invention is further configured such that when the load increases, the output voltage VOUT decreases, and the voltage difference is coupled to the gates of NMOS transistors M3 and M4 via capacitor C1, thereby reducing the gate voltage of NMOS transistor M4 and reducing the current flowing through NMOS transistor M4, thus increasing the output voltage VOUT.

[0018] Another object of the present invention is to provide an electronic device using the above-described dynamic load compensation LDO circuit, the electronic device including at least a microprocessor, analog circuit or radio frequency circuit, the LDO circuit providing a stable power supply for the electronic device.

[0019] By employing the above technical solution, the LDO circuit of this invention can accurately sense and respond to minute changes in the output voltage VOUT through a dynamic load compensation circuit. This precise voltage regulation capability is crucial for maintaining the stable operation of sensitive circuits in electronic devices, especially in applications highly sensitive to voltage fluctuations, such as high-precision analog circuits and radio frequency circuits. By reducing voltage fluctuations, this invention can significantly reduce signal distortion and noise, improving overall system performance. When the load current changes rapidly, such as when a processor switches from a low-power mode to a high-load operating mode, the LDO circuit of this invention can quickly adjust the output voltage, reducing voltage undershoot or overshoot. This rapid transient response capability is crucial for ensuring the stability and reliability of high-performance electronic devices under sudden load changes, preventing system crashes or malfunctions caused by voltage transients.

[0020] Compared to traditional LDOs, the dynamic load compensation circuit of this invention is not limited to specific load conditions and frequency ranges, but can adapt to complex and ever-changing real-world application scenarios. This broad adaptability allows the LDO circuit to provide stable power output under different operating conditions, enhancing the circuit's versatility and flexibility. This invention solves the transient response problem without significantly increasing power consumption or chip area. This is a significant advantage for mobile devices and other electronic devices with stringent power consumption and space requirements. By optimizing the circuit design, high performance can be maintained while extending battery life and reducing device size.

[0021] This invention helps extend the lifespan of circuits by reducing the damage to sensitive electronic components caused by output voltage fluctuations. This improved reliability is particularly important in applications requiring long-term stable operation, such as industrial control systems and medical devices. The LDO circuit of this invention can respond to load changes in real time, maintaining a stable output voltage by dynamically adjusting the load current.

[0022] In summary, the present invention has the following beneficial effects:

[0023] 1. The LDO circuit of this invention integrates dynamic load compensation, enabling real-time monitoring and response to changes in load current. This ability to dynamically adjust the load current significantly reduces voltage fluctuations caused by load current variations, thereby ensuring output voltage stability. Particularly when transient changes occur in the load current, this invention can quickly restore the output voltage to a stable state, reducing voltage recovery response time and thus improving circuit stability and reliability. This is especially important for high-performance electronic devices, which often need to switch rapidly between different operating modes without sacrificing power supply stability.

[0024] 2. This invention fully considers the trend of miniaturization and low power consumption in electronic devices. By optimizing the circuit design, this invention effectively solves the transient response problem without increasing power consumption and chip area excessively. This design not only helps reduce the energy consumption of electronic devices but also allows the LDO circuit to be integrated into a more compact space, meeting the stringent size and energy consumption requirements of modern electronic devices.

[0025] 3. This invention reduces the risk of damage to these components due to voltage stress by minimizing output voltage fluctuations, thereby extending the lifespan of the circuit. This is especially important for electronic devices that require stable operation over long periods, such as servers, industrial control systems, and medical devices, which have extremely high requirements for power supply stability and strict standards for equipment reliability and lifespan.

[0026] 4. The LDO circuit of this invention improves power management efficiency and reduces damage to sensitive electronic components by reducing voltage fluctuations, thereby enhancing the overall performance of the electronic system. In high-precision analog or radio frequency circuits, even minute voltage fluctuations can lead to signal distortion or increased noise. This invention reduces these problems by maintaining a stable output voltage, improving signal quality and overall system performance. Attached Figure Description

[0027] Figure 1 This is a diagram of the dynamic load compensation LDO circuit in Embodiment 1 of the present invention;

[0028] Figure 2This is a detailed LDO circuit diagram with dynamic load compensation circuit in Embodiment 1 of the present invention;

[0029] Figure 3 This is a circuit diagram of an alternative LDO with dynamic load compensation in Embodiment 2 of the present invention. Detailed Implementation

[0030] The following is in conjunction with the appendix Figure 1-3 The present invention will be described in further detail below.

[0031] Example 1: An LDO circuit with dynamic load compensation, as shown in the attached diagram. Figure 1 The circuit includes an error amplifier, a power transistor M1, a feedback circuit, and a dynamic load compensation circuit. The power transistor M1 is a P-type field-effect transistor.

[0032] In the dynamic load compensation LDO circuit of this invention, the feedback network is responsible for monitoring the circuit's output voltage VOUT in real time and accurately feeding it back to the error amplifier. Upon receiving this feedback signal, the error amplifier compares it with a pre-set reference voltage VREF. The reference voltage VREF is a stable reference value representing the ideal output voltage level. The error amplifier amplifies the error signal between the output voltage from the resistive feedback network and the constant input voltage provided by the bandgap reference. The error signal directly controls the turn-on voltage of the power transistor M1. If the output voltage VOUT deviates from the reference voltage VREF, the error signal adjusts the turn-on voltage of the power transistor M1 to fine-tune the output voltage back to the ideal reference level. This process forms a negative feedback regulation loop to maintain a constant ratio between the output voltage and the input reference voltage, ensuring the stability of the output voltage VOUT.

[0033] The calculation of the output voltage VOUT is relatively simple: it equals the input voltage VDD minus the turn-on voltage of power transistor M1. Therefore, by precisely controlling the turn-on voltage of power transistor M1, the output voltage VOUT of the LDO can be effectively controlled. In the entire negative feedback regulation loop, the two input voltages of the error amplifier: the acquisition voltage VFB (i.e., the feedback output voltage) and the reference voltage VREF must remain the same. Analysis shows that the output voltage is determined by the resistance ratio of the two resistors (R1 and R2), therefore the output voltage is:

[0034]

[0035] The negative input terminal (-) of the error amplifier is used to input the reference voltage VREF; the gate of the power transistor M1 is connected to the output terminal VG of the error amplifier, the source of the power transistor M1 is used to input the power supply voltage VDD, and the drain of the power transistor M1 is connected to the load Loading, so as to drive the load Loading with the output voltage VOUT; the feedback circuit is connected to the drain of the power transistor M1 and the positive input terminal (+) of the error amplifier.

[0036] Ideally, the output voltage VOUT of the LDO should be equal to the load current I. load The voltage remains constant and is irrelevant. However, in practice, the output voltage will be affected by the load current due to the equivalent resistance Ron of the power transistor M1. The relationship between the output voltage and the load current can be expressed by the following formula:

[0037] VOUT = V IN -I load ·R on

[0038] Where V IN It is the input voltage, I load Ron is the load current; Ron is the equivalent series resistance of power transistor M1.

[0039] The equivalent resistance Ron of power transistor M1 will affect the output voltage, especially when the load current changes:

[0040]

[0041] μ p It is hole mobility, C OX It is an oxide capacitor per unit area. It is the aspect ratio of power transistor M1, V gate1 It is the gate voltage of power transistor M1, V th This is the threshold voltage of power transistor M1.

[0042] In low-dropout linear regulator (LDO) circuits, the impact of load current fluctuations on output voltage stability is a critical issue. When the load current increases, the output voltage VOUT drops due to the limited on-resistance Ron of the power transistor M1, a phenomenon particularly pronounced under high load conditions. To effectively reduce the impact of load current variations on the output voltage, this invention proposes a dynamic load compensation circuit. This circuit is directly connected to the drain of the power transistor M1, and its main function is to monitor minute changes in the output voltage VOUT in real time. Once a fluctuation in the output voltage is detected, the dynamic load compensation circuit responds quickly by adjusting the drive current I0 output from the drain of the power transistor M1 to compensate for the change in load current. This adjustment increases the rate of change of the output voltage VOUT, thereby quickly stabilizing the output voltage and reducing voltage fluctuations. In this way, the dynamic load compensation circuit can effectively offset the output voltage drop caused by load current changes, maintaining the stability and reliability of the power supply output. This design not only improves the performance of the LDO circuit but also ensures that electronic devices can maintain a stable power supply when facing load changes, which is of great significance for improving the stability of the entire system and extending the lifespan of the equipment.

[0043] The aforementioned dynamic load compensation circuit includes a sensing circuit and a preload circuit, as shown in the attached diagram. Figure 2 As shown. The sensing circuit is used to sense the current of the power transistor M1. The preload circuit generates a preload current based on the sensed current of the power transistor M1, and adjusts the preload current according to the change of the output voltage VOUT, thereby adjusting the drive current to improve the rate of change of the output voltage VOUT.

[0044] In the dynamic load compensation LDO circuit of this invention, the key component of the sensing circuit is power transistor M2, which is a P-type field-effect transistor (PMOS). The gate of power transistor M2 is connected to the gate of power transistor M1, meaning they have the same voltage signal, allowing power transistor M2 to sense the current change through power transistor M1. The source of power transistor M2 receives the input power supply voltage VDD, while its drain is connected to the preload circuit. Power transistor M2 transmits the sensed current change to the preload circuit.

[0045] The preload circuit consists of N-type field-effect transistors (NMOS) M3, M4, M5, and M6 and capacitor C1. The drain of NMOS transistor M5 is directly connected to the drain of power transistor M2, while its source is connected to the drain of NMOS transistor M3, forming a current conduction path. The drain of NMOS transistor M6 is connected to the drain of power transistor M1 to sense the actual load current. Its source is connected to the drain of NMOS transistor M4, and its gate is connected to the gate of NMOS transistor M5. This configuration means that the gate voltage of M6 will change with the gate voltage of M5. The gates of both NMOS transistors M6 and M5 are connected to point VB, which is a bias control point used to adjust the gate voltages of M5 and M6, thereby precisely controlling the induced current.

[0046] With this design, when the current of power transistor M1 changes, power transistor M2 can sense these changes and transmit them through NMOS transistors M3 and M4 in the preload circuit. Since the gates of M5 and M6 are connected, the current transfer ratio between them can be precisely controlled by the bias voltage at point VB, allowing M2 to sense the current of M1 more accurately. This precise sensing capability is crucial for dynamic load compensation circuits, ensuring a rapid response to load changes and adjusting the output voltage VOUT accordingly to maintain power supply stability.

[0047] NMOS transistors M3 and M4 form a current mirror, which replicates the induced current of power transistor M2, thereby enabling dynamic adjustment of the load current. When the load current decreases, the output voltage VOUT increases. Capacitor C1 couples this voltage difference to the gates of NMOS transistors M3 and M4, causing the gate voltage of M4 to increase, thus increasing the current flowing through M4 and decreasing the output voltage VOUT. Conversely, when the load current increases, the output voltage VOUT decreases. Capacitor C1 couples this voltage difference to the gates of NMOS transistors M3 and M4, causing the gate voltage of M4 to decrease, thus reducing the current flowing through M4 and increasing the output voltage VOUT. This mechanism allows the LDO circuit to automatically adjust to adapt to load changes and maintain voltage stability.

[0048] During operation, since the gates of power transistors M1 and M2 are connected, and their sources are both connected to the power supply voltage VDD, power transistor M2 can sense the current in power transistor M1. The channel lengths of power transistors M1 and M2 are the same, L, and the width of power transistor M1 is K1 times that of power transistor M2 (K1 > 10). This identical length L allows the induced current to accurately replicate the current I induced by power transistor M2 in power transistor M1. M1 It is I of the current of power transistor M2 M2 K1 times, that is

[0049] I M1 =I M2 K1

[0050] The current I on power transistor M2 M2 The current flowing to NMOS transistor M5 also becomes I. M2 Right now

[0051] I M5 =I M2 =I M1 / K1

[0052] The gates of NMOS transistors M5 and M6 are controlled by the bias control point VB. The width-to-length ratio of NMOS transistor M6 is K2 (K2>10) times that of NMOS transistor M5. Therefore, the current of NMOS transistor M6 is:

[0053] I M6 =K2·I M5

[0054] The current I on NMOS transistor M5 M5 The current flows to NMOS transistor M3, causing the current I in NMOS transistor M3 to... M3 =I M5 =I M2 =I M1 / K1

[0055] Because the width-to-length ratio of NMOS transistor M4 is K3 times that of NMOS transistor M3 (K3>10), the preloaded load current is converted from the width-to-length ratio of NMOS transistors M3 and M4. In other words, NMOS transistor M4 mirrors the current of NMOS transistor M3, making the current of NMOS transistor M4 K3 times the current of NMOS transistor M3.

[0056] I M4 =I M3 ·K3

[0057] In the dynamic load compensation LDO circuit of this invention, capacitor C1 plays a crucial role. It rapidly adjusts the gate voltages of NMOS transistors M3 and M4 by coupling changes in the output voltage VOUT, thereby achieving a fast response to load changes. When the load decreases, i.e., the load current in the circuit decreases, this causes the output voltage VOUT to rise relatively. At this time, capacitor C1 senses this voltage change and couples it to the gates of NMOS transistors M3 and M4. As the gate voltage of M4 increases accordingly, the current flowing through NMOS transistor M4 increases accordingly. This increased current manifests as an additional load on the output voltage VOUT, effectively absorbing excess energy, thereby helping to reduce the excessively high output voltage VOUT and achieving a fast response to stabilize the voltage.

[0058] Conversely, when the load increases, i.e., the load current in the circuit increases, the output voltage VOUT will decrease relatively. Similarly, capacitor C1 senses this change and couples the voltage difference to the gates of NMOS transistors M3 and M4. At this time, the gate voltage of NMOS transistor M4 decreases, resulting in a reduction in the current flowing through M4. This reduced current manifests as a reduced load on the output voltage VOUT, thus providing the necessary energy replenishment to help boost the lowered output voltage VOUT, achieving a fast response to stabilize the voltage again. Capacitor C1 is used to couple changes in the output voltage, accelerating the response to load changes:

[0059] T = Rgate3,4·C1

[0060] Where R gate3,4 T represents the gate resistance of NMOS transistors M3 and M4, and T is the time constant. The time constant τ determines the speed at which the capacitor responds to load changes.

[0061] In this way, the load current can be adjusted according to the changes in the output drive voltage. On the one hand, it can respond in real time when the load voltage changes, adjusting the load current up or down to avoid affecting the performance of the load. On the other hand, by changing the load current in real time according to the changes in the induced voltage, the speed of change of the drive voltage is further improved, and a rapid response is achieved.

[0062] Example 2: The MOS transistor mentioned in Example 1 of this invention can also be a triode transistor, and its specific circuit diagram is attached. Figure 3 As shown, Q1 and Q2 are PNP type transistors, and Q3, Q4, Q5, and Q6 are NPN type transistors. Their working principle is similar to that described in Example 1.

[0063] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.

Claims

1. An LDO circuit with dynamic load compensation, characterized in that: This includes an error amplifier, power transistor M1, a feedback circuit, and a dynamic load compensation circuit. The power transistor M1 is a P-type field-effect transistor; the feedback circuit detects the output voltage and feeds the output voltage back to the error amplifier; the dynamic load compensation circuit is connected to the drain of the power transistor M1 to sense changes in the output voltage VOUT and adjusts the drive current I0 output from the drain of the power transistor M1 according to the changes in the output voltage VOUT. The dynamic load compensation circuit includes a sensing circuit and a preloading circuit. The sensing circuit is used to sense the current of the power transistor M1; The preload circuit generates a preload current based on the current sensed by the power transistor M1, and adjusts the preload current according to the change in the output voltage VOUT, thereby adjusting the drive current. The sensing circuit includes a power transistor M2, which is a P-type field-effect transistor. The gate of the power transistor M2 is connected to the gate of the power transistor M1, and the channel lengths of the power transistors M1 and M2 are the same, L. The width W of the power transistor M1 is K1 times the width W of the power transistor M2. The preload circuit includes NMOS transistors M3, M4, M5, and M6, and capacitor C1, wherein: The drain of NMOS transistor M5 is connected to the drain of power transistor M2, and the source of NMOS transistor M5 is connected to the drain of NMOS transistor M3. The drain of NMOS transistor M6 is connected to the drain of power transistor M1, the source of NMOS transistor M6 is connected to the drain of NMOS transistor M4, and the gate of NMOS transistor M6 is connected to the gate of NMOS transistor M5. The gates of NMOS transistor M6 and NMOS transistor M5 are connected at point VB, which is the bias control point. The aspect ratio of the NMOS transistor M6 is K2 times that of the NMOS transistor M5, and the aspect ratio of the NMOS transistor M4 is K3 times that of the NMOS transistor M3, wherein K1, K2, and K3 > 10. The source of the power transistor M2 is used to input the power supply voltage VDD, and the drain of the power transistor M2 is connected to the preload circuit.

2. The LDO circuit with dynamic load compensation according to claim 1, characterized in that: when When the load decreases, the output voltage VOUT increases. This voltage difference is coupled to the gates of NMOS transistors M3 and M4 via capacitor C1, which increases the gate voltage of NMOS transistor M4 and the current flowing through NMOS transistor M4, thereby reducing the output voltage VOUT.

3. The LDO circuit with dynamic load compensation according to claim 1, characterized in that: when When the load increases, the output voltage VOUT decreases. This voltage difference is coupled to the gates of NMOS transistors M3 and M4 via capacitor C1, which reduces the gate voltage of NMOS transistor M4 and decreases the current flowing through NMOS transistor M4, thereby increasing the output voltage VOUT.

4. An electronic device using an LDO circuit with dynamic load compensation as described in any one of claims 1 to 3, characterized in that: The electronic device includes at least a microprocessor, analog circuit, or radio frequency circuit, and the LDO circuit with dynamic load compensation provides a stable power supply for the electronic device.

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