A high-speed processing system and method based on a heterogeneous processing architecture

Abstract

This application discloses a high-speed processing system and method based on a heterogeneous processing architecture, relating to the field of computer data processing technology. The system includes a parser, a match-operation pipeline, and an inverse parser. The match-operation pipeline comprises multiple core modules, including an input arbitration unit, a packet processing unit, and an output buffer unit connected via an AXI bus. This application enables the system to seamlessly connect with user P4 program requirements and final processing result feedback through the collaborative work of the parser and inverse parser, improving the system's usability and compatibility. Through the polling processing method of the input arbitration unit in the core modules, the precise operation of the packet processing unit based on configuration information, and the ordered output control of the output queue unit, the system effectively reduces data packet processing latency, improves network transmission efficiency, and can flexibly handle various complex P4 program processing logics, exhibiting strong adaptability and scalability.

Description

Technical Field

[0001] This application relates to the field of computer data processing technology, and in particular to a high-speed processing system and method based on a heterogeneous processing architecture. Background Technology

[0002] The growth of network traffic and increasingly complex network applications are driving the continuous development of new network architectures. SDN architecture, with its separation of the data plane and control plane, and its ability to centralize the data plane through software programming of the control plane, achieves programmability on the control plane, effectively solving the shortcomings of traditional network devices with fixed functions.

[0003] However, the programmability of existing SDN technology is currently limited to the network control plane. The forwarding protocols and packet forwarding processing logic that the data plane can support are still mainly determined by the fixed functions of the switching equipment. The programmability of the data plane is still largely constrained by the fixed functions of the packet processing hardware. Summary of the Invention

[0004] This application provides a high-speed processing system and method based on a heterogeneous processing architecture, which overcomes the shortcomings of the prior art. By deploying the P4 program on a specific hardware platform, this application extends the programmability of the network to the data plane, providing a new solution for fully programmable network devices.

[0005] The first aspect of this application provides a high-speed processing system based on a heterogeneous processing architecture. The system includes: a parser, a matching-operation pipeline, and an inverse parser. The parser compiles a user-submitted P4 program into configuration information within the matching-operation pipeline. The matching-operation pipeline performs header matching and operation pipeline execution on the input data packet based on the configuration information to obtain processed data. The inverse parser reassembles the processed data and converts it into P4 return data format, returning it to the user.

[0006] The matching-operation pipeline includes multiple core modules, which include an input arbitration unit, a packet processing unit, and an output buffer unit connected via an AXI bus.

[0007] The input arbitration unit is used to process the input data packets in a polling manner, obtain valid message data, and send it to the packet processing unit.

[0008] The packet processing unit is used to process the valid message data according to the configuration information, obtain the processed data packet, and send it to the output queue unit.

[0009] The output queue unit is used to transmit the processed data packet to the output terminal via the AXI bus.

[0010] In an optional embodiment, the configuration information is configuration information for a user-defined packet processing function.

[0011] In an optional embodiment, each core module has an input port corresponding to multiple core modules, and the input port includes at least two network ports and at least one DMA interface, both of which are connected to a match-operation pipe.

[0012] In an optional embodiment, the input arbitration unit includes:

[0013] The analysis subunit is used to acquire and analyze input data packets using a polling method to obtain address location information and target data; the address location information is the address information of the output port of the target information.

[0014] The processing subunit processes the target data based on the address location information to obtain valid message data.

[0015] In an optional embodiment, the packet processing unit includes:

[0016] A configuration subunit is used to process the valid message data according to the configuration information to obtain a processed data packet;

[0017] The lookup subunit is used to search the routing table based on the specific address and destination address of the valid message data to obtain the lookup result.

[0018] The output subunit is used to generate corresponding output queue selection information based on the search result and send the search result to the output queue unit based on the output queue selection information.

[0019] In an optional embodiment, the output queue unit includes multiple output queues, each consisting of a buffer and read / write pointers, for caching processed data packets and outputting them in a first-in-first-out order based on the lookup result.

[0020] According to a second aspect of this embodiment, a high-speed processing method based on a heterogeneous processing architecture is provided, based on the high-speed processing implementation based on a heterogeneous processing architecture provided in the first aspect of this application. The method includes:

[0021] Compile the P4 program submitted by the user to obtain the configuration information of the matching-operation pipeline;

[0022] Based on the configuration information, header matching and operation pipeline execution are performed on the input data packets to obtain processed data.

[0023] The processed data is reorganized and converted into P4 return data format and returned to the user.

[0024] In an optional embodiment, the processed data obtained by performing header matching and operation pipeline execution on the input data packet based on the configuration information includes:

[0025] The input data packets are processed using a polling method to obtain valid message data;

[0026] The valid message data is processed according to the configuration information to obtain the processed data packet.

[0027] In an optional embodiment, the step of processing the input data packets using a polling method to obtain valid message data includes:

[0028] The input data packets are obtained and analyzed using a polling method to obtain address location information and target data. The address location information is the address information of the output port of the target information.

[0029] The target data is processed based on the address location information to obtain valid message data.

[0030] In an optional embodiment, the step of processing the valid message data according to the configuration information to obtain the processed data packet includes:

[0031] The valid message data is processed according to the configuration information to obtain the processed data packet;

[0032] The routing table is consulted based on the specific address and destination address of the valid message data to obtain the lookup result.

[0033] Based on the search results, corresponding output queue selection information is generated, and based on the search results, processed data packets are generated.

[0034] This application provides an optional high-speed processing system and method based on a heterogeneous processing architecture. The system includes a parser, a matching-operation pipeline, and an inverse parser. The parser compiles user-submitted P4 programs into configuration information within the matching-operation pipeline. The matching-operation pipeline performs header matching and pipelined operation on input data packets based on the configuration information to obtain processed data. The inverse parser reassembles the processed data and converts it into P4 return data format, returning it to the user. The matching-operation pipeline includes multiple core modules, including an input arbitration unit, a packet processing unit, and an output buffer unit connected via an AXI bus. The existence of the parser and inverse parser proposed in this invention enables the system to achieve high interactivity and compatibility with the user's P4 program. Users can flexibly customize the data packet processing logic according to their needs, accurately execute and return results. Furthermore, the design of the core modules in the matching-operation pipeline, especially the close cooperation and fine division of labor between the input arbitration unit, packet processing unit, and output queue unit, greatly improves the system's processing efficiency and accuracy of data packets. The polling analysis and processing mechanism of the input arbitration unit can effectively handle multi-source data packet input, the flexible processing capability of the packet processing unit based on configuration information can meet various complex network processing needs, and the ordered buffering and output control of the output queue unit ensures the stability and reliability of the system output.

[0035] Furthermore, the parallel processing capabilities of multiple core modules and the high-speed data transmission characteristics of the AXI bus enable the system to perform exceptionally well in large-scale network data processing scenarios, effectively improving the performance and response speed of the entire network system and providing strong technical support for the development of modern network technology. Attached Figure Description

[0036] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0037] Figure 1 A schematic diagram of the structure of an optional high-speed processing system based on a heterogeneous processing architecture, provided for an embodiment of this application;

[0038] Figure 2 This is a flowchart illustrating a high-speed processing method based on a heterogeneous processing architecture, provided in an embodiment of this application. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0040] The prior art involved in this invention will be briefly described below.

[0041] Software Defined Networking (SDN) is a novel network architecture. Compared to traditional network device architectures, its most significant feature is the separation of the data plane and control plane. SDN centralizes the control plane and makes it software-programmable, allowing network administrators to dynamically control network behavior through software programming. This improves network management flexibility while reducing development complexity. Furthermore, SDN is scalable, allowing users to control the behavior of network devices in the data plane via programming interfaces on the control plane. This enables the implementation of various customized network functions to meet diverse network application needs. These features allow the SDN architecture to monitor the entire network status at any time, easily define network functions, and enable users to dynamically configure network processing logic as needed.

[0042] OpenFlow is currently the most widely used protocol architecture in SDN technology. OpenFlow uses flow tables and predefined actions to implement packet processing logic and provides the control plane with configuration capabilities for these flow tables and actions using a standardized set of interfaces. Building upon SDN, OpenFlow integrates the network's control plane into a centralized controller. After acquiring high-level network-wide policy logic, the controller compiles these policies using the abstract configuration capabilities provided by the data plane and finally configures them to various data plane devices via flow tables, thereby controlling and managing the packet forwarding behavior of the underlying switching devices and achieving centralized management and control of all underlying switching devices in the network. The data plane consists of switches and routers, and its main function is to process packets according to the flow table rules sent by the controller. Data plane devices only need to obtain these policies from the control plane through interfaces and do not need to implement the specific packet forwarding logic. OpenFlow formally promoted the separation of the data plane and control plane, enabling the data plane to develop towards high programmability and easy reconfiguration. Its architecture of separating the data plane and control plane greatly enhances the programmability of the network.

[0043] However, the programmability of existing SDN technologies is limited to the network control plane. The forwarding protocols and packet forwarding processing logic that the data plane can support are still mainly determined by the fixed functions of the switching equipment. The programmability of the data plane is largely constrained by the fixed functions of the packet processing hardware.

[0044] The P4 language enables programmability of the data plane due to its protocol independence. Unlike SDN, which primarily programs the control plane, P4 is designed for programming the data plane or partially defining the interface between the control and data planes; it cannot be used to define control plane functionality. The SDN-P4 combination enables fully programmable packet processing in network devices, offering significant application value and broad research potential for improving network service capabilities and enhancing user experience.

[0045] However, the programmability of existing SDN technologies is currently limited to the network control plane. The forwarding protocols and packet forwarding processing logic supported by the data plane are still mainly determined by the fixed functions of the switching equipment. The programmability of the data plane is still largely constrained by the fixed-function packet processing hardware. Therefore, this application proposes a high-speed processing system based on a heterogeneous processing architecture to address this situation.

[0046] Figure 1 This is a schematic diagram of an optional high-speed processing system based on a heterogeneous processing architecture, according to an embodiment of this application. Figure 1 As shown, the system includes: a parser, a matching-operation pipeline, and an inverse parser. The parser is used to compile the P4 program submitted by the user into configuration information within the matching-operation pipeline. The matching-operation pipeline is used to perform header matching on the input data packet based on the configuration information and to execute the operation pipeline to obtain processed data. The inverse parser is used to reassemble the processed data and convert it into P4 return data format to return to the user.

[0047] The matching-operation pipeline includes multiple core modules, which include an input arbitration unit, a packet processing unit, and an output buffer unit connected via an AXI bus.

[0048] An input arbitration unit is used to process input data packets using a polling method, obtain valid message data, and send it to the packet processing unit.

[0049] The packet processing unit is used to process valid message data according to configuration information, obtain processed data packets, and send them to the output queue unit.

[0050] The output queue unit is used to transmit the processed data packets to the output terminal via the AXI bus.

[0051] Specifically, the parser plays a crucial role in compiling user-submitted P4 programs into configuration information for the match-action pipeline. For example, when a user inputs specific P4 program code that describes a series of processing rules and logic for data packets, the parser performs in-depth parsing and compilation. It identifies header field definitions, matching condition settings, and corresponding operation instructions in the P4 program, and transforms this information into configuration information that the match-action pipeline can understand and execute. This configuration information consists of user-defined data packet processing function configurations.

[0052] The matching-operation pipeline contains multiple core modules, each of which is connected to the input arbitration unit, packet processing unit, and output buffer unit via the AXI bus.

[0053] The input arbitration unit processes input data packets using a polling method. Assuming the system receives data packet streams from multiple different sources, the input arbitration unit checks each packet sequentially according to a predetermined polling order. For example, in an input stream containing packets A, B, and C, it first checks packet A to determine if it is a valid message. If packet A is correctly formatted, complete, and meets the system's initial reception conditions, it is identified as valid and sent to the packet processing unit. Then, packets B and C are processed using the same polling method, ensuring that each packet has a chance to be processed promptly and avoiding processing delays caused by a single packet waiting for an extended period.

[0054] The packet processing unit processes valid packet data based on the configuration information generated by the parser. Taking a network packet processing scenario as an example, the configuration information specifies the matching rules for specific header fields (such as source IP address, destination IP address, port number, etc.) and the corresponding operations (such as modifying certain header fields, forwarding packets to specific ports, etc.). When the packet processing unit receives valid packet data from the input arbitration unit, it performs an exact match on the packet header according to the matching rules in the configuration information. If the source IP address of the packet matches a specific range of conditions, the packet processing unit will perform the corresponding operation, such as modifying the destination port number of the packet to a new value, thereby obtaining the processed packet and sending it to the output queue unit.

[0055] The output queue unit is primarily responsible for transmitting processed data packets to the output terminal via the AXI bus. The output queue unit briefly buffers and sorts the processed data packets to ensure they are transmitted to the output terminal in the correct order. For example, in a high-traffic data center network where multiple core modules process a large number of data packets simultaneously, the output queue unit can coordinate the output order of these packets, avoiding data corruption and conflicts, and ensuring the stability and reliability of the entire system's output.

[0056] The reverse parser is responsible for reassembling the message data processed by the match-operation pipeline and converting it into P4 return data format before returning it to the user. After a series of complex processing steps, the data structure and content of the data packets may have undergone significant changes. The reverse parser will reorganize the processed data packets into a format that conforms to the P4 program output specifications according to pre-defined rules and data format requirements. For example, if the packet header is modified or additional processing information is added during the match-operation pipeline, the reverse parser will extract this key information and integrate it into the P4 return data, so that the user can clearly understand the data packet processing process and results, facilitating the user's monitoring and analysis of the system's operating status.

[0057] Through the detailed description of the above embodiments, it is clear that this high-speed processing system based on a heterogeneous processing architecture has many advantages. First, the collaborative work of the parser and inverse parser enables the system to seamlessly connect with the user's P4 program requirements and the final processing result feedback, improving the system's ease of use and compatibility. Second, the core module design in the matching-operation pipeline, especially the polling processing method of the input arbitration unit, the precise operation of the packet processing unit based on configuration information, and the ordered output control of the output queue unit, greatly improves the system's data packet processing speed and accuracy. In large-scale network data processing scenarios, it can effectively reduce data packet processing latency, improve network transmission efficiency, and flexibly handle various complex P4 program processing logics, exhibiting strong adaptability and scalability.

[0058] Based on the above embodiments, as an optional embodiment, in the high-speed processing system based on heterogeneous processing architecture provided by the present invention, each core module's input port corresponds to multiple core modules. The input port includes at least two network ports and at least one DMA interface, and both the network ports and the DMA interface are connected to a match-operation pipeline.

[0059] Based on the above embodiments, as an optional embodiment, the input arbitration unit in the high-speed processing system based on a heterogeneous processing architecture provided by the present invention includes:

[0060] The analysis subunit is used to acquire and analyze input data packets using a polling method to obtain address location information and target data; the address location information is the address information of the output port of the target information.

[0061] The processing subunit processes the target data based on the address location information to obtain valid message data.

[0062] Specifically, when multiple data sources simultaneously input data packets into the system, the analysis subunit sequentially acquires the input data packets using a polling method. For example, in a data center network, data packets may be transmitted from different network ports or via a DMA interface. The analysis subunit performs detailed analysis on the acquired data packets to determine the output port address information (address location information) of their target information and the target data within the data packets. For instance, in a network traffic monitoring system, the analysis subunit identifies key information such as the source IP address and destination IP address in the data packets and determines which subsequent processing stage or output port these data packets should be directed to.

[0063] After obtaining the address location information, the processing subunit further processes the target data based on this information to extract valid message data. For example, if the data packet format conforms to the system's pre-defined standards and the data integrity is confirmed, the processing subunit will organize it into valid message data and send it to the packet processing unit. During processing, the processing subunit may also perform some preliminary verification and preprocessing operations on the data packet, such as checking whether the data packet checksum is correct and removing redundant information from the data packet, to improve the efficiency and accuracy of subsequent processing.

[0064] Based on the above embodiments, as an optional embodiment, the packet processing unit in the high-speed processing system based on a heterogeneous processing architecture provided by the present invention includes:

[0065] A configuration subunit is used to process the valid message data according to the configuration information to obtain a processed data packet;

[0066] The lookup subunit is used to search the routing table based on the specific address and destination address of the valid message data to obtain the lookup result.

[0067] The output subunit is used to generate corresponding output queue selection information based on the search result and send the search result to the output queue unit based on the output queue selection information.

[0068] Specifically, valid packet data is processed based on the configuration information generated by the parser. After receiving valid packet data, the configuration subunit checks whether the source IP address of the data packet is within the interception range. If it is, the data packet is intercepted accordingly, such as being marked as an illegal data packet and having relevant information recorded. If not, the corresponding configuration operation is performed according to the user-defined data packet processing function to generate a processed data packet.

[0069] To determine the forwarding path of a data packet, the lookup subunit searches the routing table based on the specific address and destination address of the valid message data. The routing table records the connectivity relationships and forwarding rules between different network segments. The lookup subunit searches the routing table for an entry that matches the destination address of the data packet, obtaining the lookup result. This lookup result determines which output queue unit the data packet should be sent to next.

[0070] Based on the search results, corresponding output queue selection information is generated, and the search results are sent to the output queue unit. For example, if the search results indicate that the data packet should be forwarded to a specific area in the network, the output subunit will select the corresponding output queue and send the data packet and its related information to that queue for subsequent output operations.

[0071] Based on the above embodiments, as an optional embodiment, in the high-speed processing system based on heterogeneous processing architecture provided by the present invention, the output queue unit includes multiple output queues, each output queue consisting of a buffer and read / write pointers, used to cache processed data packets and output them in a first-in-first-out order based on the search results.

[0072] Specifically, the output queue unit contains multiple output queues, each consisting of a buffer and read / write pointers. When a processed data packet is sent to the output queue unit, it is cached in the corresponding output queue buffer based on the lookup result. For example, in a network traffic load balancing system, different types of data packets (such as video traffic, voice traffic, and data traffic) are assigned to different output queues. These output queues output data in a first-in, first-out (FIFO) order, and the read / write pointers are used to precisely control the read and write operations of data packets, ensuring that data packets are sent out from the output end in an orderly manner, avoiding data corruption and conflicts.

[0073] In summary, the existence of the parser and inverse parser enables the system to achieve high interactivity and compatibility with the user's P4 program. Users can flexibly customize the packet processing logic according to their own needs, and the system can accurately execute and return the results. Secondly, the design of the core modules in the matching-operation pipeline, especially the close cooperation and fine division of labor among the input arbitration unit, packet processing unit, and output queue unit, greatly improves the system's efficiency and accuracy in processing packets. The polling analysis and processing mechanism of the input arbitration unit can effectively handle multi-source packet input, the flexible processing capability of the packet processing unit based on configuration information can meet various complex network processing needs, and the ordered buffering and output control of the output queue unit ensures the stability and reliability of the system output. In addition, the parallel processing capability of multiple core modules and the high-speed data transmission characteristics of the AXI bus enable the system to perform excellently in large-scale network data processing scenarios, effectively improving the performance and response speed of the entire network system, and providing strong technical support for the development of modern network technology.

[0074] The invention will now be described using a specific embodiment.

[0075] This invention provides a high-speed processing system based on a heterogeneous processing architecture, comprising a parser, a match-operation pipeline, and an inverse parser. The parser compiles user-submitted P4 programs into configuration information within the match-operation pipeline; the match-operation pipeline performs header matching on input data packets based on the configuration information and executes the operation pipeline to obtain processed data; the inverse parser reassembles the processed data and converts it into P4 return data format, returning it to the user.

[0076] Specifically, the hardware system design utilizes the IP integration design tools provided by the Vivado integrated development environment. The IP integrator allows users to call and configure IP cores provided in the Xilinx IP library, and also allows users to package their own HDL source code into IP cores and place them in the IP Catalog for use as custom-packaged IPs. System design is completed by adding the required IP cores to the IP integration design interface and connecting them to the corresponding interfaces. After the system design is completed, it needs to be synthesized into a netlist, placed and routed, and constraint files added. Finally, a bitstream file for configuring the FPGA is generated.

[0077] The parser designed for the P4 language uses 256 bits for the data path width and 128 bits for the metadata width, with the system operating at a frequency of 200MHz. The theoretical throughput of the data processing module is 256 bits × 200MHz, or 51.2Gbps, which theoretically meets the goal of achieving a total system throughput of 40Gbps across four 10Gbps Ethernet ports proposed in this invention. While the theoretical maximum rate does not directly translate into actual system performance, appropriate pipelining optimizations, such as pipelining the control flow, matching table, and operation engine, can improve system performance to some extent.

[0078] The clock in the data path is provided by a clock module with a frequency of 200MHz. The width of the received header data is the same as the width of the AXI bus, which is 256 bits. In addition to the header data, each module uses the TUSER signal in the AXI-Stream bus to carry up to 128 bits of metadata (sume_metadata) to transmit information between modules.

[0079] In the data processing plane, data packets enter through four network ports. The receiving end assigns input information to the TUSER signal based on the different input ports of these data packets. The input arbitration unit processes the input data packets in the FIFO queue and transmits the valid header data in the FIFO queue to the packet processing unit.

[0080] The packet processing unit processes the data packets according to the user-defined packet processing functions. The processed data packets are then sent to the output queue unit for buffering. After receiving the incoming data, the output queue unit transmits the data packets to be output to the FIFO buffer at the output end via the AXI bus, and finally outputs them from the circuit through the output end.

[0081] The following section describes the functions of each module in the system:

[0082] In this embodiment, four SFP 10Gb / s ports are used to receive data. Theoretically, a transmission rate of 40Gb / s can be achieved. The receiver (RX) consists of four interfaces responsible for receiving network data from the network port and one DMA interface responsible for receiving host data. Each of the five ports has a buffer FIFO, which buffers the received data packets before sending them to the next module.

[0083] Since the AXKU041 development board only has two SFP+ fiber optic interfaces, this embodiment uses an Alinx FMC to four-way SFP fiber optic module to expand the AXKU041 development board to four available network ports. This module can expand the SFP, where each SFP is connected to the transceiver pins by a set of TX and a set of RX, and can support a data transmission rate of 10Gb / s.

[0084] The input arbitration unit processes data packets using a polling method and selects the output port, ultimately outputting the data packets transmitted from the four network ports in turn to the next circuit module for processing.

[0085] The packet processing unit is compiled using the Xilinx-developed P4_SDNet tool, tailored to the specific P4 application. Its function is to forward data packets according to a preset algorithm, making it the core module of the system. In actual use, the P4-defined data plane is compiled into an HDL module with a standard AXI bus interface and loaded into the system to implement the P4 application's functionality.

[0086] The output queue unit is responsible for buffering the data packets processed by the previous module into different output queues according to the destination port in the packet header and then sending them.

[0087] The sending end TX retrieves the data that has been processed by the previous module and sends it to the corresponding port.

[0088] The following section provides a detailed analysis of some modules.

[0089] 1) Input Arbitration Unit

[0090] The receiving module, consisting of MAC RX0 to MAC RX3 and DMA RX, converts the data packets obtained from the network port and the computer's DMA module into a 256-bit AXI4-Stream data stream and sends it to the input arbitration unit.

[0091] The arbitration module's output interface uses a 4-channel AXI_Stream bus to receive input data packets from four network ports, and simultaneously receives data packets from the computer via a DMA channel through a 1-channel AXI_Stream bus. The AXI_Stream streams output from each Ethernet controller, upon entering the arbitration module, are first buffered in their respective FIFO queues, and then the valid header data is retrieved from each queue through a loop.

[0092] 2) Packet processing unit

[0093] The packet processing unit is compiled from the P4 program into HDL source code, and its function is to implement user-defined data plane functions. The implementation of this part requires setting the P4-SDNet compilation parameters according to the actual hardware resources. Similar to the input arbitration unit, the input and output of this module are connected by an AXI4-Stream bus with a bit width of 256 bits, responsible for receiving data packets and DMA channel data from the input arbitration unit.

[0094] After completing the design of the P4 source code, it can be compiled into HDL files using P4-SDNet. The compilation process first converts the P4 files into PX files, and then the PX files into HDL files.

[0095] This command allows you to specify the input / output types and bus width of the generated module. After successful compilation, the generated HDL code is packaged into an IP core, which can then be used in the Vivado tool.

[0096] The HDL program is encapsulated by running a tcl script file, and the encapsulated IP core can be added to Vivado's IP library for use.

[0097] 3) Output queue unit

[0098] The output queue unit is clocked at 200MHz and has a data width of 256 bits. This unit receives signals from the packet processing unit, then, based on the output port of the processed data packet, buffers the processed data packet generated by the packet processing unit into the corresponding output queue, and finally transmits it to the sending modules including MAC TX0 to MAC TX3 and DMA TX. The sending module converts the 256-bit AXI4-Stream data stream into Ethernet data packets and sends them to the network port and the computer's DMA module. In addition to the parameters of the data packet itself, the `sume_metadata` passed from the previous module to this module also contains relevant information about the corresponding data packet processing, which can be used as a basis for determining the execution of the corresponding data packet processing operation.

[0099] Based on the same inventive concept, one embodiment of this application provides a high-speed processing method based on a heterogeneous processing architecture. (Reference) Figure 2 , Figure 2 This is a flowchart illustrating a high-speed processing method based on a heterogeneous processing architecture, proposed in an embodiment of this application. Based on the first aspect of this application, the method, which implements high-speed processing based on a heterogeneous processing architecture, includes:

[0100] S102: Compile the P4 program submitted by the user to obtain the configuration information of the matching-operation pipeline;

[0101] S104: Based on the configuration information, perform header matching and operation pipeline execution on the input data packet to obtain processed data;

[0102] S106: Reassemble the processed data and convert it into P4 return data format to return it to the user.

[0103] Furthermore, based on the configuration information, the input data packet is subjected to header matching and the operation pipeline is executed to obtain the processed data, which includes:

[0104] The input data packets are processed using a polling method to obtain valid message data;

[0105] The valid message data is processed according to the configuration information to obtain the processed data packet.

[0106] Furthermore, the process of processing the input data packets using a polling method to obtain valid message data includes:

[0107] The input data packets are obtained and analyzed using a polling method to obtain address location information and target data. The address location information is the address information of the output port of the target information.

[0108] The target data is processed based on the address location information to obtain valid message data.

[0109] Furthermore, the process of processing the valid message data according to the configuration information to obtain the processed data packet includes:

[0110] The valid message data is processed according to the configuration information to obtain the processed data packet;

[0111] The routing table is consulted based on the specific address and destination address of the valid message data to obtain the lookup result.

[0112] Based on the search results, corresponding output queue selection information is generated, and based on the search results, processed data packets are generated.

[0113] It should be noted that the high-speed processing method of the heterogeneous processing architecture provided in the embodiments of the present invention is based on the high-speed processing implementation of the heterogeneous processing architecture provided in the first aspect of the embodiments of this application during actual operation, and will not be described in detail in this embodiment.

[0114] In practice, the above modules can be implemented as independent entities or combined in any way to be implemented as the same or several entities. For the specific implementation of the above modules, please refer to the previous method implementation examples, which will not be repeated here.

[0115] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by instructions, or by instructions controlling related hardware. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor. Therefore, embodiments of the present invention provide a storage medium storing multiple instructions that can be loaded by a processor to execute the steps of any embodiment of the file processing method provided by the present invention.

[0116] The computer-readable storage medium may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0117] Since the instructions stored in the storage medium can execute the steps in any embodiment of the file processing method provided in the embodiments of the present invention, the beneficial effects that any file processing method provided in the embodiments of the present invention can achieve can be realized. For details, please refer to the previous embodiments, which will not be repeated here.

[0118] The foregoing has provided a detailed description of a file processing method, apparatus, storage medium, and electronic device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A high-speed processing system based on a heterogeneous processing architecture, characterized in that, include: A parser, a match-operation pipeline, and an inverse parser, wherein the parser is used to compile user-submitted P4 programs into configuration information within the match-operation pipeline; The matching-operation pipeline is used to perform header matching and operation pipeline execution on the input data packet based on the configuration information to obtain processed data; the reverse parser is used to reassemble the processed data and convert it into P4 return data format to return to the user. The matching-operation pipeline includes multiple core modules configured in parallel, which process a large number of data packets simultaneously. Each core module has an input port corresponding to multiple core modules, and the input port includes at least two network ports and at least one DMA interface. Both the network ports and the DMA interface are connected to the matching-operation pipeline. Each core module includes an input arbitration unit, a packet processing unit, and an output buffer unit connected via an AXI bus. Each module uses the TUSER signal in the AXI-Stream bus to carry metadata and transmit information between modules. The metadata serves as the basis for determining whether to perform data packet processing operations. The input arbitration unit is used to process the input data packet using a polling method to obtain valid message data and send it to the packet processing unit; the packet processing unit is used to process the valid message data according to the configuration information to obtain the processed data packet and send it to the output queue unit; the output queue unit is used to transmit the processed data packet to the output end through the AXI bus. The packet processing unit includes: a configuration subunit, used to process the valid message data according to the configuration information to obtain a processed data packet; a lookup subunit, used to look up the routing table according to the specific address and destination address of the valid message data to obtain a lookup result; and an output subunit, used to generate corresponding output queue selection information based on the lookup result and send the lookup result to the output queue unit based on the output queue selection information. The output queue unit includes multiple output queues, each output queue consisting of a buffer and read / write pointers, used to cache the processed data packets and output them in a first-in-first-out order based on the lookup result.

2. The high-speed processing system based on a heterogeneous processing architecture according to claim 1, characterized in that, The configuration information refers to the configuration information for user-defined data packet processing functions.

3. The high-speed processing system based on a heterogeneous processing architecture according to claim 1, characterized in that, The input arbitration unit includes: The analysis subunit is used to acquire and analyze input data packets using a polling method to obtain address location information and target data; the address location information is the address information of the output port of the target information. The processing subunit processes the target data based on the address location information to obtain valid message data.

4. A high-speed processing method based on a heterogeneous processing architecture, the method being implemented based on the system described in any one of claims 1 to 3, comprising: Compile the P4 program submitted by the user to obtain the configuration information of the matching-operation pipeline; Based on the configuration information, header matching and operation pipeline execution are performed on the input data packets to obtain processed data. The processed data is reorganized and converted into P4 return data format and returned to the user. The process of processing the valid message data according to the configuration information to obtain the processed data packet includes: The valid message data is processed according to the configuration information to obtain the processed data packet; The routing table is consulted based on the specific address and destination address of the valid message data to obtain the lookup result. Based on the search results, corresponding output queue selection information is generated, and based on the search results, processed data packets are generated.

5. The high-speed processing method based on a heterogeneous processing architecture according to claim 4, characterized in that, The processed data obtained by performing header matching and pipelined operation on the input data packet based on the configuration information includes: The input data packets are processed using a polling method to obtain valid message data; The valid message data is processed according to the configuration information to obtain the processed data packet.

6. The high-speed processing method based on a heterogeneous processing architecture according to claim 5, characterized in that, The process of processing input data packets using a polling method to obtain valid message data includes: The input data packets are obtained and analyzed using a polling method to obtain address location information and target data. The address location information is the address information of the output port of the target information. The target data is processed based on the address location information to obtain valid message data.

Images