Chip package structure and electronic device

Abstract

This application discloses a chip packaging structure and electronic device, belonging to the field of semiconductor technology, including a packaging substrate, an adapter board, and multiple chips. The adapter board includes a base layer, multiple capacitors, and multiple differential signal lines, with the capacitors embedded in the base layer. In the technical solution of this application, the capacitors are directly formed on the adapter board, and a capacitor is connected in series in each differential signal line of a pair between two chips. This allows the two chips to bypass the limitations of DDR or UCIE interfaces to achieve interconnection and communication, and avoids the need to additionally configure surface-mount capacitors within the chip packaging structure. This saves the area of ​​the packaging substrate and avoids the incompatibility problem between the surface-mount capacitor mounting process and the chip packaging structure mounting process, reducing costs and achieving higher integration, which is beneficial to improving yield.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a chip packaging structure and electronic device. Background Technology

[0002] With the development of artificial intelligence and high-performance computing, the demands on chip computing power are increasing, and chip functions are becoming more complex. Currently, the main mass-production chip packaging solution in the field of AI high-performance chips is 2.5D packaging technology. This packaging solution ensures system integration, allows the use of high-performance chips with advanced process nodes, and solves the yield reduction problem caused by larger chip size. Under this packaging structure, the communication interfaces between chips are mostly high-density parallel signal interfaces such as DDR or UCIE.

[0003] However, the application of DDR interfaces is limited by domestic manufacturing capabilities. Furthermore, there is no mature UCIE interface standard protocol in China. How to solve the communication interface connection problem between chips has become an urgent problem to be solved in this field. Summary of the Invention

[0004] This application discloses a chip packaging structure, including a packaging substrate, an adapter board, and multiple chips. The adapter board is disposed on and electrically connected to the packaging substrate. Multiple chips are disposed on the side of the adapter board away from the packaging substrate. The adapter board includes a base layer, multiple capacitors, and multiple differential signal lines. The base layer includes a first surface away from the packaging substrate, and the multiple capacitors are embedded within the first surface. The multiple capacitors include a first capacitor and a second capacitor. The multiple differential signal lines are disposed on the side of the base layer away from the packaging substrate. These multiple differential signal lines include a first differential signal line, a second differential signal line, a third differential signal line, and a fourth differential signal line. The first differential signal line is electrically connected to one electrode of the first capacitor, the second differential signal line is electrically connected to the other electrode of the first capacitor, the third differential signal line is electrically connected to one electrode of the second capacitor, and the fourth differential signal line is electrically connected to the other electrode of the second capacitor. The multiple chips include a first chip and a second chip. The first chip has a first interface, and the second chip has a second interface. The first interface is electrically connected to a first differential signal line and a third differential signal line, and the second interface is electrically connected to a second differential signal line and a fourth differential signal line.

[0005] In some embodiments, the first chip and the second chip are spaced apart along a first direction, which is parallel to the first surface. In the first direction, at least a portion of the first capacitor is located between the first chip and the second chip, and at least a portion of the second capacitor is located between the first chip and the second chip.

[0006] In some embodiments, the adapter board further includes an insulating layer and multiple conductive structures. The insulating layer is disposed between the base layer and the multiple differential signal lines, and the multiple conductive structures penetrate the insulating layer. The multiple conductive structures include a first conductive structure, a second conductive structure, a third conductive structure, and a fourth conductive structure. The first differential signal line is electrically connected to one electrode of the first capacitor through the first conductive structure, and the second differential signal line is electrically connected to the other electrode of the first capacitor through the second conductive structure. The third differential signal line is electrically connected to one electrode of the second capacitor through the third conductive structure, and the fourth differential signal line is electrically connected to the other electrode of the second capacitor through the fourth conductive structure.

[0007] In some embodiments, the plurality of capacitors further includes a third capacitor and a fourth capacitor, and the plurality of differential signal lines further includes a fifth differential signal line, a sixth differential signal line, a seventh differential signal line, and an eighth differential signal line. The fifth differential signal line is electrically connected to one electrode of the third capacitor, and the sixth differential signal line is electrically connected to the other electrode of the third capacitor. The seventh differential signal line is electrically connected to one electrode of the fourth capacitor, and the eighth differential signal line is electrically connected to the other electrode of the fourth capacitor. The second chip also has a third interface, and the plurality of chips include the third chip, which has a fourth interface. The third interface is electrically connected to the fifth and seventh differential signal lines, and the fourth interface is electrically connected to the sixth and eighth differential signal lines.

[0008] In some embodiments, the second chip and the third chip are spaced apart along a first direction, which is parallel to the first surface. In the first direction, at least a portion of the third capacitor is located between the second chip and the third chip, and at least a portion of the fourth capacitor is located between the second chip and the third chip.

[0009] In some embodiments, a plurality of trenches are provided on the first surface of the substrate, the plurality of trenches extending from the first surface into the substrate, each capacitor including a first electrode, a dielectric layer and a second electrode, the first electrode and the second electrode respectively extending from the first surface into the plurality of trenches, and the dielectric layer being disposed between the first electrode and the second electrode.

[0010] In some embodiments, both the first interface and the second interface are PCIe interfaces.

[0011] On the other hand, this application also provides an electronic device, including the chip packaging structure and circuit board in any of the above embodiments, wherein the chip packaging structure is electrically connected to the circuit board.

[0012] In the embodiments provided in this application, the communication channel between the first chip and the second chip in the chip package structure includes a pair of differential signal lines. One differential signal line includes a first differential signal line and a second differential signal line, and the other differential signal line includes a third differential signal line and a fourth differential signal line. Additionally, the adapter board of the chip package structure also includes multiple capacitors embedded in the adapter board. The first differential signal line is electrically connected to one electrode of the first capacitor, the second differential signal line is electrically connected to the other electrode of the first capacitor, the third differential signal line is electrically connected to one electrode of the second capacitor, and the fourth differential signal line is electrically connected to the other electrode of the second capacitor, thereby realizing that a capacitor is connected in series in each of the pair of differential signal lines. Based on this, the first interface of the first chip and the second interface of the second chip can bypass the limitations of DDR or UCIE interfaces. For example, a PCIE interface can be used to realize interconnection and communication between the two chips. Furthermore, the capacitors connected in the pair of differential signal lines between the two chips are capacitors directly formed in the adapter board, avoiding the need to additionally configure surface mount capacitors in the chip package structure. This helps save the area of ​​the package substrate and avoids the problem of incompatibility between the surface mount capacitor mounting process and the chip package structure mounting process. This reduces costs and achieves higher integration, which is conducive to improving yield.

[0013] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0014] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0015] Figure 1 This is a cross-sectional schematic diagram of the chip packaging structure provided in the embodiments of this application;

[0016] Figure 2 for Figure 1 The illustrated embodiment provides a top view of the chip packaging structure;

[0017] Figure 3 for Figure 1 A partial enlarged view of the chip packaging structure provided in the embodiment shown at point A;

[0018] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0019] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0020] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0021] In the description of this application, "multiple" means two or more.

[0022] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0023] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. The term "electrical connection" indicates, for example, that two or more components have direct physical or electrical contact, but may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0024] Currently, chip-on-wafer-on-substrate (CoWoS) technology is a widely used 2.5D packaging solution for high-performance chips internationally. Under this packaging structure, the communication interface between chips is mostly a high-density parallel signal interface such as DDR or UCIE.

[0025] However, due to limitations in domestic manufacturing capabilities, the application of DDR interfaces is somewhat restricted. Furthermore, there is no mature UCIE interface standard protocol in China, and commercial UCIE interfaces are not yet mature. Using other interfaces instead of these two types also presents other problems. For example, taking the PCIE interface as an example, according to the PCIE interconnect protocol, DC blocking capacitors of a certain capacitance need to be connected to the two differential signal lines of a pair of differential signal lines. However, because the current surface mount capacitor mounting process is incompatible with the chip package structure mounting process, surface mount capacitors cannot be integrated onto the chip package structure.

[0026] Based on this, this application provides a chip packaging structure, such as... Figures 1-3 As shown, Figure 1 This is a cross-sectional schematic diagram of the chip packaging structure provided in an embodiment of this application. Figure 2 for Figure 1 The illustrated embodiment provides a top view of the chip packaging structure. Figure 3 for Figure 1 The illustrated embodiment shows a partial enlarged view of the chip packaging structure at point A.

[0027] like Figure 1 As shown, the chip packaging structure 100 includes a packaging substrate 1, an adapter plate 2, and multiple chips 3. The adapter plate 2 is disposed on the packaging substrate 1 and is electrically connected to the packaging substrate 10 via C4 solder bumps. The multiple chips 3 are disposed on the side of the adapter plate 2 away from the packaging substrate 1.

[0028] like Figure 2 and Figure 3 As shown, the adapter board 2 includes a base layer 20, multiple capacitors 21, and multiple differential signal lines 22. The base layer 20 includes a first surface P1 on the side away from the packaging substrate 1. The multiple capacitors 21 are embedded in the first surface P1, including a first capacitor 211 and a second capacitor 212. The multiple differential signal lines 22 are disposed on the side of the base layer 20 away from the packaging substrate 1. The multiple differential signal lines 22 include a first differential signal line 221, a second differential signal line 222, a third differential signal line 223, and a fourth differential signal line 224. The first differential signal line 221 is electrically connected to one electrode of the first capacitor 211, and the second differential signal line 222 is electrically connected to the other electrode of the first capacitor 211. The third differential signal line 223 is electrically connected to one electrode of the second capacitor 212, and the fourth differential signal line 224 is electrically connected to the other electrode of the second capacitor 212.

[0029] like Figure 1 and 2As shown, the multiple chips 3 include a first chip 31 and a second chip 32. The first chip 31 has a first interface 311, and the second chip 32 has a second interface 321. The first interface 311 is electrically connected to a first differential signal line 221 and a third differential signal line 223, and the second interface 321 is electrically connected to a second differential signal line 222 and a fourth differential signal line 224.

[0030] In this embodiment, multiple capacitors 21 are directly formed on the adapter plate 2; that is, the multiple capacitors 21 are deep-groove capacitors. Between the two chips in the chip package structure 100, taking the first chip 31 and the second chip 32 as examples, the communication channel between the two chips includes a pair of differential signal lines, which can be denoted as differential signal line L1 and differential signal line L2. One differential signal line L1 includes a first differential signal line 221 and a second differential signal line 222, which are electrically connected to the two electrodes of the first capacitor 211, thereby connecting the first capacitor 211 in series to the differential signal line L1. The other differential signal line L2 includes a third differential signal line 223 and a fourth differential signal line 224, which are electrically connected to the two electrodes of the second capacitor 212, thereby connecting the second capacitor 212 in series to the differential signal line L2.

[0031] Based on this, a capacitor is connected in series on each of the differential signal lines of a pair of differential signal lines between the first chip 31 and the second chip 32 to block DC signals. Correspondingly, the first interface 311 and the second interface 321 can bypass the limitations of DDR or UCIE interfaces. For example, the first interface 311 and the second interface 321 can use PCIE interfaces and use the PCIE communication protocol to realize communication interconnection between the two chips.

[0032] Furthermore, since the capacitor 21 connected in series on a pair of differential signal lines between the two chips is a deep-groove capacitor directly formed on the adapter board 2, it avoids the need to additionally configure surface mount capacitors (such as multilayer ceramic chip capacitors) in the chip package structure 100. This helps to save the area of ​​the package substrate 1 and also avoids the problem of incompatibility between the surface mount capacitor mounting process and the chip package structure 100 mounting process. This reduces costs and achieves higher integration, which is beneficial to improving yield.

[0033] Since capacitor 21 is directly formed on adapter plate 2, the capacitance value of capacitor 21 can be precisely designed as needed, avoiding the limitation of fixed capacitance value of surface mount capacitors.

[0034] In addition, in this embodiment, the capacitor 21 is directly formed on the adapter board 2. The parasitic resistance and parasitic inductance of the capacitor 21 are lower. In combination with the relevant provisions of the communication protocol, the capacitor 21 in this embodiment can achieve the communication effect specified by the protocol with a lower capacitance value. This can further reduce the area occupied by the capacitor 21 on the adapter board 2, which is conducive to further reducing the size of the chip package structure 100 and further improving the integration.

[0035] In some embodiments, such as Figure 3 As shown, the first chip 31 and the second chip 32 are arranged at intervals along a first direction (X-axis direction), which is parallel to the first surface P1. In the first direction, at least a portion of the first capacitor 211 is located between the first chip 31 and the second chip 32, and at least a portion of the second capacitor 212 is located between the first chip 31 and the second chip 32.

[0036] Compared to the surface-mount capacitor connection scheme in related technologies, the capacitor 21 in this embodiment is directly formed on the adapter board 2. Therefore, the distribution of the capacitor 21 is more flexible. By placing at least a portion of the first capacitor 211 between the first chip 31 and the second chip 32, it is more conducive to the connection of the differential signal line 22, reducing the length of the differential signal line 22 and lowering the signal transmission time. Furthermore, because the distribution of the capacitor 21 is more flexible, the area of ​​the adapter board 2 can be fully utilized, which helps to optimize the size of the adapter board 2.

[0037] In some embodiments, such as Figure 3 As shown, the adapter board 2 also includes an insulating layer 23 and multiple conductive structures 24. The insulating layer 23 is disposed between the base layer 20 and multiple differential signal lines 22, and the multiple conductive structures 24 penetrate the insulating layer 23. The multiple conductive structures 24 include a first conductive structure 241, a second conductive structure 242, a third conductive structure 243, and a fourth conductive structure 244. The first differential signal line 221 is electrically connected to one electrode of the first capacitor 211 through the first conductive structure 241, and the second differential signal line 222 is electrically connected to the other electrode of the first capacitor 211 through the second conductive structure 242. Similarly, the third differential signal line 223 is electrically connected to one electrode of the second capacitor 212 through the third conductive structure 243, and the fourth differential signal line 224 is electrically connected to the other electrode of the second capacitor 212 through the fourth conductive structure 244.

[0038] The aforementioned multiple conductive structures 24 are used to realize the electrical connection between multiple differential signal lines 22 and the corresponding capacitors 21. In this way, when the capacitors 21 are embedded in the adapter board 2, it is beneficial to arrange the electrodes of the capacitors 21 and the differential signal lines 22 in layers on the adapter board 2. This is beneficial to optimize the routing design of multiple differential signal lines 22 on the adapter board 2, reduce the area of ​​the adapter board 2, and improve the packaging integration.

[0039] In some embodiments, such as Figure 2 As shown, the plurality of capacitors 21 also includes a third capacitor 213 and a fourth capacitor 214, and the plurality of differential signal lines 22 also includes a fifth differential signal line 225, a sixth differential signal line 226, a seventh differential signal line 227, and an eighth differential signal line 228. The fifth differential signal line 225 is electrically connected to one electrode of the third capacitor 213, and the sixth differential signal line 226 is electrically connected to the other electrode of the third capacitor 213. The seventh differential signal line 227 is electrically connected to one electrode of the fourth capacitor 214, and the eighth differential signal line 228 is electrically connected to the other electrode of the fourth capacitor 214. The second chip 32 also has a third interface 322, and the plurality of chips 3 includes a third chip 33, which has a fourth interface 331. The third interface 322 is electrically connected to the fifth differential signal line 225 and the seventh differential signal line 227, and the fourth interface 331 is electrically connected to the sixth differential signal line 226 and the eighth differential signal line 228.

[0040] In this embodiment, each chip may include multiple interfaces. For example, the second chip 32 includes a second interface 321 and a third interface 322. Similar to the communication interconnection between the first interface 311 of the first chip 31 and the second interface 321 of the second chip 32, the communication channel between the third interface 322 and the fourth interface 331 also includes a pair of differential signal lines, which can be denoted as differential signal line L3 and differential signal line L4. Differential signal line L3 includes a fifth differential signal line 225 and a sixth differential signal line 226, which are electrically connected to the two electrodes of the third capacitor 213, thereby connecting the third capacitor 213 in series to the differential signal line L3. The other differential signal line L4 includes a seventh differential signal line 227 and an eighth differential signal line 228, which are electrically connected to the two electrodes of the fourth capacitor 214, thereby connecting the fourth capacitor 214 in series to the differential signal line L4.

[0041] Based on this, a capacitor is connected to each differential signal line of a pair of differential signal lines between the second chip 32 and the third chip 33 to block DC signals. The corresponding third interface 322 and fourth interface 331 can also bypass the limitations of DDR or UCIE interfaces. For example, PCIE interface can be used to realize communication interconnection between the two chips using PCIE communication protocol.

[0042] In some embodiments, such as Figure 2 As shown, the second chip 32 and the third chip 33 are arranged at intervals along a first direction, where the first direction can be as follows: Figure 2 The X-axis direction shown can also be the Y-axis direction, or other directions parallel to the XY plane. The specific design can be reasonably designed according to the chip packaging requirements. In this first direction, at least a portion of the third capacitor 213 is located between the second chip 32 and the third chip 33, and at least a portion of the fourth capacitor 214 is located between the second chip 32 and the third chip 33.

[0043] By rationally arranging the positions of the third capacitor 213 and the fourth capacitor 214, it is more conducive to the connection of the differential signal line 22, to reducing the length of the differential signal line 22, reducing the signal transmission time, and to optimizing the size of the adapter board 2.

[0044] In some embodiments, such as Figure 3 As shown, the first surface P1 of the base layer 20 is provided with a plurality of grooves T1, which extend from the first surface P1 into the base layer 20. Each capacitor 21 includes a first electrode D1, a dielectric layer D3 and a second electrode D2. The first electrode D1 and the second electrode D2 extend from the first surface P1 into the plurality of grooves T1 respectively. The dielectric layer D3 is disposed between the first electrode D1 and the second electrode D2.

[0045] For example, such as Figure 3 As shown, taking the first capacitor 211 as an example, each capacitor includes multiple trenches. Within each trench, the first electrode D1, the dielectric layer D3, and the second electrode D2 can form an interleaved multilayer structure. Based on this, it is beneficial to realize the design of different capacitance values, meet the communication requirements between chips, and reduce the area occupied by the capacitor 21 on the adapter board 2, thereby reducing the size of the chip package structure 100, reducing costs, and improving integration.

[0046] In some embodiments, both the first interface 311 and the second interface 321 are PCIe interfaces. Since the adapter board 2 integrates deep-groove capacitors, the scheme of connecting the capacitor 21 in series to the differential signal line is relatively simple to operate. Based on this, it becomes possible to realize communication interconnection between two chips using the PCIe communication protocol. Furthermore, the PCIe interface technology is relatively mature, which helps to overcome technical limitations and improve the interconnection performance between chips.

[0047] Secondly, this application also provides an electronic device 200, such as... Figure 4 As shown, Figure 4 An electronic device 200 provided in this application embodiment includes the aforementioned chip package structure 100 and a circuit board 201, wherein the chip package structure 200 and the circuit board 201 are electrically connected.

[0048] In the chip package structure 100 of the electronic device 200, capacitors 21 are connected in series to the differential signal lines. Based on this, the interconnection and communication between the two chips can bypass the limitations of DDR or UCIE interfaces. For example, it can be implemented using a PCIE interface. Furthermore, the capacitors connected to the pair of differential signal lines between the two chips are deep-groove capacitors embedded in the adapter board, which avoids the need to additionally configure surface-mount capacitors in the chip package structure 100. This helps to save the area of ​​the package substrate 1 and avoids the problem of incompatibility between the surface-mount capacitor mounting process and the chip package structure mounting process. This reduces costs and achieves higher integration, which is beneficial to improving yield.

[0049] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A chip packaging structure, characterized in that, include: Packaging substrate; An adapter board is disposed on the packaging substrate and is electrically connected to the packaging substrate; Multiple chips are disposed on the side of the adapter board away from the packaging substrate; The adapter board includes a base layer, multiple capacitors, and multiple differential signal lines. The base layer includes a first surface away from the packaging substrate. The multiple capacitors are embedded in the first surface. The multiple capacitors include a first capacitor and a second capacitor. The multiple capacitors are deep-groove capacitors directly formed on the adapter board to block DC signals. The plurality of differential signal lines are disposed on the side of the base layer away from the packaging substrate. The plurality of differential signal lines include a first differential signal line, a second differential signal line, a third differential signal line, and a fourth differential signal line. The first differential signal line is electrically connected to one electrode of the first capacitor, and the second differential signal line is electrically connected to the other electrode of the first capacitor. The third differential signal line is electrically connected to one electrode of the second capacitor, and the fourth differential signal line is electrically connected to the other electrode of the second capacitor. The plurality of chips includes a first chip and a second chip, the first chip having a first interface and the second chip having a second interface; the first interface is electrically connected to the first differential signal line and the third differential signal line, and the second interface is electrically connected to the second differential signal line and the fourth differential signal line; Both the first interface and the second interface are PCIe interfaces.

2. The chip packaging structure according to claim 1, characterized in that, The first chip and the second chip are arranged at intervals along a first direction, which is parallel to the first surface; In the first direction, at least a portion of the first capacitor is located between the first chip and the second chip, and at least a portion of the second capacitor is located between the first chip and the second chip.

3. The chip packaging structure according to claim 1, characterized in that, The adapter board further includes an insulating layer and multiple conductive structures. The insulating layer is disposed between the base layer and the multiple differential signal lines, and the multiple conductive structures penetrate the insulating layer. The plurality of conductive structures include a first conductive structure, a second conductive structure, a third conductive structure, and a fourth conductive structure. The first differential signal line is electrically connected to one electrode of the first capacitor through the first conductive structure, and the second differential signal line is electrically connected to the other electrode of the first capacitor through the second conductive structure. The third differential signal line is electrically connected to one electrode of the second capacitor through the third conductive structure, and the fourth differential signal line is electrically connected to the other electrode of the second capacitor through the fourth conductive structure.

4. The chip packaging structure according to claim 1, characterized in that, The plurality of capacitors also includes a third capacitor and a fourth capacitor; The plurality of differential signal lines further includes a fifth differential signal line, a sixth differential signal line, a seventh differential signal line, and an eighth differential signal line. The fifth differential signal line is electrically connected to one electrode of the third capacitor, and the sixth differential signal line is electrically connected to the other electrode of the third capacitor. The seventh differential signal line is electrically connected to one electrode of the fourth capacitor, and the eighth differential signal line is electrically connected to the other electrode of the fourth capacitor. The second chip also has a third interface, and the plurality of chips include the third chip, which has a fourth interface; the third interface is electrically connected to the fifth differential signal line and the seventh differential signal line, and the fourth interface is electrically connected to the sixth differential signal line and the eighth differential signal line.

5. The chip packaging structure according to claim 4, characterized in that, The second chip and the third chip are arranged at intervals along a first direction, which is parallel to the first surface; In the first direction, at least a portion of the third capacitor is located between the second chip and the third chip, and at least a portion of the fourth capacitor is located between the second chip and the third chip.

6. The chip packaging structure according to claim 1, characterized in that, The first surface of the base layer is provided with a plurality of grooves, which extend from the first surface into the base layer. Each capacitor includes a first electrode, a dielectric layer, and a second electrode, wherein the first electrode and the second electrode extend from the first surface into the plurality of trenches, and the dielectric layer is disposed between the first electrode and the second electrode.

7. An electronic device, characterized in that, include: The chip packaging structure as described in any one of claims 1 to 6; The circuit board, wherein the chip package structure is electrically connected to the circuit board.

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