Driver for slew rate control of phase nodes in buck converter

Abstract

The invention relates to a driver for slew rate control of phase nodes in a buck converter. A buck converter includes a first power switch coupled between a supply voltage node and a switching node, where the first power switch is configured to be controlled by a first control signal; a bootstrap capacitor, wherein a first terminal of the bootstrap capacitor is coupled to the switching node; a first buffer coupled between the first node and a control terminal of the first power switch; a first switching circuit coupled between the first node and a second terminal of the bootstrap capacitor, where the first switching circuit is controlled by a first control signal and configured to pass through a first charging current provided by the bootstrap capacitor when the first control signal is set; and a slew rate control capacitor, wherein a first terminal of the slew rate control capacitor is coupled to the first node.

Description

Technical Field

[0001] The present invention relates generally to switched mode power supplies (SMPS) and, in a particular embodiment, to a buck converter having a driver circuit for slew-rate control of a phase node. Background Art

[0002] Power converters are ubiquitous in many electronic applications from computers to automobiles. In some embodiments, voltage is generated within a power converter by operating a switch loaded with an inductor or transformer to perform DC-DC, DC-AC, and / or AC-DC conversion. Examples of power converters include switch mode power supplies (SMPS) and linear regulators. SMPSs are generally more efficient than other types of power conversion systems because power conversion is performed by controlled charging and discharging of an inductor or transformer and reduces energy lost due to power dissipation across a resistive voltage drop.

[0003] An SMPS typically includes at least one switch (also called a power switch) and an inductor or transformer. Some specific topologies include buck converters, boost converters, and flyback converters, among others. A control circuit is typically used to open and close the switch to charge and discharge the inductor. In some applications, the current supplied to the load and / or the voltage supplied to the load is controlled via a feedback loop. In some topologies, the switches used in an SMPS are implemented using cascode switches. A linear regulator is another type of power converter in which a pass transistor is controlled (e.g., turned on and off) by a controller to provide a regulated voltage to an external load.

[0004] Buck converters are a popular choice for SMPS and are often used to provide power to downstream devices such as sensors or processors. The slew rate control of the phase node (also called the switch node) of the buck converter directly affects the performance of the buck converter. There is a need in the art for a buck converter with a good slew rate control mechanism. Summary of the invention

[0005] According to one embodiment, a switch mode power supply (SMPS) includes: a high-side switch, the high-side switch is coupled between a power supply voltage node and a switch node, wherein the high-side switch is configured to be controlled by a first control signal; a low-side switch, the low-side switch is coupled between the switch node and a reference voltage node, wherein the low-side switch is configured to be controlled by a second control signal; and a driver circuit, the driver circuit being used for the high-side switch and the low-side switch. The driver circuit includes: a first buffer circuit, the first buffer circuit is coupled between a first node and a control terminal of the high-side switch; a first switch circuit, wherein the control terminal of the first switch circuit is configured to receive the first control signal, the input terminal of the first switch circuit is coupled to a first power supply, and the output terminal of the first switch circuit is coupled to the first node, wherein the first switch circuit is configured to output a first charging current provided by the first power supply when the first control signal is set; a second buffer circuit, the second buffer circuit is coupled between a second node and the control terminal of the low-side switch; a second switch circuit, wherein the control terminal of the second switch circuit is configured to receive the second control signal, the input terminal of the second switch circuit is coupled to a second power supply, and the output terminal of the second switch circuit is coupled to the second node, wherein the second switch circuit is configured to output a second charging current provided by the second power supply when the second control signal is set; and a first slew rate control capacitor, wherein a first terminal of the first slew rate control capacitor is coupled to the first node.

[0006] According to one embodiment, a buck converter includes: a high-side switch and a low-side switch, the high-side switch and the low-side switch are coupled in series between a power supply voltage node and a reference voltage node, wherein the high-side switch and the low-side switch are configured to be controlled by a first control signal and a second control signal, respectively; a switch node, the switch node is located between the high-side switch and the low-side switch; a first buffer, the first buffer is coupled between a first node and a control terminal of the high-side switch; a first switch circuit, wherein the control terminal of the first switch circuit is configured to receive the first control signal, wherein when the first control signal is set, the first switch circuit is configured to allow a first charging current provided by a first power supply to the first node to pass through; a second buffer, the second buffer is coupled between a second node and the control terminal of the low-side switch; a second switch circuit, wherein the control terminal of the second switch circuit is configured to receive the second control signal, wherein when the second control signal is set, the second switch circuit is configured to allow a second charging current provided by a second power supply to the second node to pass through; and a first slew rate control capacitor, wherein a first terminal of the first slew rate control capacitor is coupled to the first node.

[0007] According to one embodiment, a buck converter includes: a first power switch, the first power switch is coupled between a power supply voltage node and a switch node, wherein the first power switch is configured to be controlled by a first control signal; a bootstrap capacitor, wherein a first terminal of the bootstrap capacitor is coupled to the switch node; a first buffer, the first buffer is coupled between the first node and a control terminal of the first power switch; a first switching circuit, the first switching circuit is coupled between the first node and a second terminal of the bootstrap capacitor, wherein the first switching circuit is controlled by the first control signal and is configured to allow a first charging current provided by the bootstrap capacitor to pass through when the first control signal is set; and a slew rate control capacitor, wherein a first terminal of the slew rate control capacitor is coupled to the first node. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 illustrates a block diagram of a switch mode power supply (SMPS) in one embodiment;

[0010] Figure 2 illustrates a schematic diagram of an SMPS having a driver circuit capable of slew rate control of a switch node in one embodiment;

[0011] Figure 3A and Figure 3B illustrates a buffer circuit used in a driver circuit of an SMPS in some embodiments;

[0012] Figure 4 illustrates a schematic diagram of an SMPS having a driver circuit capable of slew rate control of a switch node in another embodiment;

[0013] Figure 5 illustrates a schematic diagram of an SMPS having a driver circuit capable of slew rate control of a switch node in another embodiment;

[0014] Figure 6 illustrates a schematic diagram of an SMPS having a driver circuit capable of slew rate control of a switch node in yet another embodiment; and

[0015] Figure 7 and Figure 8 The performance of a buck converter having a slew rate control mechanism in one embodiment is illustrated. DETAILED DESCRIPTION

[0016] The making and use of the examples currently disclosed are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be implemented in a variety of specific contexts. The specific examples discussed merely illustrate specific ways to make and use the present invention and do not limit the scope of the present invention. Throughout the discussion herein, unless otherwise specified, the same or similar reference numerals or symbols in different figures refer to the same or similar components (or signals).

[0017] The present disclosure will be described with reference to examples in a specific context, namely a buck converter having a driver circuit capable of slew rate control of a switching node (also referred to as a phase node) of the buck converter.

[0018] Figure 1 A block diagram of a switch mode power supply (SMPS) 200 in one embodiment is illustrated. Note that for simplicity, not all features of the SMPS 200 are illustrated.

[0019] Figure 1 The SMPS200 in is a step-down converter. Figure 1 In an example of a buck converter, some of the components of the buck converter are integrated together on the same semiconductor substrate (e.g., silicon) to form an integrated circuit (IC) device 100 or a portion of an IC device 100. An example of an IC device 100 is a power management integrated circuit (PMIC) device. Components of the SMPS 200 that are external to the IC device 100 (e.g., not integrated therein) are referred to as external components connected to the IC device 100. The pins of the IC device 100 are Figure 1The connector is shown as a rectangular shape in the figure. Figure 1 The number and type of components of the buck converter in IC device 100 shown in FIG. 1 are only non-limiting examples. Depending on how SMPS 200 is partitioned, IC device 100 may integrate other numbers or other types of components of the buck converter.

[0020] exist Figure 1 In FIG. 1 , SMPS 200 (e.g., a buck converter) includes a switch 101 (also referred to as a high-side switch), a switch 103 (also referred to as a low-side switch), a high-side gate driver circuit 107 for the high-side switch 101, a low-side gate driver circuit 109 for the low-side switch 103, and a slew rate control capacitor 111 coupled between the high-side gate driver circuit 107 and the low-side gate driver circuit 109. The high-side gate driver circuit 107, the low-side gate driver circuit 109, and the slew rate control capacitor 111 may be collectively referred to as a driver circuit (or gate driver circuit) of a buck converter. Note that a slew rate control capacitor (e.g., 111) is provided in FIG. Figure 1 150A, 150B, 150C, and 150D) are shown as being coupled between the high-side gate driver circuit 107 and the low-side gate driver circuit 109. Of course, this is merely a non-limiting example. The driver circuit of the buck converter may have more than one slew rate control capacitor, and the slew rate capacitors may be connected in different configurations. Various embodiments of the driver circuits of the buck converter (e.g., 150A, 150B, 150C, and 150D) are discussed below.

[0021] exist Figure 1 In the example of , switches 101 and 103 are N-type transistors. In the discussion here, switches 101 and 103 may also be referred to as transistors 101 and 103. In other embodiments, switch 101 is a P-type transistor and switch 103 is an N-type transistor. These and other variations are fully intended to be included in the scope of the present disclosure. A switch node 105 (also referred to as a phase node) between switch 101 and switch 103 is connected to pin SW of IC device 100.

[0022] Figure 1 The SMPS 200 in the embodiment also includes a control loop and logic circuit 117 for generating switch control signals 128 (e.g., 128A and 128B). In some embodiments, the switch control signals 128A and 128B are pulse width modulation (PWM) signals for controlling the switches of the high-side switch 101 and the low-side switch 103, respectively. In some embodiments, the switch control signals 128A and 128B are low-voltage digital signals that can be switched between, for example, zero volts and +5V. In the illustrated embodiment, the control signal 128B is sent to the control terminal (e.g., gate terminal) of the low-side switch 103 and can be referred to as the control signal Pwm_LS The voltage of the control signal 128A is shifted by the level shifter 118 to generate a control signal P which is sent to the control terminal of the high-side switch 101. wm_HS The voltage of the control signal 128A is represented as V 128A , and the voltage at the switch node 105 is represented as voltage V SW , the output of the level shifter is V SW +V 128A Note that the voltage V at the switch node 105 is SW changes during buck converter operation, with the result that the control signal P wm_LS The voltage varies with the voltage V SW For example, when the control signal 128A rises from zero volts to V cc (e.g., +5V) to turn on the high-side switch 101, the level shifter 118 converts (e.g., shifts) the value (e.g., +5V) to match V boot Value (V SW +5V=5V, at this time V SW is zero volts because the low-side switch 103 is just turned off). Then, the high-side switch 101 is turned on, and the voltage V SW At the end of the conversion, the voltage V SW Reaching the power supply voltage V in (V SW =V in ), so the control signal P wm_HS The voltage at the end of the conversion is V in +5V (e.g., +105V). Note that the above example assumes that the logic high (HIGH) value of the control signal 128A turns on the high-side switch 101, which is a non-limiting example. As the skilled person will readily appreciate, the logic value of the control signal 128 (e.g., 128A, 128B) used to turn on the power switch (e.g., 101, 103) is determined by the structure of the driver circuit for the power switch and the type of the power switch (e.g., N-type or P-type). In subsequent examples discussed herein, a logic low (LOW) value of the control signal 128 can be used to turn on the power switch.

[0023] The control loop and logic circuit 117 can compare the feedback voltage received at the pin FB of the IC device 100 with the reference voltage V ref The comparison is based on the feedback voltage and the reference voltage V refThe value of , generates a switch control signal 128. Circuits for generating the switch control signal 128 are known and used in the art. For example, U.S. Patent Application No. 18 / 334,708 and U.S. Patent Application No. 18 / 334,757 disclose various control circuits for generating switch control signals for high-side switches and low-side switches and implementing stability control of buck converters. U.S. Patent Application No. 18 / 334,708 and U.S. Patent Application No. 18 / 334,757 are incorporated herein by reference.

[0024] exist Figure 1 In the example, SMPS 200 includes a voltage applied to pin V of IC device 100. in The power supply voltage at the source generates one or more power supply voltages (e.g., V cc ) of the power generator 115. For ease of discussion, at the pin V in The power supply voltage applied at can also be referred to as voltage V in One or more power supply voltages (eg, V cc ) may be referred to as the internal supply voltage and may have a voltage V in Low voltage.

[0025] In some embodiments, the voltage V in has a value between, for example, +10 V and approximately +100 V. The power generator 115 includes a power supply voltage V cc A linear regulator such as a low dropout (LDO) regulator (eg, a +5V supply voltage) is used to power the low-side gate driver circuit 109 and the bootstrap capacitor C boot Charge the battery. Figure 1 In the case of power supply voltage V cc Connect to the V pin of the IC device 100 cc , and use the V pin of the IC device 100 cc The capacitor 131 connected thereto filters the supply voltage. In some embodiments, the capacitor 131 is omitted. In some embodiments, the power generator 115 also includes one or more reference circuits (such as a bandgap reference voltage circuit) to generate a reference voltage V ref , which is used by the control loop and logic circuit 117 to compare with the feedback voltage at pin FB. The reference circuit can also generate a charging current for slew rate control of the phase node discussed below. In some embodiments, the power generator 115 is omitted in the IC device 100, and the various internal power supply voltages (e.g., V cc and V ref).

[0026] exist Figure 1 In the example of FIG. 1 , an enable signal is received at pin EN of IC device 100 and sent to power generator 115. The enable signal can be used to enable IC device 100 (e.g., start IC device 100 and allow power generator 115 to generate an internal power supply voltage), or disable IC device 100 (e.g., suspend the operation of IC device 100).

[0027] like Figure 1 As shown in FIG. 1 , the switch 101 is coupled to the pin V of the IC device 100. IN and the pin SW of the IC device 100, and the switch 103 is coupled between the pin SW of the IC device 100 and the pin GND. IN is configured to receive a power supply voltage (e.g., a voltage V between +10V and +100V) IN ), and the pin GND is configured to be connected to a reference voltage (e.g., electrical ground). The inductor 121 is coupled between the pin SW and a node 126 (which may also be referred to as an output terminal of the SMPS 200), and the capacitor 123 is coupled between the node 126 and a reference node 130. The reference node 130 is configured to be connected to a reference voltage (e.g., electrical ground). During buck converter operation, the voltage at the node 126 is the output voltage V of the buck converter. OUT .

[0028] In an embodiment where the buck converter operates in a continuous conduction mode and switches 101 and 103 are transistors of the same type (e.g., N-type), the control loop and logic circuit 117 generates switch control signals 128A and 128B having opposite values ​​(e.g., logic high or logic low), thereby setting switches 101 and 103 to opposite states (e.g., on state or off state) during buck converter operation. In other words, for the above example of continuous conduction mode, during buck converter operation, when switch 103 is open, switch 101 is closed, and when switch 103 is closed, switch 101 is open.

[0029] Figure 1 The buck converter also includes a bootstrap capacitor C boot . Bootstrap capacitor C boot The pin V of the IC device 100 is coupled to boot and pin SW. Figure 1 In the example, diode 113 is coupled to pin V CC and pin V boot When the voltage at the switch node 105 is lower than the power supply voltage V CC When the bootstrap capacitor C bootThe power supply voltage V CC Charge.

[0030] During the buck converter operation, when the switch 101 (eg, N-type transistor) needs to be closed (eg, needs to be turned on), the bootstrap capacitor C boot The voltage across the bootstrap capacitor C boot The charge in the switch 101 is provided to provide a gate-source voltage of, for example, +5V for the transistor 101 to turn on the transistor 101. When the voltage at the pin SW is low (for example, the pin V boot The corresponding voltage at is equal to or lower than the power supply voltage V CC ), the power supply voltage V CC For the bootstrap capacitor C boot to charge (e.g., to restore the bootstrap capacitor C boot +5V voltage across both ends). Bootstrap capacitor C boot The capacitance can be large, so an external capacitor is used as the bootstrap capacitor C boot , and pin V boot For the bootstrap capacitor C boot Provide electrical connection between and switch 101.

[0031] Still refer to Figure 1 , the output voltage of the buck converter V OUT is sent to a voltage divider formed by resistors 127 and 129 coupled between node 126 and reference voltage node 130. The output of the voltage divider, known as the feedback voltage, is sent to pin FB of IC device 110. Figure 1 In the example of , a load 125 , illustrated as a current source as a non-limiting example, is coupled between node 126 and a reference voltage node 130 .

[0032] Figure 1 The structure of the buck converter illustrated in FIG. 1 is merely a non-limiting example. Variations are possible and are fully intended to be included within the scope of the present disclosure. For example, Figure 1 The switch 103 in FIG. 10 can be replaced by a diode having its cathode connected to the pin SW and its anode connected to the pin GND. As another example, the diode 113 can be replaced by a switch (e.g., a transistor) connected between the bootstrap capacitor C boot The gate-source voltage is provided to turn off the switch 101 when it is turned on, and the voltage at the pin SW is low (eg, the pin V boot The corresponding voltage at is equal to or lower than the power supply voltage V CC ) to allow the bootstrap capacitor C boot to charge.

[0033] The slew rate control of the phase node of the buck converter refers to the control of the slew rate of the voltage at the phase node 105. For ease of discussion, the voltage at the phase node 105 is also referred to as the phase node voltage V SW or switch node voltage V SW The slew rate of the phase node voltage V SW It can refer to the phase node voltage V SW The slew rate of the rising edge and / or the phase node voltage V SW The technician will easily understand that the conversion rate of the phase node voltage V SW Affects the switching duration of the buck converter and therefore affects the switching losses of the buck converter. For example, the switching losses of the buck converter can be related to the phase node voltage V SW Therefore, it would be advantageous to be able to control the slew rate of the phase node in order to control the switching losses of the buck converter.

[0034] Slew rate control can be beneficial for other aspects of the performance of the buck converter. For example, for devices with specific electromagnetic interference (EMI) requirements, slew rate control can be used to control the amount of EMI generated by the switching of switches 101 and 103 in the buck converter. In addition, slew rate control may be required for buck converters with strong capacitive nonlinearity of power switches (e.g., 101 and 103). In addition, it may be useful to control the slew rate (e.g., slow it down) in order to avoid dynamic breakdown of the intrinsic diode of the low-side switch after the dead time. Various embodiments of the buck converter are disclosed below, wherein the driver circuit of the buck converter of each embodiment uses one or more slew rate control capacitors to control the slew rate of the phase node voltage.

[0035] Figure 2 FIG. 2 shows a schematic diagram of a SMPS 200A in an embodiment. The SMPS 200A is Figure 1 200A. In particular, the SMPS 200A has a driver circuit 150A capable of slew rate control of the phase node 105. The details of the driver circuit 150A are discussed below. Note that for simplicity, Figure 1 Some components in the circuit (such as control loop and logic circuit 117, power generator 115, diode 113, resistors 127 / 129 and capacitor 131) are not in Figure 2 It is shown in the figure, and it is understood that these components are used with Figure 1 The same or similar electrical connections shown in are included in SMPS 200A.

[0036] Figure 2Illustrated is a capacitor 131 coupled between the gate and drain terminals of transistor 101 and a capacitor 133 coupled between the gate and source terminals of transistor 101. Capacitors 131 and 133 represent the gate-drain and gate-source capacitances of transistor 101 and, as will be readily appreciated by a skilled artisan, are not external capacitors connected to transistor 101. Similarly, capacitors 141 and 143 represent the gate-drain and gate-source capacitances of transistor 103. Figure 2 Also shown are the body diodes of transistors 101 and 103 , which are not external diodes connected to transistors 101 and 103 , as will be readily appreciated by the skilled person.

[0037] exist Figure 2 , the driver circuit 150A includes a buffer circuit 135 (also referred to as a buffer) coupled between a node 165 (also referred to as a control node BUFFGATE_HS) and a control terminal (e.g., a gate terminal) of the switch 101, a voltage source 136 coupled between the node 165 and a power supply voltage V in The slew rate control capacitor 137 and the switch circuit 139 are connected between the power supply voltage nodes. Figure 2 In the example, the switch circuit 139 is implemented as a series coupled pin V boot and an inverter of transistor 138A (eg, a P-type transistor) and transistor 138B (eg, an N-type transistor) between switching node 105. A control terminal of switch circuit 139 is configured to receive control signal Pwm_HS, and an output terminal of switch circuit 139 is coupled to node 165.

[0038] Figure 2 The driver circuit 150A in FIG. 1 also includes a buffer circuit 145 (also referred to as a buffer) coupled between a node 167 (also referred to as a control node BUFFGATE_LS) and a control terminal (e.g., a gate terminal) of the switch 103, a slew rate control capacitor 147 coupled between the node 167 and the switch node 105, and a switch circuit 149. Figure 2 In the example, the switch circuit 149 is implemented as a series coupled pin V CC The control terminal of the switch circuit 149 is configured to receive the control signal Pwm_LS, and the output terminal of the switch circuit 149 is coupled to the node 167.

[0039] In some embodiments, during buck converter operation, when the switch 101 needs to be turned on, the control signal Pwm_HS is set (e.g., has a value corresponding to a logic low), and the control signal Pwm_LS is reset (e.g., has a value corresponding to a logic high). Note that in the discussion herein, when the control signal Pwm_HS (or Pwm_LS) is set, the corresponding switch 101 (or 103) is turned on; and when the control signal Pwm_HS (or Pwm_LS) is reset, the corresponding switch 101 (or 103) is turned off. The logic value (e.g., logic low or logic high) associated with the setting or resetting of the control signal depends on the specific implementation of the switch circuit 139 (or 149). Therefore, the logic values ​​given above to set or reset the control signals Pwm_HS and Pwm_LS are merely non-limiting examples.

[0040] When the control signal Pwm_HS is set, the transistor 138A in the switch circuit 139 is turned on, and the transistor 138B is turned off, which allows the output terminal of the switch circuit 139 to output the power supplied by the bootstrap capacitor C boot The charging current I sat_drv_HS . Charging current I sat_drv_HS The slew rate control capacitor 137 is charged and the voltage across the slew rate control capacitor 137 is changed. The buffer circuit 135 coupled between the node 165 and the switch 101 provides a corresponding charging current I for the gate-drain capacitance of the switch 101. buf_HS , to control the slew rate of the phase node 105 according to the voltage change across the slew rate control capacitor 137. In some embodiments, the phase node voltage V SW The conversion rate of the rising edge (expressed as SW SRUP ) is given by:

[0041]

[0042] Among them C ctrl_HS is the capacitance of the slew rate control capacitor 137, and C gd_HS is the gate-drain capacitance of switch 101. Figure 3A and Figure 3B Embodiments of buffer circuits 135 and 145 are discussed.

[0043] As shown in equation (1), at a given slew rate control capacitor 137, the capacitance C ctrl_HS In this case, the charging current I sat_drv_HS To adjust the phase node voltage V SW Note that in the illustrated embodiment, the charging current I sat_drv_HS The bootstrap capacitor C bootAs an example, to regulate the bootstrap capacitor C boot The charging current I sat_drv_HS , the size of transistor 138A (e.g., physical dimensions, such as the channel length, channel width, and / or overall dimensions of the transistor) can be adjusted to achieve a charging current I sat_drv_HS different values ​​of .

[0044] In some embodiments, during buck converter operation, when switch 103 needs to be turned on, control signal Pwm_HS is reset (e.g., has a value corresponding to a logic high), and control signal Pwm_LS is set (e.g., has a value corresponding to a logic low). As a result, transistor 148A in switch circuit 149 is turned on, and transistor 148B is turned off, which allows the power generated by power generator 115 (see FIG. 144 ) to be output at the output terminal of switch circuit 149. Figure 1 ) provides a charging current I sat_drv_LS In the illustrated embodiment, the charging current I sat_drv_LS is the power supply voltage V provided by the power generator 115 cc of current.

[0045] Charging current I sat_drv_LS The slew rate control capacitor 147 is charged and the voltage across the slew rate control capacitor 147 is changed. The buffer circuit 145 coupled between the node 167 and the switch 103 provides a corresponding charging current I for the gate-drain capacitance of the switch 103. buf_LS , to control the slew rate of the phase node 105 according to the voltage change across the slew rate control capacitor 147. In some embodiments, the phase node voltage V SW The falling edge conversion rate (expressed as SW SRDOWN ) is given by:

[0046]

[0047] Among them C ctrl_LS is the capacitance of the slew rate control capacitor 147, and C gd_LS is the gate-drain capacitance of switch 103. As shown in equation (2), at a given slew rate, the capacitance C of control capacitor 147 ctrl_LS In this case, the charging current I sat_drv_LS To adjust the phase node voltage V SW In some embodiments, the power generator 115 is designed to provide a desired value I of the charging current. sat_drv_LS The power supply voltage V cc .

[0048] In some embodiments, the gate-drain capacitance of switches 101 and 103 may exhibit nonlinear behavior and may cause nonlinearity in the slew rate of the phase node voltage. To overcome the nonlinearity of the gate-drain capacitance, for embodiments in which buffer circuits 135 and 145 are omitted, the capacitance of slew rate control capacitors 137 and 147 (which are designed to have a fixed capacitance) is selected to be much larger than the gate-drain capacitance of switches 101 and 103. For example, the gate-drain capacitance of switches 101 and 103 may be approximately 10 pF, and the capacitance of slew rate control capacitors 137 and 147 may be between 2 and 10 times the gate-drain capacitance to dominate relative to the gate-drain capacitance. In some embodiments, slew rate control capacitors 137 and 147 are implemented as metal capacitors in IC device 100. Metal capacitors may have poor integration density and may require a large area (e.g., a large silicon area) in IC device 100. However, buffer circuits 135 and 145 decouple the slew rate control nodes (e.g., 165 and 167) from the gates of transistors 101 / 103, thereby significantly reducing the capacitance required for slew rate control capacitors 137 and 147, thereby advantageously reducing the area required for implementation in IC device 100. For example, the presence of buffer circuits 135 and 145 allows the use of slew rate control capacitors 137 and 147 having a capacitance between approximately 100 fF and 400 fF.

[0049] Variations of the disclosed embodiments are possible and are fully intended to be included within the scope of the present disclosure. For example, Figure 2 The switch circuits 139 and 149 shown in FIG. 1 may be in addition to Figure 2 As an example, each of the switch circuits 139 and 149 can be implemented by a transistor (e.g., a P-type transistor), wherein a first load path terminal (e.g., a source terminal) of the transistor is connected to a corresponding power source (e.g., a bootstrap capacitor C of the switch circuit 139). boot Or generate a power supply voltage V for the switch circuit 149 cc A power generator 115 of the embodiment of the present invention is provided, wherein the second load path terminal (e.g., the drain terminal) of the transistor is connected to a corresponding control node (e.g., node 165 for switch circuit 139 or node 167 for switch circuit 149), and wherein the control terminal of the transistor is connected to a corresponding control signal (e.g., control signal Pwm_HS for switch circuit 139 or control signal Pwm_LS for switch circuit 149). Figure 5 and Figure 6, the switch circuit 149 and / or the switch circuit 139 which may be implemented as transistors as discussed above are illustrated using a general switch symbol. Therefore, in each embodiment of the present disclosure (e.g., 200A, 200B, 200C, and 200D), the switch circuits 139 and 149 may be implemented as Figure 2 The inverter shown in , or may be implemented as a transistor as discussed above.

[0050] As another example of a variation of the disclosed embodiment, each of the switch circuits 139 and 149 can be implemented as a current source (e.g., a current generator) and a switch (e.g., a transistor) coupled in series with the current source. The current source provides a corresponding charging current (I sat_drv_HS or I sat_drv_LS ), and the switch is used to enable or disable the flow of charging current. The current source can be, for example, a current mirror whose main current is defined by a trim bit so that the main current can be selected from a plurality of predetermined values. Alternatively, the current source can be an adjustable current source that can be tuned (e.g., changed) according to some settings (e.g., control bits in a control register).

[0051] As yet another example of variations of the disclosed embodiments, while the schematic diagrams of the various embodiments disclosed herein show each slew rate control capacitor (137, 147, 136, or 161) as a single capacitor, these are merely non-limiting examples. As an example, one or more of the slew rate control capacitors may be implemented as multiple capacitors coupled in parallel (e.g., with smaller capacitances) or multiple capacitors coupled in series, combinations thereof, and the like. Other variations are possible and are fully intended to be included within the scope of the present disclosure.

[0052] Figure 3A and Figure 3B Buffer circuits 135 and 145 are illustrated, respectively, for use in a driver circuit of a buck converter in some embodiments. Figure 3A As shown in FIG. 1 , the buffer circuit 135 includes a series connection between pin V boot and pin SW. A control terminal of transistor 171 is coupled to node 165 (e.g., control node BUFFGATE_HS), and a control terminal of transistor 173 is configured to receive a control signal Pwm_HS. Node 172 between transistors 171 and 173 represents an output terminal of buffer circuit 135 and is coupled to a control terminal (labeled HS_GATE) of switch 101. In some embodiments, buffer circuit 135 (e.g., implemented as an N-type pull-up MOSFET) functions as a high bandwidth and high current capacity buffer to provide the required amount of current to obtain a desired slew rate of the switch node voltage.

[0053] like Figure 3B As shown in the figure, the buffer circuit 145 includes a series connection between the pin V cc and pin GND. A control terminal of transistor 181 is coupled to node 167 (e.g., control node BUFFGATE_LS), and a control terminal of transistor 183 is configured to receive a control signal Pwm_LS. Node 182 between transistors 181 and 183 represents an output terminal of buffer circuit 145 and is coupled to a control terminal (labeled LS_GATE) of switch 103. The functionality of buffer circuit 145 is similar to that of buffer circuit 135, so the details are not repeated.

[0054] Figure 4 FIG. 2 shows a schematic diagram of a SMPS 200B in an embodiment. The SMPS 200B is Figure 1 Another example implementation of a general SMPS 200 is shown in FIG. In particular, the SMPS 200B has a driver circuit 150B capable of slew rate control of the phase node 105. The details of the driver circuit 150B are discussed below. Note that for simplicity, Figure 1 Some components in the circuit (such as control loop and logic circuit 117, power generator 115, diode 113, resistors 127 / 129 and capacitor 131) are not in Figure 4 It is shown in the figure, and it is understood that these components are used with Figure 1 The same or similar electrical connections shown in are included in SMPS 200B.

[0055] Figure 4 The driver circuit 150B in FIG. Figure 2 1, but only has one slew rate control capacitor 136 coupled between node 165 and node 167. In other words, slew rate control capacitor 136 is used to control both the slew rate of the rising edge and the falling edge of the switch node voltage. In some embodiments, the slew rate of the rising edge of the switch node voltage is determined by the charging current I sat_drv_HS and the capacitance C of the slew rate control capacitor 136 ctrl is determined and is given by the following equation:

[0056]

[0057] The dual effect is that the slew rate of the falling edge of the switch node voltage is determined by the charging current I sat_drv_LS and the capacitance C of the slew rate control capacitor 136 ctrl is determined and is given by the following equation:

[0058]

[0059] Because driver circuit 150B uses only one slew rate control capacitor 136 , the area required for an integrated slew rate control capacitor in IC device 100 is reduced compared to, for example, driver circuit 150A.

[0060] Figure 5 FIG. 2 shows a schematic diagram of a SMPS 200C in an embodiment. Figure 1 200C. In particular, the SMPS 200C has a driver circuit 150C capable of slew rate control of the phase node 105. The details of the driver circuit 150C are discussed below. Note that for simplicity, Figure 1 Some components in the circuit (such as control loop and logic circuit 117, power generator 115, resistors 127 / 129 and capacitor 131) are not in Figure 5 It is shown in the figure, and it is understood that these components are used with Figure 1 The same or similar electrical connections shown in are included in SMPS 200C.

[0061] Figure 5 The driver circuit 150C in is similar to Figure 2 1, but with the switch circuits 139 and 149 illustrated using a common switch symbol. In addition, the slew rate control capacitor 137 is coupled between the node 165 and the node 156 (e.g., the output terminal) of the voltage divider 158 formed by the resistors 155 and 157, which is coupled to the pin V in and pin GND. In addition, slew rate control capacitor 147 is coupled between node 167 and node 152 (e.g., output terminal) of voltage divider 154 formed by resistors 151 and 153, which is coupled between pin SW and pin GND. In some embodiments, resistors 151, 153, 155, and 157 can be implemented as external components of IC device 100. Figure 5 The figure also shows the coupling at pin V cc and pin V boot The diode 113 is between them.

[0062] exist Figure 2 In the driver circuit 150A, the power rating (eg, maximum voltage tolerance) of the slew rate control capacitors 137 and 147 needs to be high enough to withstand the voltage at pin V in The supply voltage at pin V inIn embodiments where the power supply voltage at is high (eg, +100 V), the power rating of the slew rate control capacitors 137 and 147 is high, so a larger area may be required to implement the slew rate control capacitors 137 and 147 in the IC device 100.

[0063] exist Figure 5 In the driver circuit 150C, the output voltages of the voltage dividers 158 and 152 are lower than their corresponding input voltages, thereby reducing the maximum voltage drop across the slew rate control capacitors 137 and 147. As a result, Figure 5 The slew rate control capacitors 137 and 147 have a power rating lower than Figure 2 The conversion rate in controls the power rating of capacitors 137 and 147.

[0064] Can be analyzed Figure 5 The slew rate used in the control capacitors 137 and 147 is used to determine their power ratings. The voltage divider ratio of the voltage divider 158 is expressed as And the voltage divider ratio of the voltage divider 152 is expressed as Where R151, R153, R155 and R157 represent the resistances of resistors 151, 153, 155 and 157, respectively. In some embodiments, when switch 101 is turned on, control node 165 has a voltage V in +V cc , where V in is the pin V of the IC device 100 in The supply voltage at the cc (e.g., +5V) is the maximum gate-source voltage of switch 101 when it is fully on. When switch 103 is on, control node 165 has a voltage of zero volts (e.g., at electrical ground). Node 156 has a fixed voltage V in * R1. Therefore, the magnitude of the maximum voltage drop across the slew rate control capacitor 137 is given by:

[0065] V1=max(V in *R1, V in *(1-R1)+V cc ) (5)

[0066] A similar analysis can be performed for slew rate control capacitor 147. In some embodiments, when switch 103 is on, the voltage at node 152 is zero and the voltage at node 167 is V cc (e.g., +5V), which is the gate-source voltage of switch 103 when it is fully turned on. When switch 101 is turned on, the voltage at node 152 is V in* R2, and the voltage at the control node 167 is zero. Therefore, the magnitude of the maximum voltage drop across the slew rate control capacitor 147 is given by:

[0067] V2=max(V in *R2, V cc ) (6)

[0068] Figure 5 The power ratings of the slew rate control capacitors 137 and 147 in should be high enough to withstand the maximum voltage drop V1 given in equation (5) and the maximum voltage drop V2 given in equation (6), respectively. In some embodiments, Figure 5 The voltage divider ratio R1 and R2 is selected to be 0.5, and assuming that the power supply voltage V in (e.g., +100V) is much larger than V cc (e.g., +5V), the maximum voltage drop V is approximately the power supply voltage V in half, which means Figure 5 The power rating of the slew rate control capacitors 137 and 147 is Figure 2 The slew rate control capacitors 137 and 147 are half of the rated power. Figure 5 The lower power rating of the slew rate control capacitors 137 and 147 in the IC device 100 advantageously reduces the area required to implement the slew rate control capacitors 137 and 147 in the IC device 100.

[0069] Figure 6 A schematic diagram of a SMPS 200D having a driver circuit 150D capable of slew rate control of a switch node in yet another embodiment is illustrated. The SMPS 200D is an abstraction of the SMPS 200A, SMPS 200B, and SMPS 200C. Figure 6 The SMPS 200D in FIG. 1 focuses on a portion of the driver circuit 150D for driving the high-side switch 101, and omits the low-side switch 103 and a portion of the driver circuit 150D for driving the low-side switch 103. Note that, Figure 6 A slew rate control capacitor 161 is shown coupled between node 165 and fixed node 163. As discussed below, Figure 6 The slew rate control capacitor 161 corresponds to Figure 2 or Figure 5 The slew rate control capacitor 137 in the Figure 4 The slew rate control capacitor 136 in the fixed node 163 corresponds to Figure 2 The pin V in , Figure 4 Node 167 or Figure 5 Node 156 in.

[0070] In the context of discussing the topic of power bridges, the term "fixed node" refers to a node that has a static (e.g., fixed) voltage or is in the driver voltage domain (e.g., at the supply voltage V cc In addition, the term "floating node" refers to a node having a voltage that moves with the voltage at the switch node 105 and can move out of the driver voltage domain.

[0071] Node 165 is a floating node because when high-side switch 101 is conducting (eg, during the on phase), the voltage at node 165 is V cc (e.g., +5V); after the high-side switch 101 is turned on, the voltage at the node 165 is V in +V ghHS (e.g., 100V+5V); and just after the high-side switch 101 is turned off, the voltage at the node 165 is approximately V in , and then decreases with the voltage at the switch node 105 (this decrease can be passively caused by the inductor current, or actively caused by the low-side switch 103 turning on). When the low-side switch 103 is turned on, the voltage at the node 165 is zero (eg, GND).

[0072] Node 163 is a fixed node. Recall that node 163 corresponds to Figure 2 The pin V in , Figure 4 Node 167 or Figure 5 Node 156. Pin V in Has a fixed voltage (eg, +100V). Figure 5 Node 156 in has a fixed voltage (eg, V in *R1). Figure 4 The voltage of the node 167 in the low-side switch 103 is V when the low-side switch 103 is conducting or after the low-side switch 103 is conducting. cc (e.g., +5V), and the voltage after the low-side switch 103 is turned off is zero (e.g., electrically grounded). Therefore, node 163 is a fixed node. Based on the above discussion, it can be said that Figure 6 The slew rate control capacitor 161 (which represents the slew rate control capacitors 137 and 136) is coupled between the floating node 165 and the fixed node 163 (which represents Figure 2 The pin V in , Figure 4 Node 167 or Figure 5 Between nodes 156).

[0073] Following the above analysis, those skilled in the art will readily understand that the switch node 105 is a floating node, and Figure 5Node 152 in is also a floating node. Therefore, it can be said that Figure 2 and Figure 5 The slew rate control capacitor 147 in the embodiment is coupled between the fixed node 167 and the floating node (eg, Figure 2 The switch node 105 or Figure 5 Between nodes 152 in .

[0074] Figure 7 and Figure 8 The performance of a buck converter with slew rate control in one embodiment is illustrated. Figure 7 The curve 301 in shows the gate-source voltage of the high-side switch 101 when the high-side switch 101 is turned on. Figure 4 The buck converter 200B shown in FIG. 1 is used to obtain the simulation results. For comparison, curve 303 shows the simulation results of a reference buck converter without the disclosed slew rate control mechanism. The reference buck converter is similar to buck converter 200B, but without buffer circuits 135 and 145 and without slew rate control capacitor 136. As a result, the reference buck converter needs to scale the charging current (e.g., I sat_drv_HS and I sat_drv_LS ) to charge the larger capacitance (e.g., gate-drain capacitance) of the power switches (e.g., 101 and 103). Figure 8 Curve 305 in FIG. 1 shows the corresponding switch node voltage of the high-side switch 101 for the disclosed buck converter with slew rate control. For comparison, Figure 8 Curve 307 in shows the corresponding switch node voltage of the high side switch of the reference buck converter.

[0075] from Figure 7 and Figure 8 As can be seen in FIG. 1 , for the buck converter with the slew rate control mechanism, the total phase node voltage slope during the rise time is extremely regular, while the reference buck converter exhibits a strong nonlinear behavior during the rise time. The shorter and smoother rise time indicates less switching loss and better performance of the buck converter with the disclosed slew rate control mechanism.

[0076] Embodiments can achieve the advantages described below. For example, by using one or more slew rate control capacitors, the driver circuit of the disclosed buck converter allows the slew rate of the switch node voltage to be accurately controlled. As a result, the switching losses of the buck converter can be significantly reduced. The slew rate control mechanism also allows the EMI generated by the buck converter to be controlled to meet regulatory and / or performance requirements. The use of buffer circuits 135 and 145 reduces the area required to implement the slew rate control capacitor in the IC device. The driver circuit 150B uses a single slew rate control capacitor for slew rate control, thereby further reducing the area required to implement the slew rate control capacitor. Figure 5 The use of voltage dividers 158 and 154 in allows the use of slew rate control capacitors having lower power ratings, thereby also reducing the cost and / or area required to implement the slew rate control capacitors.

[0077] Examples of the present invention are summarized here. Other examples can also be understood from the entire content of the specification and claims submitted herein.

[0078] Example 1. According to one embodiment, a switch mode power supply (SMPS) includes: a high-side switch, the high-side switch is coupled between a power supply voltage node and a switch node, wherein the high-side switch is configured to be controlled by a first control signal; a low-side switch, the low-side switch is coupled between the switch node and a reference voltage node, wherein the low-side switch is configured to be controlled by a second control signal; and a driver circuit, the driver circuit for the high-side switch and the low-side switch, including: a first buffer circuit, the first buffer circuit is coupled between a first node and a control terminal of the high-side switch; a first switch circuit, wherein the control terminal of the first switch circuit is configured to receive the first control signal, an input terminal of the first switch circuit is coupled to a first power supply, and an an output terminal coupled to the first node, wherein the first switch circuit is configured to output a first charging current provided by the first power supply when the first control signal is set; a second buffer circuit, wherein the second buffer circuit is coupled between the second node and the control terminal of the low-side switch; a second switch circuit, wherein the control terminal of the second switch circuit is configured to receive the second control signal, an input terminal of the second switch circuit is coupled to the second power supply, and an output terminal of the second switch circuit is coupled to the second node, wherein the second switch circuit is configured to output a second charging current provided by the second power supply when the second control signal is set; and a first slew rate control capacitor, wherein a first terminal of the first slew rate control capacitor is coupled to the first node.

[0079] Example 2. The SMPS of Example 1, further comprising: an inductor coupled between the switch node and an output terminal of the SMPS; and a capacitor coupled between the output terminal of the SMPS and the reference voltage node.

[0080] Example 3. The SMPS of Example 1, wherein the high-side switch and the low-side switch are N-type transistors, wherein the high-side switch and the low-side switch are configured to be alternately turned on and off during operation of the SMPS.

[0081] Example 4. The SMPS of example 3, wherein a second terminal of the first slew rate control capacitor is coupled to the second node.

[0082] Example 5. An SMPS according to Example 4, wherein a first ratio between a first value of the first charging current and a capacitance of the first slew rate control capacitor is equal to a first predetermined slew rate of a rising edge of a voltage at the switch node during switching of the SMPS, and wherein a second ratio between a second value of the second charging current and the capacitance of the first slew rate control capacitor is equal to a second predetermined slew rate of a falling edge of the voltage at the switch node during switching of the SMPS.

[0083] Example 6. The SMPS of Example 5, further comprising a bootstrap capacitor coupled between the switch node and an input terminal of the first switch circuit, wherein the bootstrap capacitor is the first power supply, wherein the bootstrap capacitor is configured to provide the first charging current when the high-side switch is turned on, and is configured to be charged by a power supply voltage when a voltage at the switch node is lower than the power supply voltage.

[0084] Example 7. The SMPS of Example 6, further comprising a power generator configured to generate the power supply voltage, wherein the power generator is the second power supply.

[0085] Example 8. The SMPS of Example 7, wherein the first buffer circuit comprises a first transistor and a second transistor coupled in series between the input terminal of the first switching circuit and the switching node, wherein a control terminal of the first transistor is coupled to the first node, a control terminal of the second transistor is configured to receive the first control signal, and a node between the first transistor and the second transistor is coupled to a control terminal of the high-side switch.

[0086] Example 9. An SMPS according to Example 8, wherein the second buffer circuit includes a third transistor and a fourth transistor coupled in series between the input terminal of the second switch circuit and the reference voltage node, wherein a control terminal of the third transistor is coupled to the second node, a control terminal of the fourth transistor is configured to receive the second control signal, and a node between the third transistor and the fourth transistor is coupled to a control terminal of the low-side switch.

[0087] Example 10. The SMPS of Example 3, wherein a second terminal of the first slew rate control capacitor is coupled to the supply voltage node, wherein the driver circuit further comprises a second slew rate control capacitor coupled between the second node and the switch node.

[0088] Example 11. An SMPS according to Example 10, wherein a first ratio between a first value of the first charging current and a capacitance of the first slew rate control capacitor is equal to a first predetermined slew rate of a rising edge of a voltage at the switch node during switching of the SMPS, and wherein a second ratio between a second value of the second charging current and a capacitance of the second slew rate control capacitor is equal to a second predetermined slew rate of a falling edge of the voltage at the switch node during switching of the SMPS.

[0089] Example 12. The SMPS of Example 3, further comprising: a first voltage divider coupled between the power supply voltage node and the reference voltage node, wherein a second terminal of the first slew rate control capacitor is coupled to an output terminal of the first voltage divider; a second voltage divider coupled between the switch node and the reference voltage node; and a second slew rate control capacitor coupled between the second node and the output terminal of the second voltage divider.

[0090] Example 13. According to one embodiment, a buck converter includes: a high-side switch and a low-side switch, the high-side switch and the low-side switch are coupled in series between a power supply voltage node and a reference voltage node, wherein the high-side switch and the low-side switch are configured to be controlled by a first control signal and a second control signal, respectively; a switch node, the switch node is located between the high-side switch and the low-side switch; a first buffer, the first buffer is coupled between a first node and a control terminal of the high-side switch; a first switch circuit, wherein the control terminal of the first switch circuit is configured to receive the first control signal, wherein when the first control signal is set, the first switch circuit is configured to allow a first charging current provided by a first power supply to the first node to pass through; a second buffer, the second buffer is coupled between a second node and the control terminal of the low-side switch; a second switch circuit, wherein the control terminal of the second switch circuit is configured to receive the second control signal, wherein when the second control signal is set, the second switch circuit is configured to allow a second charging current provided by a second power supply to the second node to pass through; and a first slew rate control capacitor, wherein a first terminal of the first slew rate control capacitor is coupled to the first node.

[0091] Example 14. The buck converter according to Example 13 further includes: a bootstrap capacitor coupled between the switch node and the first switch circuit, wherein the bootstrap capacitor is the first power supply, wherein the bootstrap capacitor is configured to be charged by the power supply voltage when the voltage at the switch node is lower than the power supply voltage; and a power generator configured to generate the power supply voltage, wherein the power generator is the second power supply.

[0092] Example 15. The buck converter of Example 14, wherein a second terminal of the first slew rate control capacitor is coupled to the second node.

[0093] Example 16. The buck converter of Example 14, wherein a second terminal of the first slew rate control capacitor is coupled to the supply voltage node, wherein the buck converter further comprises a second slew rate control capacitor coupled between the second node and the switch node.

[0094] Example 17. The buck converter according to Example 14 further includes: a first voltage divider, which is coupled between the power supply voltage node and the reference voltage node, wherein the second terminal of the first conversion rate control capacitor is coupled to the output terminal of the first voltage divider; a second voltage divider, which is coupled between the switch node and the reference voltage node; and a second conversion rate control capacitor, which is coupled between the second node and the output terminal of the second voltage divider.

[0095] Example 18. According to one embodiment, a buck converter includes: a first power switch, the first power switch is coupled between a power supply voltage node and a switch node, wherein the first power switch is configured to be controlled by a first control signal; a bootstrap capacitor, wherein a first terminal of the bootstrap capacitor is coupled to the switch node; a first buffer, the first buffer is coupled between a first node and a control terminal of the first power switch; a first switching circuit, the first switching circuit is coupled between the first node and a second terminal of the bootstrap capacitor, wherein the first switching circuit is controlled by the first control signal and is configured to allow a first charging current provided by the bootstrap capacitor to pass through when the first control signal is set; and a slew rate control capacitor, wherein a first terminal of the slew rate control capacitor is coupled to the first node.

[0096] Example 19. The buck converter according to Example 18 further includes: a second power switch, the second power switch is coupled between the switch node and a reference voltage node, wherein the second power switch is configured to be controlled by a second control signal; a second buffer, the second buffer is coupled between the second node and a control terminal of the second power switch; and a second switch circuit, the second switch circuit is coupled between the second node and a power supply, wherein the second switch circuit is controlled by the second control signal and is configured to allow a second charging current provided by the power supply to pass through when the second control signal is set.

[0097] Example 20. The buck converter of Example 19, wherein the second terminal of the slew rate control capacitor is coupled to the second node.

[0098] Although the present invention has been described with reference to illustrative examples, the description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative examples and other examples of the present invention will be clear to those skilled in the art when referring to the description. Therefore, the appended claims are intended to cover any such modifications or examples.

Claims

1. A switch mode power supply (SMPS), comprising: a high-side switch coupled between a supply voltage node and a switch node, wherein the high-side switch is configured to be controlled by a first control signal; a low-side switch coupled between the switch node and a reference voltage node, wherein the low-side switch is configured to be controlled by a second control signal; and A driver circuit, the driver circuit being used for the high-side switch and the low-side switch, comprising: a first buffer circuit coupled between a first node and a control terminal of the high-side switch; a first switch circuit, wherein a control terminal of the first switch circuit is configured to receive the first control signal, an input terminal of the first switch circuit is coupled to a first power source, and an output terminal of the first switch circuit is coupled to the first node, wherein the first switch circuit is configured to output a first charging current provided by the first power source when the first control signal is set; a second buffer circuit coupled between a second node and a control terminal of the low-side switch; a second switch circuit, wherein a control terminal of the second switch circuit is configured to receive the second control signal, an input terminal of the second switch circuit is coupled to a second power supply, and an output terminal of the second switch circuit is coupled to the second node, wherein the second switch circuit is configured to output a second charging current provided by the second power supply when the second control signal is set; and A first slew rate control capacitor, wherein a first terminal of the first slew rate control capacitor is coupled to the first node.

2. The SMPS according to claim 1, further comprising: an inductor coupled between the switch node and an output terminal of the SMPS; and A capacitor is coupled between an output terminal of the SMPS and the reference voltage node.

3. The SMPS according to claim 1, wherein: The high-side switch and the low-side switch are N-type transistors, wherein the high-side switch and the low-side switch are configured to be alternately turned on and off during operation of the SMPS.

4. The SMPS according to claim 3, wherein: A second terminal of the first slew rate control capacitor is coupled to the second node.

5. The SMPS according to claim 4, wherein: A first ratio between a first value of the first charging current and the capacitance of the first slew rate control capacitor is equal to a first predetermined slew rate of a rising edge of the voltage of the switch node during switching of the SMPS, wherein a second ratio between a second value of the second charging current and the capacitance of the first slew rate control capacitor is equal to a second predetermined slew rate of a falling edge of the voltage of the switch node during switching of the SMPS.

6. The SMPS of claim 5, further comprising a bootstrap capacitor coupled between the switch node and an input terminal of the first switch circuit, wherein: The bootstrap capacitor is the first power source, wherein the bootstrap capacitor is configured to provide the first charging current when the high-side switch is turned on, and is configured to be charged by a power supply voltage when a voltage at the switch node is lower than the power supply voltage.

7. The SMPS according to claim 6, further comprising a power generator configured to generate the power supply voltage, wherein: The power generator is the second power source.

8. The SMPS according to claim 7, wherein: The first buffer circuit includes a first transistor and a second transistor coupled in series between an input terminal of the first switching circuit and the switching node, wherein a control terminal of the first transistor is coupled to the first node, a control terminal of the second transistor is configured to receive the first control signal, and a node between the first transistor and the second transistor is coupled to a control terminal of the high-side switch.

9. The SMPS according to claim 8, wherein: The second buffer circuit includes a third transistor and a fourth transistor coupled in series between an input terminal of the second switch circuit and the reference voltage node, wherein a control terminal of the third transistor is coupled to the second node, a control terminal of the fourth transistor is configured to receive the second control signal, and a node between the third transistor and the fourth transistor is coupled to a control terminal of the low-side switch.

10. The SMPS according to claim 3, wherein: A second terminal of the first slew rate control capacitor is coupled to the supply voltage node, wherein the driver circuit further includes a second slew rate control capacitor coupled between the second node and the switch node.

11. The SMPS according to claim 10, wherein: A first ratio between a first value of the first charging current and the capacitance of the first slew rate control capacitor is equal to a first predetermined slew rate of a rising edge of the voltage of the switch node during switching of the SMPS, wherein a second ratio between a second value of the second charging current and the capacitance of the second slew rate control capacitor is equal to a second predetermined slew rate of a falling edge of the voltage of the switch node during switching of the SMPS.

12. The SMPS of claim 3, further comprising: a first voltage divider coupled between the supply voltage node and the reference voltage node, wherein the second terminal of the first slew rate control capacitor is coupled to an output terminal of the first voltage divider; a second voltage divider coupled between the switch node and the reference voltage node; and A second slew rate control capacitor is coupled between the second node and an output terminal of the second voltage divider.

13. A buck converter comprising: a high-side switch and a low-side switch, the high-side switch and the low-side switch being coupled in series between a power supply voltage node and a reference voltage node, wherein the high-side switch and the low-side switch are configured to be controlled by a first control signal and a second control signal, respectively; a switch node, the switch node being located between the high-side switch and the low-side switch; a first buffer coupled between a first node and a control terminal of the high-side switch; a first switch circuit, wherein a control terminal of the first switch circuit is configured to receive the first control signal, wherein when the first control signal is set, the first switch circuit is configured to allow a first charging current provided by a first power source to the first node to pass therethrough; a second buffer coupled between a second node and a control terminal of the low-side switch; a second switch circuit, wherein a control terminal of the second switch circuit is configured to receive the second control signal, wherein when the second control signal is set, the second switch circuit is configured to allow a second charging current provided by a second power source to pass through the second node; and A first slew rate control capacitor, wherein a first terminal of the first slew rate control capacitor is coupled to the first node.

14. The buck converter according to claim 13, further comprising: a bootstrap capacitor coupled between the switch node and the first switch circuit, wherein the bootstrap capacitor is the first power supply, wherein the bootstrap capacitor is configured to be charged by a power supply voltage when a voltage at the switch node is lower than the power supply voltage; and A power generator configured to generate the power supply voltage, wherein the power generator is the second power supply.

15. The buck converter according to claim 14, wherein: A second terminal of the first slew rate control capacitor is coupled to the second node.

16. The buck converter according to claim 14, wherein: A second terminal of the first slew rate control capacitor is coupled to the supply voltage node, wherein the buck converter further includes a second slew rate control capacitor coupled between the second node and the switch node.

17. The buck converter of claim 14, further comprising: a first voltage divider coupled between the supply voltage node and the reference voltage node, wherein the second terminal of the first slew rate control capacitor is coupled to an output terminal of the first voltage divider; a second voltage divider coupled between the switch node and the reference voltage node; and A second slew rate control capacitor is coupled between the second node and an output terminal of the second voltage divider.

18. A buck converter comprising: a first power switch coupled between a power supply voltage node and a switch node, wherein the first power switch is configured to be controlled by a first control signal; a bootstrap capacitor, wherein a first terminal of the bootstrap capacitor is coupled to the switch node; a first buffer coupled between a first node and a control terminal of the first power switch; a first switch circuit coupled between the first node and a second terminal of the bootstrap capacitor, wherein the first switch circuit is controlled by the first control signal and configured to pass a first charging current provided by the bootstrap capacitor when the first control signal is set; and A slew rate control capacitor is provided, wherein a first terminal of the slew rate control capacitor is coupled to the first node.

19. The buck converter of claim 18, further comprising: a second power switch, the second power switch being coupled between the switch node and a reference voltage node, wherein the second power switch is configured to be controlled by a second control signal; a second buffer coupled between a second node and a control terminal of the second power switch; and A second switch circuit is coupled between the second node and a power source, wherein the second switch circuit is controlled by the second control signal and is configured to allow a second charging current provided by the power source to pass therethrough when the second control signal is set.

20. The buck converter according to claim 19, wherein A second terminal of the slew rate control capacitor is coupled to the second node.

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