Memory cell structure and memory device

Abstract

The present invention relates to a memory cell structure and a memory device, and to the field of semiconductor technology. In the memory cell structure, since the second end of the second sub-gate is spaced from the second active region, when the first shared contact structure is set, the length of the first shared contact structure can be increased, which not only reduces the contact resistance of the first shared contact structure, but also increases the tolerance of the position deviation of the first shared contact structure, and further improves the performance of the memory cell. In addition, since the second sub-gate is tilted at the staggered vacancy part of the first active region and the second active region, the area of ​​the memory cell will not be increased, which is conducive to the miniaturization of the memory cell structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a storage unit structure and a storage device. Background Art

[0002] Memory devices are key components for storing data in computer systems. Memory devices include dynamic random access memory (DRAM) and static random access memory (SRAM).

[0003] The existing static random access memory device includes multiple memory cell structures. In order to improve the storage speed and power consumption of the memory cell, the layout design of the memory cell is essential. However, in the existing layout design, in order to improve the performance of the memory cell, the area of ​​the memory cell will be increased.

[0004] Based on this, how to improve the performance of the memory cell without increasing the structural area of ​​the memory cell has become a technical problem that those skilled in the art need to solve urgently. Summary of the invention

[0005] Based on this, it is necessary to provide a memory cell structure and a memory device for improving the performance of the memory cell without increasing the structure area of ​​the memory cell.

[0006] In order to achieve the above object, on the one hand, the present invention provides a storage unit structure, comprising:

[0007] A substrate, the substrate comprising a first active region and a second active region sequentially arranged in a first direction; in the first direction, orthographic projections of the first active region and the second active region on a projection line parallel to the second direction partially overlap; the first direction and the second direction are parallel to a plane where the substrate is located, and the first direction is perpendicular to the second direction;

[0008] A first gate and a second gate located at one side of the substrate and arranged along the second direction;

[0009] The first gate includes a first sub-gate and a second sub-gate connected to each other in the first direction; the first sub-gate extends in the first direction and crosses the first active area along the first direction, the second sub-gate includes a first end and a second end, the first end is connected to the first sub-gate, the orthographic projection of the first end on the projection line partially overlaps with the orthographic projection of the second active area on the projection line, and the orthographic projection of the second end on the projection line is spaced from the orthographic projection of the second active area on the projection line; the second gate crosses the second active area along the first direction; the first shared contact structure extends along the second direction, the first shared contact structure connects the second end, and connects the second sub-gate and the second active area between the second gate.

[0010] In one embodiment, in the second direction, the second end portion and the second active region have a first distance, and a first spacer is disposed on a side of the second sub-gate close to the second active region;

[0011] In the second direction, the length of the first interval is greater than or equal to the width of the first sidewall.

[0012] In one embodiment, a first heavily doped region is disposed in the second active region between the second gate and the second end, and the first heavily doped region extends to the end of the second active region in the second direction.

[0013] In one embodiment, the storage unit structure further includes:

[0014] a third active region, the third active region being located on a side of the second active region away from the first active region, the orthographic projection of the third active region on the projection line at least covering the orthographic projection of the first active region on the projection line and the orthographic projection of the second active region on the projection line;

[0015] The second gate extends in the first direction and crosses the third active region.

[0016] In one embodiment, the storage unit structure further includes:

[0017] A third gate is provided, wherein the third gate passes through the third active region, and an orthographic projection of the third gate on the projection line overlaps with an orthographic projection of the first sub-gate on the projection line.

[0018] In one embodiment, the second gate includes a third sub-gate and a fourth sub-gate connected to each other in the first direction; the third sub-gate extends in the first direction and passes through the second active area along the first direction; the fourth sub-gate includes a third end and a fourth end, the third end is connected to the third sub-gate, the orthographic projection of the third end on the projection line partially overlaps with the orthographic projection of the first active area on the projection line, and the orthographic projection of the fourth end on the projection line is spaced apart from the orthographic projection of the first active area on the projection line;

[0019] The second shared contact structure extends along the second direction, and the second shared contact structure is connected to the fourth end and to the first active region between the fourth sub-gate and the first sub-gate.

[0020] In one embodiment, in the second direction, the fourth sub-gate has a second spacing with the first active area, a second sidewall is provided on the side of the fourth end close to the first active area, and in the second direction, a length of the second spacing is greater than or equal to a width of the second sidewall.

[0021] In one of the embodiments, a second heavily doped region is disposed in the first active region between the fourth sub-gate and the fourth end, and the second heavily doped region extends to an end of the first active region in the second direction.

[0022] In one embodiment, the storage unit structure further includes:

[0023] a fourth active region, the fourth active region being located on a side of the first active region away from the second active region, the orthographic projection of the fourth active region on the projection line at least covering the orthographic projection of the first active region on the projection line and the orthographic projection of the second active region on the projection line;

[0024] The first gate extends in the first direction and passes through the fourth active area;

[0025] A fourth gate, wherein the fourth gate passes through the fourth active region, and an orthographic projection of the fourth gate on the projection line overlaps with an orthographic projection of the third sub-gate on the projection line.

[0026] On the other hand, the present application also provides a memory device, which includes at least one memory cell structure described in any one of the above.

[0027] Compared with the prior art, the above technical solution has the following advantages:

[0028] The memory cell structure of the present application includes a substrate, the substrate includes a first active region and a second active region; in a first direction, the first active region and the second active region are arranged alternately; a first gate and a second gate are located on one side of the substrate and arranged along a second direction. The first gate includes a first sub-gate and a second sub-gate connected to each other in the first direction; the first sub-gate passes through the first active region along the first direction, and the second sub-gate includes a first end and a second end, and the first end is connected to the first sub-gate.

[0029] Since the orthographic projection of the first end on the projection line partially overlaps with the orthographic projection of the second active area on the projection line, and the orthographic projection of the second end on the projection line is spaced apart from the orthographic projection of the second active area on the projection line, the second sub-gate can be tiltedly disposed at the intersecting vacant portion of the first active area and the second active area. The first shared contact structure extends along the second direction, and the first shared contact structure connects the second end, and connects the second active area between the second sub-gate and the second gate.

[0030] In the present application, since the second end of the second sub-gate is spaced apart from the second active region, when the first shared contact structure is set, the length of the first shared contact structure can be increased, which not only reduces the contact resistance of the first shared contact structure, but also increases the tolerance of the position deviation of the first shared contact structure, further improving the performance of the memory cell. In addition, since the second sub-gate is tilted at the staggered vacancy portion of the first active region and the second active region, the area of ​​the memory cell will not be increased, which is conducive to the miniaturization of the memory cell structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 A partial structural schematic diagram of a storage unit structure is provided for an embodiment of the present application;

[0033] Figure 2 It is a partial structural schematic diagram of an existing storage unit structure;

[0034] Figure 3 A schematic diagram of another part of the structure of a storage unit provided in an embodiment of the present application;

[0035] Figure 4 for Figure 3 Schematic diagram of the cross-sectional structure along ZZ';

[0036] Figure 5 for Figure 3 Another cross-sectional structural diagram along ZZ';

[0037] Figure 6 A schematic diagram of another part of a storage unit structure provided in an embodiment of the present application;

[0038] Figure 7 A schematic diagram of another part of a storage unit structure provided in an embodiment of the present application;

[0039] Figure 8 A schematic diagram of another part of a storage unit structure provided in an embodiment of the present application;

[0040] Fig. 9 for Figure 8 Schematic diagram of the cross-sectional structure along DD';

[0041] Fig.10 for Figure 8 Another cross-sectional structural diagram along DD';

[0042] Fig.11 A schematic diagram of another part of a storage unit structure provided in an embodiment of the present application;

[0043] Fig.12 A schematic diagram of another part of a storage unit structure provided in an embodiment of the present application;

[0044] Figure 13-Figure 21 A schematic diagram of another part of a storage unit structure provided in an embodiment of the present application;

[0045] Fig. 22 for Fig.12 Another cross-sectional structural diagram along EE'.

[0046] Description of the accompanying drawings: 01-substrate; 02-first active area; 03-second active area; 04-first gate; 04a-first sub-gate; 04b-second sub-gate; 05-second gate; 05a-third sub-gate; 05b-fourth sub-gate; A-first end; B-second end; C-third end; D-fourth end; 06-first shared contact structure; 07-first sidewall; 08-first heavily doped area; 09-third active area; 10-third gate; 11-second shared contact structure; 12-second sidewall; 13-second heavily doped area; 14-fourth active area; 15-fourth gate; 16-independent contact structure; 17-isolation structure; 18-gate oxide layer; 19-offset sidewall structure; 20-LDD lightly doped area; 21-sidewall structure; 22-metal silicide layer; 23-etching stop layer; 24-interlayer dielectric layer; 25a-independent metal contact hole; 25b-first shared contact hole. DETAILED DESCRIPTION

[0047] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0049] It should be understood that when a layer is referred to as being "on," "adjacent to," or "connected to" another layer, it can be directly on, adjacent to, or connected to the other layer, or intervening layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," or "directly connected to" another layer, there are no intervening layers.

[0050] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0051] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0052] refer to Figure 1 , Figure 1 A partial structural schematic diagram of a storage unit structure is provided for an embodiment of the present application; including:

[0053] A substrate 01, the substrate 01 includes a first active area 02 and a second active area 03 arranged in sequence in a first direction X; and in the first direction X, the orthographic projections of the first active area 02 and the second active area 03 on a projection line Q parallel to a second direction Y partially overlap; the first direction X and the second direction Y are parallel to the plane where the substrate 01 is located, and the first direction X is perpendicular to the second direction Y.

[0054] The first gate 04 and the second gate 05 are located at one side of the substrate 01 and arranged along the second direction Y.

[0055] The first gate 04 includes a first sub-gate 04a and a second sub-gate 04b connected to each other in a first direction X; the first sub-gate 04a extends in the first direction X and crosses the first active area 02 along the first direction X; the second sub-gate 04b includes a first end A and a second end B, the first end A is connected to the first sub-gate 04a, the orthographic projection of the first end A on the projection line Q partially overlaps with the orthographic projection of the second active area 03 on the projection line Q, and the orthographic projection of the second end B on the projection line Q is spaced from the orthographic projection of the second active area 03 on the projection line Q; the second gate 05 crosses the second active area 03 along the first direction X; the first shared contact structure 06 extends along the second direction Y, the first shared contact structure 06 is connected to the second end B, and connects the second sub-gate 04b and the second gate 05.

[0056] Specifically, in this embodiment, the first active area 02 and the second active area 03 sequentially arranged in the first direction X extend in the second direction Y. The orthographic projections of the first active area 02 and the second active area 03 on the projection line Q parallel to the second direction Y partially overlap, that is, the first active area 02 and the second active area 03 are staggered.

[0057] A first gate 04 and a second gate 05 are also provided on one side of the substrate 01 where the first active area 02 and the second active area 03 are provided. In the present embodiment, the first gate 04 includes a first sub-gate 04a and a second sub-gate 04b. The first sub-gate 04a extends in the first direction X and passes through the first active area 02. That is, a first transistor is formed at the first active area 02 and the first sub-gate 04a.

[0058] The second sub-gate 04b includes a first end A and a second end B, the first end A is connected to the first sub-gate 04a, and the second end B extends outward. The first end A overlaps with the orthographic projection of the first sub-gate 04a on the projection line Q, and the first end A partially overlaps with the orthographic projection of the second active area 03 on the projection line Q, and the second end B is spaced apart from the orthographic projection of the first end A on the projection line Q. In other words, the second end B and the first end A are not located on the same horizontal line, so that the second sub-gate 04b structure has a spacing with the second active area 03 in the second direction Y. It should be noted that the first sub-gate 04a and the second sub-gate 04b are integrated, and this is only for better explanation of their structure. In addition, the second gate 05 passes through the second active area 03 in the first direction X, and a second transistor is formed on the second active area 03.

[0059] A first shared contact structure 06 is also provided on the upper side of the second active area 03 and the second end B, wherein the first shared contact structure 06 extends along the second direction Y and connects the second end B with the second transistor and the second active area 03 between the second end B, that is, connects the second transistor and the first transistor.

[0060] refer to Figure 2 , Figure 2 It is a partial structural diagram of an existing memory cell structure; the orthographic projection of the existing first gate 04 on the projection line Q partially overlaps with the orthographic projection of the second active area 03 on the projection line Q. Since the first shared contact structure 06 is located in the overlapping area, the contact resistance of the first shared contact structure 06 is large, and the offset tolerance of the first shared contact structure 06 is low.

[0061] and Figure 1 In the present application, in the second direction Y, a gap is provided between the second end B of the second sub-gate 04b and the second active area 03 to increase the length of the first shared contact structure 06, which not only reduces the contact resistance of the first shared contact structure 06, but also increases the tolerance of the position deviation of the first shared contact structure 06, thereby further improving the performance of the storage unit.

[0062] Since the second active area 03 and the first active area 02 are offset, in the memory cell structure, the portion of the first active area 02 that does not overlap with the second active area 03 on the projection line Q is left vacant. The present application tilts the second sub-gate 04b in the vacant area, thereby reducing the contact resistance of the first shared contact structure 06 and increasing the tolerance for position deviation of the first shared contact structure 06 without increasing the area of ​​the memory cell structure, which is beneficial to the miniaturization of the memory cell structure.

[0063] Optionally, in another embodiment of the present application, refer to Figure 3 , Figure 3 Another partial structural diagram of a storage unit structure provided in an embodiment of the present application; Figure 4 , Figure 4 for Figure 3 Schematic diagram of the cross-sectional structure along ZZ′; in the second direction Y, the second end B has a first distance H from the second active area 03 , and a first spacer 07 is disposed on a side of the second sub-gate 04 b close to the second active area 03 .

[0064] In the second direction Y, the length of the first interval H is greater than or equal to the width of the first sidewall 07 .

[0065] Specifically, in the second direction Y, there is a first spacing H between the second end B of the second sub-gate 04b and the second active area 03, and a shallow trench isolation structure is provided in the substrate 01 of the first spacing H, and the shallow trench isolation structure isolates the second active area 03 from the second sub-gate 04b. It should be noted that a first sidewall 07 is also provided on the side of the second sub-gate 04b close to the second active area 03, and the orthographic projection of the first sidewall 07 on the substrate 01 does not overlap with the second active area 03. It should be noted that Figure 3 For the sake of clarity, the first side wall 07 is not drawn.

[0066] In the existing structure, since the second sub-gate 04b and the orthographic projection of the second active area 03 on the projection line Q partially overlap, the second sub-gate 04b will cover part of the second active area 03. At this time, there is a first side wall 07 on the side of the second sub-gate 04b close to the second gate 05. When the first shared contact structure 06 is formed, it is very easy to etch through the first side wall 07 of the second sub-gate 04b during etching, resulting in the formed first shared contact structure 06 being connected to the lightly doped area below the first side wall 07, thereby generating leakage current.

[0067] and Figure 4 In the present application, a first spacing H is set between the second end B of the second sub-gate 04b and the second active area 03, and the width of the first side wall 07 of the second sub-gate 04b is set to be less than or equal to the first spacing H. At this time, even if part of the first side wall 07 is etched away, since the lower side of the first side wall 07 is a shallow trench isolation structure, leakage current is avoided.

[0068] Optionally, in another embodiment of the present application, refer to Figure 5 , Figure 5 for Figure 3 Another schematic cross-sectional structure diagram along ZZ′; the second active region 03 between the second gate 05 and the second end B is provided with a first heavily doped region 08 , and the first heavily doped region 08 extends in the second direction Y to the end of the second active region 03 .

[0069] Specifically, in this embodiment, the second active region 03 between the second gate 05 and the second end B is provided with a first heavily doped region 08, and the first heavily doped region 08 is a P-type heavily doped region, that is, the second transistor is a PMOS tube. In order to avoid leakage current caused by the first shared contact structure 06 contacting the lightly doped region, the embodiment of the present application extends the P-type heavily doped region in the second direction Y to the end of the second active region 03. At this time, the formed first shared contact structure 06 will only form an ohmic contact with the P-type heavily doped region, and will not generate leakage current.

[0070] Optionally, in another embodiment of the present application, refer to Figure 6 , Figure 6 A schematic diagram of another part of a storage unit structure provided in an embodiment of the present application; the storage unit structure also includes:

[0071] The third active area 09 is located on a side of the second active area 03 away from the first active area 02 , and the orthographic projection of the third active area 09 on the projection line Q at least covers the orthographic projection of the first active area 02 on the projection line Q and the orthographic projection of the second active area 03 on the projection line Q.

[0072] The second gate 05 extends in the first direction X and passes through the third active region 09 .

[0073] Specifically, in the first direction X, the third active area 09 is located on a side of the second active area 03 away from the first active area 02, the third active area 09 extends in the second direction Y, and the length of the third active area 09 in the second direction Y is greater than that of the first active area 02 or the second active area 03, and the orthographic projection on the projection line Q at least covers the orthographic projection of the first active area 02 on the projection line Q and the orthographic projection of the second active area 03 on the projection line Q.

[0074] The second gate 05 extends in the first direction X and passes through the third active area 09, that is, a third transistor is formed at the intersection of the second gate 05 and the third active area 09, and the gate of the third transistor is the same as the gate of the second transistor. It should be noted that the third transistor is an N-type transistor.

[0075] Optionally, in another embodiment of the present application, Figure 6 As shown, the storage unit structure also includes:

[0076] The third gate 10 passes through the third active region 09 , and an orthographic projection of the third gate 10 on the projection line Q overlaps with an orthographic projection of the first sub-gate 04 a on the projection line Q.

[0077] Specifically, the third gate 10 passes through the third active area 09, and a fourth transistor is formed at the intersection of the third gate 10 and the third active area 09. The fourth transistor is of the same type as the third transistor, both of which are N-type transistors. At this time, on the third active area 09, side walls and source or drain are respectively provided on both sides of the second gate 05 and the third gate 10, which are not marked in the figure, wherein the source or drain between the third transistor and the fourth transistor can be shared.

[0078] The orthographic projection of the third gate 10 on the projection line Q overlaps with the orthographic projection of the first sub-gate 04a on the projection line Q, which means that the third gate 10 and the second end B of the second sub-gate 04b are staggered in the first direction X, that is, the central axis of the third gate 10 in the first direction X is spaced from the central axis of the second end B in the first direction X, which can reduce the possibility of accidental connection between the first gate 04 and the third gate 10.

[0079] In the existing manufacturing process, the actual gate morphology is not an ideal rectangle, especially at the end of the gate, there will be significant deformation. In the present application, in order to reduce the possibility of accidental connection, the length of the third gate 10 close to the second active area 03 can be increased by a certain area, for example Figure 6 The increase in the middle width L compared to the existing one is conducive to making the morphology of the third gate 10 in the overlapping area with the third active area 09 more uniform, which is further conducive to stabilizing the electrical performance of the fourth transistor.

[0080] Optionally, in another embodiment of the present application, refer to Figure 7 , Figure 7 A schematic diagram of another part of the structure of a storage unit structure provided in an embodiment of the present application; the second gate 05 includes a third sub-gate 05a and a fourth sub-gate 05b connected to each other in a first direction X; the third sub-gate 05a extends in the first direction X and passes through the second active area 03 along the first direction X, the fourth sub-gate 05b includes a third end C and a fourth end D, the third end C is connected to the third sub-gate 05a, the orthographic projection of the third end C on the projection line Q partially overlaps with the orthographic projection of the first active area 02 on the projection line Q, and the orthographic projection of the fourth end D on the projection line Q is spaced from the orthographic projection of the first active area 02 on the projection line Q.

[0081] The second shared contact structure 11 extends along the second direction Y, and the second shared contact structure 11 is connected to the fourth end D and to the first active region 02 between the fourth sub-gate 05 b and the first sub-gate 04 a .

[0082] Specifically, in this embodiment, the second gate 05 may further include a third sub-gate 05a and a fourth sub-gate 05b, wherein the third sub-gate 05a extends in the first direction X and passes through the second active region 03, thereby forming a second transistor.

[0083] In addition, the fourth sub-gate 05b includes a third end C and a fourth end D, the third end C is connected to the third sub-gate 05a, and the fourth end D extends outward. The third end C overlaps with the orthographic projection of the third sub-gate 05a on the projection line Q, and the third end C partially overlaps with the orthographic projection of the first active area 02 on the projection line Q, and the fourth end D is spaced from the orthographic projection of the third end C on the projection line Q. In other words, the fourth end D and the third end C are not located on the same horizontal line, so that the fourth sub-gate 05b structure has a spacing with the first active area 02 in the second direction Y. It should be noted that the third sub-gate 05a and the fourth sub-gate 05b are integrated, and this is only for better explanation of their structure.

[0084] It should be noted that a second shared contact structure 11 is also provided on the upper side of the first active area 02 and the fourth end D, wherein the second shared contact structure 11 extends along the second direction Y and connects the fourth end D with the first transistor and the first active area 02 between the fourth end D, that is, connects the first transistor and the second transistor.

[0085] In the second direction Y, a gap is provided between the fourth end D of the fourth sub-gate 05b and the first active area 02 to increase the length of the second shared contact structure 11, which not only reduces the contact resistance of the second shared contact structure 11, but also increases the tolerance of the position deviation of the second shared contact structure 11, thereby further improving the performance of the storage unit.

[0086] In addition, the embodiment of the present application sets the fourth sub-gate 05b in the vacant area of ​​the part that does not overlap with the second active area 03 on the projection line Q on one side of the first active area 02, thereby reducing the contact resistance of the second shared contact structure 11, increasing the tolerance of the position deviation of the second shared contact structure 11, and not increasing the area of ​​the memory cell structure, which is conducive to the miniaturization of the memory cell structure.

[0087] The second sub-gate 04b and the fourth sub-gate 05b are designed in this way, so that the performance of the memory cell structure can be improved to a greater extent.

[0088] Optionally, in another embodiment of the present application, refer to Figure 8 , Figure 8 A schematic diagram of another part of a storage unit structure provided in an embodiment of the present application; Fig. 9 , Fig. 9 for Figure 8 Schematic diagram of the cross-sectional structure along DD'; in the second direction Y, the fourth end D has a second spacing h with the first active area 02, and a second sidewall 12 is provided on the side of the fourth sub-gate 05b close to the first active area 02, and in the second direction Y, the length of the second spacing h is greater than or equal to the width of the second sidewall 12.

[0089] Specifically, in the second direction Y, there is a second spacing h between the fourth end D of the fourth sub-gate 05b and the first active area 02, and the second spacing h is provided with a shallow trench isolation structure, and the shallow trench isolation structure isolates the first active area 02 from the fourth sub-gate 05b. It should be noted that a second sidewall spacer 12 is also provided on the side of the fourth sub-gate 05b close to the first active area 02, and the lower side of the second sidewall spacer 12 does not overlap with the first active area 02.

[0090] In the existing structure, since the fourth sub-gate 05b partially overlaps with the orthographic projection of the first active area 02 on the projection line Q, the fourth sub-gate 05b will cover part of the first active area 02. At this time, the fourth sub-gate 05b has a second side wall 12 on the side close to the first gate 04. When the second shared contact structure 11 is formed, it is very easy to etch through the second side wall 12 of the fourth sub-gate 05b during etching, resulting in the formed second shared contact structure 11 being connected to the lightly doped area below the second side wall 12, thereby generating leakage current.

[0091] and Fig. 9 In the present application, a second spacing h is set between the fourth end D of the fourth sub-gate 05b and the first active area 02, and the width of the second side wall 12 of the fourth sub-gate 05b is set to be less than or equal to the second spacing h. At this time, even if part of the second side wall 12 is etched away, since the lower side of the second side wall 12 is a shallow trench isolation structure, leakage current is also avoided.

[0092] Optionally, in another embodiment of the present application, refer to Fig.10 , Fig.10 for Figure 8 Another schematic cross-sectional structure diagram along DD'; the first active region 02 between the fourth sub-gate 05b and the fourth end D is provided with a second heavily doped region 13, and the second heavily doped region 13 extends in the second direction Y to the end of the first active region 02.

[0093] Specifically, in this embodiment, the first active region 02 between the first gate 04 and the fourth end D is provided with a second heavily doped region 13, and the second heavily doped region 13 is a P-type heavily doped region, that is, the first transistor is a PMOS tube. In order to avoid leakage current caused by the second shared contact structure 11 contacting the lightly doped region, the embodiment of the present application extends the P-type heavily doped region in the second direction Y to the end of the first active region 02. At this time, the second shared contact structure 11 will only form an ohmic contact with the P-type heavily doped region, and no leakage current will be generated.

[0094] Optionally, in another embodiment of the present application, refer to Fig.11 , Fig.11A schematic diagram of another part of a storage unit structure provided in an embodiment of the present application; the storage unit structure also includes:

[0095] The fourth active area 14 is located on the side of the first active area 02 away from the second active area 03 ; the orthographic projection of the fourth active area 14 on the projection line Q at least covers the orthographic projection of the first active area 02 on the projection line Q and the orthographic projection of the second active area 03 on the projection line Q.

[0096] The first gate 04 extends in the first direction X and passes through the fourth active region 14 .

[0097] The fourth gate 15 passes through the fourth active region 14 , and an orthographic projection of the fourth gate 15 on the projection line Q overlaps with an orthographic projection of the third sub-gate 05 a on the projection line Q.

[0098] Specifically, in the first direction X, the fourth active area 14 is located on a side of the first active area 02 away from the second active area 03, the fourth active area 14 extends in the second direction Y, and the length of the fourth active area 14 in the second direction Y is greater than that of the first active area 02 or the second active area 03, and the orthographic projection on the projection line Q at least covers the orthographic projection of the first active area 02 on the projection line Q and the orthographic projection of the second active area 03 on the projection line Q. It should be noted that the orthographic projections of the fourth active area 14 and the third active area 09 on the projection line Q may overlap.

[0099] The first gate 04 extends in the first direction X and passes through the fourth active area 14, that is, a fifth transistor is formed at the intersection of the first gate 04 and the fourth active area 14, and the gate of the fifth transistor is the same as the gate of the first transistor. It should be noted that the fifth transistor is an N-type transistor.

[0100] In addition, the fourth gate 15 passes through the fourth active area 14, and a sixth transistor is formed at the intersection of the fourth gate 15 and the fourth active area 14. The sixth transistor is of the same type as the fifth transistor, both of which are N-type transistors. At this time, on the fourth active area 14, side walls and source or drain are respectively arranged on both sides of the first gate 04 and the fourth gate 15, which are not drawn in the figure, wherein the source or drain between the fifth transistor and the sixth transistor can be shared.

[0101] The orthographic projection of the fourth gate 15 on the projection line Q overlaps with the orthographic projection of the third sub-gate 05a on the projection line Q, which means that the fourth gate 15 and the second end B of the fourth sub-gate 05b are staggered in the first direction X, that is, the central axis of the fourth gate 15 in the first direction X and the central axis of the fourth end D in the first direction X are spaced apart, which can reduce the possibility of accidental connection between the first gate 04 and the fourth gate 15.

[0102] In the present application, since the possibility of accidental connection is reduced, the length of the fourth gate 15 close to the second active region 03 can be increased by a certain area, for example Fig.11 The increase in the length m of the fourth gate 15 is beneficial to making the morphology of the fourth gate 15 in the overlapping area with the fourth active area 14 more uniform, which is further beneficial to stabilizing the electrical performance of the sixth transistor.

[0103] It should be noted that, in this embodiment, the first transistor is a first PU transistor, the second transistor is a second PU transistor, the third transistor is a first PD transistor, the fourth transistor is a first PG transistor, the fifth transistor is a second PD transistor, and the sixth transistor is a second PG transistor. When forming these transistors, refer to Fig.12 , Fig.12 A schematic diagram of another part of the structure of a storage unit structure provided in an embodiment of the present application; it also includes forming side walls on both sides of the gate (not drawn in the figure), and forming independent contact structures 16 at the source and drain of each transistor. It should be noted that the other independent contact structures 16 are the same as the existing structures and are not specifically limited here.

[0104] In the examples of this application, refer to Figure 13-Figure 21 , Figure 13-Figure 21 This is another schematic diagram of a part of a memory cell structure provided in an embodiment of the present application; in order to clearly illustrate the formation process, the present application also provides a method for preparing a memory cell structure. Fig.12 Take the DD'' section in the figure as an example to illustrate.

[0105] S101: Fig.13 As shown, a substrate 01 is provided, and an isolation structure 17 and a first active area 02 are formed in the substrate 01, a first sub-gate 04a is formed on the upper side of the first active area 02, and a fourth sub-gate 05b is formed on the upper side of the isolation structure 17. It should be noted that a gate oxide layer 18 is also provided between the first sub-gate 04a and the fourth sub-gate 05b and the substrate 01.

[0106] S102: Fig.14 As shown, offset spacer structures 19 are formed on both sides of the first sub-gate 04a and the fourth sub-gate 05b.

[0107] S103: Fig.15 As shown, LDD lightly doped regions 20 are formed in the first active region 02 on both sides of the first sub-gate 04a.

[0108] S104: Fig.16As shown, spacer structures 21 are formed on both sides of the first sub-gate 04a and the fourth sub-gate 05b, respectively, wherein the spacer of the fourth sub-gate 05b close to the first sub-gate 04a is the first spacer 07.

[0109] S105: Fig.17 As shown, with the sidewall structure 21 as the injection barrier layer, P-type heavy doping is performed in the first active region 02 on both sides of the first sub-gate 04a to form a second heavily doped region 13, which is the source or drain of the first transistor. It should be noted that the side close to the fourth sub-gate 05b can be a drain to connect to the second transistor.

[0110] S106: Fig.18 As shown, a metal silicide layer 22 is formed on the first sub-gate 04a, the fourth sub-gate 05b, the source and the drain to enhance the electrical contact performance.

[0111] S107: Fig.19 As shown, an etching stop layer 23 and an interlayer dielectric layer 24 are sequentially deposited on one side of the metal silicide layer 22 and the spacer structure 21, and the surface is planarized.

[0112] S108: Fig. 20 As shown, the interlayer dielectric layer 24 and the etch stop layer 23 are etched to form metal contact holes, wherein the metal contact hole of the source region of the first sub-gate 04a is an independent metal contact hole 25a, and the metal contact hole between the fourth sub-gate 05b structure and the first sub-gate 04a is a first shared contact hole 25b.

[0113] S109: Fig.21 As shown, metal material is filled in the metal contact hole to form a contact structure. For example, the first shared contact hole 25 b contains the second shared contact structure 11 , and the independent metal contact hole 25 a contains the independent contact structure 16 .

[0114] It should be noted that the formation method of other transistors is the same as the above method, refer to Fig. 22 , Fig. 22 for Fig.12 Another schematic diagram of the cross-sectional structure along EE'; the contact structures are all independent contact structures 16, which are described here as examples and will not be described in detail.

[0115] In SRAM memory devices, the area of ​​the memory cell structure is an important parameter, which is directly related to the storage density per unit area. Since the gate length, sidewall width, and distance from the contact electrode to the sidewall of the PG transistor and the PD transistor determine the width of the memory cell, and the extended sub-gate is set at the original vacant position in the present application, the area of ​​the SRAM memory cell will not be increased, that is, the width and length of the memory cell are the same as those of the conventional SRAM cell. In other words, the performance of the memory cell is further improved without changing the area of ​​the memory cell.

[0116] Based on the above storage unit structure, the present application also provides a storage device, the storage device includes at least one of the above storage units. It should be noted that since the storage device is composed of multiple storage unit structures, the storage device also has the effects achieved by the storage unit structure. Therefore, it will not be repeated here.

[0117] In the description of this specification, the description with reference to the terms "some embodiments", "another embodiment", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0118] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0119] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A storage unit structure, characterized in that: include: A substrate, the substrate comprising a first active region and a second active region sequentially arranged in a first direction; in the first direction, orthographic projections of the first active region and the second active region on a projection line parallel to the second direction partially overlap; the first direction and the second direction are parallel to a plane where the substrate is located, and the first direction is perpendicular to the second direction; A first gate and a second gate located at one side of the substrate and arranged along the second direction; The first gate includes a first sub-gate and a second sub-gate connected to each other in the first direction; the first sub-gate extends in the first direction and crosses the first active area along the first direction, the second sub-gate includes a first end and a second end, the first end is connected to the first sub-gate, the orthographic projection of the first end on the projection line partially overlaps with the orthographic projection of the second active area on the projection line, and the orthographic projection of the second end on the projection line is spaced from the orthographic projection of the second active area on the projection line; the second gate crosses the second active area along the first direction; the first shared contact structure extends along the second direction, the first shared contact structure connects the second end, and connects the second sub-gate and the second active area between the second gate.

2. The storage unit structure according to claim 1, characterized in that: In the second direction, the second end portion and the second active region have a first distance, and a first spacer is disposed on a side of the second sub-gate close to the second active region; In the second direction, the length of the first interval is greater than or equal to the width of the first sidewall.

3. The storage unit structure according to claim 1, characterized in that: A first heavily doped region is disposed in the second active region between the second gate and the second end, and the first heavily doped region extends to the end of the second active region in the second direction.

4. The storage unit structure according to claim 1, characterized in that: The storage unit structure also includes: a third active region, the third active region being located on a side of the second active region away from the first active region, the orthographic projection of the third active region on the projection line at least covering the orthographic projection of the first active region on the projection line and the orthographic projection of the second active region on the projection line; The second gate extends in the first direction and crosses the third active region.

5. The storage unit structure according to claim 4, characterized in that: The storage unit structure also includes: A third gate is provided, wherein the third gate passes through the third active region, and an orthographic projection of the third gate on the projection line overlaps with an orthographic projection of the first sub-gate on the projection line.

6. The memory cell structure according to claim 1, characterized in that: The second gate includes a third sub-gate and a fourth sub-gate connected to each other in the first direction; the third sub-gate extends in the first direction and passes through the second active area along the first direction; the fourth sub-gate includes a third end and a fourth end, the third end is connected to the third sub-gate, the orthographic projection of the third end on the projection line partially overlaps with the orthographic projection of the first active area on the projection line, and the orthographic projection of the fourth end on the projection line is spaced from the orthographic projection of the first active area on the projection line; The second shared contact structure extends along the second direction, and the second shared contact structure is connected to the fourth end and to the first active region between the fourth sub-gate and the first sub-gate.

7. The storage unit structure according to claim 6, characterized in that: In the second direction, the fourth sub-gate has a second spacing with the first active area, a second sidewall is arranged on the side of the fourth end close to the first active area, and in the second direction, a length of the second spacing is greater than or equal to a width of the second sidewall.

8. The storage unit structure according to claim 6, characterized in that: A second heavily doped region is disposed in the first active region between the fourth sub-gate and the fourth end, and the second heavily doped region extends to an end of the first active region in the second direction.

9. The storage unit structure according to claim 8, characterized in that: The storage unit structure also includes: a fourth active region, the fourth active region being located on a side of the first active region away from the second active region, the orthographic projection of the fourth active region on the projection line at least covering the orthographic projection of the first active region on the projection line and the orthographic projection of the second active region on the projection line; The first gate extends in the first direction and passes through the fourth active area; A fourth gate, wherein the fourth gate passes through the fourth active region, and an orthographic projection of the fourth gate on the projection line overlaps with an orthographic projection of the third sub-gate on the projection line.

10. A storage device, characterized in that: The memory device comprises at least one memory cell structure according to any one of claims 1 to 9.

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