Method for manufacturing mosfet

Abstract

A method of manufacturing a semiconductor power device, the method comprising forming at least two trench regions within a semiconductor region; etching each trench region such that a mesa region extends over an upper surface of each trench region; and forming a plurality of spacers, wherein the spacers are over each trench region and adjacent the mesa region.

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor device and a method of manufacturing a power semiconductor device, and in particular, but not exclusively, the present disclosure relates to a split-gate metal oxide semiconductor field effect transistor (MOSFET). Background Art

[0002] Trench metal oxide semiconductor field effect transistors (MOSFETs) are widely known and are used in many applications. In a trench MOSFET, current is conducted vertically from one surface of the MOSFET to the other surface of the MOSFET.

[0003] The desire to produce MOSFET devices with reduced cell pitches, for example, with cell pitches less than 1.0 μm or less than 800 nm, increases the reliance on lithographic definition and alignment tolerances to avoid source-gate shorts. Typically, the minimum device pitch available is about 1 μm, with a mesa region having a width of about 500 nm and a contact width of about 200 nm. To reduce the cell pitch, other device dimensions may need to be reduced. Lithography and contact-to-trench alignment are limiting factors in achieving such reduced cell pitch and device dimensions.

[0004] Any misalignment of the MOSFET's source contact and therefore deviation in the contact-to-trench distance forces a heavy dose of implanted p-type dopant (boron in some examples) into the conducting channel on one side of the cell, while depriving the other side of the cell of p-type dopant. This results in a large difference in the threshold voltage (V T ) imbalance, which in turn affects the on-resistance (R ON ) and durability have a knock-on effect.

[0005] As an example, Figure 1 A cross section of a prior art split-gate MOSFET is schematically shown. As the cell pitch shrinks, it becomes challenging to print smaller feature sizes using available tools. The source contact and gate pickup contact of the device must be precisely positioned to avoid shorting between the gate and source. Throughout the application, the source contact may also refer to the source contact region, n+ source contact region, or n-type doped region.

[0006] US 7,579,649 B2 relates to a device having a source region arranged above an insulated gate in a trench, and US 2020 / 0243679 A1 relates to a device in which a source metallization is arranged above a gate trench of a semiconductor device. Summary of the invention

[0007] Various aspects and preferred features are set out in the appended claims.

[0008] According to a first aspect of the present disclosure, there is provided a method for manufacturing a semiconductor power device, the method comprising:

[0009] forming at least two trench regions in the semiconductor region, wherein two laterally adjacent trench regions are separated by a mesa region of the semiconductor region;

[0010] etching each trench region so that the mesa region extends above an upper surface of each trench region;

[0011] forming a plurality of spacers, wherein the spacers are located above each trench region and adjacent to the mesa region;

[0012] forming an insulating region over an upper surface of the device; and

[0013] The insulating region is etched.

[0014] The steps of the method disclosed herein can be performed in the order listed above. In particular, the step of etching the insulating region can be performed after the step of forming a plurality of spacers. This allows the etching process to be limited by the spacers, that is, the width or depth of the etched region is determined by the spacers. Alternatively, the step of forming the contact region of the conductive type can be limited by the spacers so that the position of the contact region is determined by the spacers.

[0015] The insulating regions and spacers can have high etch selectivity. In other words, the materials used for the insulating regions and spacers can be etched at significantly different etch rates when exposed to a given etchant. This allows the insulating regions to be etched and the etching process to stop on the surface of the spacers or at a low depth within the spacers.

[0016] Etching the insulating regions may include performing an etching process that terminates on or within the plurality of spacers. This increases the tolerance of the etching process and allows for better control of the etched regions without using additional photolithography steps. This allows for the formation of devices with reduced cell pitch.

[0017] Etching the insulating region may include etching insulating material above the trench region to form an etched gate recess. Etching the insulating region may include etching insulating material above the trench region and etching a semiconductor or conductive region within the trench region. The width of the etched gate recess may be limited by a spacer. This laterally aligns the etched gate recess so that it prevents a subsequently formed gate contact from contacting the mesa region and subsequently shorting the device.

[0018] The method may further include forming a gate contact by depositing a conductive material in the etched gate recess. The conductive material may be n-type doped polysilicon, and more specifically n+ polysilicon.

[0019] Etching the insulating region may include etching the insulating material above the mesa region to form an etched source recess. The depth of the etched source recess may be limited by a spacer. This prevents the etched source recess from extending downward into the trench region, so that it prevents a subsequently formed source contact from contacting the trench region (particularly the gate conductive region of the trench) and subsequently shorting the device.

[0020] The method may further include forming a source contact by depositing a conductive material in the etched source recess.

[0021] Etching the insulating regions may include performing an etching process that terminates on an upper surface of the mesa regions.

[0022] The method may further include forming a source contact by depositing a conductive material over an upper surface of the mesa region. The source contact may be located entirely over the semiconductor region.

[0023] In some examples, the insulating regions and spacers may not have high etch selectivity. An etching process that terminates on the upper surface of the mesa region may stop at the upper surface of the mesa region. This allows a subsequently formed source contact to be formed completely above the semiconductor region. When the mesa region extends above the upper surface of each trench region, this prevents a subsequently formed source contact from contacting the trench region (particularly the gate conductive region of the trench) and subsequently shorting the device.

[0024] After etching each trench region, the method may further include forming a conductive region in each trench region. The conductive region may be formed so that the mesa region extends above the upper surface of the conductive region. Etching the trench region may include etching a trench recess having a depth so that the conductive region formed subsequently does not extend to the upper surface of the mesa region.

[0025] The conductive region may include a gate conductive region. Forming each trench region may include forming a separate gate trench region having a gate conductive region within an upper region of each separate gate trench region. Etching each trench region may include etching the gate conductive region so that the mesa region extends above an upper surface of the gate conductive region.

[0026] Forming each trench region may include forming a conductive region in the etched trench recess. Etching each trench region may include etching the conductive region such that the mesa region extends above an upper surface of the conductive region.

[0027] The conductive region may include a gate conductive region. Forming each trench region may include forming a separate gate trench region having a gate conductive region within an upper region of each separate gate trench region. Etching each trench region may include etching the gate conductive region so that the mesa region extends above an upper surface of the gate conductive region.

[0028] In other words, etching each trench region such that the mesa region extends above an upper surface of each trench region may include:

[0029] 1) etching a trench recess, and after etching the trench recess, forming a conductive region in the trench recess, wherein the trench recess is etched to a depth such that the mesa region extends above an upper surface of the formed conductive region; and / or

[0030] 2) etching a trench recess, and after etching the trench recess, forming a conductive region within the trench recess, and after forming the conductive region, etching the conductive region so that the mesa region extends above an upper surface of the formed conductive region.

[0031] Before forming the spacer, the method may also include forming a plurality of contact regions of the first conductivity type in the mesa region. Forming the plurality of contact regions may include depositing a dopant of the first conductivity type above the upper surface of the device, and thermally diffusing the dopant of the first conductivity type into the mesa region. This allows for better control of the formation of the plurality of contact regions, so that the formed contact regions of the first conductivity type may each include an upper portion and a lower portion. The lower portion may contact the sidewall of one of the trench regions. The upper portion may be located in the mesa region above the upper surface of the trench region. This allows the source contact to contact the top surface of the contact region while allowing the contact region to be positioned along the sidewall of the trench.

[0032] After forming the spacer, the method may also include forming a plurality of contact regions of a second conductivity type in the mesa region. The second conductivity type may be a conductivity type opposite to the first conductivity type. During the implantation of the contact region of the second conductivity type, the spacer may act as a mask. This allows for better control of the formation of the contact region of the second conductivity type.

[0033] According to another aspect of the present disclosure, a method of manufacturing a semiconductor device having an active region and a gate pickup region is provided, which includes forming a semiconductor device including a source contact in the active region as described above, and forming a semiconductor device including a gate contact in the gate pickup region as described above. The steps of forming the source contact and forming the gate contact can be performed simultaneously. Forming the source contact and the gate contact simultaneously reduces the time and steps required to form the semiconductor device having the active region and the gate pickup region.

[0034] According to another aspect of the present disclosure, there is provided a semiconductor power device formed using the method as described above.

[0035] According to another aspect of the present disclosure, there is provided a semiconductor power device, comprising:

[0036] Semiconductor area;

[0037] at least two trench regions within the semiconductor region, wherein each trench region includes a conductive region, and wherein two laterally adjacent trench regions are separated by a mesa region of the semiconductor region, and wherein the mesa region extends above an upper surface of each trench region;

[0038] two or more contact regions of a first conductivity type located in the mesa region and wherein the contact region is in contact with two adjacent trench regions such that, in use, a channel is formed along a side of each trench region; and

[0039] A plurality of spacers are located above each trench region and adjacent to the mesa region.

[0040] The mesa region extending above the upper surface of the trench region allows the spacer to define subsequently formed source and / or gate contacts or doped conductive regions so that manufacturing tolerances of the device can be improved and cell pitch can be reduced.

[0041] The semiconductor power device may further include an insulating region located above the trench region and / or the mesa region.

[0042] The spacers and insulating regions can have high etch selectivity. In other words, the materials used for the insulating regions and the spacers can be etched at significantly different etch rates when exposed to a given etchant. This allows the insulating regions to be etched and the etching process to stop on the surface of the spacers or at a low depth within the spacers.

[0043] The insulating region may be formed of a material different from that of the spacer.The insulating region may include oxide, and the spacer may include nitride.

[0044] Each trench region may include a conductive region. The device may also include a gate contact coupled to the conductive region of at least one trench region. The gate contact may be laterally located between two spacers. The spacers may be laterally aligned with the etched gate recess so as to prevent a subsequently formed gate contact from contacting the mesa region and subsequently shorting the device.

[0045] The insulating region may be formed of the same material as the spacer.The insulating region and the spacer may both include oxide.

[0046] The contact regions of the first conductivity type may each include an upper portion and a lower portion. The lower portion may contact the sidewall of one of the trench regions. The upper portion may be located in a mesa region above the upper surface of the trench region. This allows the source contact to contact the top surface of the contact region while allowing the contact region to be positioned along the sidewall of the trench.

[0047] The device may include a source contact located completely above the mesa region. When the mesa region extends above the upper surface of each trench region, this prevents a subsequently formed source contact from contacting the trench region (particularly the gate conduction region of the trench) and subsequently shorting the device.

[0048] The trench regions may include split gate trench regions, each split gate trench region including:

[0049] an upper conductive region formed in an upper portion of each separation gate trench region;

[0050] a lower conductive region formed in a lower portion of each separation gate trench region; and

[0051] An insulating layer is formed along the sidewalls and the lower surface of each separation gate trench region and between the upper conductive region and the lower conductive region. A mesa region may extend above the upper surface of the upper conductive region of each trench region.

[0052] The semiconductor device may include a metal oxide semiconductor field effect transistor (MOSFET).

[0053] According to another aspect of the present disclosure, a semiconductor power device having an active region and a gate pickup region is provided, wherein the active region includes a semiconductor device having a source contact as described above, and the gate pickup region includes a semiconductor device having a gate contact as described above.

[0054] The manufacturing method and corresponding equipment disclosed in the present invention have the following advantages over the prior art equipment:

[0055] The self-aligned manufacturing process enables the pitch to be reduced without the need for any additional masks;

[0056] The spacers provide protection against source-gate shorts;

[0057] The ratio of n+ contact area to p+ contact area improves avalanche ruggedness;

[0058] The method can be used to simultaneously form the active region and gate pickup region of the device;

[0059] Fabrication methods enable devices with sub-micron cell pitches; and

[0060] The device can be a low voltage to high voltage MOSFET (25V to 150V). BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Some embodiments of the present disclosure will now be described, by way of example only, and with reference to the accompanying drawings, in which:

[0062] Figure 1 schematically shows a cross section of a prior art split-gate MOSFET;

[0063] Figure 2 Schematically illustrating steps in a method of manufacturing a MOSFET according to an embodiment of the present disclosure;

[0064] Figure 3 Schematically shows the Figure 2 a step of forming a spacer in the method;

[0065] Figure 4 Shows the manufacturing Figure 2 Another step in the method of the MOSFET shown in FIG.

[0066] Figure 5 Shows the manufacturing Figure 2 Another alternative step in the method of the MOSFET shown;

[0067] Figure 6 shows a simulation of steps in a method of manufacturing a MOSFET according to an embodiment of the present disclosure;

[0068] Figure 7 shows a simulated cross section of a split-gate MOSFET according to an embodiment of the present disclosure;

[0069] Figure 8 shows a simulation of the BVdss of a MOSFET according to an embodiment of the present disclosure; and

[0070] Fig. 9 A simulation of the specific on-state resistance of a MOSFET according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0071] Figure 2 (a) to 2(n) schematically illustrate steps in a method of manufacturing a split-gate MOSFET. Figure 2 (a) to 2(n) show the steps of making a region of a MOSFET having two gate trenches 110, but it should be understood that the method can be used to make more than two gate trenches. It should be understood that Figure 2 The steps shown in may show a subset of all steps for making a device, and the method may also include Figure 2 Additional steps before or after the step.

[0072] Figure 2 The steps of the method shown in are performed in the following order from (a) to (n):

[0073] (a) A pad oxide layer 102 is grown on a semiconductor substrate 104. In the depicted example, the substrate is a silicon substrate, but other semiconductor materials may be used instead. A nitride layer 106 is deposited on the pad oxide layer 102. Prior to depositing the nitride layer, another oxide layer (not shown) may be deposited on the pad oxide layer 102. The nitride layer may be Si3N4 and acts as a hard mask or resist layer to protect the mesa regions between the trenches (not shown) during the manufacturing process of the device. In some examples, the p-body and p+ contact regions may be implanted at this stage by implanting with boron in a low energy (30 keV to 180 keV) process;

[0074] (b) A photoresist layer 108 is deposited on the nitride layer 106. The photoresist layer is patterned to define the trenches during the etching process, and thus may only be present over the mesa regions (not shown) between the trenches;

[0075] (c) Two trenches 110 are etched in the semiconductor region 104. The pad oxide layer 102 and the nitride layer 108 are also etched above the trenches. The mesa region 114 is located between adjacent trenches. The photoresist layer 108 can be stripped before etching the semiconductor region 104 (between etching the pad oxide layer 102 and the nitride layer 108 and etching the semiconductor region 104) or after etching the semiconductor region 104. The trenches 110 can be etched deeper than the trenches in the prior art devices (for example, the initial overetch of the trenches can be between 100nm and 300nm, more specifically, the trenches can be etched about 0.15um deeper than known devices) so that the mesa region 114 of the device extends above the upper surface of the trenches of the device. The total trench depth will depend on the V ds (drain-source) rating, the total trench depth can be 2.5μm (at the lowest V ds rated value) to 10μm (at maximum V ds rated value);

[0076] (d) a pad oxide layer 112 is thermally grown or deposited on the inner wall and lower surface of each trench 110 and over the upper surface of the mesa region 114 between adjacent trenches 110;

[0077] (e) Polysilicon (or poly) is deposited in the two trenches and over the upper surface of the device. The poly is planarized using chemical mechanical planarization (CMP). An etching process is performed to etch the poly in the trench 110 so that the source poly is recessed below the upper surface of the trench 110 and forms a buried field plate 116;

[0078] (f) A further etching process is performed to etch back the pad oxide layer 112 in the mesa region 114 and along the sidewalls of the trench 110 above the buried field plate 116 so that the thick oxide liner 118 remains only along the sidewalls adjacent to the buried field plate 116 .

[0079] A further etching process may be performed such that only a thin oxide liner 120 (also referred to as a gate oxide layer) remains along the sidewalls of the mesa region 114 and the trench 110 at a shallower depth than the buried field plate 116 , wherein the thin oxide liner 120 has a thickness substantially less than the thick oxide liner 118 .

[0080] Alternatively, the liner oxide layer 112 may be completely removed along the sidewalls of the mesa region 114 and the trench 110 at a depth shallower than the buried field plate 116. A thin oxide layer 120 is then formed along the sidewalls of the trench 110 at a depth shallower than the buried field plate 116, wherein the thin oxide liner 120 has a thickness substantially less than the thick oxide liner 118. The thin oxide layer 120 may be grown after the formation of the inter-polysilicon oxide 122. The thin oxide layer 120 may be thermally grown at a high temperature (approximately 1100° C.) oxidation to ensure high quality oxide. The thin oxide layer 120 may have a thickness ranging between 30 nm and 80 nm depending on the threshold voltage of the device.

[0081] Then, additional oxide 122 (also referred to as inter-poly oxide) is formed within trench 110 (this may be done using high density plasma chemical vapor deposition or by oxidation), over buried field plate 116 within trench 110. Formation of inter-poly oxide 122 may involve depositing and then etching the oxide.

[0082] Alternatively, both gate oxide layer 120 and inter-poly oxide 122 may be formed in a single oxidation process.

[0083] Then, a conductive polysilicon region is deposited over the device and within each trench 110. The conductive polysilicon region is then planarized using chemical mechanical planarization (CMP) or using a dry etching step. This forms a gate polysilicon region 124. An inter-polysilicon oxide 122 separates the gate polysilicon region 124 from the source polysilicon region 116;

[0084] (g) then stripping or removing the nitride layer 106 from the mesa regions 114 on the upper surface of the device;

[0085] (h) The gate polysilicon region 124 is recessed below the upper surface of the silicon in the mesa region 114. This can be performed using an etching process. The mesa region 114 is protected by the oxide layer 102 which acts as a hard mask;

[0086] (i) performing an etching process to remove the thin oxide layer 120 along both sidewalls of each trench above the upper surface of the gate polysilicon region 126;

[0087] (j) n-type doped polysilicon 126 is deposited over the upper surface of the device, including over the trench 110 and the mesa region 114, so that an n-type doped polysilicon layer 128 is formed over the exposed upper surface of the trench 110, the mesa region 114, and the exposed areas of the sidewalls of the trench. This can be done using chemical vapor deposition (CVD) or using atomic layer deposition (ALD);

[0088] (k) The device is annealed at a high temperature to thermally drive or diffuse dopants from the n-type doped polysilicon layer 126 into the mesa region 114 to form an n-type doped region 128 (also referred to as an n+ source contact region) in the silicon substrate 104 in the mesa region 114 and adjacent to the trench 110. The n-doped region 128 may be formed of arsenic. The n-doped region 128 has an L-shape, which is formed by dopants diffused horizontally and vertically into the mesa region 114.

[0089] The process is done using diffusion rather than implantation, which can damage the silicon and leave interstitial sites after annealing. Therefore, the use of diffusion reduces the risk of defects in the diffusion. Doping by diffusion allows for more precise control of the doping profile by controlling the thermal profile.

[0090] In some examples, n-type doped region 128 has a thickness greater than or equal to 1 nm. The extent (depth and lateral extension) of the N+ source region is determined by the thermal treatment (temperature and time). Typically, the depth will be about 0.2 μm and the lateral extension will be 0.1 μm to 0.3 μm, depending on the width of the mesa region. The length or height of n-type doped region 128 can extend deeper or shallower within the p-body region than shown in the figure, although it is advantageous for n-type doped region 128 not to extend within the channel formed along the sidewalls of trench 110;

[0091] (l) A silicon isotropic etch is performed on the device. An isotropic etch etches in all directions simultaneously. The etch step may be an overetch to ensure that the etchant completely (across the wafer) removes some of the silicon of the layer we want to etch. This etch step removes excess polysilicon lines or stringers that form on the vertical edges of the device. If left on the device, these could cause the device to short. A further etch step is also performed to remove the oxide hard mask 102.

[0092] (m) forming the spacer 130. Figure 3 As shown, the spacers may be formed by depositing a nitride or oxide layer over the device and using a mask to etch the nitride or oxide material where the spacers are not located. The spacers 130 may be formed of nitride or oxide or a combination of both.

[0093] Nitrides are preferred because subsequent contact etching steps (such as Figure 4 (a) and 5(a) will etch through the oxide (TEOS). Using nitride spacers will ensure that the etching process only occurs in the desired areas.

[0094] When the spacers are formed of nitride, a thin layer of oxide is first deposited to form an oxide liner (not shown), and nitride spacers are formed over the oxide liner using ALD or CVD and etching. The thin oxide layer separates the silicon and nitride to ensure that no charge or contaminants are transferred from the nitride to the silicon.

[0095] A p-body region (not shown) may be formed at this stage using a boron (PB) implant. A p+ contact region (not shown) may also be formed using a BF2 or boron co-implant. The co-implantation ensures good ohmic contact between the metallization and the silicon. The spacers act as a mask to define the location of the p+ contact region, thereby improving the durability of the device. These implants are typically low energy (30keV to 180keV);

[0096] (n) An interlayer dielectric (ILD) 132, in this example silicon dioxide (eg, tetraethyl orthosilicate (TEOS)) is deposited over the surface of the device.

[0097] Figure 2 The steps shown in (a) through 2(g) generally represent a standard way to form a split gate trench. It should be understood that alternative steps may be used to form the split gate trench and that Figure 2 The steps shown in (a) to 2(g).

[0098] In the examples described herein, the device is a silicon-based split-gate trench MOSFET. However, those skilled in the art will appreciate that the device may include alternative semiconductor materials; for example, the device may be silicon carbide (SiC) or gallium nitride (GaN-based. The device may also be an insulated gate bipolar transistor (IGBT).

[0099] Figure 3 The method for forming the spacer 130 is shown in more detail. Figure 2 (m) steps. Figure 3 (a) to (b) show the steps of depositing a nitride or oxide layer 320 over the device, and Figure 3 (c) shows the use of dry ion etching to etch the nitride or oxide material where the spacers 330 are not located. The ion etching process uses vertical bombardment of ions for a fixed period of time, which only etches the material perpendicularly (90°) to the ion beam. This means that the nitride or oxide layer (320) is not etched parallel to the ion beam and the spacers are formed.

[0100] Figure 4 Shows the manufacturing Figure 2 and 3 Another step in the method of forming a source contact for the MOSFET shown in FIG. Figure 4 Follow the steps shown in Figure 2 steps, so that in Figure 2 After step (n) Figure 4 Step (a) in . Figure 4 Many of the features shown in Figure 2 Features shown in , therefore, have the same reference numerals.

[0101] Figure 4 The steps of the method shown in are performed in the order from (a) to (b) as follows:

[0102] (a) Etching ILD 132 in mesa region 114. A masking layer, such as photoresist, is used to etch ILD 132 in the mesa region. In this example, the spacers are nitride spacers, and the etchant is selected to have selectivity to remove only oxide or remove much more oxide than nitride. Therefore, the etching process is self-aligned with spacers 130 because the selective etchant will terminate the etching process on the surface of the nitride spacer or within the nitride spacer. Silicon in mesa region 114 will not be removed. Since mesa region 114 protrudes above the surface of trench 110, as shown in FIG. Figure 2 (h) as described, this allows greater tolerances in etching and photolithography processes, e.g., etched areas;

[0103] (b) A source contact is made by forming a titanium nitride (TiN) silicide layer (not shown) in the etched area to ensure that the ohmic contact between the n+ region 128 and the p+ region (not shown) is as low as possible. A tungsten (W) region is deposited in the etched area to form a plug contact 134. The plug contact fills the width of the etched area between two adjacent ILD regions 132. An aluminum copper (AlCu) alloy is deposited to form a source metallization 136.

[0104] Figure 5 Shows the manufacturing Figure 2 Another step in the method of replacing the MOSFET shown in FIG. Figure 5 The steps shown in Figure 2 After the steps, Figure 5 The steps in Figure 2 Executed after step (n). Figure 5 Many of the features shown in Figure 2 Features shown in , therefore, have the same reference numerals. Figure 5 The steps shown in are used to form the gate contact. Figure 5 The steps can be done with Figure 4 The steps are performed simultaneously on different zones of the same device.

[0105] Figure 5 The steps of the method shown in are performed in the order from (a) to (b) as follows:

[0106] (a) Etching the ILD 132 over the trench 110. A masking layer such as a photoresist is used to etch the ILD 132. In this example, the spacers are nitride spacers, and the etchant is selected to have selectivity to remove only oxide or remove much more oxide than nitride. Therefore, the etching process is self-aligned with the spacers 130 because the selective etchant will terminate the etching process on the surface of the nitride spacers or within the nitride spacers. Therefore, the horizontal width of the etched area is limited by the spacers 130, and the etching process will terminate on the gate polysilicon 124 and will not etch the mesa area. Therefore, this allows for greater tolerances in the etching and lithography processes; for example, etching the area;

[0107] (b) A gate pickup contact is made by forming a titanium nitride (TiN) silicide layer (not shown) in the etched region. A tungsten (W) region is deposited in the etched region to form a plug contact 134. The plug contact fills the width of the etched region between adjacent ILD regions 132. Aluminum-copper alloy is deposited to form gate metallization 138.

[0108] Figure 6 1 shows a simulation of the steps in the method of manufacturing a MOSFET according to an embodiment of the present disclosure. It should be understood that Figure 6 The steps of the method shown in (a) to 6(k) generally correspond to Figure 2 (a) to 2(n) because:

[0109] Figure 6 (a) to 6(c) represent Figure 2 The same steps as (a) to 2(c);

[0110] Figure 6 (d) indicates Figure 2 (d) and a subset of the steps shown in 2(e) until Figure 2 (e) the step of etching polysilicon;

[0111] Figure 6 (e) and 6(f) represent the Figure 2 The same steps as those shown in (f);

[0112] Figure 6 (g) indicates Figure 2 The same steps as shown in (l);

[0113] Figure 6(h) indicates Figure 2 (g) the same steps as in 2(i);

[0114] Figure 6 (i) indicates Figure 2 The same steps as shown in (l);

[0115] Figure 6 (j) indicates Figure 2 The same steps as shown in (m); and

[0116] Figure 6 (k) indicates Figure 2 The same steps as shown in (n).

[0117] Figure 6 The steps of the manufacturing method are shown, which are performed in the following order from (a) to (k):

[0118] (a) forming a layer with a thickness of A pad oxide layer 102;

[0119] (b) A trench hard mask (HM) is deposited over the pad oxide layer 102, which typically includes a nitride layer 106 and a photoresist layer;

[0120] (c) Patterning the photoresist layer 108 using photolithography. Etching the silicon substrate 104, the pad oxide layer 102, the nitride layer 106, and the photoresist layer 108 to form trenches 110 in the device;

[0121] (d) Stripping the photoresist layer. A trench oxide liner 112 is deposited on the inner walls and lower surface of the trenches and over the upper surface of the mesa regions 114 between adjacent trenches. This may be performed by oxidation of the trench sidewalls. A thin, high quality oxide may be thermally grown prior to depositing the thick liner oxide 112. Polysilicon 115 is formed within the trench 110 and over the upper surface of the device. The polysilicon is planarized using chemical mechanical planarization (CMP);

[0122] (e) etching polysilicon within trench 110 such that the polysilicon is recessed below the upper surface of trench 110 and forms buried field plate 116. A further etching step is performed to etch back pad oxide layer 112 in mesa region 114 and along the sidewalls of trench 110 above buried field plate 116 such that thick oxide liner 118 remains along the sidewalls adjacent buried field plate 116, but only thin oxide liner 120 remains along mesa region 114 and the sidewalls of trench 110 at a shallower depth than buried field plate 116, wherein thin oxide liner 120 has a thickness substantially less than thick oxide liner 118. Additional oxide 122 is then formed within trench 110 above buried field plate 116 within trench 110 (this may be accomplished using high density plasma chemical vapor deposition or by oxidation);

[0123] (f) A conductive polysilicon region is then deposited over the device and within each trench 110. The conductive polysilicon region is then planarized using chemical mechanical planarization (CMP) or using a dry etching step. This forms the gate polysilicon region 124;

[0124] (g) above the upper surface of the gate polysilicon region 126, with An isotropic etching process is performed to a depth of 1000 to remove the thin oxide layer 120 along both sidewalls of each trench;

[0125] (h) Over the upper surface of the device, including in the trenches 110 and the mesa regions 114, a thickness of n-type doped polysilicon 126 is formed so that an n-type doped polysilicon layer 128 is formed over the exposed upper surface of the trench 110, the mesa region 114, and the exposed area of ​​the trench sidewall. A rapid thermal processing (RTP) step is performed in which the device is annealed twice at a temperature of 1050° C. for only a few seconds to thermally drive dopants from the n-type doped polysilicon layer 126 into the mesa region 114;

[0126] (i) An etching process is used to remove the nitride hard mask 106. The etching process is performed to remove the polysilicon to A further etching step is performed to remove Figure 6 The area of ​​silicon exposed in step (g) is Depth

[0127] (j) In this example, the thickness is This can be done using oxide spacers such as Figure 3This is accomplished by the method shown. After forming the spacers, a p-body region can be formed at this stage using a boron (PB) implant. This is then followed by a rapid thermal process where the device is annealed at a temperature of 1050°C. After the p-body region is implanted, a p+ contact is implanted beneath the p-body. This is typically a BF2 (boron fluorine) or boron co-implant. This implant helps ensure ohmic contact to the source metallization and silicon. After the implant, a rapid thermal process is performed to anneal or activate the implant. These implants are typically low energy (30keV to 180keV). The oxide spacers act as a mask for the p+ contact implant;

[0128] (k) The thickness of the deposit above the surface of the device is An interlayer dielectric (ILD) 132 or plug is formed, in this example silicon dioxide (e.g., tetraethyl orthosilicate (TEOS)). The TEOS is then planarized using chemical mechanical planarization (CMP). To form the source contact, a TiNi silicide layer (not shown) is formed to ensure that there is a low resistance ohmic contact between the silicon and the metallization. Gate metallization is then formed on the device.

[0129] Figure 6 The steps of the method shown in are simulated as being performed to form a device having a cell pitch of 0.8 μm. It should be understood that Figure 6 The measurements and dimensions given in the examples are examples only, and the device is not limited to these dimensions.

[0130] This results in the final device having Figure 7 The cross section in Figure 7 A simulated cross section of a split-gate MOSFET according to an embodiment of the present disclosure is shown. Many features are similar to Figures 2 to 6 The features shown in , therefore have similar reference numerals. The semiconductor device 600 includes a positively doped n-type voltage maintaining region (or n drift region) 640 formed in a semiconductor substrate. In this example, the n drift region 640 is an epitaxial layer. Although not shown, the device may include a drain or collector region located below the drift region 640. In the example shown, the device includes two gate trenches 610, each extending downward from the upper surface of the n+ contact region 628 into the n drift region 640. During operation, a conductive channel is formed between the n+ contact region 628 and the drift region 640 by applying a positive voltage to the gate.

[0131] Three gate trenches 610 are formed, which are laterally spaced apart from each other. Although only three gate trenches 610 are shown as an example, it should be understood that the device may include more or fewer gate trenches. Each gate trench 610 includes an insulating layer 618, 620 formed along the inner sidewall and lower surface of the gate trench 610. In this example, the insulating layers 618, 620 are oxide layers (e.g., silicon dioxide), but other insulating materials can be used. In the example where the insulating layers 618, 620 are silicon dioxide liners, the silicon dioxide liners 618, 620 can be thermally grown and / or deposited.

[0132] The gate trenches 610 have a split gate structure including a gate conductive polysilicon region 624 formed in an upper portion of each trench 610 and a buried field plate 616 (or a source polysilicon region) formed in a lower portion of each trench 610. The gate polysilicon region 624 and the buried field plate 616 of each trench are separated by an oxide layer 622.

[0133] Along the upper portion, the insulating layer 620 is thinner and the gate conductive region 624 defines a vertical channel. In the lower portion of the gate trench, the insulating layer 618 is thicker than in the upper portion, so the conductive source polysilicon region 616 acts as a field plate at the source potential and is insulated from the drain region of the device by the thicker insulating layer. The gate conductive region 624 and the buried field plate 616 can be formed of a conductive material, such as a metal or doped polysilicon.

[0134] Above the n-drift region 640, and adjacent to and between the gate trenches 610 in the mesa region 614, a p-body region 642 is disposed. The p-body region 642 is a p-type doped semiconductor and may generally extend to a depth in the device that corresponds to or is similar to the depth of the gate conductive region 624. In the example shown, the depth of the p-body region 642 is less than the depth of the gate conductive region 624 to ensure that the gate conductive region 624 can provide switching along the entire length of the p-body region 642. An n+ contact region 628 is disposed above the p-body region 642.

[0135] Adjacent gate trenches 610 are separated by mesa regions 614. P+ contact regions 644 are formed within the mesa regions within p-body regions 642 and between adjacent n+ contact regions 628.

[0136] Figure 8 The simulation of the BVdss of a MOSFET according to an embodiment of the present disclosure is shown. The simulation is performed with a 25V V ds (Drain-Source) ratings for operation of the device. Figure 8 (a) shows the drain potential profile and depletion boundary 750 when the device is in avalanche. Figure 8(b) shows the drain current flow line through the device when the device is in avalanche. These figures show (a): how the drain voltage is supported across the cell in terms of potential (voltage) and depletion boundaries when the device is in avalanche (drain-source voltage > breakdown voltage), and (b): the flow line of the avalanche current (black line) between the drain and source. Figure 8 (c) shows a simulated plot of drain voltage versus drain current, showing at what drain voltage value the device will enter avalanche as a function of drain current. This indicates that the improved device has an increased avalanche voltage, and therefore indicates that the device disclosed herein has improved performance.

[0137] Fig. 9 A simulation of the specific on-state resistance of a MOSFET according to an embodiment of the present disclosure is shown. Fig. 9 (a) shows the on-state current flow lines between source and drain when the device is fully turned on. Fig. 9 (b) shows a simulated graph showing the specific on-state resistance as a function of gate voltage when the device is conducting current. This shows that the on-state resistance is reduced and the channel resistance is reduced.

[0138] Reference numerals

[0139] 102 pad oxide layer 134 plug contact

[0140] 104 silicon substrate 136 source metallization

[0141] 106 Nitride layer 138 Gate pickup metallization 108 Photoresist 320 Oxide or nitride layer 110 gate trench 330 spacer

[0142] 112 Pad oxide layer 600 Semiconductor device

[0143] 114 table area 610 groove

[0144] 115 polysilicon 616 buried field plate

[0145] 116 buried field plate 618 thick oxide line

[0146] 118 thick oxide liner 620 thin oxide layer

[0147] 120 thin oxide liner 622 oxide layer

[0148] 122 oxide layer 624 gate polysilicon

[0149] 124 gate polysilicon region 628 n+ contact region

[0150] 126n-type doped polysilicon 640n drift region

[0151] 128n-type doping region 642p body region

[0152] 130 spacer 644p + contact area 132Interlayer dielectric

Claims

1. A method for manufacturing a semiconductor power device, the method comprising: forming at least two trench regions in a semiconductor region, wherein two laterally adjacent trench regions are separated by a mesa region of the semiconductor region; etching each trench region so that the mesa region extends above an upper surface of each trench region; forming a plurality of spacers, wherein the spacers are located above each trench region and adjacent to the mesa region; forming an insulating region over an upper surface of the device; as well as The insulating region is etched. 2 . The method according to claim 1 , wherein the insulating region and the spacer have a high etching selectivity. 3 . The method of claim 2 , wherein etching the insulating region comprises etching an insulating material over the trench region to form an etched gate recess, and wherein a width of the etched gate recess is limited by the spacer. 4 . The method of claim 3 , wherein the method further comprises forming a gate contact by depositing a conductive material in the etched gate recess. 5 . The method of claim 2 , wherein etching the insulating region comprises etching insulating material above the mesa region to form an etched source recess, wherein a depth of the etched source recess is limited by the spacer.

6. The method of claim 5, further comprising forming a source contact region by depositing a material having a dopant of a first conductivity type over an upper surface of the device, and thermally diffusing the dopant of the first conductivity type into the mesa region.

7. The method of any one of the preceding claims, wherein forming each trench region comprises forming a conductive region in the etched trench recess, and wherein etching each trench region comprises etching the conductive region such that the mesa region extends above an upper surface of the conductive region.

8. The method according to any one of the preceding claims, wherein after etching each trench region, the method further comprises forming a conductive region in each trench region, wherein the conductive region is formed such that the mesa region extends above an upper surface of the conductive region.

9. The method according to any one of the preceding claims, wherein before forming the spacer, the method further comprises forming a plurality of contact regions of the first conductivity type in the mesa region, wherein forming the plurality of contact regions comprises: depositing a dopant of a first conductivity type over an upper surface of the device; as well as The dopant of the first conductivity type is thermally diffused into the mesa region.

10. The method according to any of the preceding claims, wherein after forming the spacer, the method further comprises forming a plurality of contact regions of a second conductivity type within the mesa region, wherein the spacer acts as a mask during implantation of the contact regions of the second conductivity type.

11. A semiconductor power device, comprising: Semiconductor area; at least two trench regions within the semiconductor region, wherein each trench region includes a conductive region, and wherein two laterally adjacent trench regions are separated by a mesa region of the semiconductor region, and wherein the mesa region extends above an upper surface of each trench region; two or more contact regions of a first conductivity type located in the mesa region and wherein the contact regions are in contact with the two adjacent trench regions such that, in use, a channel is formed along a side of each trench region; as well as A plurality of spacers are located above each trench region and adjacent to the mesa region.

12. The semiconductor power device of claim 11, wherein each trench region comprises a conductive region, and wherein the device further comprises a gate contact coupled to the conductive region of at least one trench region, and wherein the gate contact is laterally located between two spacers.

13. A semiconductor power device as claimed in any one of claims 11 to 12, wherein the device comprises a source contact located entirely above the mesa region.

14. The semiconductor device according to any one of claims 11 to 13, wherein the trench region comprises a split gate trench region, the split gate trench region comprising: an upper conductive region formed in an upper portion of each separation gate trench region; a lower conductive region formed in a lower portion of each separation gate trench region; as well as An insulating layer is formed along the sidewalls and the lower surface of each separation gate trench region and between the upper conductive region and the lower conductive region, wherein the mesa region extends above the upper surface of the upper conductive region of each trench region.

15. A semiconductor power device having an active region and a gate pickup region, wherein the active region comprises the semiconductor device having a source contact according to claim 23, and wherein the gate pickup region comprises the semiconductor device having a gate contact according to claim 20.

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