Memory controller and memory system performing data search

Abstract

In certain aspects, a memory system includes a volatile memory device and a memory controller operably coupled to the volatile memory device. The volatile memory device is configured to store a logical-to-physical (L2P) mapping table. The memory controller is configured to maintain the L2P mapping table stored in the volatile memory device such that the L2P mapping table maps a first set of logical addresses to identifiers (IDs) of cached memory blocks, respectively.

Description

Technical Field

[0001] This disclosure relates to storage devices and methods of operating storage devices. Background Technology

[0002] Solid-state drives (SSDs) are non-volatile data storage devices that have gained widespread popularity in recent years due to their numerous advantages over traditional hard disk drives (HDDs), such as faster read and write speeds, durability and reliability, lower power consumption, quiet operation, and smaller form factor. SSDs typically use NAND flash memory for non-volatile storage. Some SSDs, especially enterprise-grade SSDs, also use volatile memory (e.g., dynamic random-access memory, DRAM) to enhance their performance, allowing for faster data access and more efficient read and write operations. Summary of the Invention

[0003] In one aspect, the memory system includes a volatile memory device and a memory controller operatively coupled to the volatile memory device. The volatile memory device is configured to store a logical-to-physical (L2P) mapping table. The memory controller is configured to maintain the L2P mapping table stored in the volatile memory device, such that the L2P mapping table maps a first set of logical addresses to identifiers (IDs) of cached memory blocks.

[0004] In some implementations, the memory controller is also configured to cache the first set of data in a memory block. In some implementations, the first set of data is associated with a first set of logical addresses.

[0005] In some implementations, the memory controller is also configured to search for the first set of data cached in the memory block based on the L2P mapping table.

[0006] In some implementations, volatile storage devices include caches.

[0007] In some implementations, the memory system also includes a non-volatile memory device operatively coupled to the memory controller. In some implementations, the memory controller is further configured to store a second set of data in a memory region of the non-volatile memory device. In some implementations, this second set of data is associated with a second set of logical addresses. In some implementations, the memory controller is further configured to maintain an L2P mapping table stored in the volatile memory device, such that the L2P mapping table also maps the second set of logical addresses to physical addresses in the memory regions of the non-volatile memory device.

[0008] In some implementations, volatile memory devices include DRAM, and non-volatile memory devices include NAND flash memory.

[0009] In some implementations, the memory controller is further configured to: in response to receiving a write request indicating a segment of first group of data associated with a first logical address in the first group of logical addresses, assign the segment of the first group of data to a first memory block in the memory block. In some implementations, the first memory block has a first ID in the IDs. The memory controller is also configured to: retrieve the segment of the first group of data to cache the segment of the first group of data in the first memory block.

[0010] In some implementations, in order to maintain the L2P mapping table, the memory controller includes an L2P search engine configured to update the L2P mapping table to map the first logical address to the first ID in response to obtaining a fragment of the first set of data to the first memory block.

[0011] In some implementations, the memory controller is also configured to: in response to receiving a read request indicating a segment of first group data associated with a second logical address in the first group of logical addresses, retrieve the segment of the first group of data from a second storage block in the cache based on an L2P mapping table.

[0012] In some implementations, the memory controller includes an L2P search engine configured to determine the address of an L2P mapping table in the volatile storage device based on a second logical address; and to identify a second ID at the address in the L2P mapping table in the volatile storage device. In some implementations, the second memory block has a second ID.

[0013] On the other hand, the memory system includes: a non-volatile memory device comprising memory regions, each memory region being associated with a physical address; a volatile memory device comprising memory blocks, each memory block being associated with an ID; and a memory controller operatively coupled to the volatile and non-volatile memory devices. The volatile memory device is configured to store an L2P mapping table. The L2P mapping table maps the logical addresses of data to the IDs of memory blocks in the volatile memory device and the physical addresses of memory regions in the non-volatile memory device, respectively. The memory controller is configured to search for segments of data based on the L2P mapping table.

[0014] In some implementations, in order to search for fragments of data, the memory controller is configured to: determine the address of an L2P mapping table in a volatile storage device based on the logical address associated with the fragment of data; and determine the value at the address in the L2P mapping table.

[0015] In some implementations, in order to search for data segments, the memory controller is also configured to: retrieve a data segment from a memory block in a volatile memory device with that ID in response to the value being an ID of a memory block in a volatile memory device; or retrieve a data segment from a memory region in a non-volatile memory device with that physical address in response to the value being an address of a memory region in a non-volatile memory device.

[0016] In some implementations, in order to search for fragments of data, the memory controller includes multiple L2P search engines configured to search for multiple fragments of data in parallel, respectively, based on an L2P mapping table.

[0017] In some implementations, the memory controller is also configured to either cache fragments of data in a volatile storage device or flush fragments of data from a volatile storage device to a non-volatile storage device.

[0018] On the other hand, a memory controller includes a volatile memory device interface operatively coupled to a volatile memory device, and an L2P search engine configured to maintain an L2P mapping table stored in the volatile memory device through the volatile memory device interface, such that the L2P mapping table maps a first set of logical addresses to the IDs of memory blocks in the cache.

[0019] In some implementations, the L2P search engine is also configured to search for a first set of data that is associated with a first set of logical addresses and is cached in a storage block based on an L2P mapping table.

[0020] In some implementations, the memory controller also includes a non-volatile memory device interface operatively coupled to the non-volatile memory device. In some implementations, the L2P search engine is also configured to maintain an L2P mapping table stored in the volatile memory device, such that the L2P mapping table also maps the second set of logical addresses to the physical addresses of the storage regions of the non-volatile memory device.

[0021] In some implementations, the L2P search engine is also configured to search for a second set of data that is associated with a second set of logical addresses and is stored in the storage area based on an L2P mapping table.

[0022] In some implementations, volatile memory devices include DRAM, and non-volatile memory devices include NAND flash memory.

[0023] In some implementations, the memory controller further includes a range partitioning accelerator configured to assign the data segment to a first storage block in the memory block in response to receiving a write request indicating a segment of data associated with a first logical address in the first set of logical addresses. In some implementations, the first storage block has a first ID in the IDs. In some implementations, the memory controller further includes a host interface configured to retrieve the data segment of the first set of data and cache it in the first storage block.

[0024] In some implementations, in order to maintain the L2P mapping table, the L2P search engine is also configured to: in response to the host interface retrieving a fragment of the first set of data to the first storage block, update the L2P mapping table to map the first logical address to the first ID.

[0025] In some implementations, the memory controller also includes a host interface configured to: in response to receiving a read request indicating a segment of first data associated with a second logical address in the first set of logical addresses, retrieve the segment of the first data from a second storage block in the cache based on an L2P mapping table.

[0026] In some implementations, the L2P search engine is also configured to: determine the address of the L2P mapping table in the volatile storage device based on the second logical address; and identify the second ID at the address of the L2P mapping table in the volatile storage device, wherein the second storage block has the second ID.

[0027] In another aspect, a method for operating a memory controller is provided. An L2P mapping table is generated and stored in a volatile storage device. The L2P mapping table is maintained such that it maps a first set of logical addresses to the IDs of cached memory blocks.

[0028] In some implementations, the first set of data is cached in a storage block. In other implementations, the first set of data is associated with a first set of logical addresses.

[0029] In some implementations, the first set of data is searched in the storage block based on the L2P mapping table.

[0030] In some implementations, volatile storage devices include caches.

[0031] In some implementations, the second set of data is stored in the memory area of ​​the non-volatile memory device. In some implementations, the second set of data is associated with a second set of logical addresses. In some implementations, an L2P mapping table stored in the volatile memory device is maintained, such that the L2P mapping table also maps the second set of logical addresses to the physical addresses in the memory area of ​​the non-volatile memory device.

[0032] In some implementations, volatile memory devices include DRAM, and non-volatile memory devices include NAND flash memory.

[0033] In some implementations, in response to receiving a write request indicating a fragment of first group data associated with a first logical address in the first group of logical addresses, the fragment of the first group of data is assigned to a first storage block in the storage block. In some implementations, the first storage block has a first ID in the ID. In some implementations, the fragment of the first group of data is retrieved to be cached in the first storage block.

[0034] In some implementations, in order to maintain the L2P mapping table, in response to obtaining a fragment of the first set of data to the first storage block, the L2P mapping table is updated to map the first logical address to the first ID.

[0035] In some implementations, in response to receiving a read request indicating a fragment of first group data associated with a second logical address in the first group of logical addresses, the fragment of first group data is retrieved from a second storage block in the cache based on an L2P mapping table.

[0036] In some implementations, the address of the L2P mapping table in the volatile storage device is determined based on the second logical address, and a second ID is identified at the address in the L2P mapping table in the volatile storage device. In some implementations, the second memory block has a second ID. Attached Figure Description

[0037] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0038] Figure 1 A block diagram of a system including a memory system is shown according to some aspects of this disclosure.

[0039] Figure 2A A diagram of a memory card having a storage device according to some aspects of this disclosure is shown.

[0040] Figure 2B A diagram of an SSD having a storage device according to some aspects of this disclosure is shown.

[0041] Figure 3 A block diagram of a memory controller according to some aspects of this disclosure is shown.

[0042] Figure 4 A schematic diagram of a NAND flash memory device including peripheral circuitry is shown according to some aspects of this disclosure.

[0043] Figure 5 A schematic diagram of a DRAM device including peripheral circuitry according to some aspects of this disclosure is shown.

[0044] Figure 6 A detailed schematic diagram of a memory system performing data search according to some aspects of this disclosure is shown.

[0045] Figure 7 An L2P mapping table is shown according to some aspects of this disclosure.

[0046] Figure 8 A flowchart of a method for operating a memory controller according to some aspects of this disclosure is shown.

[0047] Figure 9 A flowchart of a method for processing write requests according to some aspects of this disclosure is shown.

[0048] Figure 10 A flowchart of a method for processing a read request according to some aspects of this disclosure is shown.

[0049] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0050] Generally, terms can be understood, at least in part, from their usage in context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or in a plural sense, to describe a combination of features, structures, or characteristics. Similarly, again, terms such as "a," "an," or "the" can be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors and can conversely allow for the existence of additional factors that are not necessarily explicitly described, again, depending at least in part on the context.

[0051] Data searching in an SSD involves locating and accessing requested data stored in a non-volatile storage device (e.g., NAND flash memory). The goal of data searching is to efficiently retrieve or modify data as needed by the system. This is achieved through a translation layer in the memory controller, which maps logical addresses used by the operating system to physical addresses within the SSD. Therefore, the memory controller plays a crucial role in managing data searching and ensuring optimal performance.

[0052] For enterprise-grade SSDs, or any SSD with volatile memory (e.g., DRAM), "hot data" refers to frequently used and / or recently accessed data stored in the cache. Hot data is typically cached in DRAM to speed up future access requests. However, the efficiency of known search algorithms for hot data in enterprise-grade SSDs is limited by the time complexity of O(n) or O(logn) of the known search algorithms and can become a performance bottleneck, especially when dealing with large amounts of data.

[0053] To address one or more of the aforementioned problems, this disclosure introduces a data search scheme in a memory system that extends the use of L2P mapping tables to both non-volatile and volatile memory, thereby reducing the complexity of searching cached data in volatile memory and improving search efficiency. In some implementations, physical addresses of storage regions in non-volatile memory (e.g., physical page addresses (PPAs) in NAND flash memory) and physical addresses of storage blocks in volatile memory (e.g., block identifiers (IDs)) are mapped to logical addresses of host / user data (e.g., logical block addresses (LBAs)) in a unified extended L2P mapping table for data searching across non-volatile and volatile memory. Thus, the time complexity of hot data searches can be reduced to O(1). In some implementations, the memory controller maintains the unified extended L2P mapping table and updates it in response to processing write and read requests from the host. In some implementations, multiple dedicated circuits (instead of firmware) are used to process data search requests in parallel to further improve search efficiency and reduce firmware overhead.

[0054] Figure 1 A block diagram of a system 100 including a memory system 102, according to some aspects of this disclosure, is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The host 108 may be configured to send data to or receive data (also known as user data or host data) from the memory system 102. The memory system 102 may be a storage device product (e.g., an SSD) integrating the memory controller 106 and one or more memory devices 104.

[0055] Storage device 104 may be any storage device disclosed herein, including non-volatile storage devices (e.g., NAND flash memory devices). In some implementations, storage device 104 may also include one or more volatile storage devices (e.g., DRAM devices or static random-access memory (SRAM) devices).

[0056] According to some implementations, memory controller 106 is operatively coupled to storage device 104 and host 108 and is configured to control storage device 104. Memory controller 106 can manage data stored in storage device 104 and communicate with host 108. In some implementations, memory controller 106 is designed to operate in a low duty cycle environment, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices (e.g., personal computers, digital cameras, mobile phones, etc.). In some implementations, memory controller 106 is designed to operate in a high duty cycle environment, where SSDs or embedded multimedia cards (eMMC) are used as data storage devices in mobile devices (e.g., smartphones, tablets, laptops, etc.) and enterprise-class storage device arrays. Memory controller 106 can be configured to control the operation of storage device 104, such as read, program / write, and / or erase operations. The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the storage device 104, including but not limited to bad block management, garbage collection, L2P address translation, wear leveling, etc. In some implementations, the memory controller 106 is also configured to handle error correction codes (ECCs) regarding data read from or written to the storage device 104. Any other suitable functions (e.g., formatting the storage device 104) can also be performed by the memory controller 106. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols.For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols (e.g., non-volatile memory express (NVMe) protocol, NVMe-over-fabric (NVMe-oF) protocol, PCI-express (PCI-E) protocol, Universal Serial Bus (USB) protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnection (PCI) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.).

[0057] Consistent with the scope of this disclosure and as detailed below, memory controller 106 may be configured to maintain an L2P mapping table that maps logical addresses of host / user data to the IDs of memory blocks in the volatile memory of storage device 104 and the addresses of memory regions in the non-volatile memory of storage device 104, respectively. Memory controller 106 may also be configured to search for segments of data based on the L2P mapping table.

[0058] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2AIn one example shown, the memory controller 106 and a single storage device 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108. In such a way... Figure 2B In another example shown, the memory controller 106 and multiple storage devices 104 can be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., ...). Figure 1 The SSD connector 208 is coupled to the host 108. In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202. In some implementations, the memory system 102 is implemented as an SSD 206, which (e.g., an enterprise-class SSD) includes both non-volatile and volatile memory devices as storage devices 104.

[0059] Figure 3 A block diagram of a memory controller 300 according to some aspects of this disclosure is shown. The memory controller 300 may be... Figure 1 An example of a memory controller 106. Figure 3As shown, the memory controller 300 may include a processing unit 308, an SRAM 310, and a read-only memory (ROM) 311. In some implementations, the processing unit 308 is implemented by a microprocessor (e.g., a digital signal processor (DSP)) or microcontroller (also known as a microcontroller unit (MCU)) that executes firmware and / or software modules to perform the various functions described herein. The various firmware modules in the memory controller 300 described herein may be implemented as firmware code or instructions stored in the ROM 311 and executed by the processing unit 308. In some implementations, the processing unit 308 includes one or more hardware circuits, such as fixed logic units (e.g., logic gates), multiplexers, flip-flops, state machines, field-programmable gate arrays (FPGAs), or programmable logic devices (PLDs). For example, the hardware circuitry may include dedicated circuitry (e.g., an application-specific integrated circuit (ASIC)) for a given logical function that is known at the time of device manufacturing.

[0060] like Figure 3 As shown, the memory controller 300 may also include various input / output (I / O) interfaces, such as a NAND interface 312 operatively coupled to the NAND flash memory 302 (e.g., an example of a non-volatile memory device), a DRAM interface 314 operatively coupled to the DRAM 304 (e.g., an example of a volatile memory device), and a host interface 316 operatively coupled to the host 306 (e.g., an example of host 108). The NAND interface 312, DRAM interface 314, and host interface 316 may be configured to transfer data, commands, clock signals, or any suitable signals between the processing unit 308 and the NAND flash memory 302, DRAM 304, and host 306, respectively. The NAND interface 312, DRAM interface 314, and host interface 316 can implement any suitable communication protocol (e.g., NVMe protocol and PCI-E protocol, double data rate (DDR) protocol, to name a few) to facilitate data transfer, communication, and management.

[0061] As described above, both SRAM 310 and DRAM 304 can be considered volatile memory devices that can be controlled and accessed by the memory controller 300 in the memory system. Consistent with the scope of this disclosure, a cache can be implemented, for example, as part of a volatile memory device via SRAM 310 and / or DRAM 304. It will be understood that, although Figure 3 The diagram shows that SRAM 310 is located inside memory controller 300 and DRAM 304 is located outside memory controller 300, but in some examples, both SRAM 310 and DRAM 304 may be located inside or outside memory controller 300.

[0062] Figure 4 A schematic circuit diagram of a NAND flash memory device 400, including peripheral circuitry 402, is shown according to some aspects of this disclosure. The NAND flash memory device 400 may be... Figure 3 An example of a NAND flash memory 302. A NAND flash memory device 400 may include a cell array 401 and peripheral circuitry 402 operatively coupled to the cell array 401. Cells 406 in the cell array 401 are provided in the form of an array of NAND memory strings 408, each NAND memory string extending vertically above a substrate (not shown). In some implementations, each NAND memory string 408 includes a plurality of cell 406 operatively coupled in series and stacked vertically. Each cell 406 may hold a continuous analog value (e.g., voltage or charge) that depends on the number of electrons trapped in the region of the cell 406. Each cell 406 may be a floating-gate cell including a floating-gate transistor or a charge-trapping cell including a charge-trapping transistor.

[0063] In some implementations, each memory cell 406 is a single-level cell (SLC) with two possible levels (memory states) and can therefore store one bit of data. For example, a first state "0" may correspond to a first range of threshold voltages, and a second state "1" may correspond to a second range of threshold voltages. In some implementations, each memory cell 406 is an xLC capable of storing more than a single bit of data in more than four levels. For example, an xLC may store two bits per cell (aka, multi-level cell (MLC)), three bits per cell (aka, triple-level cell (TLC)), or four bits per cell (aka, quad-level cell (QLC)). Each xLC can be programmed to take a range of possible nominal storage values ​​(i.e., 2^N with N bits of data). N (Corresponding to each segment). In some implementations, each memory cell 406 is set to 2. N One level in a series of levels corresponds to a segment of N bits of data, where N is an integer greater than 2.

[0064] like Figure 4 As shown, each NAND memory string 408 may further include a source select gate (SSG) transistor 410 at its source end and a drain select gate (DSG) transistor 412 at its drain end. The SSG transistor 410 and DSG transistor 412 can be configured to activate the selection of the NAND memory string 408 (column of the array) during read and program operations. In some implementations, the sources of the NAND memory strings 408 in the same block 404 are coupled via a common source line (SL) 414 (e.g., a common SL). In other words, according to some implementations, all NAND memory strings 408 in the same block 404 have an array common source (ACS). According to some implementations, the drain of each NAND memory string 408 is coupled to a corresponding bit line 416 from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 408 is configured to be selected or deselected by applying a selection voltage or deselection voltage to the gate of the corresponding DSG transistor 412 via one or more DSG lines 413 and / or applying a selection voltage or deselection voltage to the gate of the corresponding SSG transistor 410 via one or more SSG lines 415.

[0065] like Figure 4 As shown, the NAND memory string 408 can be organized into multiple blocks 404, each of which can have a common source line 414 (e.g., coupled to the ACS). In some implementations, each block 404 is the basic data unit for an erase operation, i.e., all memory cells 406 on the same block 404 are erased simultaneously. To erase the memory cells 406 in the selected block 404, the source line 414 coupled to the selected block 404 and the unselected blocks 404 in the same plane as the selected block 404 can be biased using an erase voltage (Vers) (e.g., a high positive bias (e.g., 20V or higher)).

[0066] Memory cells 406 of adjacent NAND memory strings 408 can be coupled via word lines 418, which select which row of memory cells 406 is affected by read and program operations. In some implementations, each word line 418 is coupled to a physical page 420 of memory cell 406, which is the basic data unit used for read and write (programming) operations. The size of a physical page 420 (in bits) can be related to the number of NAND memory strings 408 coupled by word lines 418 in a block 404. Each word line 418 may include multiple control gates (gate electrodes) located at each memory cell 406 in the corresponding physical page 420 and gate lines coupled to those control gates.

[0067] Peripheral circuitry 402 can be operatively coupled to memory cell array 401 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413. Peripheral circuitry 402 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory cell array 401 by applying voltage signals to each selected memory cell 406 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413 and / or sensing current signals from each selected memory cell 406 via bit line 416, word line 418, source line 414, SSG line 415, and DSG line 413. Peripheral circuitry 402 can include various types of peripheral circuitry formed using complementary metal-oxide-semiconductor (CMOS) technology.

[0068] Figure 5 A schematic circuit diagram of a DRAM device 500, including peripheral circuitry 502, is shown according to some aspects of this disclosure. The DRAM device 500 may be... Figure 3An example of DRAM 304. DRAM device 500 may include a memory cell array 501 and peripheral circuitry 502 operatively coupled to the memory cell array 501. Memory cells 503 may be arranged in the memory cell array 501 having rows and columns. DRAM device 500 requires periodic refreshing of memory cells 503. In some implementations, each memory cell 503 includes a capacitor 507 for storing 1 bit of data as a positive or negative charge and a transistor 505 for controlling access to the capacitor 507. That is, according to some implementations, such as Figure 5 Each memory cell 503 shown is a one-transistor, one-capacitor (1T1C) cell.

[0069] The DRAM device 500 may include: word lines 504 coupling peripheral circuitry 502 and memory cell array 501, the word lines 504 being used to control the switching of transistors 505 in a row of memory cells 503; and bit lines 506 coupling peripheral circuitry 502 and memory cell array 501, the bit lines 506 being used to send data to and / or receive data from memory cells 503 in a column. That is, each word line 504 is coupled to a corresponding row of memory cells 503, and each bit line 506 is coupled to a corresponding column of memory cells 503. The gate of a transistor 505 may be coupled to the word line 504, one of the source and drain of a transistor 505 may be coupled to the bit line 506, the other of the source and drain of a transistor 505 may be coupled to one electrode of a capacitor 507, and the other electrode of the capacitor 507 may be coupled to ground.

[0070] Peripheral circuitry 502 can be coupled to memory cell array 501 via bit lines 506, word lines 504, and any other suitable metal wiring. Peripheral circuitry 502 may include any suitable circuitry to facilitate operation of memory cell array 501 by applying voltage signals to each memory cell 503 via word lines 504 and bit lines 506 and / or sensing current signals from each memory cell 503 via word lines 504 and bit lines 506. Peripheral circuitry 502 may include various types of peripheral circuitry formed using CMOS technology.

[0071] Figure 6 A detailed schematic diagram of a memory system 600 performing a data search according to some aspects of this disclosure is shown. The memory system 600 may be... Figure 1 An example of memory system 102 in the example. Figure 6 As shown, the memory system 600 may include a memory controller 601, a volatile memory device 602, and a non-volatile memory device 604. The memory controller 601 may be... Figure 1 An example of a memory controller 106. Volatile memory device 602 and non-volatile memory device 604 may be... Figure 1 An example of storage device 104. In some implementations, volatile storage device 602 includes DRAM (e.g., Figure 5 The DRAM device 500 in the memory, and the non-volatile memory device 604 includes NAND flash memory (e.g., ...). Figure 4 NAND flash memory device 400 in the middle). From the host (not shown) (e.g., Figure 1 Data in host 108 can be stored as "hot data" in volatile storage device 602 or as "cold data" in non-volatile storage device 604. It is understood that in some examples, "hot data" can be stored in non-volatile storage device 604, while "cold data" can be stored in volatile storage device 602, or both "hot data" and "cold data" can be stored in either volatile storage device 602 or non-volatile storage device 604. As described above, "hot data" refers to data that is frequently used and / or recently accessed (e.g., this data is stored in cache 606 in volatile storage device 602). Conversely, "cold data" refers to data, for example, stored in non-volatile storage device 604, which is flushed from cache 606 to non-volatile storage device 604 under certain conditions (e.g., cache 606 is full, data has not been accessed or used for a period of time, etc.). In some implementations, the memory controller 601 is also configured to cache segments of host / user data in the volatile storage device 602 or flush segments of host / user data from the volatile storage device 602 to the non-volatile storage device 604.

[0072] To enable searching and accessing cold data, the non-volatile storage device 604 can be divided into multiple storage regions 605, each with a unique physical address. In some implementations, each storage region 605 includes one or more logical pages (e.g., a portion of a physical page 420 of the NAND flash storage device 400 (e.g., 1 / 2, 1 / 4, or 1 / 8)). For example, the size of each storage region 605 could be 4096 bytes. It is understood that storage regions 605 can correspond to any suitable group of storage units in the non-volatile storage device 604 other than pages (e.g., a portion of a page, a block (e.g., block 404 of the NAND flash storage device 400), etc.). For example, when a storage region 605 corresponds to a page of the non-volatile storage device 604, the physical address of the storage region 605 can be a physical page address (PPA).

[0073] Consistent with the scope of this disclosure, in order to enable searching and accessing hot data, the cache 606 of the volatile storage device 602 may be divided into multiple storage blocks 607, each of which has a unique identifier (ID), also known as a block ID. In some implementations, each storage block 607 includes one or more pages (e.g., rows or columns of memory cells 503 of the DRAM device 500). In some implementations, to enable uniform data searching between the non-volatile storage device 604 and the volatile storage device 602, the size of each storage region 605 and the size of each storage block 607 may be the same. It is understood that in some examples, the size of each storage region 605 and the size of each storage block 607 may be different. For example, the size of each storage block 607 may also be 4096 bytes. It is understood that a storage block 607 may correspond to any suitable group of memory cells in the volatile storage device 602 other than a page (e.g., a portion of a page, a codeword, etc.).

[0074] Cache 606 may be part of volatile storage device 602, temporarily storing (caching) frequently used and / or recently accessed data (i.e., hot data) to speed up read and write operations on non-volatile storage device 604. Any suitable caching algorithm (including, for example, Least Recently Used (LRU), Most Recently Used (MRU), and First-In, First-Out (FIFO)) can be used to determine which data should be stored in cache 606 and when data should be replaced. In some implementations, data from the host (host / user data) is initially cached as hot data in cache 606 of volatile storage device 602 and flushed to non-volatile storage device 604 as cold data under certain conditions based on the caching algorithm. For example, when the size of the data in cache 606 reaches a preset threshold (maximum cache size), the data in cache 606 may be flushed to non-volatile storage device 604. Cache 606 can be used with any suitable type of volatile storage device 602 (e.g., Figure 3 This is achieved using DRAM 304 and / or SRAM 310.

[0075] Consistent with the scope of this disclosure, to enable unified searching and access for both hot and cold data, a unified extended L2P mapping table 612 can be maintained and stored in volatile storage device 602 to map the logical addresses of data not only to the physical addresses 616 (e.g., PPAs) of storage regions 605 in non-volatile storage device 604, but also to the IDs 614 of storage blocks 607 in cache 606 of volatile storage device 602. The logical addresses can identify host / user data and are known to memory controller 601. In some implementations, the logical address (e.g., logical block address (LBA)) indicates the basic logical data unit used for each read or write operation. In some implementations, to enable unified data searching between non-volatile storage device 604 and volatile storage device 602, the size of each storage region 605, the size of each storage block 607, and the size of the data corresponding to each logical address can be the same. For example, the size of the data corresponding to each logical address could also be 4096 bytes. Since the memory controller 601 operates based on logical addresses rather than physical addresses (e.g., physical address 616 or ID 614), the L2P mapping table 612 can be used to enable the translation between logical and physical addresses in a uniform manner across both non-volatile memory device 604 and volatile memory device 602, as described in detail below.

[0076] The L2P mapping table 612 can be stored in any suitable type of volatile storage device 602 (e.g., Figure 3 In DRAM 304). In some implementations, the same volatile memory device 602 (e.g., Figure 3 DRAM 304 includes both cache 606 and L2P mapping table 612. It is understood that in some examples, cache 606 and L2P mapping table 612 may be included in different volatile memory devices 602. For example, SRAM 310 may include cache 606, while DRAM 304 may include L2P mapping table 612. Although L2P mapping table 612 is in... Figure 6 The L2P mapping table 612 is shown outside of cache 606, but it is understood that in some examples, the L2P mapping table 612 may also be stored in cache 606.

[0077] The L2P mapping table 612 can be stored in the volatile storage device 602 using addresses from the volatile storage device 602. For example, as Figure 7As shown, the L2P mapping table 612 may include addresses 704 (VMAdd) in volatile storage device 602, each address in 704 being associated with a value 706. Value 706 may include two types of information: the ID 614 of storage block 607 in cache 606 (e.g., ID1, ID2, ID3, etc.), and the physical address 616 (PPA, e.g., PPA1, PPA2, PPA3, PPA4, etc.) of storage region 605 in non-volatile storage device 604. Figure 7 As shown, the L2P mapping table 612 can also map the logical address 702 (LBA) of host / user data to the ID 614 of the memory block 607 in the cache 606 and the physical address 616 of the memory region 605 in the non-volatile storage device 604 via address 704. For example, for each segment of host / user data, the corresponding address 704 in the L2P mapping table 612 in the volatile storage device 602 can be determined based on the corresponding LBA 702 associated with that segment of host / user data. Figure 7 In one example shown, each address 704 can be calculated by adding an address offset (OFF) to the corresponding LBA 702 (e.g., 0, 1, 2, 3, 4, 5, 6, etc.). The address offset can be determined, for example, based on the location of the L2P mapping table 612 stored in the volatile storage device 602. Therefore, the corresponding value 706 at the determined address 704 in the L2P mapping table 612 can be determined, which indicates the ID 614 of the storage block 607 in the cache or the physical address 616 of the storage area 605 in the non-volatile storage device 604 via address 704. Thus, the LBA 702 of host / user data can be mapped via the L2P mapping table 612 to the ID 614 of the storage block 607 in the cache 606 and the physical address 616 of the storage area 605 in the non-volatile storage device 604, respectively.

[0078] Return to reference Figure 6 The memory controller 601 may include multiple I / O interfaces, including a volatile memory interface 620 operatively coupled to a volatile memory device 602, a non-volatile memory interface 622 operatively coupled to a non-volatile memory device 604, and a host interface 618 operatively coupled to a cache 606 of the volatile memory device 602 and a host (not shown). Examples of these I / O interfaces may include... Figure 3 The DRAM interface 314, NAND interface 312, and host interface 316 can implement any suitable communication protocol (e.g., NVMe protocol, PCI-E protocol, DDR protocol, to name a few) to facilitate data transfer, communication, and management.

[0079] Host interface 618 can be configured to receive write and read requests from a host. Each write request may indicate a segment of data associated with a logical address (e.g., LBA) to be written to memory system 600. Similarly, each read request may indicate a segment of data associated with a logical address (e.g., LBA) to be read from memory system 600. In some implementations, in response to receiving a write or read request, host interface 618 is also configured to retrieve the segment of data from the host to temporarily store (cache) the segment of data in cache 606, and vice versa. For example, host interface 618 may include a direct memory access (DMA) unit that accesses data going to and from cache 606.

[0080] Non-volatile memory interface 622 can be configured to enable memory controller 601 to access data stored in non-volatile memory device 604 based on the physical address (e.g., PPA) of memory region 605. Volatile memory interface 620 can be configured to enable memory controller 601 to access data stored in volatile memory device 602 (e.g., maintaining L2P mapping table 612 and accessing data in cache 606). In some implementations, volatile memory interface 620 is configured to translate the ID 614 of memory block 607 in cache 606 into a physical address of volatile memory device 602, which can be directly used by memory controller 601 to operate on memory cells of volatile memory device 602. In other words, while the ID 614 of memory block 607 in cache 606 can be used to facilitate hot data searches via L2P mapping table 612, memory controller 601 can still use the physical address of volatile memory device 602 to access data in volatile memory device 602. Therefore, depending on some implementations, the volatile storage device 602 does not need to be modified to accommodate hot data search using the ID 614 of the storage block 607.

[0081] like Figure 6 As shown, the memory controller 601 may further include a range partitioning accelerator 608 and one or more L2P search engines 610 operatively coupled to volatile memory device 602, non-volatile memory interface 622, and volatile memory interface 620. In some implementations, the range partitioning accelerator 608 and the L2P search engine 610 are stored in memory (e.g., ...). Figure 3 The firmware code / instructions in ROM 311 are implemented and processed by the processing unit (e.g., Figure 3The firmware module is executed by the processing unit 308. In some implementations, the range partitioning accelerator 608 and the L2P search engine 610 are hardware modules implemented by special-purpose circuitry (e.g., ASIC) to perform the special-purpose functions described herein. The hardware implementation of the range partitioning accelerator 608 and the L2P search engine 610 can improve search parallelism and reduce firmware overhead, thereby further improving data search performance.

[0082] Range partitioning accelerator 608 can be configured to generate data search requests based on read and write requests from the host via host interface 618 and to assign search requests to L2P search engines 610. That is, range partitioning accelerator 608 can, for example, partition read or write requests into search requests to be processed in parallel by multiple L2P search engines 610 based on different logical addresses associated with the data in the read or write request. For example, for each search request, range partitioning accelerator 608 can identify an idle L2P search engine 610 to handle the search request. In some implementations, in response to receiving a write request indicating a fragment of data associated with a logical address (e.g., LBA), range partitioning accelerator 608 is configured to assign that fragment of data to a storage block with a unique ID in ID 614 in storage block 607 of cache 606, which triggers host interface 618 to retrieve the corresponding fragment of data from the host to the corresponding storage block 607 in cache 606.

[0083] L2P search engine 610 can be configured to process search requests and, based on the processing of search requests, maintain an L2P mapping table 612 stored in volatile storage device 602 via volatile memory interface 620. In some implementations, a single L2P mapping table 612 is maintained for memory system 600, and multiple L2P search engines 610 are configured to maintain the same L2P mapping table 612 and use the same L2P mapping table 612 for hot data searches and cold data searches. For example, multiple L2P search engines 610 can be configured to search multiple fragments of data in parallel based on the same L2P mapping table 612. It is understood that, in some examples, a single L2P search engine 610 can be used to process search requests. In some implementations, in response to a write request, host interface 618 retrieves a fragment of data from the host to the corresponding storage block 607 in cache 606. L2P search engine 610 is configured to update L2P mapping table 612 to map the logical address (e.g., LBA) associated with that data fragment to the unique ID 614 of the corresponding storage block 607. For example, as... Figure 7As shown, assuming the LBA 702 of a data fragment is "3", the value 706 can be updated by search engine 610 to become "ID3", which is the unique ID 614 of the corresponding storage block 607. The value 706 can be stored at address 704 "OFF+3" of the L2P mapping table 612 in the volatile storage device 602. In some implementations, in response to flushing a fragment of cached data in cache 606 to a storage area 605 in non-volatile storage device 604 with a unique physical address 616 (e.g., PPA), L2P search engine 610 is also configured to update L2P mapping table 612 to map the logical address (e.g., LBA) associated with the data fragment to the unique physical address 616 of the corresponding storage area 605. For example, as... Figure 7 As shown, assuming the LBA 702 of the data fragment is "3", the value 706 can be updated by the L2P search engine 610 to become "PPA5", which is the unique physical address 616 of the corresponding storage area 605, because the data fragment associated with LBA 3 has been moved from ID3 in cache 606 to PPA5 in non-volatile memory 604.

[0084] In some implementations, in response to a search request that receives a read request for a segment of data indicating a logical address (e.g., LBA), the L2P search engine 610 is configured to search for the data segment based on the logical address and the L2P mapping table 612. The L2P mapping table 612 can be configured to determine the address of the L2P mapping table 612 in the volatile storage device 602 based on the logical address, and then determine the value at that address. This value can be the ID 614 of a memory block 607 in the cache or the physical address 616 of a memory region 605 in the non-volatile storage device 604. In one example, such as... Figure 7 As shown, assuming the LBA 702 of a data fragment is "0", the search engine 610 can first add LBA 702 "0" to the address offset "OFF" to obtain address 704 "OFF", and then identify the value 706 at address 704 "OFF" as "ID1". This means that the data fragment to be read is hot data in storage block ID1 currently cached in cache 606. In another example, as... Figure 7As shown, assuming the LBA 702 of the data fragment is "2", the L2P search engine 610 can first add LBA 702 "2" to the address offset "OFF" to obtain address 704 "OFF+2", and then identify the value 706 at address 704 "OFF+2" as "PPA1", which means that the data fragment to be read is cold data in the storage area PPA1 currently stored in the non-volatile storage device 604.

[0085] In some implementations, in response to identifying the ID 614 of memory block 607 in cache 606, L2P search engine 610 provides the identified ID 614 to volatile memory interface 620, and volatile memory interface 620 translates ID 614 into a corresponding physical address in volatile memory device 602, so that host interface 618 can, for example, use DMA to retrieve a segment of data from the corresponding physical address in volatile memory device 602. In some implementations, in response to identifying the physical address 616 of memory region 605 in non-volatile memory device 604, L2P search engine 610 provides the identified physical address 616 (e.g., PPA) to non-volatile memory interface 622, so that non-volatile memory interface 622 can retrieve a segment of data from the corresponding physical address in non-volatile memory device 604.

[0086] Figure 8 A flowchart of a method 800 for operating a memory controller according to some aspects of this disclosure is shown. The memory controller can be any suitable memory controller disclosed herein (e.g., memory controller 601). It is understood that the operations shown in method 800 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations in the operation may be performed simultaneously, or in different ways. Figure 8 The order shown in the diagram is executed.

[0087] The memory controller is operatively coupled to both volatile and non-volatile memory devices. The volatile memory devices may contain caches. The caches are divided into multiple memory blocks, each with a unique ID. The non-volatile memory devices are divided into memory regions, each with a unique physical address. For example, as... Figure 6As shown, the volatile storage device 602 may include a cache 606, which may be divided into storage blocks 607, each of which has a unique ID 614, and the non-volatile storage device 604 may be divided into storage regions 605, each of which has a unique physical address 616.

[0088] refer to Figure 8 Method 800 begins with operation 802, where the L2P mapping table is generated and stored in a volatile storage device. For example, as... Figure 6 As shown, the memory controller 601 can generate an L2P mapping table 612 during the startup of the memory system 600 and store the L2P mapping table 612 in the volatile storage device 602 during the operation of the memory system 600. For example, as Figure 7 As shown, the L2P mapping table 612 may include a value 706 at each address 704, which can be mapped to an LBA 702 respectively.

[0089] like Figure 8 As shown, method 800 proceeds to operation 804, where the first set of data is cached in a cache block. The first set of data is associated with a first set of logical addresses. For example, as... Figure 6 As shown, memory controller 601 can cache multiple segments of host / user data separately in memory block 607 within cache 606. Each segment of host / user data can be associated with a corresponding logical address in a logical address (e.g., LBA). In one example, host interface 618 of memory controller 601 can use DMA to retrieve host / user data from the host to cache the host / user data in memory block 607.

[0090] like Figure 8 As shown, method 800 proceeds to operation 806, where the L2P mapping table is maintained such that the L2P mapping table maps the first set of logical addresses to the IDs of the cache blocks. For example, as Figure 6 and Figure 7 As shown, the memory controller 601 can maintain an L2P mapping table 612, so that a set of LBAs 702 can be mapped to the ID 614 of the memory block 607 via address 704 respectively.

[0091] like Figure 8 As shown, method 800 proceeds to operation 808, where the second set of data is stored in the memory area of ​​a non-volatile storage device. The second set of data is associated with a second set of logical addresses. For example, as... Figure 6 As shown, memory controller 601 can store segments of host / user data separately in memory region 605 within non-volatile memory device 604. Each segment of host / user data can be associated with a corresponding logical address in a logical address (e.g., LBA). In one example, segments of host / user data can be flushed from cache 606 to non-volatile memory device 604.

[0092] like Figure 8 As shown, method 800 proceeds to operation 810, where the L2P mapping table is maintained such that the L2P mapping table maps the second set of logical addresses to the physical addresses of the storage regions of the non-volatile storage devices. For example, as Figure 6 and Figure 7 As shown, the memory controller 601 can maintain an L2P mapping table 612, so that another set of LBAs 702 can be mapped to physical addresses 616 (e.g., PPAs) of memory region 605 via address 704.

[0093] like Figure 8 As shown, method 800 proceeds to operation 812, where a fragment of data is searched based on the L2P mapping table. For example... Figure 6 As shown, the multiple L2P search engines 610 of the memory controller 601 can perform hot data searches and cold data searches on the multiple segments of the data in parallel based on the logical addresses of multiple segments of the data and the L2P mapping table 612.

[0094] In some implementations, to search for a fragment of data, the address of the L2P mapping table in the volatile storage device is determined based on the logical address associated with that fragment, and the value at that address in the L2P mapping table is determined. For example, as... Figure 6 and Figure 7 As shown, each L2P search engine 610 can calculate the address 704 of the L2P mapping table 612 based on the LBA 702 and the address offset, and identify the value 706 at address 704 as an ID or physical address (e.g., PPA). In some implementations, to search for a fragment of data, in response to the value being an ID among the IDs of memory blocks in a volatile storage device, the fragment of data is retrieved from the memory block with that ID in the volatile storage device. In some implementations, to search for a fragment of data, in response to the value being a physical address among the physical addresses of memory regions in a non-volatile storage device, the fragment of data is retrieved from the memory region with that physical address in the non-volatile storage device. For example, as... Figure 6 and Figure 7As shown, if the L2P search engine 610 identifies the value 706 at address 704 as ID 614, the host interface 618 can, for example, use DMA to retrieve a segment of data from the memory block 607 in cache 606 that has the identified ID 614. Conversely, if the L2P search engine 610 identifies the value 706 at address 704 as physical address 616 (e.g., PPA), the non-volatile memory interface 622 can retrieve a segment of data from the memory region 605 in non-volatile storage device 604 that has the identified physical address 616.

[0095] In some implementations, in response to receiving a write request indicating a fragment of first group of data associated with a first logical address in a first group of logical addresses, the fragment of the first group of data is assigned to a first storage block having a first ID in the ID. For example... Figure 9 As illustrated, for example at 902, a write request can be divided into multiple search requests by the range partitioning accelerator 608, each of which is associated with a fragment of host / user data and its logical address. For example, at 904, the range partitioning accelerator 608 can assign storage block IDs to fragments of host / user data, such that each fragment of host / user data can be associated with a corresponding storage block ID. In some implementations, fragments of a first set of data are retrieved to cache the fragments of the first set of data in a first storage block. For example, at 906, the range partitioning accelerator 608 can trigger the host interface 618 to use DMA to retrieve each fragment of host / user data to the corresponding storage block.

[0096] In some implementations, in response to retrieving a fragment of the first set of data to the first storage block, the L2P mapping table is updated to map the first logical address to the first ID. For example, at 908, the storage block ID of a fragment of cached host / user data can be updated in the L2P mapping table 612 by the L2P search engine 610 to be mapped to the logical address of that host / user data fragment. In some implementations, in response to a fragment of data being flushed from the first storage block of the cache to a storage area with a physical address in a non-volatile storage device, the L2P mapping table is updated to map the first logical address to that physical address. For example, at 910, it can be checked whether NAND flash memory programming is complete. NAND flash memory programming can be performed by flushing cached host / user data from the cache to NAND flash memory. Once NAND flash memory programming is complete, each fragment of host / user data can be stored in a corresponding storage area within the storage area, wherein each storage area in the storage area is associated with a PPA. If the answer to 910 is "yes", then at 912, the PPA of the segment storing host / user data in the NAND flash memory can be updated in the L2P mapping table 612 by the L2P search engine 610 to be mapped to the logical address of the host / user data segment, thereby replacing the storage block ID. At 914, it can be checked whether a new incoming write request has been received to determine whether the process can continue from 902 again for a new incoming write request. If the answer to 910 is "no", then the process can proceed directly to 914, bypassing 912 without updating the L2P mapping table 612.

[0097] In some implementations, in response to receiving a read request indicating a segment of data associated with a second logical address in the first set of logical addresses, the address of the L2P mapping table in the volatile storage device is based on the second logical address, and a second ID of the second memory block is identified at the address of the L2P mapping table in the volatile memory. For example, as Figure 10 As shown, at 1002, the range partitioning accelerator 608 can divide a read request into multiple search requests, each of which is associated with a logical address. At 1004, the range partitioning accelerator 608 can identify an idle L2P search engine 610 to execute the search request. At 1006, the L2P search engine 610 can locate the DRAM address by calculating the logical address, for example, by adding the logical address to an address offset to obtain the DRAM address. At 1008, the value at the DRAM address can be obtained by the L2P search engine 610.

[0098] In some implementations, in response to an ID that is an ID in the IDs of memory blocks in a volatile storage device, a fragment of the first set of data is retrieved from a second memory block in the cache based on an L2P mapping table. For example, at 1010, it can be determined whether a fragment of host / user data is in NAND flash memory based on the value (memory block ID or PPA) obtained at 1008. If the answer to 1010 is "no," it means that the fragment of host / user data is still in the cache, and at 1014, the fragment of host / user data can be retrieved from the cache by volatile memory interface 620 based on the memory block ID obtained at the DRAM address. If the answer to 1010 is "yes," it means that the fragment of host / user data is in NAND flash memory, and at 1012, the fragment of host / user data can be read from NAND flash memory by non-volatile memory interface 622 based on the PPA obtained at the DRAM address. In either case, at 1016, the fragment of host / user data can be sent to the host by host interface 618.

[0099] In all aspects of this disclosure, the functions described herein can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, these functions can be stored as instructions on a non-transitory computer-readable medium. Computer-readable media include computer storage media. Storage media can be those that can be controlled by a memory controller (e.g., Figure 6 The computer-readable medium can be any available medium accessed by the memory controller 601 in the document. By way of example, and not limitation, such computer-readable medium may include RAM, ROM, electrically erasable programmable ROM (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage devices, hard disk drive (HDD) (e.g., disk storage devices or other magnetic storage devices), flash memory drive, SSD, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures accessible by a processing system (e.g., a mobile device or a computer). Disks and optical discs as used herein include CDs, laser discs, optical discs, digital video discs (DVDs), and floppy disks, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0100] The foregoing description of the specific implementation can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementation.

[0101] The breadth and scope of this disclosure should not be limited by any of the exemplary implementations described above, but should be defined solely by the appended claims and their equivalents.

[0102] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements can be used without departing from the scope of this disclosure. Furthermore, the subject matter described in this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, modified, and rearranged in a manner consistent with the scope of this disclosure.

Claims

1. A memory system, comprising: A volatile storage device configured to store a logic-to-physical (L2P) mapping table; as well as A memory controller, operatively coupled to the volatile storage device, and configured to maintain the L2P mapping table stored in the volatile storage device, such that the L2P mapping table maps a first set of logical addresses to identifiers (IDs) of cached memory blocks. The memory controller includes an L2P search engine, and in response to receiving a read request indicating a first segment of data associated with a first logical address in the first set of logical addresses, the L2P search engine is configured to: The address of the L2P mapping table in the volatile storage device is determined based on the first logical address and the address offset associated with the L2P mapping table, wherein the address offset is determined based on the location where the L2P mapping table is stored in the volatile storage device; and Identify the first ID at the address in the L2P mapping table of the volatile storage device, and The memory controller is further configured to retrieve the first segment of the first group of data from a first storage block in the storage block of the cache based on the first ID, wherein the first storage block has the first ID, and In response to receiving a write request indicating a second segment of the first group of data associated with a second logical address in the first group of logical addresses, the memory controller is configured to: In response to the second fragment of the first set of data being cached in the second storage block of the storage block in the cache, the L2P mapping table is updated to map the second logical address to the second ID of the second storage block; and In response to the second fragment of the first set of data being flushed from the second storage block of the cache to the storage area of ​​the non-volatile storage device associated with the physical address, the L2P mapping table is updated by replacing the second ID with the physical address to map the second logical address to the physical address.

2. The memory system according to claim 1, wherein, The memory controller is further configured to cache the first set of data in the memory block, wherein the first set of data is associated with the first set of logical addresses.

3. The memory system according to claim 2, wherein, The memory controller is also configured to search for the first set of data cached in the storage block based on the L2P mapping table.

4. The memory system according to any one of claims 1-3, wherein, The volatile storage device includes the cache.

5. The memory system according to any one of claims 1-3, further comprising: The non-volatile memory device is operatively coupled to the memory controller; The memory controller is further configured to: A second set of data is stored in the storage area of ​​the non-volatile storage device, and the second set of data is associated with a second set of logical addresses, and Maintain the L2P mapping table stored in the volatile storage device, such that the L2P mapping table also maps the second set of logical addresses to the physical addresses of the storage areas of the non-volatile storage device.

6. The memory system according to claim 5, wherein, The volatile storage device includes dynamic random access memory (DRAM), and the non-volatile storage device includes NAND flash memory.

7. The memory system according to any one of claims 1-3, wherein, The memory controller is also configured to: In response to receiving the write request indicating a second segment of the first group of data associated with the second logical address in the first group of logical addresses, the second segment of the first group of data is assigned to the second storage block in the storage block; as well as Obtain the second fragment of the first set of data, and cache the second fragment of the first set of data in the second storage block.

8. A memory system, comprising: A non-volatile storage device, the non-volatile storage device including storage regions, each storage region being associated with a physical address; A volatile storage device, comprising memory blocks, each memory block being associated with an identifier (ID), the volatile storage device being configured to store a logical-to-physical (L2P) mapping table, wherein the L2P mapping table maps the logical address of data to the ID of the memory block in the volatile storage device and the physical address of the memory region in a non-volatile storage device, respectively; and A memory controller, operatively coupled to both the volatile and non-volatile memory devices, and configured to search for a first segment of the data based on the L2P mapping table. In order to search for the first segment of the data, the memory controller is configured to: The address of the L2P mapping table in the volatile storage device is determined based on a first logical address associated with the first segment of the data and an address offset associated with the L2P mapping table, wherein the address offset is determined based on the location where the L2P mapping table is stored in the volatile storage device; and Determine the value at the address in the L2P mapping table. In response to a write request indicating a second segment of data associated with a second logical address, the memory controller is configured to: In response to the second fragment of the data being cached in the first storage block of the storage block in the volatile storage device, the L2P mapping table is updated to map the second logical address to the first ID of the first storage block; and In response to the second fragment of the data being flushed from the first storage block of the volatile storage device to the first storage region of the non-volatile storage device associated with the first physical address, the L2P mapping table is updated by replacing the first ID with the first physical address to map the second logical address to the first physical address.

9. The memory system according to claim 8, wherein, In order to search for the first segment of the data, the memory controller is further configured to: In response to the value being a second ID among the IDs of the storage block in the volatile storage device, the first fragment of the data is obtained from a second storage block in the volatile storage device having the second ID; or In response to the value being a second physical address in the physical address of the storage region in the non-volatile storage device, the first segment of the data is obtained from the second storage region in the non-volatile storage device having the second physical address.

10. The memory system according to any one of claims 8-9, wherein, In order to search for the first segment of the data, the memory controller includes a plurality of L2P search engines configured to search for multiple segments of the data in parallel based on the L2P mapping table.

11. The memory system according to any one of claims 8-9, wherein, The memory controller is further configured to: cache the first fragment of the data in the volatile storage device, or flush the first fragment of the data from the volatile storage device to the non-volatile storage device.

12. A memory controller, comprising: A volatile storage device interface, which is operatively coupled to a volatile storage device; as well as A logic-to-physical (L2P) search engine, configured to maintain an L2P mapping table stored in the volatile storage device via the volatile storage device interface, such that the L2P mapping table maps a first set of logical addresses to identifiers (IDs) of cached storage blocks. In response to receiving a read request indicating a first fragment of data associated with a first logical address in the first group of logical addresses, the L2P search engine is configured to: The address of the L2P mapping table in the volatile storage device is determined based on the first logical address and the address offset associated with the L2P mapping table, wherein the address offset is determined based on the location where the L2P mapping table is stored in the volatile storage device; and Identify the first ID at the address in the L2P mapping table of the volatile storage device from the ID. The volatile storage device interface is further configured to retrieve the first fragment of the first group of data from a first storage block in the storage block of the cache based on the first ID, wherein the first storage block has the first ID, and In response to receiving a write request indicating a second fragment of the first group of data associated with a second logical address in the first group of logical addresses, the L2P search engine is configured to: In response to the second fragment of the first set of data being cached in the second storage block of the storage block in the cache, the L2P mapping table is updated to map the second logical address to the second ID of the second storage block; and In response to the second fragment of the first set of data being flushed from the second storage block of the cache to the storage area of ​​the non-volatile storage device associated with the physical address, the L2P mapping table is updated by replacing the second ID with the physical address to map the second logical address to the physical address.

13. The memory controller according to claim 12, wherein, The L2P search engine is also configured to search the first set of data, which is associated with the first set of logical addresses and is cached in the storage block based on the L2P mapping table.

14. The memory controller according to claim 12 or 13, further comprising: A non-volatile storage device interface, the non-volatile storage device interface being operatively coupled to the non-volatile storage device. The L2P search engine is further configured to maintain the L2P mapping table stored in the volatile storage device, such that the L2P mapping table also maps the second set of logical addresses to the physical addresses of the storage areas of the non-volatile storage device.

15. The memory controller according to claim 14, wherein, The L2P search engine is also configured to search for a second set of data, which is associated with a second set of logical addresses and is stored in the storage area based on the L2P mapping table.

16. The memory controller of claim 14, wherein, The volatile storage device includes dynamic random access memory (DRAM), and the non-volatile storage device includes NAND flash memory.

17. The memory controller according to any one of claims 12-13, further comprising: A range partitioning accelerator, configured to: in response to receiving a write request indicating a second segment of first group data associated with a second logical address in the first group of logical addresses, assign the second segment of the first group of data to the second storage block in the storage block, and A host interface configured to: obtain the second fragment of the first group of data, and cache the second fragment of the first group of data in the second storage block.

18. The memory controller according to any one of claims 12-13, further comprising a host interface configured to: in response to receiving a read request indicating a second segment of the first group of data associated with a second logical address in the first group of logical addresses, retrieve the second segment of the first group of data from the second storage block in the storage block in the cache based on the L2P mapping table.

19. A method for operating a memory controller, comprising: Generate a logic-to-physical (L2P) mapping table stored in volatile storage devices; Maintain the L2P mapping table so that the L2P mapping table maps the first group of logical addresses to the identifiers (IDs) of the storage blocks in the cache. In response to receiving a read request indicating a first segment of data associated with a first logical address in the first group of logical addresses, the address of the L2P mapping table in the volatile storage device is determined based on the first logical address and an address offset associated with the L2P mapping table, wherein the address offset is determined based on the location where the L2P mapping table is stored in the volatile storage device. Identify the first ID at the address in the L2P mapping table of the volatile storage device; The first fragment of the first group of data is obtained from the first storage block in the storage block of the cache based on the first ID; the first storage block has the first ID. In response to receiving a write request indicating a second fragment of the first group of data associated with a second logical address in the first group of logical addresses, and in response to the second fragment of the first group of data being cached in the second storage block of the storage block in the cache, the L2P mapping table is updated to map the second logical address to a second ID of the second storage block; and In response to the second fragment of the first set of data being flushed from the second storage block of the cache to the storage area of ​​the non-volatile storage device associated with the physical address, the L2P mapping table is updated by replacing the second ID with the physical address to map the second logical address to the physical address.

20. The method of claim 19, further comprising: The first set of data is cached in the storage block, wherein the first set of data is associated with the first set of logical addresses.

21. The method of claim 20, further comprising: The first set of data is searched in the storage block based on the L2P mapping table.

22. The method according to any one of claims 19-21, wherein, The volatile storage device includes the cache.

23. The method according to any one of claims 19-21, further comprising: A second set of data is stored in the storage area of ​​the non-volatile storage device, wherein the second set of data is associated with a second set of logical addresses, and Maintain the L2P mapping table stored in the volatile storage device, such that the L2P mapping table also maps the second set of logical addresses to the physical addresses of the storage areas of the non-volatile storage device.

24. The method according to claim 23, wherein, The volatile storage device includes dynamic random access memory (DRAM), and the non-volatile storage device includes NAND flash memory.

25. The method according to any one of claims 19-21, further comprising: In response to receiving the write request indicating a second segment of the first group of data associated with the second logical address in the first group of logical addresses, the second segment of the first group of data is assigned to the second storage block in the storage block; as well as Obtain the second fragment of the first set of data, and cache the second fragment of the first set of data in the second storage block.

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