半导体器件及其制备方法、存储系统
By introducing an isolation structure into the semiconductor device and distributing negative charges at the contact surface of the semiconductor pillar, the electrical performance and reliability problems caused by the floating body effect are solved, and higher electrical performance and reliability are achieved.
CN119629991BActive Publication Date: 2026-07-17YANGTZE MEMORY TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2023-09-12
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
As semiconductor device sizes shrink and integration increases, the floating body effect leads to an increase in channel voltage, affecting device electrical performance and reliability.
Method used
The design employs a semiconductor pillar and isolation structure. The contact surface between the isolation structure and the semiconductor pillar is negatively charged, which neutralizes the positive charge accumulated in the channel region and reduces the impact of the buoyancy effect.
Benefits of technology
This improves the electrical performance and reliability of semiconductor devices and reduces interference between adjacent gate structures.
✦ Generated by Eureka AI based on patent content.
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Figure CN119629991B_ABST
Abstract
本申请实施方式提供了一种半导体器件及制备方法、存储器系统。半导体器件包括：半导体柱、栅极结构和隔离结构，其中半导体柱包括在第一方向相对的两个侧壁；栅极结构位于相对的两个侧壁中的一个；以及隔离结构至少位于相对的两个侧壁中的另一个，其中隔离结构与半导体柱接触的接触面分布有负电荷。
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