Silicon controlled device with high surge and high stability triggering characteristics and preparation method

Abstract

The present invention relates to the technical field of power devices, and specifically to a thyristor device with high surge and high stability triggering characteristics and a preparation method thereof. It comprises: a protective layer between a front base metal electrode and a front emitter metal electrode, and a polysilicon resistance region in the protective layer, which connects electrodes on both sides for shunting. In view of the problem that thyristor devices cannot have high trigger current and high surge resistance at the same time, a parallel path is formed between the front electrodes through the polysilicon resistance region for shunting, thereby increasing the trigger current IG value. This structure allows the device to use a lighter doped base region and a wider area emitter region, thereby improving surge resistance and withstand voltage performance. By limiting the parameters of the polysilicon resistance region, the polysilicon resistance region has a negative temperature coefficient, and temperature compensation is formed for the trigger current, thereby solving the problem that the existing thyristor trigger current changes with temperature, and the current decreases as the temperature rises.

Description

Technical Field

[0001] The present invention relates to the technical field of power devices, and in particular to a thyristor device with high surge and high stability triggering characteristics and a preparation method thereof. Background Art

[0002] Silicon controlled rectifier (SCR), also known as thyristor, is a component composed of four layers of PNPN semiconductor materials, with three PN junctions and three electrodes. It is a high-power electrical component. Bidirectional thyristor is developed on the basis of ordinary thyristor. It can replace two thyristors connected in parallel with opposite polarity, and only requires one trigger circuit. It is an ideal AC switching device. Thyristor is widely used in power electronics technology. It can be used in rectification, inversion, voltage regulation and other circuits to achieve precise control and conversion of electric energy. A large number of thyristors are used in household appliances such as electric fans, electric blankets, foot washing buckets, treadmills, soybean milk machines, vacuum cleaners, washing machines and air conditioners, as well as leakage protectors, two-wheeled vehicle chargers, motorcycle ignitions, and voltage regulators. However, with the development of society and the advancement of science and technology, thyristors have also begun to be used in high-power rectifiers, high-voltage direct current transmission systems, high-power heating control systems, solar inverters and wind power generation systems, which have high requirements for the withstand voltage, trigger current and surge resistance of thyristors.

[0003] In the prior art, there are many designs of thyristor devices. For example, Chinese patent CN202011349302.1 discloses a thyristor device. In this structure, a first blank doped region is provided on the upper part of the N-type well region; any equivalent structure includes a first N-type heavily doped region and a second P-type heavily doped region arranged side by side in the left and right directions; any equivalent structure is correspondingly provided with a second polysilicon; a second blank doped region is provided on the upper part of the P-type well region; the first polysilicon and the first blank doped region have an overlapped region, and cover the top of the second blank doped region; the silicide barrier layer has an overlapped region with the first P-type heavily doped region, and has an overlapped region with the first polysilicon, and also covers the top of the second blank doped region. A silicide barrier layer is provided on the N-type well region, and the good current limiting ability of the silicide barrier layer is utilized, and an equivalent diode region is provided in the N-type well region, so as to achieve the purpose of increasing the holding voltage of the SCR, effectively reduce the leakage risk of the SCR, and improve the electrostatic discharge protection performance of the SCR.

[0004] For another example, Chinese patent CN202211342900.5 discloses a thyristor device in the field of integrated circuits, comprising a substrate and a device area formed on the substrate, wherein a first N-well area and a first P-well area are arranged in the device area; a first N+ injection area, a first isolation groove and a first P+ injection area are arranged on the first N-well area; a second N+ injection area, a second isolation groove and a second P+ injection area are arranged on the first P-well area; the first N+ injection area and the first P+ injection area are connected by metal and connected to the anode; the second N+ injection area and the second P+ injection area are connected by metal and connected to the cathode; a third P+ injection area is arranged at the junction of the first P-well area and the first N-well area; a reverse P+ / Nwell diode is formed by the first N+ injection area, the first N-well area, the third P+ injection area, the first P-well area and the second P+ injection area; the holding voltage is improved, and the high robustness of the thyristor device is maintained.

[0005] However, during the actual implementation process, the inventors found that the existing thyristor devices cannot achieve high trigger current and high surge capability at the same time, which has limitations in some application scenarios. Summary of the invention

[0006] In view of the above problems existing in the prior art, a thyristor device with high surge and high stability triggering characteristics is provided; on the other hand, a preparation method of the thyristor device is also provided.

[0007] The specific technical scheme is as follows: a thyristor device with high surge and high stability triggering characteristics, the thyristor device includes a front base metal electrode and a front emitter metal electrode formed above the front base; the front base metal electrode and the front emitter metal electrode are isolated by a protective layer; a polysilicon resistance area is formed in the protective layer; two ends of the polysilicon resistance area are respectively connected to the front base metal electrode and the front emitter metal electrode on both sides for shunting.

[0008] On the other hand, the thyristor device also includes: a silicon single crystal sheet having a first conductivity type; the front base region is formed above the silicon single crystal sheet; the front base region has a second conductivity type; a front emitter region having the first conductivity type; the front emitter region is formed in a predetermined area of ​​the upper surface of the front base region and partially covers the upper surface of the front base region; the front emitter region metal electrode is formed above the front emitter region; the front base region metal electrode is formed above the upper surface of the front base region not covered by the front emitter region; the protective layer is formed above the front base region, in the area between the front base region metal electrode and the front emitter region metal electrode; a back base region, the back base region is formed below the silicon single crystal sheet; the back base region has the second conductivity type; a back metal electrode, the back metal electrode is formed below the back base region.

[0009] On the other hand, the protective layer includes a first protective layer; the first protective layer is formed above the front base region, located in the area between the front base region metal electrode and the front emitter region metal electrode; the polysilicon resistance region is formed above the first protective layer; the protective layer also includes a second protective layer; the second protective layer is formed above the polysilicon resistance region.

[0010] On the other hand, a plurality of the front emitter regions are formed at intervals in the front base region; the metal electrode of the front emitter region completely covers the two outermost front emitter regions; and the coverage ratio of the area of ​​the front emitter region in the front base region is greater than 80%.

[0011] On the other hand, at least one group of back emission regions is formed on the lower surface of the back base region; the lower surface of the back emission region is connected to the back metal electrode; and the back emission region has a first conductivity type.

[0012] On the other hand, the polysilicon resistance region is boron-doped polysilicon; the doping concentration of the polysilicon resistance region is less than 5E18㎝-3; the thickness of the polysilicon resistance region is between 1000Å and 10000Å; the width of the polysilicon resistance region is 50~200μm; the resistance value of the polysilicon resistance region is greater than 10Ω and less than 200Ω.

[0013] On the other hand, grooves are processed on both sides of the front base region; the depth of the grooves reaches the silicon single crystal wafer; and a passivation layer is formed in the grooves.

[0014] On the other hand, through-isolating diffusion regions are formed on the left and right sides of the thyristor device respectively.

[0015] A preparation method for preparing the above-mentioned thyristor device with high surge and high stability triggering characteristics; the preparation method comprises: step S1: preparing a front base region on the upper surface of a silicon single crystal wafer, and then preparing a front emitter region in the front base region; step S2: sequentially making a protective layer and a polysilicon resistance region above the front base region; the polysilicon resistance region is located in the middle of the protective layer; step S3: etching the protective layer and the polysilicon resistance region to form a predetermined processing area; the predetermined processing areas are respectively located on the left and right sides of the protective layer and the polysilicon resistance region; step S4: forming a front base metal electrode and a front emitter metal electrode in the predetermined processing area respectively; step S5: preparing a back base region and a back electrode below the silicon single crystal wafer.

[0016] On the other hand, in the step S5, after preparing the back base region, a back emission region is also formed in the back base region.

[0017] The above technical solution has the following advantages or beneficial effects: In view of the problem that the thyristor device in the prior art cannot have both high trigger current and high surge resistance, in this solution, a polysilicon resistance area is introduced between the metal electrode of the front base region and the metal electrode of the emitter region of the thyristor device, forming a parallel path in the device. This area can achieve effective shunting, thereby increasing the overall trigger current IG value of the device. At the same time, the use of a jumper resistor structure allows the device to use a lighter doped base region and a wider emitter region than the traditional structure, thereby effectively improving the device's surge capacity and withstand voltage performance. Furthermore, by limiting the parameters of the polysilicon resistance area, the polysilicon resistance area has a negative temperature coefficient, forming temperature compensation for the trigger current, thereby solving the problem that the existing thyristor trigger current changes with temperature, and the current decreases as the temperature rises. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The embodiments of the present invention will be described more fully with reference to the attached drawings, which are provided for illustration and description only and are not intended to limit the scope of the present invention.

[0019] Figure 1 This is a schematic diagram of Embodiment 1 of the present invention;

[0020] Figure 2 This is a schematic diagram of Embodiment 2 of the present invention;

[0021] Figure 3 Schematic diagram of the circuit diagram of Embodiments 1 and 2 of the present invention;

[0022] Figure 4 This is a schematic diagram of Embodiment 3 of the present invention;

[0023] Figure 5 This is a schematic diagram of a circuit diagram of Embodiment 3 of the present invention;

[0024] Figure 6 This is a schematic diagram of the preparation method of an embodiment of the present invention;

[0025] Figure 7 Schematic diagram of a silicon single crystal wafer during the preparation process of an embodiment of the present invention;

[0026] Figure 8 A schematic diagram of a protective layer during the preparation process of an embodiment of the present invention;

[0027] Fig. 9 A schematic diagram of a diffusion window for a through isolation diffusion region during the preparation process of an embodiment of the present invention;

[0028] Fig.10 A schematic diagram of the isolation diffusion region during the preparation process of an embodiment of the present invention;

[0029] Fig.11 A schematic diagram of removing the remaining protective layer during the preparation process of an embodiment of the present invention;

[0030] Fig.12 Schematic diagram of the front base region and the back base region during the preparation process of an embodiment of the present invention;

[0031] Fig.13 This is a schematic diagram of a new protective layer in the preparation process of an embodiment of the present invention;

[0032] Fig.14 This is a schematic diagram of the front emitting area window during the preparation process of an embodiment of the present invention;

[0033] Fig.15 A schematic diagram of the front emission area during the preparation process of an embodiment of the present invention;

[0034] Fig.16 A schematic diagram of a protective layer during the preparation process of an embodiment of the present invention;

[0035] Fig.17 A schematic diagram of a polysilicon resistance region during the preparation process of an embodiment of the present invention;

[0036] Fig.18 Schematic diagram of the protective layer A10 during the preparation process of an embodiment of the present invention;

[0037] Fig.19 A schematic diagram of a groove window during the preparation process of an embodiment of the present invention;

[0038] Fig. 20 A schematic diagram of a groove during the preparation process of an embodiment of the present invention;

[0039] Fig.21 A schematic diagram of a passivation layer during the preparation process of an embodiment of the present invention;

[0040] Fig. 22A schematic diagram of a base metal electrode deposition window and an emitter metal electrode deposition window during the preparation process of an embodiment of the present invention;

[0041] Fig.23 Schematic diagram of the back metal electrode during the preparation process of an embodiment of the present invention;

[0042] Fig.24 A schematic diagram of a front base metal electrode and a front emitter metal electrode during the preparation process of an embodiment of the present invention;

[0043] Fig.25 This is a schematic diagram of the top protective layer during the preparation process of an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0046] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0047] The present invention includes the following embodiments:

[0048] Embodiment 1:

[0049] A thyristor device with high surge and high stability trigger characteristics, such as Figure 1 As shown, the thyristor device includes: a silicon single crystal chip 1, which has a first conductivity type; a front base region 2, which is formed above the silicon single crystal chip 1; the front base region 2 has a second conductivity type; a front emitter region 3, which is formed in a predetermined area on the upper surface of the front base region 2 and partially covers the upper surface of the front base region; the front emitter region 3 has the first conductivity type.

[0050] A front base region metal electrode 4 and a front emitter region metal electrode 5 are formed above the front base region 2 and the front emitter region 3, respectively.

[0051] The front emitter metal electrode 5 is formed above the front emitter region 3 ; and the front base metal electrode 4 is formed above the upper surface of the front base region 2 that is not covered by the front emitter region 3 .

[0052] The front base metal electrode 4 and the front emitter metal electrode 5 are isolated by a protective layer composed of a first protective layer 61 and a second protective layer 62 .

[0053] A polysilicon resistance region 7 is formed in the protective layer; the protective layer is formed above the front base region, and is located in the area between the front base region metal electrode and the front emitter region metal electrode; the two ends of the polysilicon resistance region 7 are respectively connected to the front base region metal electrode 4 and the front emitter region metal electrode 5 on both sides for shunting.

[0054] Below the silicon single crystal wafer 1, it also includes: a back base region 8, which is formed below the silicon single crystal wafer 1; the back base region 8 has a second conductivity type; and a back metal electrode 9, which is formed below the back base region 8.

[0055] Specifically, in view of the problem that the thyristor device in the prior art cannot have both high trigger current and high surge resistance, in this solution, a polysilicon resistance region 7 is introduced between the front base metal electrode 4 and the front emitter metal electrode 5 of the thyristor device, forming a conductive path in the device, which can achieve effective shunting, thereby increasing the overall trigger current of the device. At the same time, the use of a jumper resistor structure allows the device to use a lighter doped front base region 2 and a wider front emitter region 3 relative to the traditional structure, thereby effectively improving the device's surge capacity and withstand voltage performance.

[0056] Specifically, the above structure is a typical thyristor device, wherein the front base metal electrode 4 and the front emitter metal electrode 5 are respectively formed on the front side of the device.

[0057] A silicon single crystal wafer 1 having a first conductivity type is used as a substrate structure, and a predetermined depth above the silicon single crystal wafer 1 is doped by diffusion or ion implantation to form a front base region 2 having a second conductivity type.

[0058] A front emitter region 3 having a first conductivity type is formed by doping on a portion of the surface on the left or right side of the front base region 2 through diffusion or ion implantation.

[0059] Above these two areas, a front base metal electrode 4 and a front emitter metal electrode 5 are formed by evaporation, chemical vapor deposition and other processes, respectively forming electrical connections with the front base 2 and the front emitter 3 below, and the front base metal electrode 4 and the front emitter metal electrode 5 are isolated by insulating materials such as SiO2 or other equivalent materials.

[0060] Since the trigger current and surge resistance of the device depend on factors such as doping concentration, high trigger current and high surge resistance cannot usually be achieved at the same time. To address this problem, this embodiment introduces a polysilicon resistance region 7 in the protective layer to connect the front base metal electrode 4 and the front emitter metal electrode 5 at both ends to form an additional conductive path.

[0061] The polysilicon resistance area 7 is a resistance area formed by doping or not doping with polysilicon material. It has a higher resistance than the metal conductive layer, which helps to improve the withstand voltage level of the device. At the same time, it can conduct electricity between the front base metal electrode 4 and the front emitter metal electrode 5 on both sides, and improve the overall high trigger current of the device by parallel connection. Furthermore, the structure across the polysilicon resistance area 7 can select a second conductive type front base area 2 with a lighter doping and a wider area front emitter area 3 compared to the traditional structure, thereby effectively improving the surge capacity and withstand voltage of the device.

[0062] In another additional embodiment, the polysilicon resistance region 7 is boron-doped polysilicon; the doping concentration of the polysilicon resistance region is less than 5E18㎝-3; specifically, the thyristor devices in the prior art often have the problem that the trigger current changes with temperature, and the trigger current IG value decreases with temperature increase. In view of this problem, in this embodiment, the parameters of the polysilicon resistance region 7 are controlled within the above parameter range, so that the polysilicon resistance region 7 has a negative temperature coefficient, which can form temperature compensation for the trigger current. Thereby solving the problem that the trigger current of the existing thyristor changes with temperature, and the current decreases with temperature increase.

[0063] In another additional embodiment, the thickness of the polysilicon resistance region 7 is between 1000Å and 10000Å; the width of the polysilicon resistance region 7 is between 50 and 200 μm.

[0064] Specifically, depending on the device selection, the demand for trigger current is also different. Therefore, in this embodiment, according to different device selection combinations, the thickness of the polysilicon resistance area 7 is controlled between 1000Å and 10000Å, and the width is between 50~200μm to match devices of different sizes, and the resistance value of the polysilicon resistance area 7 is controlled to vary between 10Ω and 200Ω to meet relevant needs.

[0065] And, to achieve better device performance, the thickness of the silicon single crystal wafer 1 is 150 μm-450 μm; the crystal orientation of the silicon single crystal wafer is <100> or <111> ; At the same time, the resistivity of the front base region 2 should be controlled to be greater than 10Ω·cm.

[0066] Based on the above performance parameters, a thyristor device with a voltage higher than 1200V and a trigger current greater than 100mA can be obtained.

[0067] In another additional embodiment, through-isolating diffusion regions 10 are formed on the left and right sides of the thyristor device, respectively.

[0068] Specifically, in order to achieve a better isolation and protection effect on the device, in this embodiment, through isolation diffusion regions 10 are formed on the left and right sides of the thyristor device respectively.

[0069] Specifically, in the process of processing the silicon single crystal wafer 1, a protective layer can be made on the front and back sides of the device in advance, and then a diffusion area window can be processed at the corners. Subsequently, a through diffusion process is used to form a through isolation diffusion area 10 on the left and right sides of the thyristor device, and on this basis, structures such as the front base area 2 and the front emitter area 3 are made.

[0070] In another additional embodiment, the protective layer includes a first protective layer 61; the first protective layer 61 is formed above the front base region 2, located in the area between the front base region metal electrode 4 and the front emitter region metal electrode 5; the polysilicon resistance region 7 is formed above the first protective layer 61; the protective layer also includes a second protective layer 62; the second protective layer 62 is formed above the polysilicon resistance region 7.

[0071] Specifically, in order to achieve better isolation between the two electrodes, in this embodiment, a first protective layer 61 and a second protective layer 62 are provided to form a protective layer.

[0072] Specifically, in the process of making the protective layer, a complete first protective layer 61 is first made above the front base area 2 and the front emitter area 3. The first protective layer 61 is mainly formed of insulating materials, such as SiO2 or other equivalent materials, and then a polysilicon resistance area 7 and a second protective layer 62 are made thereon.

[0073] The material of the second protective layer 62 is the same as or different from that of the first protective layer 61. The first protective layer 61 and the second protective layer 62 clamp the polysilicon resistance area 7 to simultaneously achieve isolation between the front base metal electrode 4 and the front emitter metal electrode 5 on both sides and the formation of a conductive channel.

[0074] At the same time, in order to protect the corners of the device and prevent water vapor from entering, in some embodiments, a protective layer is also made of SiO2 or other equivalent materials on the corners of the device, mainly including the joint area between the front base region 2 and the front base metal electrode 4, the area between the front emitter region 3 and the front emitter metal electrode 5, the outer corners of the front base metal electrode 4, the outer corners of the front emitter metal electrode 5, and the left and right sides of the through isolation diffusion region 10.

[0075] In another additional embodiment, grooves 11 are processed on both sides of the front base region 2 ; the depth of the grooves 11 reaches the silicon single crystal wafer 1 ; and a passivation layer 12 is formed in the grooves 11 .

[0076] Specifically, in order to ensure that the current region has a certain distance from the edge isolation diffusion region 10, in this embodiment, grooves 11 are also processed on both sides of the front base region 2 so that the positions of the front base region 2, the front emitter region 3 and the upper front base region metal electrode 4 and the front emitter region metal electrode 5 are limited.

[0077] Generally speaking, in the process of preparing the front base region 2 , trenches 11 are opened on both sides, and other parts of the active region are prepared in the area defined by the trenches 11 , thereby limiting the width of the active region.

[0078] At the same time, in order to prevent water vapor from entering and affecting the life of the device, after the groove 11 is opened, SiO2 or other equivalent materials are backfilled therein to form a passivation layer 12.

[0079] In the above embodiment, the thickness of the silicon single crystal 1 is configured to be 300 μm; the resistivity of the front base region 2 is 20 Ω·cm; the exposed area ratio of the front emitter region 3 to the front base region 2 is 85%; the doping concentration of the polysilicon resistance region 7 is 3.5E18 cm -3 , with a thickness of 1500Å; the width of the polysilicon resistance region 7 is 60μm.

[0080] The first conductivity type is N type, and the second conductivity type is P type; or, the first conductivity type is P type, and the second conductivity type is N type.

[0081] Embodiment 2:

[0082] A thyristor device with high surge and high stability trigger characteristics, such as Figure 2 As shown, the thyristor device includes: a silicon single crystal chip 1, which has a first conductivity type; a front base region 2, which is formed above the silicon single crystal chip 1; the front base region 2 has a second conductivity type; a front emitter region 3, which is formed in a predetermined area on the upper surface of the front base region 2, and a plurality of front emitter regions 3 are arranged at intervals; each front emitter region 3 is processed into a groove shape or an independent shallow diffusion region, and each front emitter region 3 has a certain interval between them.

[0083] The front emitter region 3 has a first conductivity type.

[0084] A front base region metal electrode 4 and a front emitter region metal electrode 5 are formed above the front base region 2 and the front emitter region 3 respectively.

[0085] The front emitting region metal electrode 5 is formed above the front emitting region 3 , and the front emitting region metal electrode 5 completely covers the emitting area defined by the two outermost front emitting regions 3 .

[0086] The front base metal electrode 4 is formed above the upper surface of the front base region 2 that is not covered by the front emitter region 3 .

[0087] The front base metal electrode 4 and the front emitter metal electrode 5 are isolated by a protective layer composed of a first protective layer 61 and a second protective layer 62 .

[0088] A polysilicon resistance region 7 is formed in the protective layer; the protective layer is formed above the front base region, and is located in the area between the front base region metal electrode and the front emitter region metal electrode; the two ends of the polysilicon resistance region 7 are respectively connected to the front base region metal electrode 4 and the front emitter region metal electrode 5 on both sides for shunting.

[0089] Below the silicon single crystal wafer 1, it also includes: a back base region 8, which is formed below the silicon single crystal wafer 1; the back base region 8 has a second conductivity type; and a back metal electrode 9, which is formed below the back base region 8.

[0090] Grooves 11 are processed on both sides of the front base region 2 ; the depth of the grooves 11 reaches the silicon single crystal wafer; and a passivation layer 12 is formed in the grooves 11 .

[0091] Through isolation diffusion regions 10 are formed on the left and right sides of the silicon single crystal wafer 1, respectively.

[0092] Specifically, relative to Example 1, in this embodiment, in the process of setting the front emission region 3, a plurality of discontinuous windows with specific intervals are defined on the front base region 2 by using a photoresist or etching an oxide layer before the diffusion or ion implantation process, and the front emission region 3 is prepared in the window, thereby forming a plurality of spaced front emission regions 3, each of which has a specific interval between them.

[0093] It should be noted that in order to meet the relevant performance of the device, no matter whether the front emission region 3 is continuous or discontinuous, the coverage area ratio of the emission region defined by the two side edges of the front emission region 3 in the front base region 2 should be greater than 80%.

[0094] In this embodiment, the thickness of the silicon single crystal 1 is adjusted to 200 μm; the resistivity of the front base region 2 is 40 Ω·cm; the exposed area ratio of the front emitter region 3 to the front base region 2 is 87%; the doping concentration of the polysilicon resistance region 7 is 2.5E18 cm -3 , with a thickness of 2500Å; the width of the polysilicon resistance region 7 is 60μm.

[0095] The number of the front emitting regions 3 is configured as three, and the interval between each front emitting region 3 is 20 μm.

[0096] Embodiment three:

[0097] A thyristor device with high surge and high stability trigger characteristics, such as Figure 4 As shown, the thyristor device includes: a silicon single crystal chip 1, which has a first conductivity type; a front base region 2, which is formed above the silicon single crystal chip 1; the front base region 2 has a second conductivity type; a group of front short base regions 21 are also buried in the front base region 2, which have different doping concentrations, thereby achieving different resistivities.

[0098] The front emitter region 3 is formed in a predetermined area on the upper surface of the front base region 2 and partially covers the upper surface of the front base region; the front emitter region 3 has a first conductivity type.

[0099] A front base region metal electrode 4 and a front emitter region metal electrode 5 are formed above the front base region 2 and the front emitter region 3 respectively.

[0100] The front emitting region metal electrode 5 is formed above the front emitting region 3 , and the front emitting region metal electrode 5 completely covers the emitting area defined by the two outermost front emitting regions 3 .

[0101] The front base metal electrode 4 is formed above the upper surface of the front base region 2 that is not covered by the front emitter region 3 .

[0102] The front base metal electrode 4 and the front emitter metal electrode 5 are isolated by a protective layer composed of a first protective layer 61 and a second protective layer 62 .

[0103] A polysilicon resistance region 7 is formed in the protective layer; the protective layer is formed above the front base region, and is located in the area between the front base region metal electrode and the front emitter region metal electrode; the two ends of the polysilicon resistance region 7 are respectively connected to the front base region metal electrode 4 and the front emitter region metal electrode 5 on both sides for shunting.

[0104] Below the silicon single crystal wafer 1, it also includes: a back base region 8, which is formed below the silicon single crystal wafer 1; the back base region 8 has the second conductivity type; at least one back emission region 13 is formed in the back base region 8; the back emission region 13 has the first conductivity type.

[0105] The back metal electrode 9 is formed below the back base region 8 .

[0106] Grooves 11 are processed on both sides of the front base region 2 ; the depth of the grooves 11 reaches the silicon single crystal wafer; and a passivation layer 12 is formed in the grooves 11 .

[0107] Through isolation diffusion regions 10 are formed on the left and right sides of the silicon single crystal wafer 1, respectively.

[0108] Specifically, compared with the first embodiment, in this embodiment, a group of front short base regions 21 are added to the front base region 2, which changes the resistivity in the region through different doping concentrations.

[0109] The front short base region 21 is formed on the basis of the front base region 2 by further changing the doping concentration of the portion through processes such as diffusion or ion implantation, thereby adjusting the local resistivity of the region.

[0110] At the same time, at least one back-side emission region 13 is formed in the back-side base region 8 by diffusion or ion implantation or other processes, and the back-side emission region 13 has the first conductivity type.

[0111] In this embodiment, the thickness of the silicon single crystal 1 is adjusted to 400 μm; the resistivity of the front base region 2 is 40 Ω·cm; the resistivity of the front short base region 21 is 60 Ω·cm; the exposed area ratio of the front emitter region 3 and the front base region 2 is 90%; the doping concentration of the polysilicon resistance region 7 is 1.5E18 cm -3 , with a thickness of 3500Å; the width of the polysilicon resistance region 7 is 180μm.

[0112] The number of the front emitting regions 3 is configured as three, and the interval between each front emitting region 3 is 50 μm.

[0113] The number of back-emitting regions 13 is two.

[0114] The above three embodiments are three typical embodiments. In the actual preparation process, the combination of technical features in each embodiment can be adjusted as needed. For example, the position and number of the front emission area, the back emission area and the front short base area can be appropriately adjusted, or part of the passivation layer, the protective layer, the through isolation diffusion area, etc. can be omitted.

[0115] The present invention also provides a preparation method for preparing the above-mentioned thyristor device with high surge and high stability triggering characteristics; Figure 5 As shown, the preparation method includes: step S1: preparing a front base region on the upper surface of a silicon single crystal wafer, and then preparing a front emitter region in the front base region; step S2: sequentially forming a protective layer and a polysilicon resistance region above the front base region; the polysilicon resistance region is located in the middle of the protective layer; step S3: etching the protective layer and the polysilicon resistance region to form a predetermined processing area; the predetermined processing areas are respectively located on the left and right sides of the protective layer and the polysilicon resistance region; step S4: forming a front base metal electrode and a front emitter metal electrode in the predetermined processing area respectively; step S5: preparing a back base region and a back electrode below the silicon single crystal wafer.

[0116] Specifically, in order to achieve a better preparation effect, in this embodiment, it is selected to sequentially prepare the protection layer and the polysilicon resistance region on the basis of preparing the front base region and the front emitter region.

[0117] Specifically, it is a sandwich structure of a protective layer, a polysilicon resistance area and a protective layer, so that the polysilicon resistance area is located in the middle of the protective layer, and then the unnecessary protective layer and polysilicon resistance area are removed by etching to form an isolation area between the two electrodes and a conductive channel in the middle.

[0118] Accordingly, the front base metal electrode and the front emitter metal electrode can be formed in the etched predetermined processing area by evaporation, chemical vapor deposition and other methods.

[0119] Subsequently, the substrate is turned over, thinned and planarized from the back, and a back base region and a back metal electrode are prepared.

[0120] In the above process, as needed, the steps of trench etching, passivation layer formation, through diffusion region preparation, front short base region formation, back emission region formation, etc. will be added to the corresponding steps.

[0121] For example, in one embodiment, in step S5, after the substrate is turned over and thinned, the back base region is first prepared by diffusion or ion implantation, and then the back emission region window is defined by photoresist.

[0122] A back emission region is formed in the back emission region window by a diffusion process, and then the photoresist is removed to form a back electrode on the back side.

[0123] A typical device manufacturing process is provided below, which can be used to obtain a thyristor device similar to that of the first embodiment.

[0124] First, if Figure 7 As shown, a silicon single crystal wafer A1 having a first conductivity type is obtained, and the silicon single crystal wafer A1 has a front side and a back side.

[0125] Then, if Figure 8 As shown, an oxidation process is performed on the silicon single crystal wafer A1 to form a protective layer A2 on both the front and back sides of the silicon single crystal wafer A1; then Fig. 9 As shown, the protective layer A2 is etched to form diffusion windows for the isolation diffusion regions on the front and back sides of the silicon single crystal A1; then Fig.10 As shown, a diffusion process is performed to form a through isolation diffusion region A3 on both sides of the silicon single crystal A1; after diffusion, as shown in FIG. Fig.11As shown, the remaining SiO2 protective layer A2 on the front and back surfaces of the silicon single crystal wafer A1 is etched to remove the remaining protective layer A2, so that the front and back surfaces of the silicon single crystal wafer 1 are completely exposed; then, as shown Fig.12 As shown, two diffusion processes are performed in sequence to form a front base region A4 and a back base region A5 on the front and back surfaces of the silicon single crystal A1 respectively; on this basis, as shown in FIG. Fig.13 As shown, the front base region A4 and the back base region A5 are oxidized to form a new protective layer A6; then, as shown Fig.14 As shown, a portion of the protective layer A6 is removed by etching on the front side of the device to define a front emission area window; Fig.15 As shown, diffusion is performed in the front emission region window to form a front emission region A7; it should be noted that in this step, if it is necessary to prepare a front short base region, the etching position can be controlled to simultaneously define the front short base region window, and a front short base region can be formed on the other side through different diffusions; similarly, if it is necessary to prepare multiple front emission region windows, multiple discontinuous front emission region windows can be defined during the etching process.

[0126] Then, if Fig.16 As shown, oxidation is performed again to form a protective layer A8 above the front base region A4 and the front emitter region A7; Fig.17 As shown, on the protective layer A8, a polysilicon resistance region A9 is grown and doped by using a chemical vapor deposition process; then, as shown in FIG. Fig.18 As shown, chemical vapor deposition is performed again on the polysilicon resistance region A9 to form a protective layer A10; then as shown in FIG. Fig.19 , 20 As shown, deep etching is performed on both sides of the protective layer A10, passing through the protective layer A10, the polysilicon resistance area A9, the protective layer A8 and the front base area A4 to reach the silicon single crystal A1, forming a pair of grooves A11; the grooves A11 are located on the inner side of the through isolation diffusion area A3.

[0127] Then, if Fig.21 As shown, the trench A11 is passivated, and a passivation layer A12 is grown in the trench A11; then, as shown Fig. 22 As shown, etching is performed again, and the etching depth includes the protection layer A10 and the polysilicon resistance area A9, thereby defining the base metal electrode deposition window and the emitter metal electrode deposition window; at the same time, the protection layer A6 on the back of the device is etched to expose the back base area A5.

[0128] It should be noted that if a back emission area needs to be prepared, before this step, at least one back emission area window should be defined by etching, and then diffusion should be performed to form the back emission area, followed by re-oxidation and etching to expose the back base area A5.

[0129] Then, if Fig.23 As shown, metal material is deposited on the front and back sides of the device by chemical vapor deposition, thereby forming a complete back metal electrode A13 on the back side of the device; Fig.24 As shown, the front side is then etched to form a front base metal electrode A14 and a front emitter metal electrode A15; Fig.25 As shown, vapor deposition and etching are finally performed to form a top protective layer A16.

[0130] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A thyristor device with high surge and high stability triggering characteristics, characterized in that: The thyristor device comprises a front base metal electrode and a front emitter metal electrode formed above the front base region; The front base metal electrode and the front emitter metal electrode are isolated by a protective layer; A polysilicon resistance region is formed in the protective layer; Two ends of the polysilicon resistance region are respectively connected to the front base region metal electrode and the front emitter region metal electrode on both sides for current shunting; The polysilicon resistance region is boron-doped polysilicon; The doping concentration of the polysilicon resistance region is less than 5E18㎝-3; The resistance value of the polysilicon resistance region has a negative temperature coefficient; The thickness of the polysilicon resistance region is between 1000Å and 10000Å; The width of the polysilicon resistance region is 50-200 μm; The resistance value of the polysilicon resistance region is greater than 10Ω and less than 200Ω.

2. The thyristor device according to claim 1, characterized in that: The thyristor device also includes: A silicon single crystal wafer having a first conductivity type; The front base region is formed above the silicon single crystal wafer; The front base region has a second conductivity type; A front emitting region having a first conductivity type; The front emitter region is formed in a predetermined area of ​​the upper surface of the front base region and partially covers the upper surface of the front base region; The front emitting region metal electrode is formed above the front emitting region; The front base metal electrode is formed above the upper surface of the front base region that is not covered by the front emitter region; The protection layer is formed above the front base region and is located in a region between the front base region metal electrode and the front emitter region metal electrode; A back base region, wherein the back base region is formed below the silicon single crystal wafer; The back base region has a second conductivity type; A back metal electrode is formed below the back base region.

3. The thyristor device according to claim 1, characterized in that: The protective layer comprises a first protective layer; The first protection layer is formed above the front base region and is located in a region between the front base region metal electrode and the front emitter region metal electrode; The polysilicon resistance region is formed above the first protection layer; The protective layer also includes a second protective layer; The second protection layer is formed above the polysilicon resistance region.

4. The thyristor device according to claim 2, characterized in that: The front emitter region is formed in a plurality of intervals in the front base region; The front emitting region metal electrode completely covers the two outermost front emitting regions; The coverage ratio of the area of ​​the front emitting region to the front base region is greater than 80%.

5. The thyristor device according to claim 2, characterized in that: At least one group of back emitting regions is formed on the lower surface of the back base region; The lower surface of the back emitting region is connected to the back metal electrode; The back emitting region has a first conductivity type.

6. The thyristor device according to claim 2, characterized in that: Grooves are processed on both sides of the front base area; The depth of the groove reaches the silicon single crystal wafer; A passivation layer is formed in the groove.

7. The thyristor device according to claim 2, characterized in that: The left and right sides of the thyristor device are respectively formed with through isolation diffusion regions.

8. A preparation method, characterized in that: Used to prepare a thyristor device with high surge and high stability triggering characteristics as described in any one of claims 1 to 7; The preparation method comprises: Step S1: preparing a front base region on the upper surface of a silicon single crystal wafer, and then preparing a front emitter region in the front base region; Step S2: forming a protection layer and a polysilicon resistance region in sequence above the front base region; The polysilicon resistance region is located in the middle of the protective layer; Step S3: etching the protection layer and the polysilicon resistance region to form a predetermined processing region; The predetermined processing area is located at the left and right sides of the protective layer and the polysilicon resistance area respectively; Step S4: forming a front base metal electrode and a front emitter metal electrode in the predetermined processing area respectively; Step S5: preparing a back base region and a back metal electrode below the silicon single crystal wafer.

9. The preparation method according to claim 8, characterized in that: In the step S5, after preparing the back base region, a back emission region is also formed in the back base region.

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