Thin Film Transistors and Display Panels

Abstract

This application relates to a thin-film transistor (TFT) and a display panel. The TFT includes a substrate, a light-shielding layer, a buffer layer, an active layer, a gate, a source, and a drain. The light-shielding layer includes multiple spaced-apart first light-shielding portions. The buffer layer above the light-shielding layer has a first uneven structure, and a channel portion is disposed above the first uneven structure and has a second uneven structure. The TFT of this application has a light-shielding layer composed of multiple spaced-apart first light-shielding portions, resulting in a buffer layer above the light-shielding layer having a first uneven structure, and a channel portion formed above the first uneven structure, resulting in a channel portion having a second uneven structure. Because the channel portion is uneven, it fully utilizes the vertical space of the TFT, reducing the horizontal space occupied by the channel portion, thereby reducing the overall size of the TFT and facilitating the fabrication of high-resolution display panels.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a thin-film transistor and a display panel. Background Technology

[0002] To fabricate display panels with narrow bezels and high resolution, the size of thin-film transistors (TFTs) needs to be further reduced. However, in the current mainstream top-gate TFT structure, the gate and channel are planar structures, resulting in a relatively large TFT size. It is difficult to further reduce the size of TFTs using the existing structure. Summary of the Invention

[0003] This application provides a thin-film transistor and a display panel to solve the above-mentioned problems.

[0004] To achieve the above objectives, according to a first aspect of this application, a thin-film transistor is provided, comprising:

[0005] Substrate;

[0006] A light-shielding layer is disposed on one side of the substrate and includes a plurality of spaced-apart first light-shielding portions;

[0007] A buffer layer is disposed on the side of the light-shielding layer away from the substrate;

[0008] An active layer is disposed on the side of the buffer layer away from the light-shielding layer, and the active layer includes a channel portion and a conductor portion located at the end of the channel portion;

[0009] A gate is disposed on the side of the active layer away from the buffer layer; and

[0010] The source and drain are disposed on the side of the gate away from the active layer and are connected to the conductor portion;

[0011] The buffer layer located above the light-shielding layer has a first uneven structure, and the channel portion is disposed above the first uneven structure and has a second uneven structure.

[0012] In some embodiments, the channel portion includes a plurality of sidewalls, the plurality of sidewalls including a first sidewall located at the edge of the channel portion and a second sidewall located in the middle region of the channel portion, the inclination angle of the second sidewall being greater than or equal to the inclination angle of the first sidewall.

[0013] In some embodiments, the light-shielding layer further includes a second light-shielding portion, which is located at least between adjacent first light-shielding portions and connected to the first light-shielding portions, and the thickness of the second light-shielding portion is less than the thickness of the first light-shielding portion, and the side of the light-shielding layer away from the substrate has an uneven shape.

[0014] In some embodiments, the thickness of the second light-shielding portion is 5% to 85% of the thickness of the first light-shielding portion.

[0015] In some embodiments, the light-shielding layer further includes a connecting portion, and a plurality of the first light-shielding portions are connected to the connecting portion, wherein the orthographic projection of the connecting portion on the substrate does not overlap with the orthographic projection of the channel portion on the substrate.

[0016] In some embodiments, the first light-shielding portion is strip-shaped and extends along a first direction, and a plurality of the first light-shielding portions are arranged at intervals along a second direction, the second direction being perpendicular to the first direction.

[0017] In some embodiments, the first light-shielding portion is strip-shaped and extends along a second direction, and a plurality of the first light-shielding portions are arranged at intervals along a first direction, wherein the second direction is perpendicular to the first direction.

[0018] In some embodiments, the protrusion has opposing top and bottom surfaces, the first light-shielding portion is columnar, and a plurality of the first light-shielding portions are arranged in an array along a first direction and a second direction, the second direction being perpendicular to the first direction.

[0019] In some embodiments, the tilt angle β of the side of the first light-shielding part ranges from 20° to 80°; the distance W1 between adjacent first light-shielding parts ranges from 2µm to 5µm.

[0020] According to a second aspect of this application, a display panel is provided, including thin-film transistors as described in the first aspect.

[0021] This application provides a thin-film transistor and a display panel. The light-shielding layer of the thin-film transistor of this application is composed of a plurality of spaced-apart first light-shielding portions. Since the plurality of first light-shielding portions are spaced apart, there is a gap between adjacent first light-shielding portions. A buffer layer located above the light-shielding layer is formed between the surface of the first light-shielding portions and the gap, so that the buffer layer formed above the light-shielding layer has a first concave-convex structure. The channel portion is formed on the first concave-convex structure, so the channel portion has a second concave-convex structure corresponding to the first concave-convex structure. Since the channel portion is concave-convex, the space of the thin-film transistor in the vertical direction is fully utilized, which is equivalent to compressing the distance of the channel portion in the horizontal direction. Therefore, the space occupied by the thin-film transistor in the horizontal direction can be reduced. Therefore, when fabricating a thin-film transistor with a channel portion of the same actual length, the overall size of the thin-film transistor of this application is smaller than the overall size of the thin-film transistor with a planar channel portion in the prior art, which is more conducive to the fabrication of high-resolution display panels. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0024] Figure 1 This is a cross-sectional view of a thin-film transistor provided by existing technology;

[0025] Figure 2 This is a cross-sectional view of one of the thin-film transistors provided in the embodiments of this application;

[0026] Figure 3 This is a cross-sectional view of one of the thin-film transistors provided in the embodiments of this application;

[0027] Figure 4 This is a cross-sectional view of one of the thin-film transistors provided in the embodiments of this application;

[0028] Figure 5 This is a cross-sectional view of one of the thin-film transistors provided in the embodiments of this application;

[0029] Figure 6 This is a planar schematic diagram of one type of thin-film transistor provided in an embodiment of this application;

[0030] Figure 7This is a schematic cross-sectional view of the first light-shielding portion of a thin-film transistor provided in an embodiment of this application;

[0031] Figure 8 This is a planar schematic diagram of one type of thin-film transistor provided in an embodiment of this application;

[0032] Figure 9 This is a planar schematic diagram of one type of thin-film transistor provided in an embodiment of this application;

[0033] Figure 10 This is a planar schematic diagram of one type of thin-film transistor provided in an embodiment of this application;

[0034] Figure 11 This is a planar schematic diagram of one type of thin-film transistor provided in an embodiment of this application;

[0035] Figure 12 yes Figure 11 A schematic diagram of the structure of the first light-shielding part of a thin-film transistor is provided.

[0036] Explanation of reference numerals in the attached figures:

[0037] 100, Thin-film transistor; 110, Substrate; 120, Light-shielding layer; 121, First light-shielding portion; 1211, Side surface; 12111, First side surface; 12112, Second side surface; 12113, Third side surface; 12114, Fourth side surface; 1212, Top surface; 1213, Bottom surface; 122, Second light-shielding portion; 123, Connector portion; 130, Buffer layer; 1301, First uneven structure; 140, Active layer; 141, Channel portion; 1411, Second uneven structure Structure; 1412, protruding portion; 1413, recessed portion; 1414, sidewall; 1414a, first sidewall; 1414b, second sidewall; 142, conductor portion; 1421, source connection portion; 1422, drain connection portion; 150, gate insulating layer; 1501, third concave-convex structure; 160, gate; 1601, fourth concave-convex structure; 170, interlayer insulating layer; 171, first via; 172, second via; 181, source; 182, drain. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0039] Please see Figure 1 , Figure 1This is a cross-sectional view of a thin-film transistor (TFT) provided in the prior art. The existing TFT includes a substrate 110, a light-shielding layer (LS) 120, a buffer layer 130, an active layer 140, a gate insulating layer (GI) 150, a gate (GE) 160, an interlayer insulating layer (ILD) 170, and a source 181 and a drain 182, which are stacked sequentially. The active layer 140 includes a channel portion 141, with a first direction X defined as the channel length direction, and the actual length of the channel portion 141 in the first direction X is L1. The orthogonal projection of the light-shielding layer 120 onto the substrate 110 at least covers the orthogonal projection of the channel portion 141 onto the substrate 110. The light-shielding layer 120 protects the channel portion 141 to prevent light emitted from the backlight from illuminating photogenerated carriers generated in the semiconductor layer and damaging the electrical properties of the semiconductor, and to block the influence of impurities. The orthogonal projection of the gate 160 onto the substrate 110 is within the range of the orthogonal projection of the channel portion 141 onto the substrate 110. In existing thin-film transistors, the gate 160 and the channel 141 are usually planar structures, which makes the thin-film transistors large in size and difficult to compress, thus limiting the fabrication of high-resolution (PPI) products.

[0040] Resolution (Pixels Per Inch, PPI) is a metric used to measure image resolution. It represents the number of pixels contained within a single inch of surface area. A higher PPI value means richer image detail because there are more pixels per unit area, resulting in higher image clarity and quality. Therefore, to achieve high resolution, pixel size needs to be compressed, and TFT size reduced.

[0041] This application provides a thin-film transistor 100, please refer to... Figures 2-4 The thin-film transistor 100 includes a substrate 110, a light-shielding layer 120, a buffer layer 130, an active layer 140, a gate 160, a source 181, and a drain 182. The light-shielding layer 120 is disposed on one side of the substrate 110 and includes a plurality of spaced-apart first light-shielding portions 121. The buffer layer 130 is disposed on the side of the light-shielding layer 120 away from the substrate 110. The active layer 140 is disposed on the side of the buffer layer 130 away from the light-shielding layer 120 and includes a channel portion 141 and a... The conductor portion 142 is located at the end of the channel portion 141; the gate 160 is disposed on the side of the active layer 140 away from the buffer layer 130; the source 181 and the drain 182 are disposed on the side of the gate 160 away from the active layer 140 and are respectively connected to the conductor portion 142; wherein, the buffer layer 130 located above the light-shielding layer 120 has a first uneven structure 1301, and the channel portion 141 is disposed above the first uneven structure 1301 and has a second uneven structure 1411.

[0042] In this application, the number of first light-shielding portions 121 included in the light-shielding layer 120 can be two, three, four, or more. Please refer to [link / reference needed]. Figures 2-4 , Figure 2 The light-shielding layer 120 of the thin-film transistor shown includes two first light-shielding portions 121. Figure 3 The light-shielding layer 120 of the thin-film transistor shown includes three first light-shielding portions 121. Figure 4 The light-shielding layer 120 of the thin-film transistor shown includes four first light-shielding portions 121. Specifically, the number of first light-shielding portions 121 included in the light-shielding layer 120 can be designed according to the actual size of the thin-film transistor, and no specific limitation is made here.

[0043] Please refer to the following in this application: Figures 2-4 The conductor portion 142 of the active layer 140 includes a source connection portion 1421 and a drain connection portion 1422 located on opposite sides of the channel portion 141 in the first direction X. The source 181 is connected to the source connection portion 1421 through a first via 171, and the drain 182 is connected to the drain connection portion 1422 through a second via 172. The channel portion 141 is located between the source 181 and the drain 182 as a carrier channel. The size of the channel portion 141 is an important factor determining the size of the thin-film transistor. The first direction X is the channel length direction.

[0044] For further details, please refer to Figure 3 The thin-film transistor 100 further includes, but is not limited to, a gate insulating layer 150 located between the active layer 140 and the gate 160, an interlayer insulating layer 170 located between the gate 160 and the source 181 and drain 182, and a passivation layer (PV) located on the side of the source 181 and drain 182 away from the interlayer insulating layer 170. The gate insulating layer 150 above the channel portion 141 has a third uneven structure 1501 corresponding to the second uneven structure 1411, and the gate 160 above the gate insulating layer 150 has a fourth uneven structure 1601 corresponding to the third uneven structure 1501.

[0045] The light-shielding layer 120 of the thin-film transistor 100 of this application is composed of a plurality of spaced-apart first light-shielding portions 121. Since the plurality of first light-shielding portions 121 are spaced apart, there are gaps between adjacent first light-shielding portions 121. A buffer layer 130 located above the light-shielding layer 120 is formed between the surfaces of the first light-shielding portions 121 and the gaps, such that the buffer layer 130 formed above the light-shielding layer 120 has a first uneven structure 1301. A channel portion 141 is formed on the first uneven structure 1301, therefore the channel portion 141 has a second uneven structure 1411 corresponding to the first uneven structure 1301. By forming a portion of the channel portion 141 on the sidewall of the first concave-convex structure 1301, the space of the thin-film transistor 100 in the vertical direction (i.e., the Z direction) is fully utilized, which is equivalent to compressing the distance of the channel portion 141 in the horizontal direction (i.e., the X direction). Therefore, the space occupied by the thin-film transistor 100 in the horizontal direction can be reduced. Thus, when fabricating a thin-film transistor with the same actual length of channel portion 141, the overall size of the thin-film transistor of this application is smaller than the overall size of the thin-film transistor in the prior art where the channel portion 141 is a planar structure, which is more conducive to the fabrication of high-resolution display panels.

[0046] For details, please refer to Figures 2-4 When fabricating a channel portion 141 with an actual length of L1, using the thin-film transistor structure of this application, the horizontal length of the channel portion 141 in the first direction X is L2, where L2 < L1. Here, L1 refers to the length of the concave-convex line between the two ends of the channel portion 141 in the first direction X, and L2 refers to the horizontal distance between the two ends of the channel portion 141 in the first direction X. In other words, when fabricating a thin-film transistor with a channel portion 141 of the same actual length L1 as in the prior art (the actual length L1 of the channel portion 141 in the prior art is equal to the horizontal length of the channel portion 141 in the first direction X), the horizontal length L2 of the channel portion 141 in this application is smaller. Therefore, the space occupied by the thin-film transistor in the horizontal direction can be reduced, resulting in a smaller overall size of the thin-film transistor, which is beneficial for the fabrication of high-resolution display panels.

[0047] In this application, the gate 160 covers the channel portion 141, and the gate 160 has a fourth concave-convex structure 1601 similar to the channel portion 141. Therefore, the actual length of the gate 160 in the first direction X is less than the horizontal length of the gate 160 in the first direction X. Since the gate 160 has a concave-convex shape, it makes full use of the space of the thin-film transistor 100 in the vertical direction, which is equivalent to compressing the distance of the gate 160 in the horizontal direction (i.e., the X direction). Therefore, the space occupied by the thin-film transistor 100 in the horizontal direction can be reduced. Thus, when fabricating a thin-film transistor with the same actual length of gate 160, the overall size of the thin-film transistor of this application is smaller than the overall size of the thin-film transistor with a planar gate 160 in the prior art, which is more conducive to the fabrication of high-resolution display panels.

[0048] In some embodiments, please refer to Figures 2-4 The channel portion 141 includes a plurality of protruding portions 1412, and a recessed portion 1413 is provided between adjacent protruding portions 1412. The protruding portions 1412 and the recessed portions 1413 together constitute a second convex-concave structure 1411. The inclination angle α of the sidewall 1414 of the protruding portion 1412 is in the range of 20° to 80°, that is, 20°≤α≤80°, wherein the size of the angle α is related to the inclination angle of the side surface 1211 of the first light-shielding portion 121.

[0049] In some embodiments, please refer to Figure 3 The channel portion 141 includes a plurality of protrusions 1412, each of which has a plurality of sidewalls 1414. That is, the channel portion 141 includes a plurality of sidewalls 1414, the plurality of sidewalls 1414 including a first sidewall 1414a located at the edge of the channel portion 141 and a second sidewall 1414b located in the middle region of the channel portion 141. The tilt angle α2 of the second sidewall 1414b is greater than or equal to the tilt angle α1 of the first sidewall 1414a. Since the size of the thin film transistor is usually small, the recess 1413 in the middle region of the channel portion 141 is limited by the device size and cannot reserve much space. Therefore, the tilt angle of the second sidewall 1414b located in the middle region of the channel portion 141 will be larger, while the first sidewall 1414a located at the edge of the channel portion 141 is not limited by space on the side away from the middle region, and the tilt angle of the first sidewall 1414a can be relatively smaller.

[0050] In some embodiments, please refer to Figure 5The light-shielding layer 120 further includes a second light-shielding portion 122, which is located at least between adjacent first light-shielding portions 121 and connected to them. The thickness of the second light-shielding portion 122 is less than the thickness of the first light-shielding portion 121. The side of the light-shielding layer 120 away from the substrate 110 has an uneven shape. In this embodiment, the orthographic projection of the second light-shielding portion 122 on the substrate 110 covers the gap between the orthographic projections of the first light-shielding portions 121 on the substrate 110. That is, the surface of the light-shielding layer 120 near the substrate 110 is a solid structure, and the surface of the light-shielding layer 120 away from the substrate 110 is uneven. Therefore, the light-shielding function of the light-shielding layer 120 can be guaranteed, and the channel portion 141 above the light-shielding layer 120 can form an uneven structure.

[0051] In some embodiments, the thickness of the first light-shielding portion 121 ranges from [specific value]. The thickness range of the second light-shielding part 122 is Furthermore, the thickness of the second light-shielding part 122 is 5% to 85% of the thickness of the first light-shielding part 121. The thicknesses of the first light-shielding part 121 and the second light-shielding part 122 satisfy the aforementioned thickness difference, so that the process can realize the formation of the first concave-convex structure 1301 and the second concave-convex structure 1411.

[0052] In some embodiments, please refer to Figure 5 A second light-shielding portion 122 is provided at the outer edge of the light-shielding layer 120, so that the orthogonal projection of the first light-shielding portion 121 and the second light-shielding portion 122 on the substrate 110 completely covers the orthogonal projection of the channel portion 141 on the substrate 110, so that the light-shielding layer 120 protects the entire channel portion 141.

[0053] In this application, the first light-shielding part 121 can be strip-shaped or column-shaped, or it can be straight, broken, or curved, etc., without any specific limitation.

[0054] In one embodiment, please refer to Figure 2 and Figure 4 The light-shielding layer 120 includes a plurality of spaced-apart first light-shielding portions 121, wherein the first light-shielding portions 121 are strip-shaped and extend along the second direction Y, and the plurality of first light-shielding portions 121 are spaced-apart along the first direction X, the first direction X being the channel length direction, and the second direction Y being perpendicular to the first direction X.

[0055] For details, please refer to Figure 3 and Figure 6This is one embodiment of a thin-film transistor structure provided in this application. The thin-film transistor includes a substrate 110, a light-shielding layer 120, a buffer layer 130, an active layer 140, a gate insulating layer 150, a gate 160, an interlayer insulating layer 170, and a source 181 and a drain 182. The light-shielding layer 120 is located on one side of the substrate 110 and includes a plurality of spaced-apart first light-shielding portions 121. The first light-shielding portions 121 extend along a second direction Y in a strip-like structure. The plurality of first light-shielding portions 121 are spaced along a first direction X, and the adjacent first light-shielding portions 121 are hollowed out, i.e., the substrate 110 is exposed. The buffer layer 130 is located on the side of the light-shielding layer 120 away from the substrate 110. The buffer layer 130 covers the first light-shielding portions 121 and the substrate 110. The buffer layer 130 located above the light-shielding layer 120 has a first uneven structure 1301. The active layer 140 is located on the side of the buffer layer 130 away from the light-shielding layer 120. The active layer 140 includes a channel portion 141 and source connection portions 1421 and drain connection portions 1422 located at opposite ends of the channel portion 141 in a first direction X. The channel portion 141 is disposed above the first uneven structure 1301 and has a second uneven structure 1411. The gate insulating layer 150 is located on the side of the active layer 140 away from the buffer layer 130. The orthographic projection of the gate insulating layer 150 on the substrate 110 covers the orthographic projection of the channel portion 141 on the substrate 110. The gate insulating layer 150 has a third uneven structure 1501. The gate 160 is located on the side of the gate insulating layer 150 away from the active layer 140. The orthographic projection of the gate 160 on the substrate 110 covers the orthographic projection of the channel portion 141 on the substrate 110. The gate 160 has a fourth uneven structure 1601. An interlayer insulating layer 170 is located on the side of the gate 160 away from the gate insulating layer 150, and covers the gate 160, the active layer 140, and the buffer layer 130. A first via 171 and a second via 172 are provided on the interlayer insulating layer 170. The first via 171 and the second via 172 are located on opposite sides of the channel portion 141 in the first direction X and expose the active layer 140. The source 181 and the drain 182 are located on the side of the interlayer insulating layer 170 away from the gate 160. The source 181 is connected to the source connection portion 1421 through the first via 171, and the drain 182 is connected to the drain connection portion 1422 through the second via 172.

[0056] For further details, please refer to Figure 6 The light-shielding layer 120 also includes a connecting portion 123, wherein a plurality of first light-shielding portions 121 extend to and are connected to the connecting portion 123. The orthographic projection of the connecting portion 123 on the substrate 110 does not overlap with the orthographic projection of the channel portion 141 on the substrate 110, so as to ensure the uniformity of the channel portion 141. The connecting portion 123 is used to connect a plurality of independent first light-shielding portions 121 so that the plurality of first light-shielding portions 121 can share a signal.

[0057] In this embodiment, the first light-shielding portion 121 has a strip-shaped structure, and its extending direction is perpendicular to the length direction (first direction X) of the channel portion 141. In the region corresponding to the channel portion 141, such as... Figure 7 As shown, the first light-shielding portion 121 has a top surface 1212 and a bottom surface 1213 opposite to each other, and two opposite side surfaces 1211 located between the top surface 1212 and the bottom surface 1213, namely the first side surface 12111 and the second side surface 12112. Since a portion of the channel portion 141 is formed above the first side surface 12111 and the second side surface 12112 of the first light-shielding portion 121, the space of the thin film transistor in the vertical direction is fully utilized. Therefore, the space occupied by the thin film transistor in the horizontal direction can be reduced, which is beneficial to the fabrication of high-resolution display panels.

[0058] In another embodiment, please refer to Figure 8 The light-shielding layer 120 includes a plurality of spaced-apart first light-shielding portions 121, wherein the first light-shielding portions 121 are strip-shaped and extend along a first direction X, and the plurality of first light-shielding portions 121 are arranged at intervals along a second direction Y. The thin-film transistor structure of this embodiment is the same as that described above. Figure 6 The thin-film transistor structure is similar to that of the corresponding embodiment, the only difference being the extension direction and arrangement direction of the first light-shielding portion 121. Figure 6 Although the embodiments differ, their principles and beneficial effects are the same, and will not be repeated here.

[0059] In the above embodiments, although a hollow structure is formed between the first light-shielding portions 121 of the light-shielding layer 120, it does not affect the light-shielding effect of the light-shielding layer 120, or the effect is negligible. The light-shielding layer 120 is mainly used to block the influence of backlight on the channel portion 141. For OLED display panels, the light-emitting devices are located on the side of the active layer 140 away from the light-shielding layer 120, and the hollow structure of the light-shielding layer 120 does not affect the light-shielding effect of the light-shielding layer 120. For liquid crystal display panels, although the backlight is located on the side of the light-shielding layer 120 away from the active layer 140, the effect on the light-shielding layer 120 is relatively small and can be ignored because the gap between adjacent first light-shielding portions 121 is small.

[0060] In one embodiment, please refer to Figure 5 and Figure 9 The light-shielding layer 120 includes a plurality of first light-shielding portions 121 spaced apart and second light-shielding portions 122 located between adjacent first light-shielding portions 121, wherein the first light-shielding portions 121 are strip-shaped and extend along the second direction Y, and the plurality of first light-shielding portions 121 are arranged at intervals along the first direction X.

[0061] The thin-film transistor structure in this embodiment is the same as described above. Figure 6 The thin-film transistor structure is similar to that of the corresponding embodiment, the only difference being the structure of the light-shielding layer 120. Figure 6 Different implementation methods Figure 6 In the corresponding embodiment, a hollow structure is formed between adjacent first light-shielding portions 121, while in this embodiment, a second light-shielding portion 122 is also included between adjacent first light-shielding portions 121. In this embodiment, the surface of the light-shielding layer 120 near the substrate 110 is a solid structure, which does not affect the function of the light-shielding layer 120. The surface of the light-shielding layer 120 away from the substrate 110 is uneven, which allows the channel portion 141 above the light-shielding layer 120 to form an uneven structure. Furthermore, adjacent first light-shielding portions 121 are connected through the second light-shielding portion 122, enabling signal communication between multiple first light-shielding portions 121. Therefore, in this embodiment, it is no longer necessary to set up a second light-shielding portion 122. Figure 6 The corresponding embodiment has a connecting part 123. However, the principle and beneficial effects of this embodiment are different. Figure 6 The corresponding implementation methods are the same, and will not be described again here.

[0062] In another embodiment, please refer to Figure 10 The light-shielding layer 120 includes a plurality of first light-shielding portions 121 spaced apart and second light-shielding portions 122 located between adjacent first light-shielding portions 121, wherein the first light-shielding portions 121 are strip-shaped and extend along the first direction X, and the plurality of first light-shielding portions 121 are arranged at intervals along the second direction Y.

[0063] The thin-film transistor structure in this embodiment is the same as described above. Figure 9 The thin-film transistor structure is similar to that of the corresponding embodiment, the only difference being the extension direction and arrangement direction of the first light-shielding portion 121. Figure 9 Although the embodiments differ, their principles and beneficial effects are the same, and will not be repeated here.

[0064] In one embodiment, please refer to Figure 5 and Figure 11 The light-shielding layer 120 includes a plurality of first light-shielding portions 121 spaced apart and second light-shielding portions 122 located between adjacent first light-shielding portions 121, wherein the first light-shielding portions 121 are columnar, and the plurality of first light-shielding portions 121 are arranged in an array along the first direction X and the second direction Y.

[0065] The thin-film transistor structure in this embodiment is the same as described above. Figure 9 The thin-film transistor structure is similar to that of the corresponding embodiment, the only difference being the shape and arrangement of the first light-shielding portion 121. Figure 9 The embodiments differ, and other structures are the same. Figure 9 The corresponding implementation methods are all the same, and will not be described again here.

[0066] In this embodiment, the light-shielding layer 120 is composed of a plurality of first light-shielding portions 121 arranged in an array, wherein the first light-shielding portions 121 have an independent columnar structure, and second light-shielding portions 122 are arranged around the first light-shielding portions 121. In the region corresponding to the channel portion 141, such as Figure 12 As shown, the first light-shielding portion 121 has opposing top and bottom surfaces, and four side surfaces located between the top and bottom surfaces, namely, a first side surface 12111, a second side surface 12112, a third side surface 12113, and a fourth side surface 12114. A partial channel portion 141 is formed above the first side surface 12111, the second side surface 12112, the third side surface 12113, and the fourth side surface 12114 of the first light-shielding portion 121, compared to... Figure 9 and Figure 10 In the corresponding embodiment, the first light-shielding portion 121 of this embodiment has more side surfaces 1211, so that more channel portions 141 can be formed above the side surfaces 1211 of the first light-shielding portion 121. Therefore, the horizontal length of the channel portion 141 is reduced in both the first direction X and the second direction Y, that is, the overall planar projection area of ​​the channel portion 141 is reduced, thereby reducing the space occupied by the thin film transistor in the first direction X and the second direction Y, and further making the overall size of the thin film transistor smaller.

[0067] Furthermore, the second light-shielding part 122 is located between adjacent first light-shielding parts 121 to connect multiple first light-shielding parts 121. On the one hand, it can block the gap between the first light-shielding parts 121 without affecting the light-shielding function of the light-shielding layer 120. On the other hand, the second light-shielding part 122 connects to the first light-shielding parts 121, which can realize signal transmission between multiple first light-shielding parts 121 without the need to set up an additional connecting part 123 to connect each first light-shielding part 121.

[0068] In some embodiments, please refer to Figure 7 The first light-shielding portion 121 has a top surface 1212 and a bottom surface 1213 facing each other, and a side surface 1211 located between the top surface 1212 and the bottom surface 1213. The tilt angle β of the side surface 1211 ranges from 20° to 80°, that is, the angle β between the side surface 1211 and the bottom surface 1213 ranges from 20° ≤ β ≤ 80°. In this application, the side surface 1211 of the first light-shielding portion 121 is inclined. For example, the cross-section of the first light-shielding portion 121 can be trapezoidal, and further, it can be an isosceles trapezoid. On the one hand, the inclined arrangement of the side surface 1211 of the first light-shielding portion 121 can increase the length of the channel portion 141 formed above the side surface 1211. And when the angle β is smaller, the length b of the side surface 1211 of the first light-shielding portion 121 is longer, the channel portion 141 formed on the side surface 1211 of the first light-shielding portion 121 is longer, and the space utilization of the thin-film transistor is greater. On the other hand, the side 1211 of the first light-shielding part 121 is inclined, which can reduce the impact of the step difference of the light-shielding layer 120 on the subsequently deposited film.

[0069] In some other embodiments, the cross-section of the first light-shielding part 121 may also be a semi-circular arc, a triangle, etc., but is not limited thereto.

[0070] In some embodiments, please refer to Figure 6 The spacing W1 between adjacent first light-shielding portions 121 is in the range of 2µm ≤ W1 ≤ 5µm. Considering the light-shielding effect of the light-shielding layer 120, the spacing between adjacent first light-shielding portions 121 should not be too large, preferably less than 5µm. However, due to the limitations of the etching process, the spacing between adjacent first light-shielding portions 121 is usually greater than 2µm. Specifically, the spacing W1 between adjacent first light-shielding portions 121 and the width W2 of the first light-shielding portion 121 are also related to the design size of the thin-film transistor. W1 and W2 can be designed according to the specific size of the thin-film transistor.

[0071] This application also provides a method for fabricating a thin-film transistor 100, comprising:

[0072] Provide a substrate 110;

[0073] A patterned light-shielding layer 120 is formed on the substrate 110. The light-shielding layer 120 includes a plurality of spaced first light-shielding portions 121.

[0074] A buffer layer 130 is formed on the side of the light-shielding layer 120 away from the substrate 110, and the buffer layer 130 located above the light-shielding layer 120 has a first uneven structure 1301.

[0075] An active layer 140 is formed on the side of the buffer layer 130 away from the light-shielding layer 120. The active layer 140 includes a channel portion 141 and a conductor portion 142 located at the end of the channel portion 141. The channel portion 141 is formed above the first uneven structure 1301 and has a second uneven structure 1411.

[0076] A gate 160 is formed on the side of the active layer 140 away from the buffer layer 130;

[0077] A source 181 and a drain 182 are formed on the side of the gate 160 away from the active layer 140, and the source 181 and the drain 182 are respectively connected to the conductor portion 142 of the active layer 140.

[0078] Furthermore, before forming the gate 160, the method further includes forming a gate insulating layer 150 on the side of the active layer 140 away from the buffer layer 130.

[0079] Before forming the source 181 and drain 182, the method further includes: forming an interlayer insulating layer 170 on the side of the gate 160 away from the active layer 140;

[0080] After forming the source 181 and drain 182, the process also includes forming a passivation layer on the source 181 and drain 182.

[0081] For details, please refer to Figure 3 and Figure 6 ,by Figure 3 and Figure 6 Taking the thin-film transistor structure as an example, the fabrication steps of a thin-film transistor include:

[0082] S1. Provide a substrate 110 and clean the substrate 110.

[0083] The substrate 110 may be, but is not limited to, a glass substrate or a flexible substrate.

[0084] S2. A light-shielding layer material is deposited and patterned on one side surface of the substrate 110 to form a light-shielding layer 120. The light-shielding layer 120 includes a plurality of spaced first light-shielding portions 121, with gaps between adjacent first light-shielding portions 121 to expose the substrate 110. The plurality of first light-shielding portions 121 are arranged at intervals along a first direction X, and each first light-shielding portion 121 extends along a second direction Y. The light-shielding layer 120 also includes a connecting portion 123, and the plurality of first light-shielding portions 121 extend to the connecting portion 123 and are connected to the connecting portion 123.

[0085] The light-shielding layer 120 may include one or more film layers, without limitation. The material of the light-shielding layer 120 may be a metal, such as Cu (top layer) / Mo (bottom layer), Cu (top layer) / MoTi (bottom layer), Mo, or MoAl. The thickness of the light-shielding layer 120 ranges from [specific thickness range missing].

[0086] S3. A buffer layer 130 is formed on the side of the light-shielding layer 120 away from the substrate 110. The buffer layer 130 covers the first light-shielding part 121 and the substrate 110. The buffer layer 130 located above the light-shielding layer 120 has a first uneven structure 1301.

[0087] The buffer layer 130 can be made of inorganic materials, such as one or more of SiNx, SiOx, and SiONx. The thickness of the buffer layer 130 ranges from [specific thickness range missing].

[0088] S4. An active layer material is deposited and patterned on the side of the buffer layer 130 away from the light-shielding layer 120 to form an active layer 140. The active layer 140 includes a channel portion 141 and a source connection portion 1421 and a drain connection portion 1422 located on opposite sides of the channel portion 141 in the first direction X. The channel portion 141 is formed above the first concave-convex structure 1301 and has a second concave-convex structure 1411. The source connection portion 1421 and the drain connection portion 1422 are formed by conductiveization or laser crystallization.

[0089] The active layer 140 can be made of oxide semiconductor materials, such as IGZO, IZTO, IGZTO, etc., or amorphous silicon (A-Si). When the active layer 140 is made of oxide semiconductor material, its source connection portion 1421 and drain connection portion 1422 are formed by conductive bonding; when the active layer 140 is made of A-Si material, its source connection portion 1421 and drain connection portion 1422 are formed of p-Si material by excimer laser annealing. The thickness range of the active layer 140 is...

[0090] S5. A gate insulating layer material is deposited and patterned on the side of the active layer 140 away from the light-shielding layer 120 to form a gate insulating layer 150. The gate insulating layer 150 covers the channel portion 141 and has a third concave-convex structure 1501.

[0091] The gate insulating layer 150 may include one or more film layers. The material of the gate insulating layer 150 may be an inorganic material, such as SiOx or SiNx. The thickness of the gate insulating layer 150 ranges from [specific thickness range missing].

[0092] S6. A gate material is deposited and patterned on the side of the gate insulating layer 150 away from the active layer 140 to form a gate 160. The gate 160 covers the gate insulating layer 150 and has a fourth concave-convex structure 1601.

[0093] The gate 160 can be made of a metal, such as Mo, Al, Cu, Ti, etc., or an alloy. The thickness of the gate 160 ranges from [specific thickness range missing].

[0094] In some embodiments, steps S4 to S6 can also involve first forming a gate insulating layer material and a gate material sequentially on the side of the active layer 140 away from the buffer layer 130, and then using a photolithography process to first etch the gate 160 pattern, and then using the gate 160 pattern as self-alignment to etch the gate insulating layer material again to form the gate insulating layer 150 pattern. This method can save processing steps. The active layer 140 is then subjected to a conductor treatment to form the source connection portion 1421 and the drain connection portion 1422.

[0095] S7. An interlayer insulating layer 170 is formed on the side of the gate 160 away from the gate insulating layer 150. The interlayer insulating layer 170 covers the gate 160, the active layer 140 and the buffer layer 130. A first via 171 and a second via 172 are formed on the interlayer insulating layer 170. The first via 171 exposes the source connection portion 1421 and the second via 172 exposes the drain connection portion 1422.

[0096] The interlayer insulating layer 170 may comprise one or more film layers. The material of the interlayer insulating layer 170 may be an inorganic material, such as SiOx or SiNx. The thickness of the interlayer insulating layer 170 ranges from [specific thickness range missing].

[0097] S7. Deposit and pattern source and drain metal materials on the interlayer insulating layer 170 to form source 181 and drain 182. Source 181 is connected to source connection portion 1421 through first via 171, and drain 182 is connected to drain connection portion 1422 through second via 172.

[0098] The source electrode 181 and drain electrode 182 are made of metals, such as Mo, Al, Cu, Ti, etc., or alloys. The thickness range of the source electrode 181 and drain electrode 182 is...

[0099] Furthermore, step S8 may be included after step S7:

[0100] S8. A passivation layer is formed on the side of the source 181 and drain 182 away from the interlayer insulating layer 170, and the passivation layer covers the source 181, drain 182 and interlayer insulating layer 170.

[0101] The passivation layer may comprise one or more film layers. The material of the passivation layer may be an inorganic material, such as SiOx or SiNx. The thickness of the passivation layer ranges from [specific thickness range missing].

[0102] It should be noted that in step S2 of this embodiment, the entire surface of the light-shielding layer material can be deposited first, and then the patterns of the first light-shielding portion 121 and the connecting portion 123 can be formed in one step by an etching process to form the light-shielding layer 120. In other embodiments, when the light-shielding layer 120 includes the first light-shielding portion 121 and the second light-shielding portion 122, the entire surface of the light-shielding layer material can be deposited first, and then the patterns of the first light-shielding portion 121 and the second light-shielding portion 122 can be formed simultaneously by a half-tone process to form the light-shielding layer 120.

[0103] The thin-film transistor fabrication methods in other embodiments of this application can be referred to the above embodiments, and will not be repeated here.

[0104] This application also provides a display panel including the thin-film transistor 100 as described above.

[0105] In some embodiments, the display panel may be an organic light-emitting diode (OLED) display panel. When it is an OLED display panel, the display panel includes a thin-film transistor as described above, a first electrode on the thin-film transistor, an organic light-emitting layer on the first electrode, a second electrode on the organic light-emitting layer, and a counter substrate on the second electrode, wherein one of the first electrode and the second electrode is an anode and the other is a cathode.

[0106] In other embodiments, the display panel may also be a liquid crystal display panel. When it is a liquid crystal display panel, the display panel includes the thin film transistors as described above, a counter substrate disposed opposite to the thin film transistors, a liquid crystal layer located between the thin film transistors and the counter substrate, and a backlight module on the side of the thin film transistors away from the liquid crystal layer.

[0107] In summary, this application provides a thin-film transistor and a display panel. The light-shielding layer of the thin-film transistor of this application is composed of a plurality of spaced-apart first light-shielding portions. Since the plurality of first light-shielding portions are spaced apart, there is a gap between adjacent first light-shielding portions. A buffer layer located above the light-shielding layer is formed between the surface of the first light-shielding portions and the gap, so that the buffer layer formed above the light-shielding layer has a first concave-convex structure. The channel portion is formed on the first concave-convex structure. Therefore, the channel portion has a second concave-convex structure corresponding to the first concave-convex structure. Since the channel portion is concave-convex, the space of the thin-film transistor in the vertical direction is fully utilized, which is equivalent to compressing the distance of the channel portion in the horizontal direction. Therefore, the space occupied by the thin-film transistor in the horizontal direction can be reduced. Therefore, when fabricating a thin-film transistor with a channel portion of the same actual length, the overall size of the thin-film transistor of this application is smaller than the overall size of the thin-film transistor with a planar channel portion in the prior art, which is more conducive to the fabrication of high-resolution display panels.

[0108] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0109] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0110] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0111] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A thin-film transistor, characterized in that, include: Substrate; A light-shielding layer is disposed on one side of the substrate and includes a plurality of spaced-apart first light-shielding portions; A buffer layer is disposed on the side of the light-shielding layer away from the substrate; An active layer is disposed on the side of the buffer layer away from the light-shielding layer. The active layer includes a channel portion and a conductor portion located at the end of the channel portion. The channel portion includes a plurality of sidewalls, the plurality of sidewalls including a first sidewall located at the edge of the channel portion and a second sidewall located in the middle region of the channel portion. The inclination angle of the second sidewall is greater than or equal to the inclination angle of the first sidewall. A gate is disposed on the side of the active layer away from the buffer layer; as well as The source and drain are disposed on the side of the gate away from the active layer and are connected to the conductor portion; The buffer layer located above the light-shielding layer has a first uneven structure, and the channel portion is disposed above the first uneven structure and has a second uneven structure.

2. The thin-film transistor according to claim 1, characterized in that, The light-shielding layer further includes a second light-shielding portion, which is located at least between adjacent first light-shielding portions and connected to the first light-shielding portions. The thickness of the second light-shielding portion is less than the thickness of the first light-shielding portion, and the side of the light-shielding layer away from the substrate has an uneven shape.

3. The thin-film transistor according to claim 2, characterized in that, The thickness of the second light-shielding part is 5% to 85% of the thickness of the first light-shielding part.

4. The thin-film transistor according to claim 1, characterized in that, The light-shielding layer further includes a connecting portion, and multiple first light-shielding portions are connected to the connecting portion. The orthographic projection of the connecting portion on the substrate does not overlap with the orthographic projection of the channel portion on the substrate.

5. The thin-film transistor according to any one of claims 1 to 4, characterized in that, The first light-shielding part is strip-shaped and extends along a first direction, and a plurality of the first light-shielding parts are arranged at intervals along a second direction, the second direction being perpendicular to the first direction.

6. The thin-film transistor according to any one of claims 1 to 4, characterized in that, The first light-shielding part is strip-shaped and extends along the second direction, and a plurality of the first light-shielding parts are arranged at intervals along the first direction, and the second direction is perpendicular to the first direction.

7. The thin-film transistor according to any one of claims 1 to 4, characterized in that, The first light-shielding part is columnar, and a plurality of the first light-shielding parts are arranged in an array along a first direction and a second direction, wherein the second direction is perpendicular to the first direction.

8. The thin-film transistor according to any one of claims 1 to 4, characterized in that, The tilt angle β of the side of the first light-shielding part ranges from 20° to 80°; The spacing W1 between adjacent first light-shielding parts ranges from 2µm to 5µm.

9. A display panel, characterized in that, Includes the thin-film transistor as described in any one of claims 1 to 8.

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