Array substrate and display panel

Abstract

This application discloses an array substrate and a display panel. The first thin-film transistor located in the pixel area of ​​the array substrate includes a first electrode, a first insulating layer, a second electrode, a first active portion, a second insulating layer, and a first gate disposed on the substrate. One end of the first active portion is connected to the second electrode, and the other end of the first active portion extends along the sidewall of a first via in the first insulating layer and is connected to the first electrode corresponding to the first via. This application reduces the channel length of the transistor in the pixel area by making the first electrode and the second electrode connected to the first active portion perpendicularly arranged, that is, the longitudinal distance between the first electrode and the second electrode is the channel length of the first active portion, thereby reducing the size of the transistor and improving the resolution of small-sized display devices.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] As the size of thin-film transistors (TFTs) decreases, their channels also become smaller, leading to decreased stability and increased leakage current. Current ultra-short channel TFTs have channel lengths of approximately 2 to 3 micrometers. The channel size of TFTs is mainly limited by the precision of the exposure machine, preventing further reduction in channel size and thus failing to meet the high-resolution requirements of small-sized display devices. Summary of the Invention

[0003] This application provides an array substrate and a display panel to improve the problem that the channel size of existing thin-film transistors cannot be reduced.

[0004] To address the above issues, the technical solution provided in this application is as follows:

[0005] This application discloses an array substrate, the array substrate including a pixel region and a non-pixel region, wherein a substrate and a first thin-film transistor disposed on the substrate are provided in the pixel region; wherein the first thin-film transistor includes:

[0006] The first electrode is disposed on one side of the substrate;

[0007] A first insulating layer is disposed on one side of the substrate and covers the first electrode, and a first via corresponding to a portion of the first electrode is formed on the first insulating layer;

[0008] The second electrode is disposed on the side of the first insulating layer away from the substrate;

[0009] A first active part, one end of which is connected to the second electrode, and the other end of which extends along the sidewall of the first via and is connected to the first electrode corresponding to the first via.

[0010] A second insulating layer is disposed on the side of the first insulating layer away from the substrate, and the second insulating layer covers the second active portion;

[0011] A first gate is disposed on the side of the second insulating layer away from the substrate.

[0012] Optionally, the non-pixel region is provided with the substrate and a second thin-film transistor disposed on the substrate;

[0013] The second thin-film transistor includes a second active portion, the material of which is different from that of the first active portion.

[0014] Optionally, the material of the second active part is the same as the material of the first electrode, and the second active part and the first electrode are both located on the surface of the same film layer.

[0015] Optionally, the channel length of the first active part is less than the channel length of the second active part.

[0016] Optionally, the second thin-film transistor further includes:

[0017] The first insulating layer covers the second active part;

[0018] The second gate is disposed on the side of the first insulating layer away from the substrate, and the second gate corresponds to the second active portion;

[0019] The material of the second gate is the same as that of the second electrode, and both the second gate and the second electrode are disposed on the surface of the first insulating layer away from the substrate.

[0020] Optionally, the second thin-film transistor further includes:

[0021] The second insulating layer covers the second gate;

[0022] The third electrode is disposed on the side of the second insulating layer away from the substrate, and the third electrode passes through the second via and is connected to the conductor portion of the second active portion;

[0023] The material of the third electrode is the same as that of the first gate, and both the third electrode and the first gate are disposed on the surface of the second insulating layer away from the substrate.

[0024] Optionally, the first thin-film transistor further includes an extension connected to the first electrode, the extension being made of the same material as the first electrode, and the extension being a semiconductor.

[0025] Wherein, the orthogonal projection of the extension segment on the substrate lies within the orthogonal projection of the second electrode on the substrate.

[0026] Optionally, a third via corresponding to the first via is formed on the second insulating layer, and the depth of the third via is less than the thickness of the second insulating layer;

[0027] Wherein, one end of the first gate overlaps the surface of the second insulating layer away from the substrate, and the other end of the first gate extends along the sidewall of the third via to the bottom surface of the third via.

[0028] Optionally, the orthographic projection of the third via on the substrate is located within the orthographic projection of the first via on the substrate, and the orthographic projection area of ​​the third via on the substrate is smaller than the orthographic projection area of ​​the first via on the substrate.

[0029] Optionally, the first thin-film transistor further includes:

[0030] A third insulating layer is disposed on the side of the second insulating layer away from the substrate, and the third insulating line covers the first gate.

[0031] The fourth electrode is disposed on the side of the third insulating layer away from the substrate, and the fourth electrode is electrically connected to the first electrode through the fourth via.

[0032] A fourth insulating layer is disposed on the side of the third insulating layer away from the substrate, and the fourth insulating line covers the fourth electrode;

[0033] The first pixel electrode is disposed on the side of the fourth insulating layer away from the substrate, and the first pixel electrode is electrically connected to the second electrode through the fifth via.

[0034] This application also proposes a display panel that includes the aforementioned array substrate.

[0035] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0038] Figure 1 A top view of the array substrate provided in the embodiments of this application;

[0039] Figure 2 This is a structural diagram of the display panel provided in an embodiment of this application;

[0040] Figure 3 This is a first type of film layer diagram of the array substrate provided in the embodiments of this application;

[0041] Figure 4 This is a second film layer diagram of the array substrate provided in an embodiment of this application;

[0042] Figure 5 This is a process step diagram of the array substrate provided in the embodiments of this application;

[0043] Figures 6A to 6J This is a process flow diagram of the array substrate provided in the embodiments of this application. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0045] Please see Figures 1 to 4 This application proposes a display panel 100, which includes an array substrate 100a and a light-emitting component 100b disposed on one side of the array substrate 100a. The array substrate 100a includes a pixel region AA and a non-pixel region NA. The pixel region AA is provided with a substrate 110 and a first thin-film transistor T1 disposed on the substrate 110. The first thin-film transistor T1 includes a first electrode 141, a first insulating layer IL1, a second electrode 151, a first active portion 144, a second insulating layer IL2, and a first gate 161.

[0046] In this embodiment, the first electrode 141 is disposed on one side of the substrate 110; the first insulating layer IL1 is disposed on one side of the substrate 110 and covers the first electrode 141, and a first via HL1 corresponding to a portion of the first electrode 141 is formed on the first insulating layer IL1; the second electrode 151 is disposed on the side of the first insulating layer IL1 away from the substrate 110; one end of the first active portion 144 is connected to the second electrode 151, and the other end of the first active portion 144 extends along the sidewall of the first via HL1 and is connected to the first electrode 141 corresponding to the first via HL1; the second insulating layer IL2 is disposed on the side of the first insulating layer IL1 away from the substrate 110, and the second insulating layer IL2 covers the second active portion 142; the first gate 161 is disposed on the side of the second insulating layer IL2 away from the substrate 110.

[0047] This application arranges the first electrode 141 and the second electrode 151 connecting the first active part 144 vertically, that is, the longitudinal distance between the first electrode 141 and the second electrode 151 is the channel length of the first active part 144. The channel length of the first active part 144 is changed from horizontal to vertical, which reduces the channel length of the transistor in the pixel area AA, which is equivalent to reducing the size of the transistor. This allows more transistors to be placed in the same area, thereby improving the resolution of small-sized display devices.

[0048] The technical solution of this application will now be described in conjunction with specific embodiments.

[0049] Please see Figure 1 The non-pixel area NA surrounds the pixel area AA. The area of ​​the display panel 100 corresponding to the pixel area AA is used for display functions, and it contains multiple display units that implement these functions. The area of ​​the display panel 100 corresponding to the non-pixel area NA can be the border area of ​​the display panel 100, and it can contain functional components that assist the display units within the pixel area AA in displaying information.

[0050] In this embodiment, multiple pixel driving circuits can be disposed within the pixel region AA, and each pixel driving circuit may include at least one first thin-film transistor T1. A gate driving circuit is disposed within the non-pixel region NA for outputting control signals to the pixel driving circuits within the pixel region AA, and the gate driving circuit may include at least one second thin-film transistor T2.

[0051] In this embodiment, the second thin-film transistor T2 includes a second active portion 142, the material of which is different from that of the first active portion 144; for example, the material of the first active portion 144 in this application can be an oxide semiconductor, and the material of the second active portion 142 can be a polycrystalline silicon semiconductor.

[0052] Please see Figure 2 When the display panel 100 is a liquid crystal display panel, the light-emitting component 100b can be a backlight module, and the side of the display panel 100 away from the light-emitting component 100b is the light-emitting side; when the display panel 100 is an organic light-emitting diode display panel, the light-emitting component 100b can be an organic light-emitting diode; when the display panel 100 is a direct-view display panel, the light-emitting component 100b can be MiniLED, MicroLED, etc.

[0053] Please see Figure 3 The array substrate 100a may include a substrate 110 and an array layer 120 disposed on the substrate 110. The substrate 110 is a single layer, and the substrate 110 is disposed in both the pixel area AA and the non-pixel area NA. The material of the substrate 110 may be a rigid substrate, such as rigid materials such as glass or quartz; or the material of the substrate 110 may be a flexible substrate, such as flexible materials such as polyimide.

[0054] Please see Figure 3The array substrate 100a includes a light-shielding layer (not shown) disposed on one side of the substrate 110. The orthographic projection of the first active portion 144 on the substrate 110 is located within the orthographic projection of the light-shielding layer on the substrate 110, so as to avoid the reduction of the device effect of the transistor due to light entering the channel portion. At the same time, the orthographic projection of the second active portion 142 on the substrate 110 can also be located within the orthographic projection of the light-shielding layer on the substrate 110.

[0055] Please see Figure 3 The light-shielding layer can be a light-shielding metal or other materials with light-shielding properties, such as molybdenum, aluminum, copper, titanium, or alloys of the above materials or a stack of the above materials.

[0056] Please see Figure 3 The array substrate 100a also includes a buffer layer 130 disposed on the side of the light-shielding layer away from the substrate 110. The buffer layer 130 covers the light-shielding layer and is laid on the entire array substrate 100a. The material of the buffer layer 130 may be a compound composed of nitrogen, silicon and oxygen elements. For example, the material of the buffer layer 130 may be a single layer of silicon oxide, a silicon oxide film, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc. For example, the buffer layer 130 of this application may be a stacked structure of silicon oxide, silicon nitride and silicon oxide.

[0057] Please see Figure 3 The array substrate 100a also includes a first active layer 140 disposed on the side of the buffer layer 130 away from the substrate 110. The material of the first active layer 140 can be polycrystalline silicon, which can be formed by amorphous silicon laser annealing crystallization or other crystallization processes.

[0058] In this embodiment, the first active layer 140 may include a first electrode 141 located in the pixel region AA and a second active portion 142 located in the non-pixel region NA. That is, in the process of forming the second active portion 142 of the second thin film transistor T2, the first electrode 141 of the first thin film transistor T1 is formed at the same time. That is, the material of the second active portion 142 is the same as the material of the first electrode 141, and the second active portion 142 and the first electrode 141 are both located on the surface of the same film layer, that is, both are located on the surface of the buffer layer 130.

[0059] In this embodiment, the second active portion 142 includes a second channel 142a and conductor portions 142b disposed on both sides of the second channel 142a. The conductor portions 142b and the first electrode 141 are formed of polycrystalline silicon by ion doping or plasma treatment.

[0060] Please see Figure 3The array substrate 100a also includes a first insulating layer IL1 disposed on the side of the buffer layer 130 away from the substrate 110. The first insulating layer IL1 is laid out in its entirety and covers both the second active part 142 and the first electrode 141. At the same time, a first via HL1 is formed on the first insulating layer IL1, which exposes part of the first electrode 141.

[0061] In this embodiment, the material of the first insulating layer IL1 may be a compound composed of nitrogen, silicon and oxygen. For example, the material of the first insulating layer IL1 may be a single layer of silicon oxide, a silicon oxide film, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0062] Please see Figure 3 The array substrate 100a further includes a first metal layer 150 disposed on the side of the first insulating layer IL1 away from the substrate 110. The material of the first metal layer 150 may include metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or a single-layer or multi-layer metal structure composed of at least two of the above metals. For example, the material of the first metal layer 150 may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0063] In this embodiment, the first metal layer 150 includes a second electrode 151 located in the pixel region AA and a second gate 152 located in the non-pixel region NA. That is, when the patterning process of the first metal layer 150 is performed, the second electrode 151 of the first thin film transistor T1 and the second gate 152 of the second thin film transistor T2 are formed simultaneously. The material of the second gate 152 is the same as the material of the second electrode 151, and the second gate 152 and the second electrode 151 are both disposed on the surface of the first insulating layer IL1 away from the substrate 110.

[0064] In this embodiment, the second gate 152 corresponds to the channel of the second active portion 142, that is, the second gate 152 can be used as a mask to perform conductor processing on the second active portion 142.

[0065] In this embodiment, the first electrode 141 can be the drain of the first thin-film transistor T1, and the second electrode 151 can be the source of the first thin-film transistor T1.

[0066] Please see Figure 3 The array substrate 100a also includes a first active portion 144 located in the pixel area AA. One end of the first active portion 144 is connected to the second electrode 151, and the other end of the first active portion 144 extends along the sidewall of the first via HL1 and is connected to the first electrode 141 corresponding to the first via HL1.

[0067] In this embodiment, the first active part 144 can be formed by physical vapor deposition and patterning through photolithography and etching processes; the material of the first active part 144 can be an oxide semiconductor, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other oxides.

[0068] In this embodiment, the first active part 144 can fill the first via HL1 so that the first active part 144 covers the first electrode 141 corresponding to the first via HL1, thereby increasing the contact area between the first active part 144 and the first electrode 141; at the same time, the first active part 144 of this application can also contact the surface of the first insulating layer IL1 on the side of the first via HL1 away from the second electrode 151.

[0069] In this embodiment, since the second active portion 142 of the second thin-film transistor T2 of this application has a conventional channel structure, while the first electrode 141, the first active portion 144, and the second active portion 142 of the first thin-film transistor T1 of this application have a vertical structure, that is, the channel length of the first active portion 144 is changed from horizontal to vertical, reducing the channel length of the first active portion 144, making the channel length of the first active portion 144 smaller than the channel length of the second active portion 142, which is equivalent to reducing the size of the transistor in the pixel area AA, so that more transistors can be set in the same area, thereby improving the resolution of small-sized display devices.

[0070] In this embodiment, the channel length of the first active part 144 can be from 0.3 micrometers to 0.5 micrometers.

[0071] Please see Figure 3 The first thin-film transistor T1 also includes an extension 143 connected to the first electrode 141. The material of the extension 143 is the same as that of the first electrode 141, and the extension 143 is a semiconductor. The orthogonal projection of the extension 143 on the substrate 110 is located within the orthogonal projection of the second electrode 151 on the substrate 110.

[0072] In this embodiment, since the channel length of the first active portion 144 is the distance between the first electrode 141 and the second electrode 151, in order to reduce the channel length of the first active portion 144, this application increases the amount of non-conductive semiconductor material as much as possible when preparing the first electrode 141. That is, the non-conductive semiconductor material can partially overlap with the second electrode 151. After forming the first via HL1, it is necessary to use the second electrode 151 as a mask to conduct the non-conductive semiconductor material so that the non-conductive semiconductor material forms the first electrode 141 and the extension 143 that overlaps with the second electrode 151.

[0073] The extension 143 of this application reduces the distance between the second electrode 151 and the first electrode 141, thereby reducing the channel length of the first active portion 144 and improving the device performance of the first thin film transistor T1.

[0074] Please see Figure 3 The array substrate 100a also includes a second insulating layer IL2 disposed on the side of the first insulating layer IL1 away from the substrate 110. The second insulating layer IL2 is laid in the entire layer and covers the second gate 152 and the first active portion 144.

[0075] In this embodiment, the material of the second insulating layer IL2 may be a compound composed of nitrogen, silicon and oxygen. For example, the material of the second insulating layer IL2 may be a single layer of silicon oxide, a silicon oxide film, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0076] Please see Figure 3 The array substrate 100a further includes a second metal layer 160 disposed on the side of the second insulating layer IL2 away from the substrate 110. The material of the second metal layer 160 may include metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or a single-layer or multi-layer metal structure composed of at least two of the above metals. For example, the material of the second metal layer 160 may be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0077] In this embodiment, the second metal layer 160 includes a third electrode 162 located in the non-pixel region NA and a first gate 161 located in the pixel region AA. That is, when the patterning process of the second metal layer 160 is performed, the third electrode 162 of the second thin film transistor T2 and the first gate 161 of the first thin film transistor T1 are formed simultaneously. The material of the third electrode 162 is the same as the material of the first gate 161, and both the third electrode 162 and the first gate 161 are disposed on the surface of the second insulating layer IL2 away from the substrate 110.

[0078] In this embodiment, the third electrode 162 passes through the second via HL2 and is connected to the conductor portion 142b of the second active portion 142. The second via HL2 penetrates the second insulating layer IL2 and a portion of the first insulating layer IL1.

[0079] Please see Figure 3 In order to reduce the spacing between the first gate 161 and the first active portion 144 and improve the conduction rate of the first active portion 144, this application may provide a third via HL3 corresponding to the first via HL1 on the second insulating layer IL2. The depth of the third via HL3 is less than the thickness of the second insulating layer IL2. One end of the first gate 161 is attached to the surface of the second insulating layer IL2 away from the substrate 110, and the other end of the first gate 161 extends along the sidewall of the third via HL3 to the bottom surface of the third via HL3.

[0080] In this embodiment, the third via HL3 is configured such that the first gate 161 can extend along the sidewall of the third via HL3 and extend to the bottom surface of the third via HL3 near the first active portion 144. The first gate 161 located on the sidewall of the third via HL3 corresponds to the sidewall of the first active portion 144, reducing the distance between the first gate 161 and the first active portion 144, increasing the turn-on voltage applied to the first active portion 144 by the first gate 161, and improving the conduction rate of the first active portion 144.

[0081] Please see Figure 3 The orthographic projection of the third via HL3 onto the substrate 110 can lie within the orthographic projection of the first via HL1 onto the substrate 110, and the area of ​​the orthographic projection of the third via HL3 onto the substrate 110 is smaller than the area of ​​the orthographic projection of the first via HL1 onto the substrate 110. This is equivalent to the area of ​​the third via HL3 being smaller than the area of ​​the first via HL1, allowing the sidewall of the third via HL3 to correspond to the sidewall of the first via HL1. This also means that the first active portion 144 on the sidewall of the first via HL1 can correspond to the first gate 161 on the sidewall of the third via HL3, further increasing the turn-on voltage applied to the first active portion 144 by the first gate 161 and improving the conduction rate of the first active portion 144.

[0082] Please see Figure 3 The array substrate 100a also includes a third insulating layer IL3 disposed on the side of the second insulating layer IL2 away from the substrate 110. The third insulating layer IL3 is laid in the entire layer and covers the first gate 161 and the third electrode 162.

[0083] In this embodiment, the material of the third insulating layer IL3 may be a compound composed of nitrogen, silicon and oxygen. For example, the material of the third insulating layer IL3 may be a single layer of silicon oxide, a silicon oxide film, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0084] Please see Figure 3 The array substrate 100a also includes a third metal layer 170 disposed on the side of the third insulating layer IL3 away from the substrate 110, and the material of the third metal layer 170 may be the same as the material of the second electrode 151.

[0085] In this embodiment, the third metal layer 170 includes a fourth electrode 171 located in the pixel area AA. The fourth electrode 171 can be electrically connected to the first electrode 141 through a fourth via HL4. The fourth via HL4 penetrates the third insulating layer IL3, the second insulating layer IL2 and part of the first insulating layer IL1. The fourth via HL4 can be located on the side of the third via HL3 away from the second electrode 151, that is, the fourth via HL4 and the first via HL1 do not overlap.

[0086] Please see Figure 3 The array substrate 100a also includes a fourth insulating layer IL4 disposed on the side of the third insulating layer IL3 away from the substrate 110. The fourth insulating layer IL4 is laid in the entire layer and covers the fourth electrode 171.

[0087] In this embodiment, the material of the fourth insulating layer IL4 may be a compound composed of nitrogen, silicon and oxygen. For example, the material of the fourth insulating layer IL4 may be a single layer of silicon oxide, a silicon oxide film, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0088] Please see Figure 3 The array substrate 100a also includes a first pixel electrode PE1 disposed on the side of the fourth insulating layer IL4 away from the substrate 110. The first pixel electrode PE1 is located in the pixel area AA, and the first pixel electrode PE1 is electrically connected to the second electrode 151 through the fifth via HL5. The fifth via HL5 passes through the fourth insulating layer IL4, the third insulating layer IL3 and part of the second insulating layer IL2.

[0089] In this embodiment, the material of the first pixel electrode PE1 may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi, etc.

[0090] In this embodiment, the first electrode 141 can be the drain of the first thin-film transistor T1, and the second electrode 151 can be the source of the first thin-film transistor T1.

[0091] In this embodiment, the third metal layer 170 may further include at least one transmission line for transmitting voltage signals, such as a high potential line, a low potential line, a clock signal line, a start signal line, a data signal line, etc. For example, the data line located in the third metal layer 170 is connected to the fourth electrode 171 to guide the data signal in the data line into the first electrode 141. At the same time, the first active part 144 is turned on, and the data signal is transmitted to the second electrode 151 and guided into the first pixel electrode PE1 through the second electrode 151.

[0092] exist Figure 3 Based on this, please refer to Figure 4 The array substrate 100a also includes a planarization layer PLN disposed on the side of the fourth insulating layer IL4 away from the substrate 110. The planarization layer PLN covers the first pixel electrode PE1. The material of the planarization layer PLN includes flexible materials such as polytetrafluoroethylene.

[0093] Please see Figure 4 The array substrate 100a also includes a second pixel electrode PE2 disposed on the side of the planarization layer PLN away from the substrate 110. The second pixel electrode PE2 is electrically connected to the first pixel electrode PE1 through a sixth via HL6 on the planarization layer PLN.

[0094] In this embodiment, the material of the second pixel electrode PE2 may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi, etc.

[0095] Please also see Figure 4 The array substrate 100a also includes a common electrode AE ​​that is in the same layer as the first pixel electrode PE1 and is fabricated in the same process. The common electrode AE ​​and the second pixel electrode PE2 form a driving electric field to drive the liquid crystal in the display panel 100 to deflect.

[0096] It should be noted that, Figure 4 The structures described herein are all only applicable to LCD display panels. Figure 3 The structure can be applied to direct-view display panels such as liquid crystal display panels, organic light-emitting diode display panels, MiniLED or MicroLED.

[0097] Please see Figure 5 This application also proposes a method for fabricating an array substrate, in order to Figure 3 Taking the structure as an example, the fabrication method of the array substrate includes:

[0098] S10. Provide a substrate 110 and form a buffer layer 130 on the substrate 110;

[0099] Please see Figure 6AThe material of the substrate 110 can be a rigid substrate 110, such as glass, quartz and other rigid materials; the material of the substrate 110 can be a flexible substrate 110, such as polyimide and other flexible materials.

[0100] In this embodiment, a light-shielding layer may also be provided between the substrate 110 and the buffer layer 130. The first active portion 144 of the first thin film transistor T1 in the pixel area AA can be located within the orthogonal projection of the light-shielding layer on the substrate 110, so as to avoid the reduction of the device effect of the transistor due to light entering the channel portion.

[0101] In this embodiment, the buffer layer 130 is laid on the entire array substrate 100a and covers the light-shielding layer. For example, the material of the buffer layer 130 may include a single layer of silicon oxide, a silicon oxide film layer, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc. For example, the buffer layer 130 of this application may be a stacked structure of silicon oxide, silicon nitride, and silicon oxide.

[0102] S20. A semiconductor material layer ACT is formed on the surface of the buffer layer 130 away from the substrate 110, and a first semiconductor pattern ACT1 located in the pixel area AA and a second semiconductor pattern ACT2 located in the non-pixel area NA are formed by patterning.

[0103] Please see Figure 6B The semiconductor material layer ACT can be made of polycrystalline silicon, which can be formed by amorphous silicon laser annealing crystallization or other crystallization processes.

[0104] S30. A first insulating layer IL1 and a first metal layer 150 are formed on the side of the semiconductor material layer ACT away from the substrate 110. A first metal pattern 150a located in the pixel area AA and a second metal pattern 150b located in the non-pixel area NA are formed by patterning. The first semiconductor pattern ACT1 is conductiveized using the first metal pattern 150a as a mask so that the first semiconductor pattern ACT1 forms a second active part 142. The second semiconductor pattern ACT2 is conductiveized using the second metal pattern 150b as a mask so that the second semiconductor pattern ACT2 not covered by the second metal pattern 150b forms a first electrode 141. The second semiconductor pattern ACT2 covered by the second metal pattern 150b forms an extension 143.

[0105] Please see Figure 6C The second active portion 142 includes a second channel 142a and conductor portions 142b disposed on both sides of the second channel 142a. The conductor portions 142b and the second electrode 151 are formed of polysilicon by ion doping or plasma treatment. The first metal pattern 150a is a second gate 152 corresponding to the second channel 142a.

[0106] In this embodiment, the material of the first insulating layer IL1 may include a single layer of silicon oxide, a silicon oxide film, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0107] In this embodiment, the material of the first metal layer 150 can be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0108] S40. The second metal pattern 150b and the first insulating layer IL1 are patterned to form the second electrode 151, and a first via HL1 is formed on the first insulating layer IL1. Then, using the second electrode 151 as a mask, the second semiconductor pattern ACT2 not covered by the second electrode 151 is conductiveized to make a portion of the extension 143 conductive and form the first electrode 141. For example... Figure 6D The structure.

[0109] S50, a first active portion 144 is formed on the side of the first insulating layer IL1 away from the substrate 110;

[0110] Please see Figure 6E One end of the first active part 144 is connected to the second electrode 151, and the other end of the first active part 144 extends along the side wall of the first via HL1 and is connected to the first electrode 141 corresponding to the first via HL1.

[0111] In this embodiment, the first active part 144 can be formed by physical vapor deposition and patterning through photolithography and etching processes; the material of the first active part 144 can be an oxide semiconductor, such as IGZO, IGTO, Ln-IZO, ITZO, ITGZO, HIZO, IZO (InZnO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, Cd-Sn-O or other oxides.

[0112] In this embodiment, the first active part 144 can fill the first via HL1 so that the first active part 144 covers the first electrode 141 corresponding to the first via HL1, thereby increasing the contact area between the first active part 144 and the first electrode 141; at the same time, the first active part 144 of this application can also contact the surface of the first insulating layer IL1 on the side of the first via HL1 away from the second electrode 151.

[0113] S60, a second insulating layer IL2 is formed on the side of the first insulating layer IL1 away from the substrate 110, and the second insulating layer IL2 is patterned to form a second via HL2 and a third via HL3;

[0114] Please see Figure 6F The second via HL2 penetrates the second insulating layer IL2 and part of the first insulating layer IL1, exposing part of the conductor portion 142b, and the third via HL3 penetrates part of the second insulating layer IL2.

[0115] S70, a second metal layer 160 is formed on the side of the second insulating layer IL2 away from the substrate 110, and a first gate 161 located in the pixel region AA and a third electrode 162 located in the non-pixel region NA are formed by patterning.

[0116] Please see Figure 6G The material of the second metal layer 160 can be Mo, Mo / Al, Mo / Cu, MoTi / Cu, MoTi / Cu / MoTi, Ti / Al / Ti, Ti / Cu / Ti, Mo / Cu / IZO, IZO / Cu / IZO, Mo / Cu / ITO, etc.

[0117] In this embodiment, the third electrode 162 passes through the second via HL2 and is connected to the conductor portion 142b of the second active portion 142. One end of the first gate 161 is attached to the surface of the second insulating layer IL2 away from the substrate 110, and the other end of the first gate 161 extends along the sidewall of the third via HL3 to the bottom surface of the third via HL3.

[0118] In this embodiment, the material of the second insulating layer IL2 may include a single layer of silicon oxide, a silicon oxide film, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0119] S80, a third insulating layer IL3 and a fourth electrode 171 are formed on the surface of the second insulating layer IL2 away from the substrate 110.

[0120] Please see Figure 6H The fourth electrode 171 can be electrically connected to the first electrode 141 through the fourth via HL4. The fourth via HL4 passes through the third insulating layer IL3, the second insulating layer IL2 and part of the first insulating layer IL1. The fourth via HL4 can be located on the side of the third via HL3 away from the second electrode 151, that is, the fourth via HL4 and the first via HL1 do not overlap.

[0121] In this embodiment, the material of the third insulating layer IL3 may include a single layer of silicon oxide, a silicon oxide film, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.; the material of the third metal layer 170 may be the same as the material of the second metal layer 160.

[0122] S90, A fourth insulating layer IL4 and a first pixel electrode PE1 layer are formed on the surface of the third insulating layer IL3 away from the substrate 110;

[0123] Please see Figure 6I The first pixel electrode PE1 layer includes a first pixel electrode PE1 and a common electrode. The first pixel electrode PE1 passes through the fifth via HL5 and is electrically connected to the second electrode 151. The fifth via HL5 passes through the fourth insulating layer IL4, the third insulating layer IL3 and part of the second insulating layer IL2.

[0124] In this embodiment, the material of the fourth insulating layer IL4 may include a single layer of silicon oxide, a silicon oxide film, or a stacked structure of silicon oxide, silicon nitride, aluminum oxide, etc.

[0125] In this embodiment, the material of the first pixel electrode PE1 layer may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi, etc.

[0126] Based on step S90, the method for fabricating the array substrate includes:

[0127] S100, a planarization layer PLN and a second pixel electrode PE2 are formed on the surface of the fourth insulating layer IL4 away from the substrate 110.

[0128] Please see Figure 6J A sixth via HL6 is provided on the planarization layer PLN, and the first pixel electrode PE1 passes through the sixth via HL6 and is electrically connected to the first pixel electrode PE1.

[0129] In this embodiment, the array substrate 100a also includes a common electrode AE ​​that is in the same layer as the first pixel electrode PE1 and is fabricated in the same process. The common electrode AE ​​and the second pixel electrode PE2 form a driving electric field to drive the liquid crystal in the display panel 100 to deflect.

[0130] In this embodiment, the material of the planarization layer PLN includes flexible materials such as polytetrafluoroethylene.

[0131] In this embodiment, the material of the second pixel electrode PE2 may include ITO, IZO, ITO / Ag / ITO, IZO / Ag / IZO, Mo / Cu, MoTi / Cu / MoTi, etc.

[0132] It should be noted that, Figure 6J The structures described herein are all only applicable to LCD display panels. Figure 6I The structure can be applied to direct-view display panels such as liquid crystal display panels, organic light-emitting diode display panels, MiniLED or MicroLED.

[0133] The second active portion 142 of the second thin-film transistor T2 in this application has a conventional channel structure, while the first electrode 141, the first active portion 144, and the second active portion 142 of the first thin-film transistor T1 in this application have a vertical structure. That is, the channel length of the first active portion 144 is changed from horizontal to vertical, which reduces the channel length of the first active portion 144. This makes the channel length of the first active portion 144 smaller than the channel length of the second active portion 142, which is equivalent to reducing the size of the transistor in the pixel area AA. This allows more transistors to be placed in the same area, thereby improving the resolution of small-sized display devices.

[0134] In this embodiment, the channel length of the first active part 144 can be from 0.3 micrometers to 0.5 micrometers.

[0135] Meanwhile, in this application, when fabricating the second active portion of the second thin-film transistor, the first electrode of the first thin-film transistor is also fabricated simultaneously; when fabricating the second gate of the second thin-film transistor, the second electrode of the first thin-film transistor is also fabricated simultaneously; when fabricating the third electrode of the second thin-film transistor, the first gate of the first thin-film transistor is also fabricated simultaneously. That is, this application can utilize three layers of insulation to simultaneously fabricate transistors in the pixel area and non-pixel area, reducing the number of photomasks, simplifying the fabrication process of the array substrate, and reducing the fabrication cost of the display panel.

[0136] This application also proposes a mobile terminal, which includes a terminal body and the aforementioned display panel, the terminal body and the display panel being integrated into one unit. The terminal body may include components such as a circuit board bonded to the display panel, and a cover plate disposed on the display panel. The mobile terminal may include electronic devices such as mobile phones, televisions, and laptops.

[0137] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0138] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0139] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0140] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An array substrate, characterized in that, The array substrate includes a pixel region and a non-pixel region. The array substrate includes a first thin-film transistor located within the pixel region and a second thin-film transistor located within the non-pixel region. The array substrate includes: Substrate; A first active layer is disposed on one side of the substrate and includes a first electrode of the first thin-film transistor and a second active portion of the second thin-film transistor. A first insulating layer is disposed on one side of the substrate and covers the first active layer, and a first via corresponding to a portion of the first electrode is formed on the first insulating layer; A first metal layer is disposed on the side of the first insulating layer away from the substrate, and includes the second electrode of the first thin-film transistor and the second gate of the second thin-film transistor; The second active layer includes a first active portion of the first thin-film transistor. One end of the first active portion is connected to the second electrode, and the other end of the first active portion extends along the sidewall of the first via and is connected to the first electrode corresponding to the first via. The materials of the first active layer and the second active layer are different. A second insulating layer is disposed on the side of the first insulating layer away from the substrate, and the second insulating layer covers the second active portion; A first gate is disposed on the side of the second insulating layer away from the substrate; The first thin-film transistor further includes an extension segment connected to the first electrode. The material of the extension segment is the same as that of the first electrode, and the extension segment is a non-conductive semiconductor. The first electrode is a conductive semiconductor, and the orthogonal projection of the extension segment on the substrate is located within the orthogonal projection of the second electrode on the substrate.

2. The array substrate according to claim 1, characterized in that, The material of the second active part is different from the material of the first active part.

3. The array substrate according to claim 2, characterized in that, The channel length of the first active part is less than the channel length of the second active part.

4. The array substrate according to claim 2, characterized in that, The second thin-film transistor further includes: The second insulating layer covers the second gate; The third electrode is disposed on the side of the second insulating layer away from the substrate, and the third electrode passes through the second via and is connected to the conductor portion of the second active portion; The material of the third electrode is the same as that of the first gate, and both the third electrode and the first gate are disposed on the surface of the second insulating layer away from the substrate.

5. The array substrate according to any one of claims 1 to 4, characterized in that, A third via corresponding to the first via is formed on the second insulating layer, and the depth of the third via is less than the thickness of the second insulating layer; Wherein, one end of the first gate overlaps the surface of the second insulating layer away from the substrate, and the other end of the first gate extends along the sidewall of the third via to the bottom surface of the third via.

6. The array substrate according to claim 5, characterized in that, The orthographic projection of the third via on the substrate is located within the orthographic projection of the first via on the substrate, and the orthographic projection area of ​​the third via on the substrate is smaller than the orthographic projection area of ​​the first via on the substrate.

7. The array substrate according to any one of claims 1 to 4, characterized in that, The first thin-film transistor further includes: A third insulating layer is disposed on the side of the second insulating layer away from the substrate, and the third insulating layer covers the first gate. The fourth electrode is disposed on the side of the third insulating layer away from the substrate, and the fourth electrode is electrically connected to the first electrode through the fourth via. A fourth insulating layer is disposed on the side of the third insulating layer away from the substrate, and the fourth insulating layer covers the fourth electrode; The first pixel electrode is disposed on the side of the fourth insulating layer away from the substrate, and the first pixel electrode is electrically connected to the second electrode through the fifth via.

8. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 7.

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