Logic circuit and operation method in digital correlated double sampling

Abstract

The logic circuit (34) includes a first logic circuit, a second logic circuit, and a selector. The first logic circuit is used for outputting a first operation result. And the second logic circuit is used for outputting a second operation result. The first operation result is a result obtained by performing XOR operation on the input bit. The second operation result is a result obtained by performing XOR operation on the input bit including the first operation result. In the code conversion mode, the selector outputs the second operation result, the input bits of the first logic circuit comprise the bits in the Gray code representation of a second to-be-added number and the bits in the binary code representation, and the input bits of the second logic circuit further comprise the bits in the Gray code representation of the second to-be-added number. In the addition mode, the selector outputs a carry bit when a first to-be-added number and a second to-be-added number are added, the input bit of the first logic circuit comprises the bit of the first to-be-added number and the carry bit lower than the digit of the carry bit, and the input bit of the second logic circuit comprises the bit of the second to-be-added number.

Description

Technical Field

[0001] Embodiments disclosed herein relate to logic circuits and operation methods in digital correlated double sampling (CDS), or more generally, to logic circuits and operation methods in correlated multiple sampling (CMS). Background Art

[0002] Mobile terminals such as smartphones and tablets need to be designed with low power consumption because they need to operate for long periods of time. Low power consumption also helps suppress the generation of heat radiation, which may cause performance degradation issues such as noise and dark current.

[0003] Since most mobile terminals include one or more image sensors, the image sensors (especially the analog-to-digital converter (ADC)) should also operate with low power consumption.

[0004] Figure 1 The image sensor 10 is partially configured as shown. For example, the image sensor 10 may be a CMOS image sensor. In the image sensor 10, sensor elements are arranged in an array, each sensor element converts a certain physical quantity into an electrical signal, and the output signal of the sensor element is used for sensing. The image sensor 10 may be used for any sensor, such as a fingerprint sensor.

[0005] exist Figure 1 In FIG. 1 , a plurality of pixels 11, a row decoding circuit 12, a readout circuit 13, a horizontal scanner 18, a ramp waveform generator (RAMP) 16, and a clock supplier (CLK) 17 are shown. Figure 1 Elements related to the following description are shown. However, in practice, other elements may exist. Each column provides a readout circuit 13, and each readout circuit 13 includes a comparator 14 and a counter and latch circuit 15. A ramp waveform generator 16 and a clock supply 17 are shared in multiple readout circuits 13.

[0006] Each pixel 11 of the plurality of pixels 11 has the same configuration and the same function. The operation will be described taking the pixel 11 located at the nth row and the mth column as a representative example. Figure 1 The pixel 11 shown includes a photodiode (PD) having an anode connected to a low power supply V SS (For example, V SS can be GND); transfer transistor Tr1, connected between the cathode of PD and the floating diffusion layer (FD); reset transistor Tr2, connected between the floating diffusion layer (FD) and the high power supply VDD Although only one PD is shown, multiple PDs and Tr1 may be connected to the floating diffusion layer (FD). The pixel 11 further includes: an amplifying transistor Tr3, forming a source follower, wherein a gate receiving an input voltage is connected to the floating diffusion layer; a selecting transistor Tr4, controlling Tr3 and an output signal line ( Figure 1 Data line D m ) is connected between the output signal line D. m and provides source follower bias current.

[0007] The row decoding circuit 12 controls the selection of the pixel 11 and the operation of the pixel 11. Basically, the pixel 11 is driven (activated or deactivated) by the selection signal SEL n and transmission signal TG n,x To choose. Figure 1 In the example shown, the reset signal RST n , transmission signal TG n,x and the selection signal SEL n The operation of some signals such as , is controlled by the vertical scanner. The level converter converts the levels of these kinds of signals to appropriate levels for the pixel 11. The selection signal SEL n and transmission signal TG n,x It can be called a scan line. Since the scan line is connected to a plurality of pixels 11, a plurality of pixels can be designated at the same time by designating one scan line.

[0008] The readout circuit 13 can read out the data through a plurality of data lines (...D m , D m+1 ……) reads analog data from the pixel 11, converts the analog data into digital data, and then sends the converted data to the horizontal scanner 18. More specifically, the comparator 14 receives the analog voltage signal of the pixel 11 and the ramp waveform signal that gradually decreases at a predetermined ratio, and the comparator 14 compares them. The counter and latch circuit 15 stores the level (digital value) corresponding to the time when the ramp waveform signal and the analog voltage signal cross. The stored level will be provided to the horizontal scanner 18 at the appropriate time. Therefore, the readout circuit 13 can be used as an analog-to-digital converter (ADC). Figure 1 The illustrated comparator 14 comprises a differential amplifier.

[0009] Figure 1 The multiple readout circuits (ADC) 13 shown can operate in parallel. Each readout circuit 13 operates in a time-division multiplexing manner with respect to k pixels. "k" represents the number of pixels connected in parallel to one readout circuit 13. Figure 1In the example of , the following operation is repeated k times: an analog signal is read from a pixel 11, and then a digital signal corresponding to the analog signal is output (i.e., analog-to-digital conversion). The number of pixels (specifically, the number of rows and columns) can be any suitable positive integer. For example, the number of rows and columns can be hundreds or thousands, etc.

[0010] The analog signal read from the pixel 11 may include some noise. For example, it may include error components such as feedthrough due to the switching of the reset transistor Tr2, kTC noise of the diffusion capacitance, etc. In order to properly eliminate such noise effects, it is necessary to perform correlated double sampling (CDS).

[0011] Figure 2 An explanatory diagram describing correlated double sampling (CDS) is shown. Figure 2 , the selection signal SEL in an example of measuring the signal level of the pixel 11 is shown. n , the AZ switch signal AZ_SW of the comparator 14 , the input signal INN of the negative side input port of the comparator 14 , the input signal INP of the positive side input port of the comparator 14 , the output signal OUT of the comparator 14 , and the counter value.

[0012] refer to Figure 1 and Figure 2 The operation is described. First, the two AZ switches AZ_SW are changed from the open state to the closed state, and then the input (INP, INN) of the comparator 14 is reset to a predetermined voltage level (auto-zero). Preferably, the predetermined voltage level is a high voltage level (hereinafter referred to as "high voltage level"). In this case, the floating layer FD as the input of the pixel source follower is precharged to a known level (for example, V DD ). The term "toggling" refers to the OFF-ON-OFF operation, which can also be called "switching".

[0013] After AZ_SW is restored to the disconnected state (OFF), the voltage supplied to the input port INP of the comparator 14 will change from a high voltage level, depending on the change in the level of the ramp waveform relative to the closed AZ_SW, that is, the change in the output level of the ramp waveform generator relative to the voltage level during the "auto-zero" period. Similar to INP, the voltage supplied to INN will also change from a high voltage level, depending on the change in the analog input level in the closed state of AZ_SW, that is, the change in the FD level or the source follower output. During the period when Tr1 and Tr2 are in the OFF state, Tr4 is turned on in the pixel 11, and an analog signal corresponding to the level of the floating diffusion layer (FD) is supplied to the input port INN of the comparator 14. This level of the floating diffusion layer (FD) in this case can be called a reference level.

[0014] Next, the ramp waveform signal provided to the input port INP of the comparator 14 is usually gradually reduced from a high level to a low level over time. The step width of the change is determined by the resolution of the analog-to-digital conversion. The reference voltage level can be determined by measuring the time when the analog voltage signal level and the ramp voltage signal level become the same. At this time, for example, the output of the comparator 14 changes from low to high. As described above, the reference voltage level may include error components such as kTC noise of the diffusion capacitance and feedthrough that may occur when AZ_SW returns to the disconnected state.

[0015] Next, the charge stored in the photodiode (PD) in the pixel 11 is converted into the input voltage of the comparator 14. Specifically, the photoelectrons stored in the photodiode (PD) according to the amount of light are transferred to the floating diffusion layer (FD) by converting (or switching) the transfer transistor Tr1 of the pixel 11, and an analog voltage signal corresponding to the amount of photoelectrons is generated according to the proportional coefficient, wherein the proportional coefficient is the product of the inverse of the capacitance of the floating diffusion layer (FD) and the source follower gain. The analog voltage signal is provided to the input port INN of the comparator 14. The voltage is generated by adding the <voltage corresponding to the amount of photoelectrons from the pixel 11> to the <reference voltage level>. More precisely, the former is set to a negative number and the latter is set to a positive number, they are added, and then their difference is measured. The analog voltage signal of the photodiode (PD) will experience large instantaneous fluctuations immediately after the input until it stabilizes. This is because there is capacitive coupling of Tr1, Tr3 and Tr4 when the photoelectrons are transferred. As long as there is no risk of confusion, the “reference (signal) level” may also be referred to as the “known (signal) level”, and the analog voltage signal level of the photodiode (PD) may be referred to as the “unknown (signal) level”.

[0016] like Figure 2 As shown, when electrons are used as signal carriers, the voltage corresponding to the amount of photoelectrons is usually lower than the reference voltage. Therefore, when the photoelectrons stored in the photodiode (PD) are at the maximum level, the "MAX" level can be obtained, and when it is at the minimum level, the "MIN" level can be obtained. Therefore, a single waveform is actually drawn between the MAX level line and the MIN level line. It should be noted that the characteristics of the photodiode (PD), the characteristics of the floating diffusion layer (FD), the maximum output range of the source follower, etc. are designed so that the ramp waveform can cover the maximum detectable charge amount.

[0017] In this example, the reference level corresponds to the upper limit of the ADC acceptable voltage, and it is assumed that the input voltage within the acceptable range is less than or equal to the reference level. However, this is not essential for the embodiments. For example, in the case of different polarities of the signal charge (e.g., holes), the amplitude relationship of the voltage is opposite. Such cases are also included in the scope of the present application.

[0018] The ramp waveform signal provided to the input port INP of the comparator 14 usually gradually decreases from a high level to a low level over time. The step width of the change is determined by the resolution of the analog-to-digital conversion. The range of change of the ramp signal (the range between the high level and the low level) can be the same as or different from the range used in the reference level measurement. In any case, it is ensured that the reference level and the unknown signal level (the voltage at the input port INN) are within the corresponding range of the ramp signal. The pixel voltage corresponding to the state of the photodiode (PD) can be determined by measuring the time when the analog voltage signal level and the ramp voltage signal level become the same.

[0019] Basically, only the AD conversion corresponding to the unknown signal level may be required. This is because the CDS result is based on analog operation. However, the error component caused when the auto-zero switch is disconnected needs to be eliminated. Therefore, the error component is usually eliminated by measuring the reference level (resetting the ADC), measuring the analog signal voltage level of the photodiode (PD), and calculating their difference. More specifically, the reference level is expressed as a negative number and the unknown signal level is expressed as a positive number. The negative reference level can be determined by gradually counting down according to a ramp waveform. The difference between the unknown signal level and the reference level can be obtained by gradually counting up from the latest down-counting value according to the ramp waveform. Figure 2In the example of , correlated double sampling (CDS) based on digital calculation is performed by sampling the reference level once and the unknown signal level once. It is named digital correlated double sampling (digital CDS). Correlated multiple sampling (CMS) can be performed by repeatedly performing AD conversion (sampling more than twice) (i.e., applying multiple sampling to the reference level / unknown level). For example, for one pixel, the reference level can be sampled four times and the unknown signal level can be sampled four times. For convenience, digital CDS will be referred to as CDS below.

[0020] When the reference level and the unknown signal level are directly expressed as digital values, a simple method is to express them as binary codes. Not only binary codes can be used, but Gray codes can also be used additionally. In this case, the measurement results of the reference level and / or the unknown signal level are first expressed as Gray codes, and then the Gray codes are converted into binary codes for subsequent digital signal processing. By also using Gray codes, rather than just binary codes, it is expected that the effective frequency can be reduced, power consumption can be reduced, bit errors can be suppressed, etc. It is also possible to easily share Gray code counters between multiple columns, thereby reducing power consumption more than ever before. Summary of the invention

[0021] However, when converting Gray code to binary code and performing full addition, the conventional method is not necessarily efficient.

[0022] According to an aspect of the present embodiment, when a Gray code is converted into a binary code and full addition is performed in correlated double sampling, efficiency can be improved.

[0023] According to one aspect of the embodiment, there is provided a logic circuit (34), the logic circuit (34) being configured to operate in an operation mode including a code conversion mode and an addition mode. The logic circuit comprises:

[0024] a first logic circuit (LC1) outputting a first operation result, wherein the first operation result is a result of performing an exclusive-OR operation on input bits;

[0025] Output the second operation result (B n / X n ) of the second logic circuit (LC2), the second operation result (B n / X n ) is a result of performing an XOR operation on input bits including the first operation result;

[0026] a selector (SEL) for operating according to said operating mode;

[0027] (i) wherein, in the code conversion mode, the selector (SEL) outputs the second operation result (B n ), the input bit of the first logic circuit (LC1) includes a bit (G n+1 ) and the bit in the binary code representation (B n+2 ), the input bits of the second logic circuit (LC2) also include bits (G n );

[0028] (ii) wherein, in the addition mode, the selector (SEL) outputs a carry bit (C) when the first addend (A) and the second addend (B) are added. n ), the input bits of the first logic circuit (LC1) include the bits of the first addend (A n ) and below the carry bit (C n ) of the digits (C n–1 ), the input bits of the second logic circuit (LC2) include the bits (B n ). BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram showing a partial configuration of the image sensor 10 .

[0030] Figure 2 This is an explanatory diagram describing correlated double sampling (CDS).

[0031] Figure 3A is a schematic diagram of a partial configuration of the image sensor 300 .

[0032] Figure 3B An exemplary pulse generation circuit 315 is shown.

[0033] Figure 3C A timing diagram showing waveforms of signals in the pulse generating circuit 315 is shown.

[0034] Figure 4 This is an explanatory diagram describing Gray code.

[0035] Figure 5 Shown included in Figure 3A The conversion and addition core circuit 34 in the arithmetic logic operation circuit (ALU) 33 is shown.

[0036] Figure 6 The configuration of the conversion and addition core circuit 34 when operating in the conversion mode is shown.

[0037] Figure 7 The configuration of the conversion and addition core circuit 34 when operating in the addition mode is shown.

[0038] Figure 8 A sampling unit including a conversion and addition core circuit 34 and a latch circuit is shown.

[0039] Fig. 9 A schematic flow chart describing operation according to one embodiment is shown.

[0040] Fig.10 A timing diagram is shown for describing the operation.

[0041] Fig.11 An exemplary data movement in conversion mode is shown.

[0042] Fig.12 An exemplary data movement in addition mode is shown.

[0043] Fig.13 One example of an exemplary conversion and addition core circuit 34 is shown that performs a 4-bit conversion and a 2-bit addition.

[0044] Fig.14 Another example of an exemplary conversion and addition core circuit 34 is shown that performs a 4-bit conversion and a 2-bit addition.

[0045] Fig.15 One example of a sampling unit is shown when the exemplary conversion and addition core circuit 34 performs a 4-bit conversion and a 2-bit addition.

[0046] Fig.16 Another example of a sampling unit is shown when the exemplary conversion and addition core circuit 34 performs a 4-bit conversion and a 2-bit addition.

[0047] Fig.17 An exemplary operation of correlated double sampling (CDS) is shown.

[0048] Fig.18 An exemplary operation of correlated multiple sampling (CMS) is shown.

[0049] Fig.19 An exemplary operation of correlated multiple sampling (CMS) is shown.

[0050] Fig. 20An exemplary operation of correlated double sampling (CDS) is shown.

[0051] Fig.21 An example of an electronic device is shown. DETAILED DESCRIPTION

[0052] Embodiments are described below with reference to the accompanying drawings in the context of the following sections.Throughout the drawings, the same reference numerals or reference symbols are assigned to the same elements.

[0053] 1. System Overview

[0054] 2. Gray code

[0055] 3. Reconfigurable logic circuits

[0056] 3.1 Conversion and addition core circuit

[0057] 3.2 Conversion Mode (G2B)

[0058] 3.3 Additive mode (CDS)

[0059] 4. Operation

[0060] 5. Variant

[0061] 5.1 Multi-bit

[0062] 5.2CMS

[0063] 5.3 Sunspot Correction

[0064] 6. Electronic devices

[0065] Each part in the following description is not essential to the embodiment. The descriptions in two or more parts can be combined, and the description in one part can be applied to the description in another part as appropriate (unless contradictory).

[0066] 1. System Overview

[0067] Figure 3A 3 is a schematic diagram of a partial configuration of the image sensor 300. For example, the image sensor 300 may be a CMOS image sensor. In the image sensor 300, sensor elements are arranged in an array, each sensor element converts a certain physical quantity into an electrical signal, and the output signal of the sensor element is used for sensing. The image sensor 300 may be used for any sensor, such as a fingerprint sensor.

[0068] exist Figure 3AIn the figure, a plurality of pixels 311, a row decoding circuit 312, a readout circuit 313, a horizontal scanner 318, a ramp waveform generator (RAMP) 316, a clock supplier (CLK) 317, a Gray code counter 319 and a controller 320 are shown. Figure 3A Elements related to the following description are shown. However, in reality, other elements may exist. A readout circuit 313 is provided for each column, and each readout circuit 313 includes a comparator 314, a pulse generating circuit 315, a gray code (GC) latch circuit 32, an S latch circuit 36, and an I / F latch circuit 37. A ramp waveform generator (RAMP) 316, a clock supplier (CLK) 317, and a gray code counter 319 are shared among multiple readout circuits 313. An arithmetic logic operation circuit (ALU) 33 that performs code conversion and addition operations may be provided to each readout circuit 313 (each column), or may be shared between multiple columns. In Figure 3A In the example shown, the arithmetic logic circuit (ALU) 33 is shared between the two columns. The arithmetic logic circuit (ALU) 33 includes a conversion and addition core circuit 34 and a T latch circuit 35.

[0069] The controller 320 controls Figure 3A For ease of illustration, the connection lines between the controller 320 and other components are not shown.

[0070] Each pixel 311 of the plurality of pixels 311 has the same configuration and the same function. The operation is described using the pixel 311 located at the nth row and the mth column as a representative example. Figure 3A The pixel 311 shown includes a photodiode (PD) having an anode connected to a low power supply V SS (For example, V SS can be GND); transfer transistor Tr1, connected between the cathode of PD and the floating diffusion layer (FD); reset transistor Tr2, connected between the floating diffusion layer (FD) and the high power supply V DD Although only one PD is shown in one pixel 311, multiple PDs and Tr1 may be connected to the floating diffusion layer (FD). The pixel 311 further includes: an amplifying transistor Tr3, forming a source follower, wherein a gate receiving an input voltage is connected to the floating diffusion layer (FD); a selecting transistor Tr4, controlling the connection between Tr3 and an output signal line ( Figure 3A Data line D m ) is connected between the output signal line D. m and provides source follower bias current.

[0071] The row decoding circuit 312 controls the selection of the pixel 311 and the operation of the pixel 311. Basically, the pixel 311 is driven (activated or deactivated) by the selection signal SEL n and transmission signal TG n,x To choose. Figure 3A In the example shown, the reset signal RST n , transmission signal TG n,x and the selection signal SEL n The operation of some signals such as , is controlled by the vertical scanner. The level converter converts the levels of these kinds of signals to appropriate levels for the pixel 311. The selection signal SEL n and transmission signal TG n,x It can be called a scan line. Since the scan line is connected to a plurality of pixels 311, a plurality of pixels can be designated at the same time by designating one scan line.

[0072] The readout circuit 313 can read out the data through a plurality of data lines (...D m , D m+1 ...) reads analog data from the pixel 311, converts the analog data into digital data, and then sends the converted data to the horizontal scanner 318. Therefore, the readout circuit 313 can function as an analog-to-digital converter (ADC). Figure 3A The comparator 314 shown includes a differential amplifier. For example, the pulse generation circuit 315 can be as follows Figure 3B The configuration shown in FIG. 1 and generates a pulse when the polarity of the output of comparator 314 changes, such as Figure 3C The Gray code (GC) latch circuit 32 receives the output pulse as input and stores the Gray code corresponding to the count value at that time.

[0073] The horizontal scanner 318 receives the digital data from the readout circuit 313 and transmits the digital data to a processing block (not shown) in the subsequent stage. The processing block may be an internal image processing processor or an interface circuit, etc.

[0074] Figure 3A The multiple readout circuits (ADC) 313 shown can operate in parallel. Each readout circuit 313 operates in a time-division multiplexing manner with respect to k pixels. "k" represents the number of pixels connected in parallel to one readout circuit 313. Figure 3A In the example of , the following operation is repeated k times: an analog signal is read from a pixel 311, and then a digital signal corresponding to the analog signal is output (i.e., analog-to-digital conversion). The number of pixels (specifically, the number of rows and columns) can be any suitable positive integer. For example, the number of rows and columns can be hundreds or thousands, etc.

[0075] 2. Gray code

[0076] As described above, in order to reduce the effect of error components included in the reference level (the voltage level of the floating diffusion layer (FD)) and the unknown signal level (the signal level of the photodiode (PD)) of the pixel 311, correlated double sampling (CDS) or correlated multiple sampling (CMS) is performed. When the reference level and the unknown signal level are represented as digital values, not only binary code but also Gray code can be used additionally. In this case, the measurement results of the reference level and / or the unknown signal level are first represented as Gray code, and then the Gray code is converted into binary code for subsequent digital signal processing. By also using Gray code, rather than just binary code, it is expected that some technical effects can be provided, such as improving accuracy or reducing power consumption, etc.

[0077] Figure 4 is an illustration of Gray code. Usually, the left side shows the 5-bit Gray code, the right side shows the corresponding decimal code, and the middle shows the 5-bit binary code. Gray code has a property that only one bit is different when incrementing or decrementing by 1. For example, when a certain amount in the decimal code changes from 7 to 8, the corresponding binary code changes from 1 to 5.

[0078] 00111 becomes

[0079] 01000.

[0080] In this case, in (7) 10 To (8) 10 Before the change is complete, 4 bits need to be changed. Therefore, if the unfinished value is used incorrectly, some large errors may occur. In contrast, Gray code

[0081] 00100 becomes

[0082] 01100.

[0083] From (7) 10 To (8) 10 Only 1 bit is changed before the change is completed. Therefore, even if the value that has not yet been completed is used incorrectly, it is unlikely that a large error will occur. This is because the number of bit errors is at most 1.

[0084] In addition, the most significant bit (MSB) of Gray code and binary code can correspond to positive / negative signs. Specifically, consider a positive number (+14) based on 10 Get a negative number (–14)10 Such a negative number is equal to the 2's complement of the positive number. The 2's complement can be easily obtained by changing the MSB (i.e. the sign) of the Gray code of the positive number from 0 to 1 (for example, (01001) G ->(11001) G ), and add 1 to the binary code corresponding to the Gray code after the sign change ((00001) B +(10001) B =(10010) B ). It should be noted that the binary code (10001) corresponding to the Gray code after the sign change is B Equal to a positive number (+14) 10 The 1's complement of the corresponding binary code. It should also be noted that the 2's complement can be obtained by adding 1 to the 1's complement. (If the 1's complement of the binary code is calculated directly, all bits of the binary code must be inverted.) Therefore, when performing addition operations, negative addition, that is, subtraction, can be performed by setting the MSB of the addend to a positive value (MSB = 1) and setting the carry bit to 1 in the LSB bit addition.

[0085] The following formula is in Gray code (G N–1 G N–2 ……G n ...G0) and binary code (B N–1 B N–2 ……B n Valid between:

[0086] G n xor B n+1 =B n

[0087] Therefore, Gray code can be converted to binary code by the following operation:

[0088] B N–1 =G N–1

[0089] B N–2 =G N–2 xor B N–1 =G N–2 xor G N–1

[0090] …

[0091] B n =G n xor B n+1 =G n xor G n+1 xor……G N–1

[0092] …

[0093] B0=G0 xor B1=G0 xor G1 xor……G N–1

[0094] B N–1 is the most significant bit (MSB) of the binary code in this example, and B N–1 Equal to the most significant bit (MSB) of Gray code, that is, G N–1 Therefore, based on B N–1 (MSB), the binary bits can be derived in sequence until B0 (LSB).

[0095] The current converted binary value is added to a previously converted value. In this embodiment, the previously converted value is usually a known level (reference level), while the current converted binary value is an unknown signal level. Addition operation, such as

[0096] (first addend)+(second addend)=(addition result),

[0097] The calculation must start from the LSB.

[0098] (A N–1 A N–2 ...A n ...A0)+(B N–1 B N–2 ……B n ...B0) = (X N–1 X N–2 ...X n ...X0),

[0099] It is necessary to start from X0. Therefore, the execution order of addition is opposite to the order of code conversion. In the traditional method, the following calculations are usually performed step by step.

[0100] G2B_Step 0:B N–1 =G N–1

[0101] G2B_Step 1:B N–2 =G N–2 xor B N–1 =G N–2 xor G N–1

[0102] …

[0103] G2B_Step N–1–n: Bn =G n xor B n+1 =G n xor G n+1 xor……G N–1

[0104] …

[0105] G2B_Step N–1:B0=G0 xor B1=G0 xor G1 xor……G N–1 ;X0,C=A0+B0

[0106] Add_Step 0: B1=G0xorB0 ;X1,C=A1+B1

[0107] …

[0108] Add_Step N–1–n: B n =G n–1 xorB n–1 ;X n ,C=A n +B n

[0109] …

[0110] Add_Step N–1: B N–1 =G N–2 xor B N–2 ;X N–1 ,C=A N–1 +B N–1

[0111] When calculating the underlined part, use the following formula: B n =G n–1 xor B n–1

[0112] The “,C” in the addition operation indicates the carry bit for the digit to be carried. In general, (G2B_Step 0) to (G2B_StepN–1) correspond to converting the Gray code (G N–1 G N–2 ……G n ……G0) into binary code (B N–1 B N–2 ……B n The steps from the second half of (G2B_Step N–1) to (Add_Step N–1) correspond to the following operations: the bits (B0) of the second addend required for the new calculation of the addition are n ), the first bit of the number to be added (A n ) and the second digit to be added (B n ) are added to obtain the operation result (X n). In the conventional method, the process from (G2B_Step 0) to (G2B_Step N–1) and the process from (Add_Step 0) to (Add_Step N–1) are performed independently.

[0113] However, for the underlined portion in the process from (Add_Step 0) to (Add_Step N-1), similar operations are performed in the process from (G2B_Step 0) to (G2B_Step N-1). The present embodiment improves the operation efficiency based on at least this knowledge.

[0114] 3. Reconfigurable logic circuits

[0115] 3.1 Conversion and addition core circuit

[0116] Figure 5 Shown included in Figure 3A The conversion and addition core circuit (CDS / G2B) 34 in the arithmetic logic operation circuit (ALU) 33 is shown.

[0117] The conversion and addition core circuit (CDS / G2B) 34 includes: a first half adder circuit (LC1), including a first XOR circuit (XOR1) for performing an XOR operation on input bits; and a first logic AND circuit (AND1) for performing a logic AND operation on input bits.

[0118] The conversion and addition core circuit (CDS / G2B) 34 includes: a second half adder circuit (LC2), including a second XOR circuit (XOR2), which performs an XOR operation on an input bit, the input bit including another input bit and the output of the first XOR circuit (XOR1); and a second logic AND circuit (AND2), which performs a logic AND operation on the input bit of the second XOR circuit (XOR2).

[0119] The conversion and addition core circuit 34 includes: a logic OR circuit (OR) that performs a logic OR operation on the output of the first logic AND circuit (AND1) and the output of the second logic AND circuit (AND2); and a selector (SEL) that selects the output of the second XOR operation circuit (XOR2) or the output of the logic OR circuit (OR) according to the operation mode. The operation mode includes a code conversion mode (G2B) and an addition mode (CDS). The conversion and addition core circuit 34 can switch the circuit configuration according to the operation mode.

[0120] 3.2 Conversion Mode (G2B)

[0121] Figure 6 The configuration of the conversion and addition core circuit 34 when operating in the conversion mode is shown.

[0122] A first XOR circuit (XOR1) in the first half adder circuit (LC1) outputs a first operation result (B n+1 ), the first operation result (B n+1 ) is the result of an XOR operation on the input bits, the input bits including the bits (G n+1 ) and the bit in the binary code representation (B n+2 ).

[0123] Next, the second XOR circuit (XOR2) in the second half adder circuit (LC2) outputs the second operation result (B n ), the second operation result (B n ) is the result of performing an XOR operation on the input bits, the input bits including the first operation result (B n+1 ) and the second bit (G in the Gray code representation of the number to be added n ).

[0124] The selector (SEL) selects and outputs the output of the second XOR circuit (XOR2). In contrast to the conventional method, in this embodiment, such derived bits in the binary code representation are stored in the T latch 35.

[0125] As an example, consider the case where the Gray code corresponding to the second addend is (G5 G4 G3 G2 G1 G0) and the Gray code is converted into a binary code. The Gray code of the second addend is stored in the GC latch 32. The MSB of the Gray code is G5 (MSB=G5), and the LSB is G0 (LSB=G0).

[0126] In the initial operation step of this embodiment, the first XOR circuit (XOR1) outputs the first operation result (B5), which is the result of performing an XOR operation on the input bits (G5 and 0). For this "0", alternatively, the reset latch output of the carry bit can be used. Therefore, the MSB of the Gray code and the MSB of the binary code are equal, B5=G5. In addition, in order to obtain a negative number, G5 can be assigned to the sign, and an XOR operation can be performed on G5 and 1 (for this "1", the set latch output of the carry bit can be used). In this case, the fixed input bit can be stored as a code bit.

[0127] The second XOR circuit (XOR2) outputs a second operation result (B4), which is a result of performing an XOR operation on G4 and the first operation result (B5). The selector (SEL) selects and outputs the output (B4) of the second XOR circuit (XOR2).

[0128] In this case, for example, the output (B4) is stored in the latch circuit as a carry bit. The input bits (G5, G4) of the first XOR circuit and the second XOR circuit (XOR1, XOR2) are updated to the next input bits (G3, G2). The first XOR circuit (XOR1) outputs a first operation result (B3), which is a result of performing an XOR operation on the input bits (G3 and B4). B4 is obtained from the selector (SEL).

[0129] The second XOR circuit (XOR2) outputs a second operation result (B2), which is a result of performing an XOR operation on G2 and the first operation result (B3). The selector (SEL) selects and outputs the output (B2) of the second XOR circuit (XOR2).

[0130] Next, the first XOR circuit (XOR1) outputs a first operation result (B1), which is the result of performing an XOR operation on the input bits (G1 and B2). B2 is obtained from the selector (SEL). The second XOR circuit (XOR2) outputs a second operation result (B0), which is the result of performing an XOR operation on G0 and the first operation result (B1).

[0131] Thus, a binary code (B5 B4 B3 B2 B1 B0) is obtained. The binary code (B5 B4 B3 B2 B1 B0) corresponds to the Gray code (G5 G4 G3 G2 G1 G0) of the second addend. As described above, by changing the sign of the Gray code and adding 1 to the binary code corresponding to the Gray code after the sign change, the negative code of the binary code can be easily obtained. Contrary to the conventional method, in this embodiment, such derived binary bits (B5 B4 B3 B2 B1 B0) are stored in the T latch 35.

[0132] 3.3 Additive mode (CDS)

[0133] Figure 7 FIG. 2 shows the configuration of the conversion and addition core circuit 34 when it is operating in the addition mode. Before the operation in the addition mode begins, the bits (A1...A n ) is stored in the S latch circuit 36. The bits (B1...B n ) is stored in the T latch circuit 35.

[0134] In addition mode, a first XOR circuit (XOR1) of a first adder circuit (LC1) outputs a calculation result, which is a result of performing an XOR operation on input bits, the input bits including bits of a first addend (A n ) and below the carry bit (C n) of the digits (C n–1 The first logic AND circuit (AND1) of the first half adder circuit (LC1) outputs an operation result, which is the result of performing a logic AND operation on the input bits, the input bits including the bits of the first addend (A n ) and the carry bit of the digit below the carry bit (C n–1 ).

[0135] The exclusive OR circuit (XOR2) of the second half adder circuit (LC2) outputs an operation result, which is the result of performing an exclusive OR operation on the input bits (XOR2). n ), which includes another input bit (B n ) and the output of the first XOR circuit (XOR1). The second logic AND circuit (AND2) of the second half adder circuit (LC2) outputs an operation result, which is the result of performing a logic AND operation on the input bits, the input bits including another input bit (B n ) and the output of the first XOR circuit (XOR1).

[0136] The logic OR circuit (OR) performs a logic OR operation on inputs including the output of the first logic AND circuit (AND1) and the output of the second logic AND circuit (AND2). The selector (SEL) selects and outputs the output of the logic OR circuit (OR) as a carry bit (C n ).

[0137] As an example, consider 6-bit addition, as follows:

[0138] (A5 A4 A3 A2 A1 A0)+(B5 B4 B3 B2 B1 B0)=(X5 X4 X3 X2 X1 X0)

[0139] Before the operation in the addition mode starts, the first addend ( A0 . . . A5 ) is stored in the S latch circuit 36 ​​, and the second addend ( B0 . . . B5 ) is stored in the T latch circuit 35 .

[0140] The first XOR circuit (XOR1) outputs an operation result, which is the result of performing an XOR operation on input bits, the input bits including the bit (A0) of the first addend and the carry bit (C –1 =0). The first logic AND circuit (AND1) outputs an operation result, which is the result (0) of performing a logic AND operation on the input bits, the input bits including A0 and C –1 In addition, if the second addend (B5 B4 B3 B2 B1 B0) is obtained through the code conversion process including the above-mentioned sign inversion process, the lower digit carry bit can be set to 1 (C –1 =1) to handle the sign reversal process.

[0141] The second XOR circuit (XOR2) outputs an operation result, which is a result (X0) of performing an XOR operation on an input bit, the input bit including another input bit (B0) and the output of the first XOR circuit (XOR1). The second logic AND circuit (AND2) outputs an operation result, which is a result of performing a logic AND operation on an input bit, the input bit including B0 and the output of the first XOR circuit (XOR1).

[0142] The logic OR circuit (OR) performs a logic OR operation on the inputs, which include the output of the first logic AND circuit (AND1) and the output of the second logic AND circuit (AND2). The selector (SEL) selects and outputs the output of the logic OR circuit (OR) as the carry bit (C0). In this way, the addition result (X0) of A0 and B0 and the carry bit C0 are obtained. A0 in the first addend (A5 A4A3 A2 A1 A0) stored in the S latch circuit 36 ​​is replaced by X0.

[0143] For the first to fifth bits, operations similar to those for the 0th bit are repeated. After the operation on the fifth bit is completed, the first addend (A5 A4 A3 A2 A1 A0) stored in the S latch circuit 36 ​​has been replaced by the addition result (X5 X4 X3X2 X1 X0). In addition, by using 2's complement, positive and negative numbers can be used. The MSB corresponds to the sign code.

[0144] 4. Operation

[0145] Next, combine Figure 3A The readout circuit 313 in FIG. 1 is used to describe the operation in more detail. In the readout circuit 313 used for this description, the components after the pulse generating circuit 315 are as follows: Figure 8 Assume that the Gray code and binary code to be operated are both 6-bit codes. The conversion and addition core circuit 34 converts two bits at a time in the conversion mode and performs 1-bit addition in the addition mode. Therefore, the conversion and addition core circuit 34 performs code conversion and full addition in a time-division multiplexing manner.

[0146] Fig. 9 A schematic flow chart describing operation according to one embodiment is shown. Fig.10 A timing diagram is shown for describing the operation. Fig.10 In the figure, the bottom row shows the timeline. For ease of explanation, the time labels after 10 are expressed in units of 5. Fig. 9 and Fig.10As shown in the top row of , an operation cycle according to this embodiment generally includes a level measurement cycle (ADC) (step 902), a code conversion cycle (G2B) (step 904) and an addition cycle (CDS) (step 906).

[0147] The operation in the level measurement cycle (ADC) (step 902) is described. The level measurement cycle corresponds to the operation of measuring the unknown level. The operation of measuring the known level (reference level) is completed. Fig.10 The waveform represented by RSTCNTB in FIG. 1 represents the state of the reset transistor of the photodiode (PD). During the period when RSTCNTB is OFF, the floating diffusion layer (FD) is in a floating state. During this period, the charge in the photodiode (PD) is transferred to the floating diffusion layer (FD), and the unknown signal level is measured.

[0148] Fig.10 The waveform represented by CMPIN in FIG. 3 represents the pulse generating circuit 315 ( Figure 3A ) output. The output pulse occurs when the gradually decreasing ramp waveform matches the level to be measured. This time Fig.10 The corresponding bit of the Gray code (G5 G4 G3 G2 G1 G0) corresponding to the time "GC" is stored in the Gray code latch (GCLAT) 32 ( Figure 8 ) in the 6 latches (GCLAT0 to GCLAT5). Fig.10 As shown, at time "GC", the data stored in GCLAT changes from "xxxxxx" to "G<5:0>".

[0149] On the other hand, the first number to be added (A5 A4 A3 A2 A1 A0) has been stored in the S latch 36. Fig.10 As shown, the data stored in SLAT remains as “A<5:0>” until time “11”. As an example, the first addend is a binary code representing a reference level for measuring a photodiode (PD).

[0150] Fig.10 The waveform represented by G2B / CDS in FIG. 1 represents the operation mode of the conversion and addition core circuit 34. Fig.10 In the waveform, a low level corresponds to a conversion mode, a high level corresponds to an addition mode, and the waveform changes from a low level to a high level. However, such a waveform is not limited as long as the two modes can be distinguished.

[0151] Fig.10The waveform denoted by OCLK in shows a clock for controlling the operation of transmitting the output of the conversion and addition core circuit 34 to the S latch circuit 36.

[0152] Fig.10 The waveform denoted by CCLK in FIG. 1 represents a clock for controlling the operation of the conversion and addition core circuit 34 .

[0153] Fig.10 The waveform represented by RSTCB in FIG. 1 represents the reset signal for resetting the carry bit. Fig.10 (bottommost item) is represented as "CARRY". The carry bit is reset immediately before the code conversion mode starts and immediately before the addition mode starts. Therefore, at the times represented by "1" and "8", the carry bit is reset to "0".

[0154] Next, the operation in the code conversion cycle (G2B) (step 904) is described. In the cycle from time "1" to time "8", the conversion and addition core circuit 34 operates in the conversion mode (G2B).

[0155] Fig.10 The waveform indicated by S54 in FIG. 1 represents a selection signal for connecting or disconnecting between the output of the Gray code latch circuit 32 (GCLAT5, GCLAT4) and the input of the conversion and addition core circuit 34. The waveform indicated by CK54 represents a clock for controlling the operation of the T latch circuit (TLAT5, TLAT4).

[0156] During the period from time "1" to "3" when S54 is at a high level, the data (G5, G4) stored in GCLAT5 and GCLAT4 are used as input bits of the conversion and addition core circuit 34. Since the code conversion is performed sequentially starting from the most significant bit (MSB), G5 is selected first. In the code conversion mode, the conversion and addition core circuit 34 converts the input Gray code representation bits (G5, G4) into corresponding binary code representation bits (B5, B4). The operation results (B5, B4) are stored in the T latch circuits (TLAT5, TLAT4) ( Fig.11 ).like Fig.10 As shown in FIG. 1 , at time “2”, the data stored in TLAT changes from “xxxxxx” to “B<5:4>, xxxx”. Since B4 is used for subsequent operations, it is stored as a carry bit. Fig.10 As shown, the carry bit (CARRY) changes from "0" to "B <4> ”.

[0157] A similar operation is performed for the subsequent lower Gray code bits (G3 G2 G1 G0). Fig.10The waveform indicated by S32 in FIG. 1 represents a selection signal for connecting or disconnecting between the output of the Gray code latch circuit 32 (GCLAT3, GCLAT2) and the input of the conversion and addition core circuit 34. The waveform indicated by CK32 represents a clock for controlling the operation of the T latch circuit (TLAT3, TLAT2).

[0158] During the period from time "3" to "5" when S32 is at a high level, the data (G3, G2) stored in GCLAT3 and GCLAT2 are used as input bits of the conversion and addition core circuit 34. The conversion and addition core circuit 34 converts the input Gray code representation bits (G3, G2) into corresponding binary code representation bits (B3, B2). The operation results (B3, B2) are stored in the T latch circuits (TLAT3, TLAT2). Fig.10 As shown in FIG. 1 , at time “4”, the data stored in TLAT changes from “B<5:4>, xxxx” to “B<5:2>, xx”. Since B2 is used for subsequent operations, it is stored as a carry bit. Fig.10 As shown, the carry bit (CARRY) is from "B <4> ” becomes “B <2> ”.

[0159] Fig.10 The waveform indicated by S10 in FIG. 1 represents a selection signal for connecting or disconnecting between the output of the Gray code latch circuit 32 (GCLAT1, GCLAT0) and the input of the conversion and addition core circuit 34. The waveform indicated by CK10 represents a clock for controlling the operation of the T latch circuit (TLAT1, TLAT0).

[0160] During the period from time "5" to "7" when S10 is at a high level, the data (G1, G0) stored in GCLAT1 and GCLAT0 are used as input bits of the conversion and addition core circuit 34. The conversion and addition core circuit 34 converts the input Gray code representation bits (G1, G0) into corresponding binary code representation bits (B1, B0). The operation results (B1, B0) are stored in the T latch circuits (TLAT1, TLAT0). Fig.10 As shown in FIG. 1 , at time “6”, the data stored in TLAT changes from “B<5:2>,xx” to “B<5:0>”. B0 is stored as a carry bit. Fig.10 As shown, the carry bit (CARRY) is from "B <2> ” becomes “B <0> ”.

[0161] Next, the operation in the addition cycle (CDS) (step 906) is described. In the cycle starting from time "8", the conversion and addition core circuit 34 operates in the addition mode (CDS). In this example, a 6-bit addition is performed as follows:

[0162] (A5 A4 A3 A2 A1 A0)+(B5 B4 B3 B2 B1 B0)=(X5 X4 X3 X2 X1 X0)

[0163] Before the operation in the addition mode starts, the first addend (A0 ... A5) is stored in the S latch circuit 36 ​​(SLAT0 ... SLAT5). The second addend (B1 ... B5) is stored in the T latch circuit 35 (TLAT0 ... TLAT5).

[0164] Fig.10 The waveform indicated by S0 in FIG. 1 represents a selection signal for connecting or disconnecting between the outputs of the T latch circuit (TLAT0) and the S latch circuit (SLAT0) and the input of the conversion and addition core circuit 34. The waveform indicated by CK0 represents a clock for controlling the operation of the S latch circuit (SLAT0).

[0165] In the period from time "8" to "11" when S0 is at a high level, the data (B0, A0) stored in TLAT0 and SLAT0 is used as the input bit of the conversion and addition core circuit 34. Since the addition operation is performed sequentially starting from the least significant bit (LSB), the LSB (A0, B0) is selected first. In the addition mode, the conversion and addition core circuit 34 performs the addition operation according to the input bit (B0, A0) and outputs the addition result (X0). Specifically, in the period from time "11" to "12" when OCLK is at a high level, the operation result (X0) is stored in the S latch circuit (SLAT0) ( Fig.12 ).like Fig.10 As shown, at time "11", the data stored in SLAT changes from "A<5:0>" to "A<5:1>, X <0> In addition, the carry bit is stored accordingly. Fig.10 As shown, during the period from time "10" to "13", the carry bit (CARRY) indicates that "Cout <0> ”.

[0166] A similar operation is performed on subsequent higher bits. Fig.10 The waveform indicated by S1 in FIG. 1 represents a selection signal for connecting or disconnecting between the outputs of the T latch circuit (TLAT1) and the S latch circuit (SLAT1) and the input of the conversion and addition core circuit 34. The waveform indicated by CK1 represents a clock for controlling the operation of the S latch circuit (SLAT1).

[0167] In the period from time "11" to "14" when S1 is at a high level, the data (B1, A1) stored in TLAT1 and SLAT1 are used as input bits of the conversion and addition core circuit 34. The conversion and addition core circuit 34 performs an addition operation based on the input bits (B1, A1) and outputs the addition result (X1). Specifically, in the period from time "14" to "15" when OCLK is at a high level, the operation result (X1) is stored in the S latch circuit (SLAT1). Fig.10 As shown, at time "14", the data stored in SLAT is changed from "A<5:1>, X <0> ” becomes “A<5:2>,X<1:0>”. In addition, the carry bit is stored accordingly. Fig.10 As shown, during the period from time "13" to "16", the carry bit (CARRY) indicates that "Cout <1> ”.

[0168] Fig.10 The waveforms represented by S2 to S5 in the figure respectively represent the T latch circuit (TLAT 2–5 ) and S latch circuit (SLAT 2–5 ) and the input of the conversion and addition core circuit 34. The waveforms represented by CK2 to CK5 respectively represent the selection signals for controlling the S latch circuit (SLAT 2–5 )’s operating clock.

[0169] During the period from S2 to S5 being high, the current stored in TLAT 2–5 and SLAT 2–5 The data in (B 2–5 , A 2–5 ) is used as an input bit of the conversion and addition core circuit 34. The conversion and addition core circuit 34 calculates the input bit (B) according to the input bit (B 2–5 , A 2–5 ) performs addition operation and outputs the addition result (X 2–5 Specifically, during the period when OCLK is at a high level, the operation result (X 2–5 ) is stored in the S latch circuit (SLAT 2–5 ). Fig.10 As shown in the figure, the data stored in SLAT becomes "A<5:3>,X<2:0>", "A<5:4>,X<3:0>", "A <5> ,X<4:0>” and “X<5:0>”. In addition, the carry bit is stored accordingly. Fig.10 As shown, the carry bit (CARRY) becomes "Cout <2> ”, “Cout <3> ”, “Cout <4> ” and “Cout <5> ”.

[0170] Stored in Figure 8The addition result X<5:0> in the S latch circuit (SLAT0 to SLAT5) shown in FIG. 1 is stored in the I / F latch circuit 37 (I / FLAT0 to I / FLAT5) according to the horizontal synchronization clock HCLK, and then transmitted to the horizontal scanner 318 ( Figure 3A ).

[0171] According to this embodiment, the conversion and addition core circuit 34, the T latch circuit 35 and the S latch circuit 36 ​​cooperate with each other to efficiently perform code conversion and full addition in correlated double sampling (CDS). Since the conversion and addition core circuit 34 can be shared for code conversion and full addition, there is no need to provide a code conversion circuit and a full addition circuit separately. In this way, operating resources can be saved. Specifically, power consumption and space in the operation circuit can be reduced.

[0172] 5. Variant

[0173] 5.1 Multi-bit

[0174] exist Figure 5 and Figure 8 In the example of FIG. 3 , the conversion and addition core circuit 34 converts two bits at a time in the conversion mode and performs a 1-bit addition in the addition mode. If the number to be operated includes 6 bits, the conversion and addition core circuit 34 is used in a time-division multiplexing manner. However, this is only an example. More bits can be operated at a time, and / or another repeat count can also be used.

[0175] Fig.13 An example of an exemplary conversion and addition core circuit 34 that performs 4-bit conversion and 2-bit addition at a time is shown. In conversion mode, 4-bit Gray code (G3 G2 G1 G0) is converted to 4-bit binary code (B3 B2 B1 B0). In the case of conversion mode, the selector selects "0".

[0176] In addition mode, two bits (A1 A0) of the first addend and two bits (B1 B0) of the second addend are added, and the operation result (X1 X0) is output. In addition mode, the selector selects "1". Latch circuit LAT C Used to store the carry bit. The operations of conversion and addition are similar to those described in the previous section. We will not repeat them here.

[0177] Fig.14 Another example of an exemplary conversion and addition core circuit 34 is shown that performs 4-bit conversions and 2-bit additions at a time. Fig.14 The conversion and addition core circuit 34 in the embodiment can be similar to Fig.13 Configure and run as shown. Fig.13and Fig.14 The conversion and addition core circuit 34 shown includes a latch circuit LAT C ,and Fig.14 The conversion and addition core circuit 34 shown also includes a latch circuit LAT B . Latch circuit LAT B The most recently acquired operation result can be stored. After the 4-bit Gray code (G3 G2 G1 G0) is converted into a 4-bit binary code (B3 B2 B1 B0), the LSB (B0) can be stored in the latch circuit LAT. B The operations of conversion and addition are similar to those described in the previous section and will not be described in detail.

[0178] Fig.15 FIG. 2 shows an example of a sampling unit when the conversion and addition core circuit 34 performs 4-bit conversion and 2-bit addition. Fig.15 In the example of , the Gray code and binary code to be operated include 12 bits. Therefore, the conversion and addition core circuit 34 performs code conversion and full addition in a time-division multiplexing manner. Specifically, the code conversion of all 12 bits is performed by repeating 4-bit code conversion 3 times, and the full addition of all 12 bits is performed by repeating 2-bit addition 6 times, as follows:

[0179] (Code switching: first time)

[0180] T latch 35: ________ B8 B9 B 10 B 11

[0181] (Code switching: second time)

[0182] T latch 35: ____ B4 B5 B6 B7 B8 B9 B 10 B 11

[0183] (Code switching: third time)

[0184] T latch 35: B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B 10 B 11

[0185] (Addition: First time)

[0186] T latch 35: B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B 10 B 11

[0187] S latch 36: X0 X1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A 11

[0188] (Addition: Second time)

[0189] T latch 35: B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B 10 B 11

[0190] S latch 36: X0 X1 X2 X3 A4 A5 A6 A7 A8 A9 A 10 A 11

[0191] (Addition: third time)

[0192] T latch 35: B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B 10 B 11

[0193] S latch 36: X0 X1 X2 X3 X4 X5 A6 A7 A8 A9 A 10 A 11

[0194] (Addition: fourth time)

[0195] T latch 35: B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B 10 B 11

[0196] S latch 36: X0 X1 X2 X3 X4 X5 X6 X7 A8 A9 A 10 A 11

[0197] (Addition: fifth time)

[0198] T latch 35: B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B 10 B 11

[0199] S latch 36: X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 A 10 A 11

[0200] (Addition: Sixth time)

[0201] T latch 35: B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B 11

[0202] S latch 36: X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X 10 X 11

[0203] Fig.16 Another example of a sampling unit is shown when the exemplary conversion and addition core circuit 34 performs a 4-bit conversion and a 2-bit addition. Fig.16 In the example of , the Gray code and binary code to be operated also include 12 bits. Fig.16 and Fig.15 The difference is that Fig.16 The T latch circuit 35 includes only four components, and Fig.15 The T latch circuit includes 12 elements. Therefore, first, the binary code bits required for addition are obtained and used for addition, and then the binary code bits required for the next addition are obtained and used for the next addition. Specifically, the 4-bit code conversion is repeated 7 times in total, and the 2-bit full addition is repeated 6 times in total.

[0204] ( Code switching: First time )

[0205] Carry latch of G2B: 0xor G0 xor G1 xor G2

[0206] S latch 36: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A 10 A 11

[0207] (Code switching: second time)

[0208] Carry latch of G2B: (0xor G0 xor G1 xor G2)xor G3 xor G4 xor G5 xor G6

[0209] S latch 36: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A 10 A 11

[0210] (Code switching: third time)

[0211] Carry latch of G2B: ((0xor G0 xor G1 xor G2)xor G3 xor G4 xor G5 xor G6)xorG7 xor G8 xor G9 xor G 10

[0212] S latch 36: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A 10 A 11

[0213] (Code conversion: fourth time)

[0214] Carry latch of G2B: (((0xor G0 xor G1 xor G2)xor G3 xor G4 xor G5 xor G6)xor G7 xor G8 xor G9 xor G 10 )xor xor G 11 xor 0xor 0xor 0=B0

[0215] S latch 36: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A 10 A 11

[0216] (Code switching: fifth time)

[0217] Carry latch of G2B: B3

[0218] Carry latch of CDS: 0

[0219] T latch 35: B0 B1 B2 B3

[0220] S latch 36: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A 10 A 11

[0221] (Addition: First time)

[0222] Carry latch of GDS: C1

[0223] T latch 35: B0 B1 B2 B3

[0224] S latch 36: X0 X1 A2 A3 A4 A5 A6 A7 A8 A9 A 10 A 11

[0225] (Addition: Second time)

[0226] Carry latch of CDS: C3

[0227] T latch 35: B0 B1 B2 B3

[0228] S latch 36: X0 X1 X2 X3 A4 A5 A6 A7 A8 A9 A 10 A 11

[0229] (Code switching: sixth time)

[0230] Carry latch of G2B: B7

[0231] T latch 35: B4 B5 B6 B7

[0232] S latch 36: X0 X1 X2 X3 A4 A5 A6 A7 A8 A9 A 10 A 11

[0233] (Addition: third time)

[0234] Carry latch of CDS: C5

[0235] T latch 35: B4 B5 B6 B7

[0236] S latch 36: X0 X1 X2 X3 X4 X5 A6 A7 A8 A9 A 10 A 11

[0237] (Addition: fourth time)

[0238] Carry latch of CDS: C7

[0239] T latch 35: B4 B5 B6 B7

[0240] S latch 36: X0 X1 X2 X3 X4 X5 X6 X7 A8 A9 A 10 A 11

[0241] (Code switching: seventh time)

[0242] Carry latch of G2B: B 11

[0243] T latch 35: B8 B9 B 10 B 11

[0244] S latch 36: X0 X1 X2 X3 X4 X5 X6 X7 A8 A9 A 10 A 11

[0245] (Addition: fifth time)

[0246] Carry latch of CDS: C9

[0247] T latch 35: B8 B9 B 10 B 11

[0248] S latch 36: X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 A 10 A 11

[0249] (Addition: Sixth time)

[0250] Carry latch of CDS: C 11

[0251] T latch 35: B8 B9 B 10 B 11

[0252] S latch 36: X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X 10 X 11

[0253] It should be noted that B0=G 11 xor...xor G1 xor G0, and Z xor 0 = Z (for any bit Z). C i A i and B i Carry bit generated during addition (i=0...11).

[0254] 5.2CMS

[0255] As reference Figure 2 As shown, correlated double sampling (CDS) may be performed to eliminate error effects such as feedthrough due to switching of the reset transistor Tr2 or kTC noise of the diffusion capacitor.

[0256] Fig.17 An exemplary operation of correlated double sampling (CDS) is shown. First, within the reference level sampling period, the time when the ramp waveform signal (RAMP) that decreases at a constant rate is equal to the voltage level of the floating diffusion layer (FD) is determined. The voltage level corresponding to this time is determined as the reference signal. Fig.17In the example shown, reference level sampling is performed at point "S1" by providing a pulse (CMP) from the comparator. The gray code (GC) of the amplitude corresponding to this point "S1" is stored in the gray code latch circuit. Therefore, the data stored in the GC latch changes from an undetermined state "X" to a certain value "–r1". The most significant bit of the reference level can be set to 1, which indicates a negative number ( Figure 4 ).

[0257] Next, during the signal level sampling period, the analog voltage signal of the photodiode (PD) is provided to the comparator and the signal level is measured. The time when the ramp waveform signal (RAMP) that decreases at a constant rate is equal to the signal voltage level is determined. The voltage level corresponding to this time is determined as the signal level. Fig.17 In the example shown, signal level sampling is performed at point "S2" by supplying a pulse (CMP) from the comparator. The gray code (GC) of the amplitude corresponding to this point "S2" is stored in the gray code latch circuit. Therefore, the data stored in the GC latch changes from the previous value "–r" to the current value "s". The most significant bit of the reference level can be set to 0, which indicates a positive number ( Figure 4 ).

[0258] The difference (–r+s) between the signal level and the reference level can be obtained by setting the reference level to a negative number, setting the (subsequently measured) signal level to a positive number, and adding them. Specifically, the obtained value is represented by (–r+s). This value is stored in the S latch circuit 36. Fig.17 As shown in FIG. 1 , the data represented by “Calc.Latch” rises from the level “–r” to the level “–r+s”.

[0259] like Fig.17 As shown, correlated double sampling (CDS) can be performed by sampling the reference level once and the unknown signal level once. Correlated multiple sampling (CMS) can be performed by sampling the voltage level twice or more. Using correlated multiple sampling (CMS) can reduce noise, but the analog-to-digital conversion rate may be reduced. It should be noted that the noise reduction effect of correlated multiple sampling (CMS) is particularly effective for small signals. Therefore, the problem of reduced ADC rate can be offset by applying CMS only to small signals.

[0260] Fig.18FIG. 4 shows an exemplary operation of partially correlated multiple sampling (CMS). Fig.18 In the example shown, the reference level is sampled 4 times at points S1, S2, S3, and S4, and the result values ​​–r1, –r2, –r3, and –r4 are obtained, which are then added and stored. Therefore, immediately before the unknown signal measurement, the data represented in “Calc.Latch” is equal to the level “–r1–r2–r3–r4=–(r1+r2+r3+r4)”. The unknown signal level is sampled 4 times at points S5, S6, S7, and S8, and the result values ​​+s1, +s2, +s3, and +s4 are obtained, which are then added and stored. Therefore, immediately after the unknown signal is completed, the data represented in “Calc.Latch” is equal to the level “–r1–r2–r3–r4+s1+s2+s3+s4”. By repeatedly sampling the voltage level, the accuracy of the level measurement can be improved.

[0261] exist Fig.18 In the example shown, the reference level and the unknown signal level can be sampled evenly (sampling the same number of times). However, there may be Fig.19 In this case, the amount of charge stored in the photodiode (PD) is very large, and the difference between the reference level and the unknown signal level is large (the environment is very bright). Fig.19 In the example shown, only one of the four samples is successful for the unknown signal level (only S8). In this case, an unknown signal level (s4) can be added to the reference level (including 4 sample values) to obtain "–r1–r2–r3–r4+s4". However, this value is not suitable for measuring the difference between the reference level and the unknown signal level.

[0262] To deal with this problem, according to this embodiment, the number of failed samplings is counted, the unknown signal level of failed sampling is forced to be "0", and the unknown signal level of successful sampling is multiplied by a multiplier. The multiplier is equal to the "number of failed samplings" plus 1. Fig.19 It is represented as "increment i" in . Therefore, the difference is

[0263] “–r1–r2–r3–r4+0+0+0+4*(s4)”.

[0264] This allows known and unknown level measurements to be scaled evenly. Adding the appropriately scaled values ​​to the four reference levels will yield the appropriate difference values.

[0265] 5.3 Sunspot Correction

[0266] Correlated double sampling (CDS) has an advantage because it can reduce noise components. However, CDS may cause the sunspot phenomenon. In normal operation, when the image sensor receives strong light, the corresponding pixel indicates a bright value. In the case of the sunspot phenomenon, even if the image sensor receives very strong light, the corresponding pixel level is set to a "low value", so the pixel disadvantageously appears as a black spot.

[0267] When performing correlation double sampling (CDS), as shown in Figure 3A As described in pixel 311, first, when the transfer transistor Tr1 and the reset transistor Tr2 are in the OFF state, the selection transistor Tr4 is turned on, and the voltage level of the floating diffusion layer (FD) is measured as the reference level. However, when the sensor receives abnormally strong light, the charge of the photodiode (PD) can flow into the floating diffusion layer (FD) even if Tr1 is in the OFF state. In this case, the voltage level of the floating diffusion layer (FD) moves toward the lower limit of the output voltage range, and the voltage level actually becomes equivalent to the unknown signal level. Even if the difference between the unknown signal level and the voltage level of the floating diffusion layer (FD) in this case is measured, only the 0 level (0–0=0) can be obtained, and the appropriate difference cannot be obtained. Therefore, the sunspot phenomenon occurs.

[0268] To deal with this phenomenon, the image sensor according to this embodiment can use a clamping circuit to detect that the voltage level of the floating diffusion layer (FD) or the pixel source follower is near the lower limit of the output voltage range, and clamp the column voltage to a predetermined voltage, thereby detecting and correcting the sunspot phenomenon.

[0269] Specifically, when the output signal line (for example, D m ) is at the lower limit of the output voltage range due to the sunspot phenomenon, the clamp circuit detects this situation and pulls up the output signal line voltage to a predetermined voltage, and then performs an auto-zero operation (AZ switch is closed). After the auto-zero operation, the clamp circuit is turned off. Then, the voltage level of the pixel-side input port INN of the comparator 314 moves toward the lower limit of the INP operating voltage range (such as Fig. 20 In this case, since the comparator 314 does not output any normal output pulse, a normal reference level cannot be obtained, and thus the image sensor can detect that a sunspot phenomenon has occurred.

[0270] In this case, in this embodiment, the reference level is forcibly set to the clamp voltage level. When entering the unknown signal level sampling, the predetermined Gray code is forcibly set in the Gray code latch circuit 32. The predetermined Gray code can be a code corresponding to the full code of the ADC. In other words, although the reference level or the unknown signal level is not successfully sampled in the correlated double sampling (CDS), the readout circuit 313 can output the full code after the CDS cycle, thereby correcting the sunspot in the image (a strong bright environment can be forcibly set).

[0271] 6. Electronic devices

[0272] The embodiments described herein may be applied to various devices including mobile devices and stationary devices. Fig.21 An exemplary electronic device according to an embodiment is described. The electronic device may be a device that provides image acquisition functions and / or data connectivity for a user, a handheld device with wireless connection function, or other processing devices connected to a wireless modem (e.g., a digital camera, a SLR camera, a smart phone, etc.). Alternatively, the electronic device may be other smart devices with image acquisition functions and display functions (e.g., a wearable device, a tablet computer, a personal digital assistant (PDA), a drone, an aerial camera).

[0273] Fig.21 is a schematic diagram of an optional hardware structure of an electronic device 100 as an exemplary electronic device. Fig.10 The electronic device 100 may include components such as a radio frequency unit 110, a memory 120, an input unit 130, a display unit 140, an imaging device 101, an audio circuit 160, a speaker 161, a microphone 162, an earphone jack 163, a processor 170, an external interface 180 and a power supply 190.

[0274] The radio frequency (RF) unit 110 can be used to send and receive information or send and receive signals during the call process. Generally, the RF unit includes but is not limited to an antenna, an amplifier, a transceiver, a coupler, a low noise amplifier (LNA), a duplexer, etc. In addition, the radio frequency unit 110 can communicate with network devices and other devices through wireless communication. Wireless communication can use any communication standard or protocol.

[0275] The memory 120 may be used to store instructions and data. The memory 120 may mainly include an instruction storage area and a data storage area. The instruction storage area may store software such as an operating system, applications, and instructions. The data storage area may store images acquired by the imaging device 101, audio data input or output by the audio circuit 160, images displayed by the display unit 140, data used for the operation process executed by the processor 170, and various other transient or permanent data.

[0276] The input unit 130 can be used to receive input digital or character information in the electronic device 100. Specifically, the input unit 130 may include a touch screen 131 and other input devices 132. The touch screen 131 can collect the user's touch operation on the touch screen or near the touch screen, and drive the corresponding connection device according to a preset program. The touch screen 131 can detect the user's touch action on the touch screen, and convert the touch action into a touch signal, send the touch signal to the processor 170, and receive and execute the command sent by the processor 170. Other input devices 132 may include, but are not limited to, one or more of the following: a physical keyboard, function keys (such as volume control keys, power on / off keys), a trackball, a mouse, a joystick, etc.

[0277] The display unit 140 may be used to display information input by the user, information provided to the user, various menus of the electronic device 100, etc. In an embodiment, the display unit 140 is used to display an image acquired by the imaging device 101, wherein the image may include a preview image in certain shooting modes, an acquired image, or an image processed by a specific algorithm after shooting, etc.

[0278] The imaging device 101 is used to capture still images or moving images, and can be triggered to start by application instructions to realize the shooting function or the video recording function. The imaging device 101 may include components such as an imaging lens, a filter, and an image sensor. Specifically, the imaging device 101 according to the embodiment is an image sensor such as a CMOS image sensor. The image sensor may include a reference Figure 1 , Figure 3A The analog-to-digital converter shown in the figure. The light emitted or reflected by the object to be photographed enters the imaging lens and is gathered on the image sensor through the filter. The imaging lens is mainly used to gather the light emitted or reflected by the object to be photographed in the shooting field of view and to perform imaging. The filter is mainly used to filter out extra light waves in the light (for example, light waves other than visible light, such as infrared light). The image sensor is mainly used to perform photoelectric conversion on the received light signal, convert the light signal and light intensity change into an electrical signal, and input the electrical signal into the processor 170 for subsequent processing.

[0279] The audio circuit 160, the speaker 161, the microphone 162 and the headphone jack 163 can provide an audio interface between the user and the electronic device 100. The audio circuit 160 can send an electrical signal converted from the received audio data to the speaker 161, and the speaker 161 converts the electrical signal into a sound signal for output. Conversely, the microphone 162 is used to collect sound signals and can convert the collected sound signals into electrical signals. The audio circuit can also include a headphone jack 163, which is used to provide a connection interface between the audio circuit and the headphones.

[0280] The processor 170 is the control center of the electronic device 100 and is connected to various components of the electronic device 100 through various interfaces and signal lines. The processor 170 performs various functions of the electronic device 100, executes instructions stored in the memory 120, and calls data stored in the memory 120 to process the data. In some embodiments, the processor and the memory can be implemented on a single chip. In some embodiments, the processor and the memory can be implemented on separate chips.

[0281] The electronic device 100 further includes an external interface 180. The external interface 180 may be a standard micro USB interface or a multi-pin connector. The external interface may be used to connect the electronic device 100 to other devices for communication, or may be used to connect to a charger to charge the electronic device 100.

[0282] The electronic device 100 further includes a power source 190 (eg, a battery) for supplying power to each component. Preferably, the power source can be logically connected to the processor 170, so as to implement functions such as charging, discharging, and power consumption management through a power management system.

[0283] Those skilled in the art will understand that Fig.21 This is only an example of an electronic device and does not constitute any limitation on the embodiments. The electronic device may include more or fewer components than shown in the figure, or combine some components, or have different components.

[0284] The partial division of the components in this specification is only for the logical function division, which gives priority to the convenience of explanation. It is understandable that some or all of the divided components can be integrated into a physical entity or physically separated in actual implementation. For example, each of the above-mentioned components can be a separate processing element or integrated on a chip of an electronic device. Alternatively, the processing element can be stored in a storage element of a controller in the form of a program code, and various functions can be called and executed as needed. In addition, the processing element can be integrated together or implemented independently. The processing element can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step in the above method or the above-mentioned elements can be implemented by a hardware integrated logic circuit in the processing element or by instructions in the form of software.

[0285] Those skilled in the art will appreciate that the embodiments of the present invention may be provided as methods, devices, storage media or computer programs. Therefore, the present invention may be implemented in the form of pure hardware embodiments or in the form of a combination of software and hardware embodiments.

[0286] The method, device, storage medium and computer program related to the embodiments of the present invention are described with reference to the flowcharts and / or block diagrams. It should be understood that the computer program instructions can be used to implement each process and / or each box in the flowcharts and / or block diagrams. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or any other programmable data processing device so that the executed instructions produce the functions described with reference to the embodiments.

[0287] These computer program instructions may be stored in an appropriate storage medium or transmitted on a transmission medium. These computer program instructions may be loaded onto a computer or other programmable data processing device to enable the computer to perform a series of operations, thereby generating the functions described in the reference embodiments.

[0288] Although the embodiments of the present invention have been described, those skilled in the art may make changes and modifications to these embodiments. Therefore, the following claims should be interpreted as including the embodiments within the scope of the present invention and all changes and modifications thereof.

[0289] Reference Symbols List

[0290] 10.300 Image Sensor

[0291] 11,311 pixels

[0292] 12, 312 line decoding circuit

[0293] 13.313 Readout circuit

[0294] 14.314 Comparator

[0295] 320 processor

[0296] Related technical documents

[0297] Patent Document 1: International Patent Publication No. WO2018 / 123609

[0298] Patent Document 2: U.S. Patent No. 9380246

[0299] Patent Document 3: International Patent Publication No. WO2018 / 123609

[0300] Patent Document 4: Japanese Patent Publication No. 2011-60046

[0301] Patent Document 5: Japanese Patent Publication No. 2005-57612

Claims

1. A logic circuit (34), characterized in that: For operation in operation modes including a code conversion mode and an addition mode, the logic circuit comprises: a first logic circuit (LC1) outputting a first operation result, wherein the first operation result is a result of performing an exclusive-OR operation on input bits; Output the second operation result (B n / X n ) of the second logic circuit (LC2), the second operation result (B n / X n ) is a result of performing an XOR operation on input bits including the first operation result; a selector (SEL) for operating according to said operating mode; (i) wherein, in the code conversion mode, the selector (SEL) outputs the second operation result (B n ), the input bit of the first logic circuit (LC1) includes a bit (G in the Gray code representation of the second addend n+1 ) and the bit in the binary code representation (B n+2 ), the input bits of the second logic circuit (LC2) also include bits (G n ); (ii) wherein, in the addition mode, the selector (SEL) outputs a carry bit (C) when the first addend (A) and the second addend (B) are added. n ), the input bits of the first logic circuit (LC1) include the bits of the first addend (A n ) and below the carry bit (C n ) of the digits (C n–1 ), the input bits of the second logic circuit (LC2) include the bits (B n ).

2. A cascade logic circuit, characterized in that: The method comprises a plurality of cascade-connected logic circuits, each logic circuit comprising the logic circuit (34) according to claim 1, wherein the second operation result of the logic circuit in the first stage or the carry bit output from the logic circuit in the first stage is selectively connected as a carry bit to the logic circuit in the second stage according to the mode setting of the code conversion mode or the addition mode.

3. The cascade logic circuit according to claim 2, characterized in that: It also includes a first latch circuit, which stores (i) the lowest output bit among the bits converted at one time in the code conversion mode, or (ii) the carry bit in the operation of the highest bit in the operation performed at one time in the addition mode according to the operation mode, wherein the output of the first latch is provided to the logic circuit in the first stage as a carry bit input.

4. The cascade logic circuit according to claim 3, characterized in that: The first latch circuit stores the carry bit in the operation of (i) the lowest output bit in the code conversion mode and (ii) the highest bit in the addition mode as two types of data according to the operation mode, wherein one of the two types of data is provided to the logic circuit in the first stage as the carry bit input.

5. An arithmetic logic unit (ALU), characterized in that: include: The logic circuit (34) according to claim 1; A second latch circuit (35) stores the output of the selector (SEL).

6. The arithmetic logic circuit (ALU) according to claim 5, characterized in that: Before starting the addition mode, the second latch circuit (35) acquires and stores bits in the binary code representation of the second addend (B) through the code conversion mode.

7. The arithmetic logic circuit (ALU) according to claim 6, characterized in that: In the code conversion mode, it also has: A function wherein, in the code conversion mode, the most significant bit (MSB) is selectively set to a fixed value of 1 to obtain a 1's complement in the binary code representation; A function wherein in the addition mode, a carry bit in the operation of the least significant bit (LSB) is set to 1 so as to obtain a 2's complement for addition.

8. A Gray code sampling unit, characterized in that: include: a fourth latch circuit (32) for storing a Gray code; The arithmetic logic operation circuit (ALU, 33) according to claim 6, converting the Gray code obtained from the fourth latch circuit (32) into a binary code; The third latch circuit (36) stores the first addend (A) before the addition mode starts, and stores an addition result (X) of the first addend (A) and the second addend (B) when the addition mode ends.

9. The Gray code sampling unit according to claim 8, characterized in that: When the bit in the binary code representation of the first addend is stored in the third latch (36), the following operations are repeatedly performed: in the code conversion mode, providing the bits in the Gray code representation of the second addend (B) to the first logic circuit (LC1) and the second logic circuit (LC2), At the end of the addition mode, the first addend (A n ) and the second number to be added (B n ) of the addition result (X n ) is stored in the third latch circuit (36); The addition result stored in the third latch circuit (36) corresponds to a result of Correlated Double Sampling (CDS) or Correlated Multiple Sampling (CMS).

10. The Gray code sampling unit according to claim 9, characterized in that: If the Gray code is not sampled within a predetermined sampling period in multiple sampling operations for unknown levels in the CMS, then in the code conversion mode, the Gray code bit corresponding to the 0 level is input into the first logic circuit, and the second addend weighted by the number of occurrences of the 0 level input event is used for addition.

11. The Gray code sampling unit according to claim 9, characterized in that: If the Gray code is not sampled within a predetermined sampling period in the sampling operation for the reference level in the CDS or the CMS, a predetermined Gray code bit is input into the first logic circuit in the code conversion mode.

12. A single slope analog-to-digital (AD) conversion circuit, characterized in that: The Gray code sampling unit according to claim 8 is included, wherein the single slope AD conversion circuit obtains a digital output from a Gray code counter.

13. The single slope analog-to-digital (AD) conversion circuit according to claim 12, characterized in that: If the amplitude of the signal level is not within a predetermined level range in multiple sampling operations for unknown levels in the CMS, then in the code conversion mode, the Gray code bit corresponding to the 0 level is input into the first logic circuit, and the second addend weighted by the number of occurrences of the 0 level input event is used for addition.

14. The single-slope analog-to-digital (AD) conversion circuit according to claim 12, characterized in that: If the amplitude of the reference level for measuring the signal level is not within a predetermined level range in the sampling operation for the reference level in the CDS or CMS, a predetermined Gray code bit is input into the first logic circuit in the code conversion mode.

15. A parallel AD conversion circuit, characterized in that: A plurality of AD converters are included in parallel, wherein each AD converter includes the single-slope analog-to-digital (AD) conversion circuit according to claim 12, and the plurality of AD converters share the Gray code counter.

16. A CMOS image sensor, characterized in that: Includes the parallel AD conversion circuit according to claim 15.

17. A method of operation in a logic circuit, characterized in that: The logic circuit is configured to operate in an operation mode including a code conversion mode and an addition mode, and the method comprises: In the code conversion mode, The first logic circuit outputs the first operation result (B n+1 ), the first operation result (B n+1 ) is the result of an XOR operation on the input bits, wherein the input bits include the bits (G n+1 ) and the bit in the binary code representation (B n+2 ), The second logic circuit outputs the second operation result (B n ), the second operation result (B n ) is the result of performing an XOR operation on input bits, wherein the input bits include the first operation result and the bits in the Gray code representation of the second addend (G n ); In the addition mode, The first logic circuit outputs a third operation result, wherein the third operation result is a result of performing an XOR operation on input bits, wherein the input bits include bits of the first addend (A n ) and below the carry bit (C n ) of the digits (C n–1 ), The second logic circuit outputs a fourth operation result (X n ), the fourth operation result (X n ) is the result of performing an XOR operation on input bits, wherein the input bits include the third operation result and the bits of the second addend (B n ).

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