Method, host, electronic device and computer device for adjusting priority of submission queue

Abstract

The present disclosure provides a submission queue priority adjustment method, a host, an electronic device and a computer device, and relates to the technical field of data storage. The method comprises the following steps: obtaining the delay duration of a plurality of submission queues, the delay duration of the submission queue being determined by the average value of the completion duration of a plurality of commands in the submission queue, the completion duration being the difference between the execution completion time of the command and the time when the command is added to the submission queue; determining the delay score of the submission queue based on the delay duration of the submission queue; determining the target submission queue among the plurality of submission queues based on the delay score of the submission queue, and adjusting the priority of the target submission queue; and sending an instruction, the instruction being used to notify the priority adjustment result of the target submission queue. The longer the delay duration of the submission queue is, the longer the time for the command in the submission queue to wait to be executed is. Therefore, the priority of the submission queue is adjusted by the delay score determined by the delay duration, thereby reducing the risk that the command cannot be executed for a long time.

Description

Technical Field

[0001] This disclosure belongs to the field of data storage technology, and in particular relates to a method for adjusting the priority of a submission queue, a host, an electronic device, and a computer device. Background Technology

[0002] The Non-volatile Memory Express (NVMe) specification is a communication protocol and interface standard for connecting a host (such as a computer) and a non-volatile storage device (such as a solid-state drive). It aims to optimize the read and write performance of non-volatile storage devices, achieving higher data transfer rates and lower access latency. Summary of the Invention

[0003] Embodiments of this disclosure provide a method for adjusting the priority of a submission queue, a host, an electronic device, and a computer device to reduce the risk that commands cannot be executed for a long time.

[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0005] Firstly, a method for adjusting the priority of a submission queue is provided. The method includes: obtaining the delay duration of multiple submission queues, wherein the delay duration of a submission queue is determined by the average completion duration of multiple commands in the submission queue, and the completion duration is the difference between the execution completion time of the command and the time when the command is added to the submission queue; determining the delay score of the submission queue based on the delay duration of the submission queue; determining a target submission queue among the multiple submission queues based on the delay score of the submission queue, and adjusting the priority of the target submission queue; and sending an instruction to notify the target submission queue of the priority adjustment result.

[0006] The submission queue priority adjustment method disclosed herein calculates a latency score for each submission queue based on its latency duration. Then, based on the latency score, it identifies the target submission queue whose priority needs adjustment. Since the latency duration of a submission queue reflects, to some extent, the time required for the execution of a single command within that queue to complete, a longer latency duration indicates a longer waiting time for commands to be executed. Therefore, the latency score calculated from the latency duration of each submission queue can assess the urgency of each queue, thereby adjusting its priority and issuing an instruction to notify the target submission queue of the priority adjustment result. This reduces the risk of commands remaining unexecuted for extended periods due to unreasonable command allocation by the host.

[0007] In some embodiments, the priority of a submission queue includes an urgent priority and a weighted priority, with the urgent priority being higher than the weighted priority. Based on the latency score of the submission queues, a target submission queue is determined from multiple submission queues, and the priority of the target submission queue is adjusted. This includes: determining the submission queue with the highest latency score as the first target submission queue and adjusting its priority to an urgent priority; and / or, determining the submission queue with the lowest latency score as the second target submission queue and adjusting its priority to a weighted priority. The higher the latency score of a submission queue, the longer the commands in that queue will wait to be executed, meaning there is a greater risk that the commands in that queue will not be executed for an extended period. Therefore, by adjusting the priority of the first target submission queue with the highest latency score to an urgent priority, commands in the first target submission queue are processed first; and by adjusting the priority of the second target submission queue with the lowest latency score to a weighted priority, multiple urgent priority submission queues are avoided from being polled, preventing commands in the first target submission queue from being executed in a timely manner, thereby reducing the risk of commands not being executed for an extended period.

[0008] In some embodiments, a target submission queue is determined from multiple submission queues based on the latency score of the submission queue, and the priority of the target submission queue is adjusted. This includes: determining a priority score for the submission queue based on its latency score and the number of commands in the submission queue; determining the target submission queue from multiple submission queues based on its priority score, and adjusting the priority of the target submission queue. For submission queues with a large number of commands, commands at the end of the submission queue may also be at risk of not being executed for a long time. Therefore, determining the priority score of the submission queue based on the number of commands in the submission queue and its latency score, and then determining the target submission queue based on the priority score, can reduce the risk that commands at the end of the submission queue may not be executed for a long time.

[0009] In some embodiments, the priority of a submission queue includes an urgent priority and a weighted priority, with the urgent priority being higher than the weighted priority. Based on the priority scores of the submission queues, a target submission queue is determined from multiple submission queues, and its priority is adjusted. This includes: determining the submission queue with the highest priority score as the first target submission queue and adjusting its priority to an urgent priority; and / or, determining the submission queue with the lowest priority score as the second target submission queue and adjusting its priority to a weighted priority. In this disclosure, the more commands in a submission queue, the higher its latency score, and consequently, the higher its priority score. Therefore, adjusting the priority of the first target submission queue with the highest priority score to an urgent priority prioritizes the commands in that queue; adjusting the priority of the second target submission queue with the lowest priority score to a weighted priority avoids polling multiple urgent priority submission queues, preventing commands in the first target submission queue from being executed in a timely manner, thereby reducing the risk that commands at later stages of the process may not be executed for an extended period.

[0010] In some embodiments, the method further includes: determining a target submission queue among multiple submission queues based on the priority score and the latency score of the submission queues, and adjusting the priority of the target submission queue. Adjusting the priority of submission queues by combining the priority score and latency score of the submission queues makes the priority adjustment more accurate to some extent.

[0011] In some embodiments, the priority of a commit queue includes an urgent priority and a weighted priority, with the urgent priority being higher than the weighted priority. Based on the priority score and latency score of each commit queue, a target commit queue is determined from multiple commit queues, and its priority is adjusted. This includes: among commit queues with a latency score greater than a first threshold, determining the commit queue with the highest priority score as the first target commit queue and adjusting its priority to urgent priority; and / or, among commit queues with a latency score less than a second threshold, determining the commit queue with the lowest priority score as the second target commit queue and adjusting its priority to weighted priority; where the second threshold is less than the first threshold. This approach, to some extent, avoids inaccurate priority adjustments caused by a large number of commands in the commit queue resulting in a high priority score.

[0012] In some embodiments, the priority score of the submission queue is determined by the product of the latency score of the submission queue and the number of commands in the submission queue.

[0013] In some embodiments, a latency score for a submission queue is determined based on its latency duration; this includes: calculating the average latency μ of multiple submission queues; calculating the standard deviation σ of the latency durations of multiple submission queues; and applying a mean normalization formula: Determine the latency score for the submission queue; where lat i Let be the delay duration of the i-th submission queue, and let be the score. i Let be the delay score of the i-th submission queue. This normalizes the feature values ​​to the same dimension, eliminating the problem of unbalanced weighting.

[0014] Secondly, a host is provided, including a host processor and an interface circuit for coupling a memory system. The host processor is configured to: acquire the latency duration of multiple submission queues, the latency duration of which is determined by the average completion duration of multiple commands in the submission queues, the completion duration being the difference between the execution completion time of a command and the time when the command is added to the submission queue; determine the latency score of the submission queues based on their latency durations; determine a target submission queue among the multiple submission queues based on their latency scores, and adjust the priority of the target submission queue; the interface circuit is configured to: send an instruction to notify the target submission queue of the priority adjustment result.

[0015] In some embodiments, the priority of the commit queue includes an urgent priority and a weighted priority, with the urgent priority being higher than the weighted priority. The host processor determines a target commit queue from among multiple commit queues based on the latency scores of the commit queues and adjusts the priority of the target commit queue. Specifically, this is configured to: determine the commit queue with the highest latency score as the first target commit queue among the multiple commit queues and adjust the priority of the first target commit queue to the urgent priority; and / or, determine the commit queue with the lowest latency score as the second target commit queue among the multiple commit queues and adjust the priority of the second target commit queue to the weighted priority.

[0016] In some embodiments, the host processor determines a target commit queue from multiple commit queues based on the latency score of the commit queues and adjusts the priority of the target commit queue. Specifically, this is configured to: determine the priority score of the commit queue based on the latency score of the commit queue and the number of commands in the commit queue; determine the target commit queue from multiple commit queues based on the priority score of the commit queues and adjust the priority of the target commit queue.

[0017] In some embodiments, the priority of the commit queue includes an urgent priority and a weighted priority, with the urgent priority being higher than the weighted priority. The host processor determines a target commit queue from among multiple commit queues based on the priority scores of the commit queues and adjusts the priority of the target commit queue. Specifically, it is configured to: determine the commit queue with the highest priority score as the first target commit queue from among the multiple commit queues and adjust the priority of the first target commit queue to the urgent priority; and / or, determine the commit queue with the lowest priority score as the second target commit queue from among the multiple commit queues and adjust the priority of the second target commit queue to the weighted priority.

[0018] In some embodiments, the host processor is further configured to: determine a target submission queue among multiple submission queues based on the priority score and the latency score of the submission queues, and adjust the priority of the target submission queue.

[0019] In some embodiments, the priority of the commit queue includes an urgent priority and a weighted priority, with the urgent priority being higher than the weighted priority. The host processor determines a target commit queue from among multiple commit queues based on the priority score and the latency score of the commit queue, and adjusts the priority of the target commit queue. Specifically, it is configured to: determine the commit queue with the largest priority score as the first target commit queue among the commit queues whose latency score is greater than a first threshold, and adjust the priority of the first target commit queue to an urgent priority; and / or, determine the commit queue with the smallest priority score as the second target commit queue among the commit queues whose latency score is less than a second threshold, where the second threshold is less than the first threshold, and adjust the priority of the second target commit queue to a weighted priority.

[0020] In some embodiments, the priority score of the submission queue is determined by the product of the latency score of the submission queue and the number of commands in the submission queue.

[0021] In some embodiments, the host processor determines the latency score of a submission queue based on the latency duration of the submission queue; specifically configured to: calculate the average latency μ of multiple submission queues; calculate the standard deviation σ of the latency duration of multiple submission queues; and apply the mean normalization formula: Determine the latency score for the submission queue; where lat i Let be the delay duration of the i-th submission queue, and let be the score. i Let be the delay score for the i-th submission queue.

[0022] Thirdly, an electronic device is provided, including a host and a memory system. The host includes a first interface, and the memory system includes a second interface. The host and the memory system are coupled through the first interface and the second interface, wherein: the first interface is configured to send a first instruction for notifying the adjustment result of the priority of a target submission queue in a plurality of submission queues; and the second interface is configured to receive the first instruction and send a second instruction to the host based on the received first instruction.

[0023] Fourthly, a computer device is provided, including a processor and a readable storage medium coupled to the processor, the readable storage medium storing executable instructions that, when executed by the processor, enable the implementation of any of the methods in the first aspect above.

[0024] Fifthly, a computer-readable storage medium is provided, which stores computer-executable instructions; when executed, the computer-executable instructions are able to implement any of the methods in the first aspect above. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0026] Figure 1 A schematic diagram of the polling arbitration mechanism provided in the embodiments of this disclosure;

[0027] Figure 2 A schematic diagram of a weighted round-robin arbitration mechanism with urgent priority provided in an embodiment of this disclosure;

[0028] Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure;

[0029] Figure 4 This is a schematic diagram of the structure of NAND flash memory provided in an embodiment of this disclosure;

[0030] Figure 5 A flowchart illustrating the submission queue priority adjustment method provided in this embodiment of the disclosure;

[0031] Figure 6 This is a schematic diagram of the specific process of S2 provided in the embodiments of this disclosure;

[0032] Figure 7A schematic diagram of one specific process of S3 provided in an embodiment of this disclosure;

[0033] Figure 8 This is another specific flowchart of S2 provided in an embodiment of the present disclosure.

[0034] Reference numerals: 100, electronic device; 110, host; 111, host processor; 112, host memory; 113, bus; 114, first interface; 120, memory system; 121, memory controller; 122, memory; 123, second interface; 210, die; 220, plane; 230, block; 240, page. Detailed Implementation

[0035] The following will combine Figures 1-8 The technical solutions in some embodiments of this disclosure are clearly and completely described. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments provided in this disclosure, all other embodiments obtained by those skilled in the art are within the scope of protection of this disclosure.

[0036] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplarily," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, materials, or characteristics may be included in any suitable manner in any one or more embodiments or examples.

[0037] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0038] In describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, in describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical or electrical contact; in this case, "coupled" can also be described as "connected." Furthermore, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0039] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0040] Currently, the main data transfer protocol specifications between storage systems and hosts include the Advanced Host Controller Interface (AHCI) specification and the Non-volatile Memory Express (NVMe) specification. AHCI uses a single-queue mode; that is, data exchange between the host and the storage system occurs through a single queue. Hard disk drives (HDDs) and early solid-state drives (SSDs) generally use the AHCI protocol.

[0041] Unlike HDDs, which are characterized by sequential read / write operations, SSDs can read data from multiple different locations simultaneously, exhibiting high concurrency. Therefore, the single-queue mode of the AHCI protocol becomes a bottleneck limiting SSD concurrency. In contrast, the NVMe protocol supports multiple queues (up to 65,536), fully leveraging the parallel storage advantages of SSDs and significantly improving their read / write performance. In the NVMe protocol, the host can place administrative (admin) commands primarily used to manage the storage system in the admin submission queue (ASQ), and NVM commands primarily responsible for data transfer in the submission queue (SQ). For example, the host can place a command in the submission queue and then use a doorbell register to notify the memory system to retrieve the command from the submission queue. After the memory system completes the execution of the command, it writes the execution result to the completion queue (CQ) corresponding to the submission queue and triggers an interrupt to notify the host that the execution of the command has been completed. The host reviews the execution result in the completion queue and then notifies the memory system that the execution result in the completion queue has been reviewed, and the command execution is complete.

[0042] Memory systems need to determine the order in which commands are retrieved from the management commit queue and multiple commit queues according to certain rules. These rules are called multi-queue arbitration mechanisms. Currently, the NVMe protocol mainly defines two arbitration mechanisms: round-robin arbitration (RR) and weighted round-robin arbitration (WRR) with urgent priority.

[0043] Polling arbitration mechanism, such as Figure 1 As shown, the arbitration mechanism polls the management commit queue and multiple commit queues, and sequentially retrieves a certain number of commands from each commit queue and executes them. The management commit queue and multiple commit queues have the same priority.

[0044] Weighted round-robin arbitration mechanism with urgency priority, such as Figure 2 As illustrated, the weighted round-robin arbitration mechanism with urgent priority defines three strict priorities. These are the admin priority, the urgent priority, and the weighted priority (WWR class), with admin priority being higher than urgent priority, which in turn is higher than weighted priority. That is, the memory system always retrieves and executes commands from the admin commit queue first, then from the commit queues with urgent priority, and finally from the commit queues with weighted priority. In some embodiments, the admin commit queue always holds the highest admin priority, and the host only configures the absolute priority of the commit queues; for example, the host can configure the absolute priority of a commit queue as either urgent or weighted priority. A round-robin arbitration mechanism is used between admin commit queues and between commit queues with the same absolute priority.

[0045] The lowest absolute priority weighted priority can include high, medium, and low priorities. These three priority queues are arbitrated using a weighted round-robin arbitration mechanism. The host can configure the weights of these three priorities, representing the number of commands retrieved from the commit queue each time.

[0046] In some embodiments, the polling arbitration mechanism reads commands from each submission queue sequentially without priority, and all submission queues are scheduled with the same probability. This fails to differentiate between latency-sensitive critical and non-critical tasks, leading to delays in the execution of critical tasks. While weighted polling arbitration with urgency priority can ensure sufficient scheduling of commands in high-priority submission queues, there is no fair agreement between priorities. Commands in low-priority (e.g., low-priority in a weighted priority system) submission queues may also wait for extended periods, impacting command execution and response. When the waiting time reaches a certain threshold, even if a command is completed, it may no longer be of practical significance.

[0047] This disclosure periodically calculates the latency of a submission queue by comparing the completion time of multiple commands in the queue with the time the command was added to the queue. A longer latency indicates a higher risk that commands in the queue may not be executed for an extended period, thus increasing the likelihood of command timeouts and other system crashes. Therefore, this disclosure treats submission queues with relatively long latency as more urgent, and the host changes the priority of these queues and notifies the memory system to reduce the risk of commands in the queue not being executed for an extended period.

[0048] like Figure 3 As shown, this disclosure provides an electronic device 100, which includes a host 110 and a memory system 120. The electronic device 100 can be a terminal device such as a mobile phone, television, monitor, or tablet computer; or a smart wearable device such as a smartwatch, smart bracelet, or virtual reality (VR) glasses; or a communication device such as a server or base station; or a control device such as an in-vehicle computer. This disclosure does not impose any special limitations on the specific form of the electronic device 100.

[0049] Specifically, the host 110 may include a host processor 111, host memory 112, a bus 113, and interface circuitry. The host processor 111, interface circuitry, and host memory 112 are coupled to each other via the bus 113. The interface circuitry includes a first interface 114. The memory system 120 may be an NVMe SSD. The memory system 120 may include a storage controller 121, memory 122, and a second interface 123. The host 110 and the memory system 120 are coupled via the first interface 114 and the second interface 123.

[0050] The host processor 111 or memory controller 121 described above can be a chip. For example, it can be a field programmable gate array (FPGA), application specific integrated circuit (ASIC), system on chip (SoC), central processor (CPU), digital signal processor (DSP), micro controller unit (MCU), programmable logic device (PLD), or other integrated chip.

[0051] The host memory 112 can be a volatile storage medium, such as random access memory (RAM). RAM can include various forms, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM), etc. This disclosure does not limit the types of RAM.

[0052] The memory 122 can be flash memory (such as NAND flash memory or NOR flash memory). Flash memory eliminates the mechanical components of traditional hard disk drives, such as read / write heads, disk spindles, and motors. Without the motor rotation process, it avoids mechanical failures and is resistant to collisions, impacts, and vibrations. Therefore, flash memory has absolute advantages over hard disk drives in terms of performance, reliability, energy consumption, and portability, and is widely used in civilian, automotive, industrial control, power, medical, aerospace, and navigation equipment fields. This disclosure uses NAND flash memory as an example for memory 122, but it is not intended to be limited to this. In this case, the storage controller 121 can control the memory 122 through an open NAND flash interface (ONFI) or a toggle interface. Figure 4The structure of NAND flash memory is shown. NAND flash memory includes multiple dies 210, each die 210 includes multiple planes 220, each plane 220 includes multiple blocks 230, and each block includes multiple pages 240.

[0053] Specifically, the host processor 111 in the aforementioned host 110 can execute the submission queue priority adjustment method.

[0054] like Figure 5 As shown, the method includes steps S1-S4, as follows:

[0055] S1, The host obtains the latency of multiple submission queues.

[0056] Alternatively, host 110 obtains the latency duration of each of multiple commit queues. Host 110 can obtain the latency duration of multiple commit queues according to preset time rules; for example, obtaining it every ten minutes. Figure 3 As shown, multiple submission queues and corresponding completion queues are created in shared memory (e.g., host memory 112) between host 110 and memory system 120, and the doorbell register is located in the controller at the memory system 120. The latency of each submission queue is determined by the average completion time of multiple commands in that submission queue. As described above, host 110 can add one or more prepared commands to the submission queue; then, it uses the doorbell register to inform memory system 120 to retrieve the commands from the submission queue to the controller buffer; memory system 120 can retrieve one or more commands for execution. Regardless of whether the command execution is successful or not, the execution result of the command is always written to the completion queue, and an interrupt is triggered to notify host 110 that the command execution has been completed; host 110 reviews the execution result on the completion queue, and then notifies memory system that the execution result on the completion queue has been reviewed, and the command execution is complete. It can be understood that the completion time of a command is equal to the difference between the time when the command is completed and the time when the command is added to the submission queue. In this embodiment of the present disclosure, the latency of each submission queue can be equal to the average completion time of multiple commands in that submission queue.

[0057] S2. Based on the delay duration of the submission queue, the host determines the delay score of the submission queue.

[0058] Alternatively, host 110 determines the latency score for each submission queue based on the latency duration of each submission queue. For example... Figure 6 As shown, step S2 may include sub-steps S201-S203, as follows:

[0059] S201. Calculate the average delay duration μ of multiple submission queues.

[0060] In some embodiments, the average latency μ of multiple submission queues can be expressed by the formula: The calculation shows that, where n is the number of submission queues, lat i Let be the delay duration of the i-th submission queue out of n submission queues; that is, the average completion time of multiple commands in that submission queue.

[0061] S202. Calculate the standard deviation σ of the delay duration of multiple submission queues.

[0062] Specifically, the standard deviation σ of the latency of multiple submission queues can be expressed by the formula... The calculation yielded the result.

[0063] S203. According to the mean normalization (also known as z-score normalization) formula: Determine the delay score for the submission queue.

[0064] Among them, scor i e is the delay score of the i-th submission queue out of n submission queues. It should be understood that the delay score can also be calculated using other data standardization methods, including but not limited to linear normalization (also known as min-max normalization), which will not be elaborated here.

[0065] S3. Based on the latency score of the commit queue, the host determines the target commit queue from multiple commit queues and adjusts the priority of the target commit queue.

[0066] Specifically, the higher the latency score of a submission queue, the longer the commands in that queue will wait to be executed. In other words, the risk of commands in that queue not being executed for an extended period is greater. Therefore, among multiple submission queues, the queue with the highest latency score is designated as the first target submission queue, and its priority is adjusted to urgent priority to prioritize the processing of commands in the first target submission queue. And / or, among multiple submission queues, the queue with the lowest latency score is designated as the second target submission queue, and its priority is adjusted to a weighted priority. For example, the priority of the second target submission queue can be adjusted to a high priority within the weighted priority range to avoid polling multiple urgent priority submission queues, which could prevent commands in the first target submission queue from being executed in a timely manner. This reduces the risk of commands not being executed for an extended period.

[0067] In some embodiments, for submission queues with low priority and a large number of commands, commands at the end of the submission queue also risk not being executed for a long time. Therefore, as Figure 7 As shown, step S3 may include sub-steps S311-S312, as follows:

[0068] S311. Based on the latency score of the commit queue and the number of commands in the commit queue, the host determines the priority score of the commit queue.

[0069] Specifically, the priority score of the i-th commit queue out of n commit queues. i The delay score of the submission queue i The number of commands in the submission queue, cmd_num i The product determines the priority score of the i-th commit queue out of n commit queues. i From the formula priority i =score i ×cmd_num i The calculation yielded the result.

[0070] S312. Based on the priority score of the commit queue, the host determines the target commit queue from multiple commit queues and adjusts the priority of the target commit queue.

[0071] Specifically, among multiple submission queues, the submission queue with the highest priority score is determined as the first target submission queue, and its priority is adjusted to urgent priority; and / or, among multiple submission queues, the submission queue with the lowest priority score is determined as the second target submission queue, and its priority is adjusted to weighted priority.

[0072] For commit queues containing a large number of commands, commands later in the queue may also face the risk of not being executed for an extended period. Compared to... Figure 6 The method shown, Figure 7 The provided method determines the priority score of the submission queue based on the number of commands in the queue and the latency score. This priority score is then used to determine and adjust the priority of the target submission queue. This reduces the risk of commands later in the submission queue of a large number of commands failing to execute for an extended period.

[0073] like Figure 8 As shown, in some embodiments, step S3 may further include sub-steps S321-322; wherein, sub-step S321 is the same as sub-step S311, and will not be described again in this disclosure.

[0074] S322. Based on the priority score and latency score of the commit queue, the host determines the target commit queue from multiple commit queues and adjusts the priority of the target commit queue.

[0075] Specifically, among the submission queues whose delay score is greater than the first threshold, the submission queue with the highest priority score is determined as the first target submission queue, and its priority is adjusted to urgent priority; and / or, among the submission queues whose delay score is less than the second threshold, the submission queue with the lowest priority score is determined as the second target submission queue, and its priority is adjusted to weighted priority; the second threshold is less than the first threshold.

[0076] The first and second thresholds can be set based on historical experience; for example, a delay score greater than or equal to 3 is considered a threshold. i Submissions with a latency score of ≥3 or higher and the highest priority score are prioritized as urgent. Similarly, submissions with a latency score less than or equal to -3 are prioritized as urgent. i The priority of the submission queue with the lowest priority score (≤-3) is adjusted to a weighted priority.

[0077] For a commit queue with a large number of commands but a low latency score, the execution time of a single command in the queue is relatively short, and commands can be executed quickly even if the queue is full. However, because the number of commands in the queue is too large, the priority score of the commit queue is also high. Adjusting the priority of the commit queue solely based on its priority score may lead to inaccurate priority adjustments. Therefore, compared to... Figure 7 The method shown, Figure 8 The proposed method combines the priority score and latency score of the commit queue to adjust the priority of the commit queue. This can, to some extent, avoid inaccurate priority adjustment caused by a large priority score due to an excessive number of commands in the commit queue.

[0078] It should be understood that if the priority of the first target submission queue determined by host 110 is an urgent priority, then host 110 will maintain the priority of the first target submission queue as an urgent priority. Alternatively, if the priority of the first target submission queue determined by host 110 is an urgent priority, then host 110 will not adjust the priority of the first target submission queue. Similarly, if the priority of the second target submission queue determined by host 110 is a weighted priority, then host 110 will maintain the priority of the second target submission queue as a weighted priority (for example, if the priority of the second target submission queue is a high priority among the weighted priorities, then host 110 will maintain the priority of the second target submission queue as a high priority among the weighted priorities). Alternatively, if the priority of the second target submission queue determined by host 110 is an urgent priority, then host 110 will not adjust the priority of the second target submission queue.

[0079] S4. The host sends instructions to the memory system.

[0080] Specifically, the host processor 111 of host 110 controls the first interface 114 to send a first instruction to the second interface 123 of memory system 120. The first instruction is used to notify memory system 120 of the adjustment result of the priority of the target submission queue among multiple submission queues. After receiving the first instruction through the second interface 123, memory system 120 sends a second instruction to the first interface 114 of host 110 through the second interface 123. The second instruction is used to feedback to host 110 that memory system 120 has received the first instruction.

[0081] After host 110 adjusts the priorities of the submission queues, memory system 120, through second interface 123, retrieves commands from multiple submission queues for execution based on a weighted round-robin arbitration mechanism with urgent priority, according to the adjusted priorities. Furthermore, after memory system 120 completes command execution, it can also write the command execution result to the completion queue through second interface 123 and notify host 110 that command execution has been completed. Memory system 120 also receives notification through second interface 123 that the execution result in the completion queue has been reviewed by host 110.

[0082] This disclosure also provides a computer-readable storage medium storing computer-executable instructions; when executed, these computer-executable instructions can implement the various steps in the above method embodiments, such as performing... Figures 5-8 The method shown.

[0083] This disclosure provides a computer device including a processor and a readable storage medium coupled to the processor. The readable storage medium stores executable instructions, which, when executed by the processor, can implement the various steps in the above method embodiments, such as executing... Figures 5-8 The method shown.

[0084] This disclosure provides a method, host, electronic device, and computer device for adjusting the priority of a submission queue. The method uses a latency score calculated from the latency duration of the submission queue to adjust the priority of the submission queue and issues an instruction to notify the target submission queue of the priority adjustment result. Since the latency duration of a submission queue can reflect, to some extent, the time required for the execution of a single command in the queue, adjusting the priority of the submission queue based on the latency score calculated from the latency duration can reduce the risk of commands not being executed for extended periods due to unreasonable command allocation by the host.

[0085] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the descriptions of each embodiment in the above embodiments have different focuses. For parts not described in detail in a certain embodiment, refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0086] It should be understood that in the various embodiments of this disclosure, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0087] Those skilled in the art will recognize that the modules and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0088] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for adjusting the priority of a submission queue, characterized in that, The priority of the submission queue includes an urgent priority and a weighted priority, wherein the urgent priority is higher than the weighted priority, and the method includes: The delay duration of multiple submission queues is obtained. The delay duration of the submission queue is determined by the average completion duration of multiple commands in the submission queue. The completion duration is the difference between the execution completion time of the command and the time when the command is added to the submission queue. The delay score of the submission queue is determined based on the delay duration of the submission queue and the delay duration of the multiple submission queues; The priority score of the submission queue is determined based on the latency score of the submission queue and the number of commands in the submission queue; Among the submission queues whose delay scores are greater than a first threshold, the submission queue with the highest priority score is determined as the first target submission queue, and its priority is adjusted to the urgent priority; and / or, among the submission queues whose delay scores are less than a second threshold, the submission queue with the lowest priority score is determined as the second target submission queue, and its priority is adjusted to the weighted priority; wherein the second threshold is less than the first threshold; Send an instruction to notify the target submission queue of the priority adjustment result.

2. The method according to claim 1, characterized in that, The priority score of the submission queue is determined by the product of the latency score of the submission queue and the number of commands in the submission queue.

3. The method according to claim 1 or 2, characterized in that, The step of determining the latency score of the submission queue based on the latency duration of the submission queue and the latency duration of the multiple submission queues includes: Calculate the average latency of the multiple submission queues. ; Calculate the standard deviation of the latency of the multiple submission queues. ; According to the mean normalization formula: Determine the delay score of the submission queue; in, For the first The delay duration of the submitted queue, For the first The delay score of each of the submitted queues.

4. A host computer, characterized in that: Includes a host processor and interface circuitry for coupling a memory system, the host processor being configured to: The delay duration of multiple submission queues is obtained. The delay duration of the submission queue is determined by the average completion duration of multiple commands in the submission queue. The completion duration is the difference between the execution completion time of the command and the time when the command is added to the submission queue. The delay score of the submission queue is determined based on the delay duration of the submission queue and the delay duration of the multiple submission queues; The priority score of the submission queue is determined based on the latency score of the submission queue and the number of commands in the submission queue; Among the submission queues whose delay scores are greater than a first threshold, the submission queue with the highest priority score is determined as the first target submission queue, and its priority is adjusted to an urgent priority; and / or, among the submission queues whose delay scores are less than a second threshold, the submission queue with the lowest priority score is determined as the second target submission queue, and its priority is adjusted to a weighted priority; wherein the urgent priority is higher than the weighted priority, and the second threshold is less than the first threshold; The interface circuit is configured as follows: Send an instruction to notify the target submission queue of the priority adjustment result.

5. The host computer according to claim 4, characterized in that, The priority score of the submission queue is determined by the product of the latency score of the submission queue and the number of commands in the submission queue.

6. The host computer according to claim 4 or 5, characterized in that, The host processor determines the latency score of the submission queue based on the latency duration of the submission queue and the latency duration of the multiple submission queues; specifically configured as follows: Calculate the average latency of the multiple submission queues. ; Calculate the standard deviation of the latency of the multiple submission queues. ; According to the mean normalization formula: Determine the delay score of the submission queue; in, For the first The delay duration of the submitted queue, For the first The delay score of each of the submitted queues.

7. An electronic device, characterized in that, The system includes a memory system and a host according to any one of claims 4-6, the host including a first interface, the memory system including a second interface, and the host and the memory system being coupled through the first interface and the second interface, wherein: The first interface is configured to send a first instruction to the memory system for notifying the adjustment results of the priority of a target submission queue among multiple submission queues; The second interface is configured to receive the first instruction from the host and send a second instruction to the host to acknowledge receipt of the first instruction.

8. A computer device, characterized in that: The method includes a processor and a readable storage medium coupled to the processor, the readable storage medium storing executable instructions that, when executed by the processor, enable the implementation of the method according to any one of claims 1-3.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions; when the computer-executable instructions are executed, they can implement the method described in any one of claims 1-3.

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