Display panel, driving method thereof, and display device

Abstract

Embodiments of the present application provide a display panel and a driving method thereof and a display device, and relate to the technical field of display, which optimizes the driving mode of pixel circuit. The display panel comprises a pixel circuit, which comprises: a driving module; a first reset module, a control end of which is connected with a first scan line, a first end of which is connected with a first reset line, and a second end of which is connected with a control end of the driving module; a data writing module, a control end of which is connected with a second scan line, a first end of which is connected with a data line, and a second end of which is connected with a first end of the driving module; and a first light emitting control module, a control end of which is connected with a light emitting control line, a first end of which is connected with a second end of the driving module, and a second end of which is connected with a light emitting element. The enable level of the first scan signal and the second scan signal is low, the second scan signal has an enable level in the time covered by one non-enable level of the light emitting control signal, and the total time length of the enable level in the first scan signal is greater than the time length of the enable level in the second scan signal.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel and its driving method, and a display device. Background Technology

[0002] The display panel includes pixel circuits, which output driving current to the light-emitting elements to drive them to emit light. However, in related technologies, the driving method of the pixel circuits is suboptimal, which can easily lead to some display defects and thus affect display performance. Summary of the Invention

[0003] This invention provides a display panel and its driving method and display device, which are used to optimize the driving mode of pixel circuits and improve display performance.

[0004] In a first aspect, embodiments of the present invention provide a display panel, including a pixel circuit, the pixel circuit comprising: Driver module; A first reset module, wherein the control terminal of the first reset module is electrically connected to a first scan line for providing a first scan signal, the first terminal of the first reset module is electrically connected to the first reset line, and the second terminal of the first reset module is electrically connected to the control terminal of the drive module; A data writing module, wherein the control terminal of the data writing module is electrically connected to the second scan line for providing the second scan signal, the first terminal of the data writing module is electrically connected to the data line, and the second terminal of the data writing module is electrically connected to the first terminal of the driving module; A first light-emitting control module, wherein the control terminal of the first light-emitting control module is electrically connected to a light-emitting control line for providing light-emitting control signals, the first terminal of the first light-emitting control module is electrically connected to the second terminal of the driving module, and the second terminal of the first light-emitting control module is electrically connected to a light-emitting element. Wherein, the enable levels of both the first scanning signal and the second scanning signal are low, and during the time covered by a non-enable level in the light emission control signal, the second scanning signal has an enable level, and the total duration of the enable level in the first scanning signal is greater than the duration of the enable level in the second scanning signal.

[0005] Secondly, based on the same inventive concept, embodiments of the present invention also provide a driving method for a display panel, the display panel including a pixel circuit, the pixel circuit including: Driver module; A first reset module, wherein the control terminal of the first reset module is electrically connected to a first scan line for providing a first scan signal, the first terminal of the first reset module is electrically connected to the first reset line, and the second terminal of the first reset module is electrically connected to the control terminal of the drive module; A data writing module, wherein the control terminal of the data writing module is electrically connected to the second scan line for providing the second scan signal, the first terminal of the data writing module is electrically connected to the data line, and the second terminal of the data writing module is electrically connected to the first terminal of the driving module; A first light-emitting control module, wherein the control terminal of the first light-emitting control module is electrically connected to a light-emitting control line for providing light-emitting control signals, the first terminal of the first light-emitting control module is electrically connected to the second terminal of the driving module, and the second terminal of the first light-emitting control module is electrically connected to a light-emitting element. Wherein, the enable levels of both the first scan signal and the second scan signal are low; The driving method includes: controlling the second scan signal to output an enable level during the time covered by a non-enable level in the light emission control signal, and controlling the total duration of the enable level in the first scan signal to be greater than the duration of the enable level in the second scan signal.

[0006] Secondly, based on the same inventive concept, embodiments of the present invention also provide a display device, including the aforementioned display panel.

[0007] The technical solution provided by the embodiments of the present invention has the following beneficial effects: In this embodiment of the invention, during the time covered by a single high level of the light emission control signal, the total duration of the low level in the first scan signal is relatively long. The first reset transistor resets the gate of the driving transistor for a longer period, allowing the driving transistor to be restored to its initial operating state to a greater extent, and its threshold voltage to return to normal levels. Consequently, during grayscale switching, the driving transistor can quickly return to normal operation, effectively improving the problems of short-term ghosting and brightness differences in the first frame. Simultaneously, during the time covered by a single high level of the light emission control signal, the second scan signal only has one low level. Therefore, the driving transistor only performs one voltage write, and the written voltage is the data voltage it requires. This way, the node potential of the driving transistor is not affected by the display signals in the preceding circuit rows, avoiding the problem of black text with bright bars.

[0008] Furthermore, the second scanning signal outputs fewer pulses in this embodiment of the invention, which can reduce panel power consumption to some extent. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of a display panel structure in related technologies; Figure 2 This is a schematic diagram of a pixel circuit structure in related technologies; Figure 3 This is a timing diagram in related technologies; Figure 4 This is a schematic diagram of a display panel provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 6 A timing diagram provided in an embodiment of the present invention; Figure 7 A box plot provided in an embodiment of the present invention; Figure 8 Another box plot provided in an embodiment of the present invention; Figure 9 This is another timing diagram provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of a structure of the first shifting unit provided in an embodiment of the present invention; Figure 11 for Figure 10 A corresponding timing diagram; Figure 12 This is a schematic diagram of a structure of the second shifting unit provided in an embodiment of the present invention; Figure 13 for Figure 12 A corresponding timing diagram; Figure 14 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention; Figure 15 This is another timing diagram provided in an embodiment of the present invention; Figure 16 This is yet another timing diagram provided in an embodiment of the present invention; Figure 17 This is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention; Figure 18 This is yet another timing diagram provided in an embodiment of the present invention; Figure 19 This is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention; Figure 20 This is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention; Figure 21 This is yet another timing diagram provided in an embodiment of the present invention; Figure 22 This is yet another timing diagram provided in an embodiment of the present invention; Figure 23 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention; Figure 24 This is yet another timing diagram provided in an embodiment of the present invention; Figure 25 This is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention; Figure 26 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0011] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0012] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0013] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0014] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0015] Before describing the technical solutions provided by the embodiments of the present invention, the present invention first explains the problems existing in the related technologies.

[0016] like Figure 1 and Figure 2 As shown, Figure 1 This is a schematic diagram of a display panel structure in related technologies. Figure 2 This is a schematic diagram of a pixel circuit in the related technology. The display panel includes a plurality of circuit rows 1' arranged along a first direction x, and the circuit rows 1' include a plurality of pixel circuits 2' arranged along a second direction y. The first direction x and the second direction y intersect.

[0017] The pixel circuit 2' includes a driving transistor M1', a first reset transistor M2', a data writing transistor M3', a threshold compensation transistor M4', and a first light-emitting control transistor M5'.

[0018] Specifically, the gate of the first reset transistor M2' is electrically connected to the first scan line Scan1', its first terminal is electrically connected to the reset line Ref', and its second terminal is electrically connected to the gate of the driving transistor M1'. The gate of the data write transistor M3' is electrically connected to the second scan line Scan2', its first terminal is electrically connected to the data line Data', and its second terminal is electrically connected to the first terminal of the driving transistor M1'. The gate of the threshold compensation transistor M4' is electrically connected to the second scan line Scan2', its first terminal is electrically connected to the second terminal of the driving transistor M1', and its second terminal is electrically connected to the gate of the driving transistor M1'. The gate of the first light-emitting control transistor M5' is electrically connected to the light-emitting control line Emit', its first terminal is electrically connected to the second terminal of the driving transistor M1', and its second terminal is electrically connected to the light-emitting element D'.

[0019] When the display panel switches grayscale levels, the hysteresis effect of the driving transistor M1' causes short-term ghosting and differences in brightness between the first frame and other frames after the switch. To solve these problems, such as... Figure 3 As shown, Figure 3 As a timing diagram in related technologies, the related technologies propose that during the time covered by a high level in the light emission control signal, both the first scan signal and the second scan signal are driven by multiple pulses, such as driving the first scan signal and the second scan signal by three pulses, so as to reset the driving transistor M1' multiple times and write the voltage multiple times, so as to achieve the purpose of repeatedly refreshing the node potential of the driving transistor M1'.

[0020] For example, in one structure, see Figure 1 The display panel also includes a shift register 3', which comprises multiple cascaded shift units 4'. Each shift unit 4' is electrically connected to both the second scan line Scan2' corresponding to the preceding circuit row 1' and the first scan line Scan1' corresponding to the following circuit row 1'. By controlling the shift unit 3' to output multiple pulses, the first and second scan signals can be driven by multiple pulses.

[0021] Alternatively, in other structures, the display panel may include at least two sets of shift registers, one set of shift registers being electrically connected to the first scan line Scan1' to control the first scan line Scan1' to perform multi-pulse driving, and the other set of shift registers being electrically connected to the second scan line Scan2' to control the second scan line Scan2' to perform multi-pulse driving.

[0022] However, the inventors discovered during their research that during the multiple voltage writes of the driving transistor M1', in the first few writes, because the data line Data' transmits the data voltage required by the pixel circuit 2' in the preceding circuit row 1', the voltage written in the first few writes is the data voltage corresponding to the pixel circuit 2' in the preceding circuit row 1'. Only in the last write will the data voltage corresponding to its own pixel circuit row 1' be written. As a result, the voltage write of this circuit row 1' will be affected by the display signals of other circuit rows 1'.

[0023] For example, if the preceding circuit row 1' needs to display a black pattern, while this circuit row 1' needs to display a white pattern, the data voltage required by pixel circuit 2' in the preceding circuit row 1' will be larger, while the data voltage required by pixel circuit 2' in this circuit row 1' will be smaller. For instance, the data voltage corresponding to pixel circuit 2' in the preceding circuit row 1' is 7V, while the data voltage corresponding to pixel circuit 2' in this circuit row 1' is 3V. Therefore, during the first few resets and voltage writes, the gate-source voltage of the driving transistor M1' in pixel circuit 2' will be very high, leading to a more severe negative bias. Consequently, during the final write of the data voltage required by this circuit row 1' itself, insufficient voltage write will result in excessive brightness, causing the display panel to display a black text with bright bars, a poor display problem.

[0024] In response to this, this invention proposes a technical solution that effectively improves the problems of short-term ghosting and brightness differences in the first frame while avoiding the phenomenon of bright bars on black text.

[0025] This invention provides a display panel that can be of various types, such as Organic Light Emitting Diode (OLED), Active Matrix Organic Light Emitting Diode (AMOLED), and Light Emitting Diode (LED).

[0026] like Figure 4 and Figure 5 As shown, Figure 4 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. The display panel includes a pixel circuit 01 and a light-emitting element 02.

[0027] The pixel circuit 01 includes a driving module 1, a first reset module 2, a data writing module 3, and a first light emission control module 4.

[0028] The control terminal of the first reset module 2 is electrically connected to the first scan line Scan1, which provides the first scan signal; the first end of the first reset module 2 is electrically connected to the first reset line Ref1; and the second end of the first reset module 2 is electrically connected to the control terminal of the drive module 1.

[0029] The control terminal of the data writing module 3 is electrically connected to the second scan line Scan2, which provides the second scan signal. The first terminal of the data writing module 3 is electrically connected to the data line Data. The second terminal of the data writing module 3 is electrically connected to the first terminal of the drive module 1.

[0030] The control terminal of the first light-emitting control module 4 is electrically connected to the light-emitting control line Emit, which provides light-emitting control signals. The first terminal of the first light-emitting control module 4 is electrically connected to the second terminal of the drive module 1. The second terminal of the first light-emitting control module 4 is electrically connected to the light-emitting element 02.

[0031] like Figure 6 As shown, Figure 6 As provided in an embodiment of the present invention, the enable levels of both the first scan signal and the second scan signal are low. During the time covered by a non-enable level in the light emission control signal, the second scan signal has an enable level, and the total duration of the enable level in the first scan signal is greater than the duration of the enable level in the second scan signal.

[0032] In a more specific structure, the driving module 1 includes a driving transistor M1. The first reset module 2 includes a first reset transistor M2, the gate of which is electrically connected to the first scan line Scan1, the first terminal of which is electrically connected to the first reset line Ref1, and the second terminal of which is electrically connected to the gate of the driving transistor M1. The data writing module 3 includes a data writing transistor M3, the first terminal of which is electrically connected to the second scan line Scan2, the first terminal of which is electrically connected to the data line Data, and the second terminal of which is electrically connected to the first terminal of the driving transistor M1. The first light emission control module 4 includes a first light emission control transistor M4, the gate of which is electrically connected to the light emission control line Emit, the first terminal of which is electrically connected to the second terminal of the driving transistor M1, and the second terminal of which is electrically connected to the light-emitting element O2.

[0033] In this embodiment of the invention, the enable level of the first scan signal is low and the disable level is high, and the enable level of the second scan signal is low and the disable level is high. This means that both the first reset transistor M2 and the data write transistor M3 are P-type transistors, such as low-temperature polysilicon (LTPS) transistors with better device stability. The first reset transistor M2 turns on in response to the low level of the first scan signal, writing a reset voltage to the gate of the drive module 1. The data write transistor M3 turns on in response to the low level of the second scan signal, writing a data voltage to the first terminal of the drive module 1.

[0034] Furthermore, the light-emitting control signal can also be a low-level enable signal and a high-level disable signal. In this case, the first light-emitting control transistor M4 can also be an LTPS transistor. The first light-emitting control transistor M4 turns on in response to the low-level light-emitting control signal, transferring the drive current converted by the drive transistor M1 to the light-emitting element O2.

[0035] In this embodiment of the invention, during the time covered by a single high level of the light emission control signal, the total duration of the low level in the first scan signal is greater than the duration of the low level in the second scan signal. Therefore, the first reset transistor M2 can reset the driving transistor M1 for a longer period, improving the reset capability of the driving transistor M1 and allowing it to be restored to its initial working state to a greater extent, with its threshold voltage returning to normal levels. Consequently, during grayscale switching, the driving transistor M1 can quickly return to its normal state, effectively improving the problems of short-term ghosting and brightness differences in the first frame. Simultaneously, during the time covered by a single high level of the light emission control signal, the second scan signal only has one low level, meaning the driving transistor M1 only performs one voltage write, and the written voltage is the data voltage it requires. Thus, the node potential of the driving transistor M1 is not affected by the display signals in the preceding circuit rows, thereby avoiding the problem of black text with bright bars.

[0036] Furthermore, compared to related technologies, the second scanning signal outputs fewer pulses in this embodiment of the invention, which can reduce panel power consumption to some extent.

[0037] It should be noted that the embodiments of the present invention utilize two different sets of shift registers to drive the first scan line Scan1 and the second scan line Scan2 separately, thereby making the above-mentioned different designs for the timing of the first scan signal and the second scan signal, and thus achieving the purpose of improving afterimages, improving the brightness difference of the first frame, and preventing the appearance of black text and bright bars.

[0038] In one feasible implementation, combined with Figure 5 and Figure 6During the time covered by a non-enable level in the light emission control signal, the first scan signal has an enable level, and the enable level in the first scan signal is ahead of the enable level in the second scan signal.

[0039] In the first scan signal, the duration of the enable level is t1, and in the second scan signal, the duration of the enable level is t2, where t1 > t2.

[0040] Based on this driving method, both the first and second scan signals are driven by a single pulse during the time covered by a non-enable level in the light emission control signal. Specifically, the single low level in the first scan signal has a relatively long duration, driving the first reset transistor M2 to conduct for an extended period, continuously resetting the driving transistor M1 for a longer time. This allows the driving transistor M1 to be restored to its initial operating state to a greater extent, effectively improving the problems of image retention and brightness differences in the first frame during grayscale switching. Moreover, compared to related technologies, this driving method results in fewer pulses output by the first scan signal, further reducing panel power consumption, for example, by approximately 10mW.

[0041] In one feasible implementation, t1≥2 t2, thereby significantly lengthening the duration of the low level in the first scan signal to ensure sufficient reset time for the driving transistor M1.

[0042] During the display process, circuit line 5 is scanned line by line. The scan time for a single circuit line 5 can be defined as the line time H. .

[0043] Where n is the row number of pixel circuits 0 and 1 in the display panel. In other words, combining Figure 4 The display panel includes multiple circuit rows 5 arranged along a first direction x, and multiple pixel circuits 01 arranged along a second direction y. The first direction x and the second direction y intersect, and n is the number of circuit rows 5.

[0044] f is the base frequency or the current driving frequency of the display panel.

[0045] Regarding the value of f, in one scenario, the display panel has a base frequency, and other lower-frequency drives are implemented by reducing the base frequency. For example, if the base frequency is 120Hz, one frame is 8.33ms. When the display panel needs to be driven at 60Hz, one data refresh cycle at 60Hz includes two frames, one of which is a write frame and the other is a hold frame. When the display panel needs to be driven at 30Hz, one data refresh cycle at 30Hz includes four frames, one of which is a write frame and the other three are hold frames. In this case, the scan time of circuit row 5 is one frame corresponding to the base frequency divided by the number of circuit rows 5. Therefore, the value of f in the formula is the base frequency.

[0046] In another scenario, the lower frequency driving is not achieved by downclocking, but rather by increasing the scan time of circuit row 5 to lengthen the data refresh cycle corresponding to the lower frequency. For example, when the display panel needs to be driven at 60Hz, one data refresh cycle at 60Hz is one frame, and one frame is 16.67ms. When the display panel needs to be driven at 30Hz, one data refresh cycle at 30Hz is one frame, and one frame is 33.33ms. In this case, the scan time of circuit row 5 is one frame corresponding to the current driving frequency divided by the number of circuit rows 5. Therefore, the value of f in the formula is the current driving frequency of the display panel.

[0047] In this embodiment of the invention, t2 can be equal to 1H, and correspondingly, t1 ≥ 2H.

[0048] Furthermore, t1≤20 t2. As mentioned earlier, when t2 = 1H, t1 satisfies: 2H ≤ t1 ≤ 20H. For example, t1 can be equal to 2H, 4H, 8H, or 12H, etc.

[0049] Given that the issues of short-term afterimages and brightness differences in the first frame have been mitigated, t1 should not be designed to be too large. If t1 is too large, the high-level duration of the emission control signal needs to be further extended to ensure complete coverage of the low levels of the first and second scan signals, but this would reduce the emission time. The duration of the emission time affects the human eye's perception of brightness changes; if the emission time is too short, the brightness changes rapidly, and the human eye may perceive flicker more easily. Therefore, considering the need to ensure optimal stroboscopic effect visibility measure (SVM), t1 can be designed to be less than or equal to 20. t2.

[0050] In this regard, the embodiments of the present invention have also conducted tests: like Figure 7 As shown, Figure 7A box plot provided in an embodiment of the present invention, wherein, Figure 7 The vertical axis “JNCD” represents the minimum perceptible chromatic aberration, which can be used to reflect the short-term afterimage capability. The larger the value, the more obvious the short-term afterimage. Figure 7 In the horizontal axis, [T0] refers to the instantaneous afterimage capability of the black-to-white transition, [T10] refers to the afterimage capability 10 seconds after the black-to-white transition, "3pulse-POR" means that in related technologies, within the time covered by a high level in the light emission control signal, the first scan signal outputs three low levels, and the duration of each low level is 1H, and "1 pulse-4H" means that in the embodiment of this invention, within the time covered by a high level in the light emission control signal, the first scan signal outputs a low level, and the duration of the low level is 4H.

[0051] according to Figure 7 As can be seen, compared with related technologies, the JNCD value is significantly reduced and short-term afterimages are significantly improved based on the design of the first scanning signal in this embodiment of the invention. For example, compared with "3 pulse-POR[T0]", the JNCD corresponding to "1 pulse-4H[T0]" decreased from 5.19 to 4.09. like Figure 8 As shown, Figure 8 Another box plot provided in an embodiment of the present invention, wherein, Figure 8 The vertical axis represents the percentage of the actual brightness of the first frame to the target brightness. The larger the value, the closer the actual brightness of the first frame is to the target brightness, and the smaller the brightness difference between the first frame and other frames. The horizontal axis is t1, which means that in this embodiment of the invention, the first scan signal outputs a low level within the time covered by a high level in the light emission control signal. The horizontal axis represents the duration of the low level in the first scan signal.

[0052] according to Figure 8 It can be seen that when t1 increases to more than 2H, the actual brightness of the first frame is significantly improved, and it is closer to the target brightness.

[0053] In one feasible implementation, see Figure 6 The moment when the light emission control signal changes from the enabled level to the disabled level is the first moment p1, and the moment when the first scan signal changes from the disabled level to the enabled level is the second moment p2. The interval between the first moment p1 and the second moment p2 is ΔT1, where 0 < ΔT1 ≤ 1H.

[0054] The moment when the first scan signal changes from the enabled level to the disabled level is the third moment p3, and the moment when the second scan signal changes from the disabled level to the enabled level is the fourth moment p4. The interval between the third moment p3 and the fourth moment p4 is ΔT2, where 0 < ΔT2 ≤ 1H.

[0055] Where n is the row number of pixel circuit 01 in the display panel, and f is the base frequency or the current driving frequency of the display panel. The definition of the row time H has been explained in detail in the above embodiments and will not be repeated here.

[0056] When ΔT1 and ΔT2 satisfy the above constraints, the interval between the low edge of the first scan signal and the high edge of the light emission control signal is at most 1H, which is a short interval. Simultaneously, the interval between the high edge of the first scan signal and the low edge of the second scan signal is also at most 1H, which is also a short interval. Therefore, under the condition that the high-level duration of the light emission control signal is constant, the low-level duration of the first scan signal can be significantly increased, thereby increasing the reset time.

[0057] In one feasible implementation, such as Figure 9 As shown, Figure 9 In another timing diagram provided in an embodiment of the present invention, during the time covered by a non-enable level in the light emission control signal, the first scan signal has at least two enable levels, and the enable level in the first scan signal is located before the enable level in the second scan signal.

[0058] In this driving method, the first scan signal is driven by multiple pulses. Before the driving transistor M1 writes data, it is reset multiple times. This also increases the total reset time of the driving transistor M1, effectively improving the problems of image retention and brightness difference in the first frame. Moreover, this first scan signal can still use the shift register corresponding to the first scan signal in related technologies for driving, without the need to match an additional shift register for the first scan signal, resulting in minimal adjustments to the panel design.

[0059] In one feasible implementation, see Figure 4 The display panel also includes a first shift register 6, which includes a plurality of first shift units 7 cascaded together. The first shift units 7 are electrically connected to the first scan line Scan1 and are used to output a first scan signal to the first scan line Scan1 connected thereto.

[0060] The display panel also includes a second shift register 8, which includes a plurality of cascaded second shift units 9. The second shift units 9 are electrically connected to the second scan line Scan2 and are used to output a second scan signal to the second scan line Scan2 connected thereto.

[0061] The display panel also includes a third shift register 10, which includes a plurality of cascaded third shift units 11. The third shift units 11 are electrically connected to the light emission control line Emit and are used to output light emission control signals to the light emission control line Emit connected thereto.

[0062] In this embodiment of the invention, separate shift registers are configured to drive the first scan line Scan1 and the second scan line Scan2. Different timing designs can be made for the first scan signal and the second scan signal. For example, the number of pulses of the first scan signal or the low-level duration of a single pulse can be adjusted more flexibly to better achieve the goals of improving afterimages, improving the brightness difference of the first frame, and preventing the appearance of black text and bright bars.

[0063] The first shift unit 7, the second shift unit 9, and the third shift unit 11 can adopt different circuit structures, thereby outputting signals with different waveforms as the first scan signal, the second scan signal, and the light emission control signal, respectively.

[0064] The following embodiments of the present invention illustrate a circuit structure of the first shift unit 7 and the second shift unit 9.

[0065] In one possible circuit structure for the first shift unit 7, such as Figure 10 and Figure 11 As shown, Figure 10 This is a schematic diagram of a structure of the first shifting unit 7 provided in an embodiment of the present invention. Figure 11 for Figure 10 A corresponding timing diagram includes the following: The first shift unit 7 includes: The first transistor T1 has its gate electrically connected to the first clock line CK1, its first terminal electrically connected to the output terminal Out1_i-1 of the previous stage first shift unit 7, and its second terminal electrically connected to the first node N1.

[0066] The second transistor T2 has its gate electrically connected to the first clock line CK1, its first terminal electrically connected to the low-potential signal line VGL, and its second terminal electrically connected to the second node N2.

[0067] The third transistor T3 has its gate electrically connected to the first node N1, its first terminal electrically connected to the first clock line CK1, and its second terminal electrically connected to the second node N2.

[0068] The fourth transistor T4 has its gate electrically connected to the low-potential signal line VGL and its first terminal electrically connected to the second node N2.

[0069] The fifth transistor T5 has its gate electrically connected to the second terminal of the fourth transistor T4, and its first terminal electrically connected to the second clock line CK2.

[0070] The sixth transistor T6 has its gate electrically connected to the second clock line CK2, its first terminal electrically connected to the second terminal of the fifth transistor T5, and its second terminal electrically connected to the third node N3.

[0071] The seventh transistor T7 has its gate electrically connected to the first node N1, its first terminal electrically connected to the high-potential signal line VGH, and its second terminal electrically connected to the third node N3.

[0072] The eighth transistor T8 has its gate electrically connected to the second node N2 and its first terminal electrically connected to the high-potential signal line VGH.

[0073] The ninth transistor T9 has its gate electrically connected to the low-potential signal line VGL, its first electrode electrically connected to the first node N1, and its second electrode electrically connected to the fourth node N4.

[0074] The tenth transistor T10 has its gate electrically connected to the fourth node N4, its first terminal electrically connected to the second clock line CK2, and its second terminal electrically connected to the second terminal of the eighth transistor T8.

[0075] The eleventh transistor T11 has its gate electrically connected to the control line Reset, its first terminal electrically connected to the high-potential signal line VGH, and its second terminal electrically connected to the first node N1.

[0076] The twelfth transistor T12 has its gate electrically connected to the third node N3, its first terminal electrically connected to the high-potential signal line VGH, and its second terminal electrically connected to the output terminal Out1_i.

[0077] The thirteenth transistor T13 has its gate electrically connected to the fourth node N4, its first terminal electrically connected to the low-potential signal line VGL, and its second terminal electrically connected to the output terminal Out1_i.

[0078] The first capacitor C1 has its first plate electrically connected to the gate of the fifth transistor T5, and its second plate electrically connected to the second electrode of the fifth transistor T5.

[0079] The second capacitor C2 has its first plate electrically connected to the second plate of the tenth transistor T10, and its second plate electrically connected to the fourth node N4.

[0080] The third capacitor C3 has its first plate electrically connected to the third node N3 and its second plate electrically connected to the high-potential signal line VGH.

[0081] It should be noted that, Figure 10 This is just one example of the structure of the first shift unit 7. In other optional embodiments of the present invention, other structures of the first shift unit 7 may also be used to output the signal waveform required for the first scan line Scan1.

[0082] In one possible circuit structure for the second shift unit 9, such as Figure 12 and Figure 13 As shown, Figure 12 This is a schematic diagram of a structure of the second shifting unit 9 provided in an embodiment of the present invention. Figure 13 for Figure 12 A corresponding timing diagram, the second shift unit 9 includes: The fourteenth transistor T14 has its gate electrically connected to the third clock line CK3, and its first terminal electrically connected to the output terminal Out2_i-1 of the second shift unit 9 of the previous stage.

[0083] The fifteenth transistor T15 has its gate electrically connected to the third clock line CK3, its first terminal electrically connected to the second terminal of the fourteenth transistor T14, and its second terminal electrically connected to the fifth node N5.

[0084] The sixteenth transistor T16 has its gate electrically connected to the fifth node N5, its first terminal electrically connected to the third clock line CK3, and its second terminal electrically connected to the sixth node N6.

[0085] The seventeenth transistor T17 has its gate electrically connected to the third clock line CK3, its first terminal electrically connected to the low-potential signal line VGL, and its second terminal electrically connected to the sixth node N6.

[0086] The eighteenth transistor T18 has its gate electrically connected to the sixth node N6 and its first terminal electrically connected to the high-potential signal line VGH.

[0087] The nineteenth transistor T19 has its gate electrically connected to the fourth clock line CK4, its first terminal electrically connected to the second terminal of the eighteenth transistor T18, and its second terminal electrically connected to the fifth node N5.

[0088] The twentieth transistor T20 has its gate electrically connected to the low-potential signal line VGL, its first terminal electrically connected to the fifth node N5, and its second terminal electrically connected to the seventh node N7.

[0089] The 21st transistor T21 has its gate electrically connected to the 7th node N7, its first terminal electrically connected to the 4th clock line CK4, and its second terminal electrically connected to the output terminal Out_i.

[0090] The gate of the twenty-second transistor T22 is electrically connected to the sixth node N6, the first terminal is electrically connected to the high-potential signal line VGH, and the second terminal is electrically connected to the output terminal Out_i.

[0091] The fourth capacitor C4 has its first plate electrically connected to the seventh node N7 and its second plate electrically connected to the output terminal Out_i.

[0092] The fifth capacitor C5 has its first plate electrically connected to the sixth node N6 and its second plate electrically connected to the high-potential signal line VGH.

[0093] It should be noted that, Figure 12 This is just one example of the structure of the second shift unit 9. In other optional embodiments of the present invention, other structures of the second shift unit 9 may also be used to output the signal waveform required by the second scan line Scan2.

[0094] In one feasible implementation, such as Figure 14 and Figure 15 As shown, Figure 14 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. Figure 15 In another timing diagram provided in an embodiment of the present invention, the display panel further includes a plurality of circuit rows 5 arranged along a first direction x, and the circuit rows 5 include a plurality of pixel circuits 01 arranged along a second direction y, wherein the first direction x and the second direction y intersect.

[0095] A first shift unit 7 is electrically connected to the first scan line Scan1 corresponding to m circuit rows 5, and a third shift unit 11 is electrically connected to the light emission control line Emit corresponding to m circuit rows 5, where m ≥ 2.

[0096] in, Figure 14 and Figure 15 This illustration is based on the example of m=2. Figure 15 In this context, Emit_x~Emit_x+1 represent the light emission control signals corresponding to the xth circuit row 5 and the (x+1)th circuit row 5, Scan1_x~Scan1_x+1 represent the first scan signals corresponding to the xth circuit row 5 and the (x+1)th circuit row 5, Scan2_x represents the second scan signal corresponding to the xth circuit row 5, and Scan2_x+1 represents the second scan signal corresponding to the (x+1)th circuit row 5.

[0097] In this structure, a first shift unit 7 is used to output the first scan signal to m circuit rows 5, and a third shift unit 11 is used to output the light emission control signal to m circuit rows 5. This configuration has two advantages: first, it reduces the number of shift units required in the first shift register 6 and the third shift register 10, which is more conducive to achieving a narrow bezel design; second, it reduces the number of pulses output by the first shift register 6 and the third shift register 10, thereby reducing power consumption.

[0098] Furthermore, when a third shift unit 11 is electrically connected to the Emit control lines corresponding to m circuit rows 5, if a first shift unit 7 is electrically connected to only one first scan line Scan1 corresponding to one circuit row 5, such as Figure 16 As shown, Figure 16 In another timing diagram provided by an embodiment of the present invention, a high level in the light emission control signal needs to cover the low level of the m first scan signals corresponding to each of the m circuit rows 5. Therefore, with a fixed high level duration in the light emission control signal, the low level duration of the first scan signal corresponding to a single circuit row 5 will be relatively short. However, in this embodiment of the present invention, by also electrically connecting a first shift unit 7 to the first scan line Scan1 corresponding to the m circuit rows 5, these m circuit rows 5 share a single first scan signal. Therefore, the duration of a single low level in the first scan signal can be lengthened, increasing the reset time.

[0099] Furthermore, considering that an excessively large m will affect the signal load and voltage drop, in this embodiment of the invention, m can be designed to be equal to 2.

[0100] Furthermore, in embodiments of the present invention, see... Figure 14 A second shift unit 9 can be electrically connected to only one second scan line Scan2 corresponding to one circuit row 5, so that each pixel circuit 01 in circuit row 5 can accurately receive the data voltage required by itself, ensuring display accuracy.

[0101] In one feasible implementation, see Figure 14 The display panel includes two second shift registers 8, which are electrically connected to the second scan line Scan2 on both sides of the second scan line Scan2.

[0102] The second scan line Scan2 is used to control the data writing voltage of the data writing transistor M3. Since the data voltage determines the magnitude of the drive current, the stability of the driving force of the second scan line Scan2 is required to be higher. To address this, this embodiment of the invention utilizes two sets of second shift registers 8 to drive the second scan line Scan2 on both sides, thereby improving the writing stability and accuracy of the second scan signal.

[0103] In one feasible implementation, see Figure 14 The display panel also includes a display area 12.

[0104] The display panel includes two second shift registers 8. The first shift register 6 and one of the second shift registers 8 are located on one side of the display area 12, and the third shift register 10 and the other second shift register 8 are located on the other side of the display area 12.

[0105] In this configuration, two of the four shift registers are located on one side of the display area 12, and the other two are located on the other side of the display area 12. The distribution of the shift registers is more reasonable and helps to optimize the design of the left and right bezels of the display panel.

[0106] In other optional embodiments of the present invention, the shift registers may also employ other designs. For example, in a display panel with low requirements for bezel width, such as a display panel for an automotive display, a first shift unit 7 may be electrically connected to a first scan line Scan1 corresponding to a circuit row 5, a second shift unit 9 may be electrically connected to a second scan line Scan2 corresponding to a circuit row 5, and a third shift unit 11 may be electrically connected to an emission control line Emit corresponding to a circuit row 5. Further, the display panel may include two sets of first shift registers 6, two sets of second shift registers 8, and two sets of third shift registers 10. The two sets of first shift registers 6 are respectively connected to the first scan line Scan1 on both sides, the two sets of second shift registers 8 are respectively connected to the second scan line Scan2 on both sides, and the two sets of third shift registers 10 are respectively connected to the emission control line Emit on both sides.

[0107] See Figure 5 The pixel circuit 01 also includes a threshold compensation module 13. The first terminal of the threshold compensation module 13 is electrically connected to the second terminal of the driving module 1, and the second terminal of the threshold compensation module 13 is electrically connected to the control terminal of the driving module 1. More specifically, the threshold compensation module 13 includes a threshold compensation transistor M5. The first terminal of the threshold compensation transistor M5 is electrically connected to the second terminal of the driving transistor M1, and the second terminal is electrically connected to the gate of the driving transistor M1.

[0108] In a structure, combination Figure 4 and Figure 5 The control terminal of the threshold compensation module 13 is electrically connected to the second scan line Scan2, meaning the gate of the threshold compensation transistor M5 is electrically connected to the second scan line Scan2. In this case, the threshold compensation transistor M5 can be the same type of transistor as the first reset transistor M2 and the data writing transistor M3, such as an LTPS transistor. The threshold compensation transistor M5 turns on in response to a low level of the second scan signal, further writing the data voltage written to the second terminal of the driving transistor M1 into the gate of the driving transistor M1. This structure eliminates the need for an additional scan line for the threshold compensation module 13, simplifying the structural design.

[0109] Or, in another structure, such as Figure 17 and Figure 18 As shown, Figure 17 This is a schematic diagram of another structure of the pixel circuit 01 provided in an embodiment of the present invention. Figure 18 In another timing diagram provided by this embodiment of the invention, the control terminal of the threshold compensation module 13 is electrically connected to the fourth scan line Scan4, which provides the fourth scan signal; that is, the gate of the threshold compensation transistor M5 is electrically connected to the fourth scan line Scan4. The enable level of the fourth scan signal is high, and the disable level is low. Furthermore, the time covered by the high level in the fourth scan signal overlaps with the time covered by the low level in the second scan signal. The threshold compensation transistor M5 turns on in response to the high level of the fourth scan signal, further writing the data voltage written by the second electrode of the driving transistor M1 into the gate of the driving transistor M1. At this time, the threshold compensation transistor M5 is an N-type transistor. For example, to reduce the influence of the off-state leakage current of the threshold compensation transistor M5 on the gate potential of the driving transistor M1, the threshold compensation transistor M5 can be an indium gallium zinc oxide (IGZO) transistor.

[0110] In one feasible implementation, see Figure 5 The display panel also includes a second reset module 14. The first end of the second reset module 14 is electrically connected to the second reset line Ref2, and the second end of the second reset module 14 is electrically connected to the light-emitting element 02. The first reset line Ref1 and the second reset line Ref2 provide different reset voltages.

[0111] More specifically, the second reset module 14 includes a second reset transistor M6. The first terminal of the second reset transistor M6 is electrically connected to the second reset line Ref2, and the second terminal is electrically connected to the light-emitting element 02. When the second reset transistor M6 is turned on, it writes a second reset voltage into the light-emitting element 02, thereby resetting the anode of the light-emitting element 02.

[0112] By using different reset voltages to reset the driving transistor M1 and the light-emitting element O2, the driving process becomes more flexible. For example, the second reset voltage can be designed to be lower to better prevent sub-pixel stealing light.

[0113] Alternatively, in another feasible implementation, such as Figure 19 As shown, Figure 19 This is another schematic diagram of the pixel circuit 01 provided in the embodiment of the present invention. The first end of the second reset module 14 can also be electrically connected to the first reset line Ref1, so that only one reset line is configured for the first reset module 2 and the second reset module 14, simplifying the structural design.

[0114] In one feasible implementation, see Figure 5 and Figure 6The display panel also includes a second reset module 14. The control terminal of the second reset module 14 receives a scan signal, the first terminal of the second reset module 14 receives a reset voltage, and the second terminal of the second reset module 14 is electrically connected to the light-emitting element 02.

[0115] In particular, during the time covered by a non-enable level in the light emission control signal, the total duration of the enable level in the scan signal received by the second reset module 14 is greater than the duration of the enable level in the second scan signal, thereby increasing the reset time of the light emission element 02 and resetting the anode potential of the light emission element 02 more thoroughly. Before emitting light, the anode voltage of the light emission element 02 in different sub-pixels will be set to a consistent initial state, which helps to improve display uniformity.

[0116] In one feasible implementation, see Figure 5 and Figure 6 The control terminal of the second reset module 14 is electrically connected to the first scan line Scan1. The first scan signal is used to drive the second reset module 14 to increase the reset time of the light-emitting element 02, so there is no need to configure an additional scan line for the second reset module 14.

[0117] Alternatively, in another feasible implementation, such as Figure 20 As shown, Figure 20 This is another schematic diagram of the pixel circuit 01 provided in an embodiment of the present invention. The control terminal of the second reset module 14 is electrically connected to the third scan line Scan3 used to provide the third scan signal.

[0118] The second reset module 14 is driven by a separate third scan line Scan3, allowing for individual design of the reset time of the light-emitting element 02. For example, ... Figure 21 As shown, Figure 21 In another timing diagram provided by an embodiment of the present invention, the waveform of the third scan signal and the waveform of the first scan signal can be the same, or, as shown... Figure 22 As shown, Figure 22In another timing diagram provided by this embodiment of the invention, the waveform of the third scan signal and the waveform of the first scan signal may not be consistent. For example, during the operation of the pixel circuit 01, the conduction time of the first reset transistor M2 and the conduction time of the data writing transistor M3 and the threshold compensation transistor M5 need to be staggered; otherwise, the gate potential of the driving transistor M1 will be disordered. Therefore, the low level of the first scan signal and the low level of the second scan signal cannot overlap. However, the conduction time of the second reset transistor M6 can overlap with the conduction time of the data writing transistor M3 and the threshold compensation transistor M5. Therefore, when the second reset transistor M6 is connected to the third scan line Scan3, the duration of the low level in the third scan signal can be designed to be longer. The low level in the third scan signal can overlap with the low level in the first scan signal and the low level in the second scan signal, so that the reset time of the light-emitting element 02 can be longer.

[0119] Furthermore, such as Figure 23 and Figure 24 As shown, Figure 23 This is a schematic diagram of another structure of the display panel provided in an embodiment of the present invention. Figure 24 In another timing diagram provided by an embodiment of the present invention, the display panel further includes a plurality of circuit rows 5 arranged along a first direction x, and the circuit rows 5 include a plurality of pixel circuits 01 arranged along a second direction y, wherein the first direction x and the second direction y intersect.

[0120] The display panel also includes a first shift register 6, which includes a plurality of cascaded first shift units 7. The output of the first shift unit 7 is electrically connected to at least one first scan line Scan1 corresponding to a circuit row 5.

[0121] The display panel also includes a fourth shift register 15, which includes a plurality of cascaded fourth shift units 16. The output terminal Out3 of the fourth shift unit 16 is electrically connected to at least one third scan line Scan3 corresponding to a circuit row 5.

[0122] Specifically, for the first shift unit 7 and the fourth shift unit 16 corresponding to the same circuit row 5, the output terminal Out1 of the first shift unit 7 is also electrically connected to the shift control terminal Next of the fourth shift unit 16.

[0123] In this driving mode, the third scan line Scan3 is driven by a separate fourth shift register 15. The signals output by different shift registers only need to be transmitted to one scan line, resulting in a smaller scan signal voltage drop.

[0124] In general, in a cascaded shift register configuration of multiple shift units, the signal output from the previous shift unit also serves as the shift control signal for the next shift unit, thereby enabling multiple shift units to output enable levels sequentially. To drive the first shift unit to operate normally, its shift control terminal needs to be electrically connected to a frame start signal line. After the frame start signal line outputs a signal, the first shift unit will begin outputting signals under the influence of the frame start signal, clock signal, etc. The signal output by the first shift unit serves as the shift signal for the second shift unit, driving the second shift unit to operate, causing it to output signals sequentially, and so on, until the third, fourth, ..., and finally the last shift unit.

[0125] In the above structure, the shift control signal of the fourth shift unit 16 is not provided by the output terminal Out3 of the previous fourth shift unit 16, but by the output terminal Out1 of the first shift unit 7. With this setting, only the signal output by the first first shift unit 7 needs to be used as the frame start signal of the first fourth shift unit 16, and there is no need to configure an additional frame start signal line for the fourth shift register 15, thus saving the number of traces.

[0126] In other optional embodiments of the present invention, the control terminal of the second reset module 14 may also be electrically connected to the second scan line Scan2.

[0127] In an embodiment of the present invention, see Figure 5 The pixel circuit 01 also includes a second light emission control module 17. The control terminal of the second light emission control module 17 is electrically connected to the light emission control line Emit. The first terminal of the second light emission control module 17 is electrically connected to the power line PVDD. The second terminal of the second light emission control module 17 is electrically connected to the first terminal of the driving module 1.

[0128] More specifically, the second light-emitting control module 17 includes a second light-emitting control transistor M7, the gate of the second light-emitting control transistor M7 is electrically connected to the light-emitting control line Emit, the first electrode is electrically connected to the power supply line PVDD, and the second electrode is electrically connected to the first electrode of the driving transistor M1.

[0129] The pixel circuit 01 also includes a storage capacitor Cst, the first plate of which is electrically connected to the power line PVDD, and the second plate of which is electrically connected to the gate of the driving transistor M1.

[0130] In this embodiment of the invention, to reduce the impact of the off-state leakage current of the first reset transistor M2 and the threshold compensation transistor M5 on the gate potential of the driving transistor M1, such as... Figure 25 As shown, Figure 25This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. The first reset transistor M2 includes a first sub-transistor M21 and a second sub-transistor M22. The gates of both the first sub-transistor M21 and the second sub-transistor M22 are electrically connected to the first scan line Scan1. The first terminal of the first sub-transistor M21 is electrically connected to the first reset line Ref1. The second terminal of the first sub-transistor M21 is electrically connected to the first terminal of the second sub-transistor M22. The second terminal of the second sub-transistor M22 is electrically connected to the gate of the driving transistor M1. The threshold compensation transistor M5 includes a third sub-transistor M51 and a fourth sub-transistor M52. The gates of both the third sub-transistor M51 and the fourth sub-transistor M52 are electrically connected to the second scan line Scan2. The first terminal of the third sub-transistor M51 is electrically connected to the second terminal of the driving transistor M1. The second terminal of the third sub-transistor M51 is electrically connected to the first terminal of the fourth sub-transistor M52. The second terminal of the fourth sub-transistor M52 is electrically connected to the gate of the driving transistor M1.

[0131] Based on the same inventive concept, embodiments of the present invention also provide a method for driving a display panel, combined with Figures 4-6 The display panel includes a pixel circuit 01. The pixel circuit 01 includes a driving module 1, a first reset module 2, a data writing module 3, and a first light emission control module 4.

[0132] The control terminal of the first reset module 2 is electrically connected to the first scan line Scan1, which provides the first scan signal; the first end of the first reset module 2 is electrically connected to the first reset line Ref1; and the second end of the first reset module 2 is electrically connected to the control terminal of the drive module 1.

[0133] The control terminal of the data writing module 3 is electrically connected to the second scan line Scan2, which provides the second scan signal. The first terminal of the data writing module 3 is electrically connected to the data line Data. The second terminal of the data writing module 3 is electrically connected to the first terminal of the drive module 1.

[0134] The control terminal of the first light-emitting control module 4 is electrically connected to the light-emitting control line Emit, which provides light-emitting control signals. The first terminal of the first light-emitting control module 4 is electrically connected to the second terminal of the drive module 1. The second terminal of the first light-emitting control module 4 is electrically connected to the light-emitting element 02.

[0135] The enable levels for both the first and second scan signals are low.

[0136] The driving method includes: controlling the second scan signal to output an enable level during the time covered by a non-enable level in the light emission control signal, and controlling the total duration of the enable level in the first scan signal to be greater than the duration of the enable level in the second scan signal.

[0137] In this embodiment of the invention, during the time covered by a single high level of the light emission control signal, the total duration of the low level in the first scan signal is greater than the duration of the low level in the second scan signal. Therefore, the first reset transistor M2 can reset the driving transistor M1 for a longer period, improving the reset capability of the driving transistor M1 and allowing it to be restored to its initial working state to a greater extent, with its threshold voltage returning to normal levels. Consequently, during grayscale switching, the driving transistor M1 can quickly return to its normal state, effectively improving the problems of short-term ghosting and brightness differences in the first frame. Simultaneously, during the time covered by a single high level of the light emission control signal, the second scan signal only has one low level, meaning the driving transistor M1 only performs one voltage write, and the written voltage is the data voltage it requires. Thus, the node potential of the driving transistor M1 is not affected by the display signals in the preceding circuit rows, thereby avoiding the problem of black text with bright bars.

[0138] Furthermore, compared to related technologies, the second scanning signal outputs fewer pulses in this embodiment of the invention, which can reduce panel power consumption to some extent.

[0139] In one feasible implementation, combined with Figure 5 and Figure 6 During the time covered by a non-enable level in the light emission control signal, the first scan signal is controlled to output an enable level, and the enable level in the first scan signal is located before the enable level in the second scan signal.

[0140] In the first scan signal, the duration of the enable level is t1, and in the second scan signal, the duration of the enable level is t2, where t1 > t2.

[0141] Based on this driving method, both the first and second scan signals are driven by a single pulse during the time covered by a non-enable level in the light emission control signal. Specifically, the single low level in the first scan signal has a relatively long duration, driving the first reset transistor M2 to conduct for an extended period, continuously resetting the driving transistor M1 for a longer time. This allows the driving transistor M1 to be restored to its initial operating state to a greater extent, effectively improving the problems of image retention and brightness differences in the first frame during grayscale switching. Moreover, compared to related technologies, this driving method results in fewer pulses output by the first scan signal, further reducing panel power consumption.

[0142] Furthermore, 2 t2≤t1≤20 t2.

[0143] Based on the foregoing analysis, the minimum value of t1 is set to 2. t2 ensures sufficient reset time for the drive transistor M1. Further, the maximum value of t1 is set to 20. t2 can ensure a better SVM and avoid flickering that can be detected by the human eye.

[0144] In one feasible implementation, see Figure 6 The moment when the light emission control signal changes from the enabled level to the disabled level is the first moment p1, and the moment when the first scan signal changes from the disabled level to the enabled level is the second moment p2. The interval between the first moment p1 and the second moment p2 is ΔT1, where 0 < ΔT1 ≤ 1H.

[0145] The moment when the first scan signal changes from the enabled level to the disabled level is the third moment p3, and the moment when the second scan signal changes from the disabled level to the enabled level is the fourth moment p4. The interval between the third moment p3 and the fourth moment p4 is ΔT2, where 0 < ΔT2 ≤ 1H.

[0146] n is the row number of pixel circuit 01, and f is the base frequency or the frequency currently driven by the display panel.

[0147] When ΔT1 and ΔT2 satisfy the above constraints, the interval between the low edge of the first scan signal and the high edge of the light emission control signal is at most 1H, which is a short interval. Simultaneously, the interval between the high edge of the first scan signal and the low edge of the second scan signal is also at most 1H, which is also a short interval. Therefore, under the condition that the high-level duration of the light emission control signal is constant, the low-level duration of the first scan signal can be significantly increased, thereby increasing the reset time.

[0148] Based on the same inventive concept, embodiments of the present invention also provide a display device, such as... Figure 26 As shown, Figure 26 This is a schematic diagram of a display device provided in an embodiment of the present invention, the display device including the aforementioned display panel 100. Of course, Figure 26 The display device shown is for illustrative purposes only. The display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader or television.

[0149] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0150] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized by, Includes a pixel circuit, the pixel circuit comprising: Driver module; A first reset module, wherein the control terminal of the first reset module is electrically connected to a first scan line for providing a first scan signal, the first terminal of the first reset module is electrically connected to the first reset line, and the second terminal of the first reset module is electrically connected to the control terminal of the drive module; A data writing module, wherein the control terminal of the data writing module is electrically connected to the second scan line for providing the second scan signal, the first terminal of the data writing module is electrically connected to the data line, and the second terminal of the data writing module is electrically connected to the first terminal of the driving module; A first light-emitting control module, wherein the control terminal of the first light-emitting control module is electrically connected to a light-emitting control line for providing light-emitting control signals, the first terminal of the first light-emitting control module is electrically connected to the second terminal of the driving module, and the second terminal of the first light-emitting control module is electrically connected to a light-emitting element. Wherein, the enable levels of both the first scanning signal and the second scanning signal are low, and during the time covered by a non-enable level in the light emission control signal, the second scanning signal has an enable level, and the total duration of the enable level in the first scanning signal is greater than the duration of the enable level in the second scanning signal. Wherein, the total duration of the enable level in the first scan signal is t1, the duration of the enable level in the second scan signal is t2, and 2×t2≤t1≤20×t2; During the time covered by a non-enable level in the light emission control signal, the first scan signal has an enable level, and the enable level in the first scan signal is located before the enable level in the second scan signal; The moment when the light emission control signal changes from an enabled level to an disabled level is the first moment, and the moment when the first scan signal changes from an disabled level to an enabled level is the second moment. The interval between the first moment and the second moment is ΔT1, where 0 < ΔT1 ≤ 1H. The moment when the first scan signal changes from an enabled level to an disabled level is the third moment, and the moment when the second scan signal changes from an disabled level to an enabled level is the fourth moment. The interval between the third moment and the fourth moment is ΔT2, where 0 < ΔT2 ≤ 1H. wherein, n is the number of rows of pixel circuits in the display panel, and f is a base frequency or a current driving frequency of the display panel.

2. The display panel according to claim 1, characterized in that, During the time covered by a non-enable level in the light emission control signal, the first scan signal has at least two enable levels, and the enable level in the first scan signal precedes the enable level in the second scan signal.

3. The display panel according to claim 1, characterized in that, The display panel also includes: The first shift register includes a plurality of first shift units arranged in cascade, and the first shift units are electrically connected to the first scan line; The second shift register includes a plurality of cascaded second shift units, the second shift units being electrically connected to the second scan line; The third shift register includes multiple cascaded third shift units, which are electrically connected to the light-emitting control line.

4. The display panel according to claim 3, characterized in that, The display panel further includes a plurality of circuit rows arranged along a first direction, the circuit rows including a plurality of pixel circuits arranged along a second direction, the first direction intersecting the second direction; Wherein, one of the first shift units is electrically connected to the first scan lines corresponding to m of the circuit rows, and one of the third shift units is electrically connected to the light emission control lines corresponding to m of the circuit rows, where m ≥ 2.

5. The display panel according to claim 3, characterized in that, The display panel includes two second shift registers, which are electrically connected to the second scan line on both sides of the second scan line.

6. The display panel according to claim 3, characterized in that, The display panel also includes a display area; The display panel also includes two second shift registers, with the first shift register and one of the second shift registers located on one side of the display area, and the third shift register and the other second shift register located on the other side of the display area.

7. The display panel according to claim 1, characterized in that, The display panel further includes a second reset module, the first end of which is electrically connected to a second reset line, and the second end of which is electrically connected to a light-emitting element. The first reset line and the second reset line provide different reset voltages.

8. The display panel according to claim 1, characterized in that, The display panel further includes a second reset module. The control terminal of the second reset module receives a scan signal, the first terminal of the second reset module receives a reset voltage, and the second terminal of the second reset module is electrically connected to the light-emitting element. Specifically, during the time covered by a non-enable level in the light emission control signal, the total duration of the enable level in the scan signal received by the second reset module is greater than the duration of the enable level in the second scan signal.

9. The display panel according to claim 8, characterized in that, The control terminal of the second reset module is electrically connected to the first scan line.

10. The display panel according to claim 8, characterized in that, The control terminal of the second reset module is electrically connected to the third scan line.

11. The display panel according to claim 10, characterized in that, The display panel also includes: A plurality of circuit rows arranged along a first direction, the circuit rows including a plurality of pixel circuits arranged along a second direction, the first direction intersecting the second direction; The first shift register includes a plurality of first shift units arranged in cascade, and the output of the first shift unit is electrically connected to at least one of the first scan lines corresponding to the circuit row; The fourth shift register includes a plurality of cascaded fourth shift units, the output of which is electrically connected to at least one of the third scan lines corresponding to the circuit row; Specifically, for the first shift unit and the fourth shift unit corresponding to the same circuit row, the output terminal of the first shift unit is also electrically connected to the shift control terminal of the fourth shift unit.

12. A driving method for a display panel, characterized in that, The display panel includes a pixel circuit, the pixel circuit comprising: Driver module; A first reset module, wherein the control terminal of the first reset module is electrically connected to a first scan line for providing a first scan signal, the first terminal of the first reset module is electrically connected to the first reset line, and the second terminal of the first reset module is electrically connected to the control terminal of the drive module; A data writing module, wherein the control terminal of the data writing module is electrically connected to the second scan line for providing the second scan signal, the first terminal of the data writing module is electrically connected to the data line, and the second terminal of the data writing module is electrically connected to the first terminal of the driving module; A first light-emitting control module, wherein the control terminal of the first light-emitting control module is electrically connected to a light-emitting control line for providing light-emitting control signals, the first terminal of the first light-emitting control module is electrically connected to the second terminal of the driving module, and the second terminal of the first light-emitting control module is electrically connected to a light-emitting element. Wherein, the enable levels of both the first scan signal and the second scan signal are low; The driving method includes: controlling the second scan signal to output an enable level during the time covered by a non-enable level in the light emission control signal, and controlling the total duration of the enable level in the first scan signal to be greater than the duration of the enable level in the second scan signal; Wherein, the total duration of the enable level in the first scan signal is t1, the duration of the enable level in the second scan signal is t2, and 2×t2≤t1≤20×t2; During the time covered by a non-enable level in the light emission control signal, the first scan signal is controlled to output an enable level, and the enable level in the first scan signal is located before the enable level in the second scan signal; The moment when the light emission control signal changes from an enabled level to an disabled level is the first moment, and the moment when the first scan signal changes from an disabled level to an enabled level is the second moment. The interval between the first moment and the second moment is ΔT1, where 0 < ΔT1 ≤ 1H. The moment when the first scan signal changes from an enabled level to an disabled level is the third moment, and the moment when the second scan signal changes from an disabled level to an enabled level is the fourth moment. The interval between the third moment and the fourth moment is ΔT2, where 0 < ΔT2 ≤ 1H. in, n is the number of rows of the pixel circuit, and f is the base frequency or the frequency currently driven by the display panel.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 11.

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