Semiconductor device and manufacturing method thereof, electronic device

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic device, the semiconductor device comprising: a plurality of transistors distributed in different layers stacked along a vertical substrate direction; a bit line extending through the plurality of transistors of the different layers and along a vertical direction of the substrate; the transistor comprising a gate electrode and a semiconductor layer, the semiconductor layer comprising a first semiconductor sub-layer extending along a direction parallel to the substrate direction and a second semiconductor sub-layer extending along a direction perpendicular to the substrate direction, the first semiconductor sub-layer comprising a strip extending along a first direction, the second semiconductor sub-layer connecting the bit line, the gate electrode extending along a direction parallel to the substrate direction and surrounding the strip. The embodiment provides a ring-gate type semiconductor device facilitating stacking, which can simplify the process and improve the gate control ability.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0002] Semiconductor memory can be divided into volatile memory and non-volatile memory based on its application.

[0003] To minimize the cost of memory products, the goal is to fabricate as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet the demands of current products. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a semiconductor device that simplifies the manufacturing process and improves gate control capability.

[0006] This application provides a semiconductor device, including:

[0007] Multiple transistors are stacked in different layers along the direction perpendicular to the substrate;

[0008] Bit lines are connected to the plurality of transistors in the different layers and extend along a direction perpendicular to the substrate;

[0009] The transistor includes a gate electrode and a semiconductor layer. The semiconductor layer includes a first semiconductor sublayer extending in a direction parallel to the substrate and a second semiconductor sublayer extending in a direction perpendicular to the substrate. The first semiconductor sublayer includes a strip-shaped portion extending in a first direction. The second semiconductor sublayer is connected to the bit line. The gate electrode extends in a direction parallel to the substrate and surrounds the strip-shaped portion.

[0010] In some embodiments, the second semiconductor sublayer surrounds the bit line.

[0011] In some embodiments, on a plane perpendicular to the substrate and the first direction, the orthographic projection of the strip portion lies within the orthographic projection of the second semiconductor sublayer, and the orthographic projection of the gate electrode on the substrate lies outside the orthographic projection of the second semiconductor sublayer on the substrate.

[0012] In some embodiments, the first semiconductor sublayer further includes an end portion disposed away from the bit line of the strip portion, wherein, on a plane perpendicular to the substrate and the first direction, the orthographic projection of the strip portion is located within the orthographic projection of the end portion, and the orthographic projection of the gate electrode on the substrate is located outside the orthographic projection of the end portion on the substrate.

[0013] In some embodiments, the end is provided with a first groove with an opening away from the bit line, and the transistor further includes a first source / drain electrode, the first source / drain electrode filling the first groove.

[0014] In some embodiments, the first source / drain electrode includes a first portion filling the first groove and a second portion disposed on the side of the first groove opposite to the bit line, the second portion overlapping the first portion.

[0015] In some embodiments, a second portion of the first source / drain electrode is provided with a second groove with an opening opposite to the bit line, and the semiconductor device further includes a capacitor, the capacitor including a second electrode, the second electrode being insulated from the first source / drain electrode through a dielectric layer and filling the second groove.

[0016] In some embodiments, the second portion of the first source / drain electrode is a block electrode, and the semiconductor device further includes a capacitor, the capacitor including a second electrode, the second electrode being provided with a third groove with an opening facing the bit line, the second portion of the first source / drain electrode being insulated from the second electrode by a dielectric layer and filling the third groove.

[0017] In some embodiments, the semiconductor device includes a multilayer memory cell array distributed along a direction perpendicular to the substrate, wherein each layer of the memory cell array includes multiple rows and columns of memory cells distributed along a first direction and a second direction, multiple word lines extending along the second direction and spaced apart along a direction perpendicular to the substrate, and multiple bit lines extending along a direction perpendicular to the substrate and spaced apart along the second direction; each memory cell includes a transistor and a capacitor, the plurality of transistors being located on different layers and arranged in an array; the same word line includes multiple connection electrodes distributed along the second direction; the multiple connection electrodes of the same word line are connected through the gate electrodes of transistors in the same column distributed along the second direction; each bit line is connected to a transistor in at least one column of memory cells arranged perpendicular to the substrate.

[0018] In some embodiments, the connection electrode is connected to the region of the gate electrode near the bit line.

[0019] In some embodiments, the semiconductor layers of the plurality of transistors at the same location on different layers are connected to form an integral structure.

[0020] In some embodiments, the transistors and capacitors of the same memory cell are arranged in a direction parallel to the first direction. In memory cells of the same layer, the transistors and capacitors of adjacent memory cells along the first direction are arranged in opposite directions. The semiconductor layers of memory cells that are adjacent along the first direction and whose transistors are close to each other are connected to form an integral structure.

[0021] In some embodiments, the semiconductor layer of the monolithic structure is connected to the same bit line and surrounds the connected bit line.

[0022] This disclosure provides a method for manufacturing a semiconductor device, the semiconductor device comprising: a plurality of transistors stacked on different layers along a direction perpendicular to a substrate, and bit lines, wherein the transistors include a gate electrode and a semiconductor layer, comprising:

[0023] A stacked structure of alternating first insulating layers and sacrificial layers is formed on the substrate;

[0024] The stacked structure is patterned to form a word line area extending along a second direction and a plurality of memory cell areas extending along a first direction and spaced apart along the second direction; a trench extending along the first direction through the stacked structure is provided between any two adjacent memory cell areas.

[0025] A first hole is formed in the word line area, penetrating the stacked structure; a portion of each sacrificial layer is removed to form a plurality of first grooves communicating with the first hole;

[0026] A gate electrode is formed that covers the sidewall of the first groove;

[0027] A gate insulating film and a semiconductor film are sequentially deposited in the first groove and the first hole to form the gate insulating layer and the semiconductor layer of the transistor. The semiconductor layer fills the first groove and covers the bottom wall and side wall of the first hole. The gate insulating layer surrounds the semiconductor layer, and the gate electrode surrounds the gate insulating layer.

[0028] The bit line is formed by depositing a first conductive thin film within the first hole in which the semiconductor layer is formed.

[0029] In some embodiments, the method further includes:

[0030] The sacrificial layer of the storage cell area is removed to form a second groove that communicates with the first groove. The second groove is located on the side of the first groove away from the first hole.

[0031] The process of sequentially depositing a gate insulating film and a semiconductor film in the first groove and the first hole to form the gate insulating layer and the semiconductor layer of the transistor, wherein the semiconductor layer fills the first groove and covers the bottom wall and sidewall of the first hole, the gate insulating layer surrounds the semiconductor layer, and the gate electrode surrounds the gate insulating layer; and depositing a first conductive film in the first hole where the semiconductor layer is formed to form the bit line includes:

[0032] A gate insulating film, a semiconductor film, and a first conductive film are sequentially deposited in the second groove, the first groove, and the first hole, with the semiconductor film filling the first groove. The gate insulating film, the semiconductor film, and the first conductive film in the second groove are etched to a predetermined length to form the gate insulating layer, the semiconductor layer, and the bit line. The first conductive film retained in the second groove forms the first part of the first source / drain electrode of the transistor.

[0033] A second portion of the first source / drain electrode is formed within the second groove, and the second portion of the first source / drain electrode overlaps with the first portion of the first source / drain electrode.

[0034] In some embodiments, a second portion of the first source / drain electrode covers the bottom and sidewalls of the second groove; the method further includes: forming a second electrode that fills the second groove, and a dielectric layer disposed between the second electrode and the first source / drain electrode.

[0035] In some embodiments, a second portion of the first source / drain electrode fills the second groove; the method further includes exposing an outer wall of the second portion of the first source / drain electrode, the outer wall including an end face of the second portion of the first source / drain electrode facing away from the first portion of the first source / drain electrode, and each sidewall connected to the end face; forming a second pole surrounding the outer wall; and forming a dielectric layer disposed between the outer wall and the second pole.

[0036] In some embodiments, removing a portion of each of the sacrificial layers to form a plurality of first grooves communicating with the first hole includes:

[0037] Lateral etching is performed through the first hole to remove a portion of each of the sacrificial layers, forming a plurality of first grooves communicating with the first hole;

[0038] Alternatively, before forming the first hole, the first part of the sacrificial layer of each sacrificial layer is replaced with a dummy layer, and a second part of the sacrificial layer exists between the dummy layer and the first hole; after etching away the second part of the sacrificial layer, the dummy layer is then etched away to form a plurality of first grooves communicating with the first hole.

[0039] In some embodiments, the method further includes:

[0040] A second hole is formed in each of the trenches, penetrating the stacked structure. The second hole exposes the sidewall of the sacrificial layer of the word line region but does not expose the sidewall of the sacrificial layer of the memory cell region. A plurality of third grooves are formed by laterally etching the sacrificial layer of the word line region through each of the second holes. The third grooves connect two adjacent second holes along a first direction.

[0041] A second conductive film is deposited and filled in the plurality of third grooves, and a third hole is formed in the word line area to penetrate the stacked structure. The third hole disconnects the second conductive film in each of the third grooves to form two disconnected connection electrodes. The connection electrodes are connected to the gate electrode. A plurality of connection electrodes distributed along the second direction are connected to form word lines through a plurality of gate electrodes distributed along the second direction.

[0042] Alternatively, a second hole is formed in each of the trenches, penetrating the stacked structure. The second hole exposes the sidewall of the sacrificial layer in the word line region but does not expose the sidewall of the sacrificial layer in the memory cell region. A plurality of third grooves are formed by laterally etching the sacrificial layer in the word line region through each of the second holes. The third grooves connect two adjacent second holes along a first direction. The second holes are enlarged along a second direction to expose the sidewall of the sacrificial layer located in the memory cell region.

[0043] A second conductive film is deposited and filled in the plurality of third grooves, and a third hole is formed in the word line region to penetrate the stacked structure. The third hole disconnects the second conductive film in each of the third grooves to form two disconnected connection electrodes. The connection electrodes are connected to the gate electrode. The plurality of connection electrodes distributed along the second direction are connected to form word lines through the plurality of gate electrodes distributed along the second direction.

[0044] In some embodiments, the method further includes:

[0045] When the stacked structure is patterned, multiple third holes that penetrate the stacked structure are also formed in the letter line area;

[0046] After the third hole and the trench are filled with a second insulating layer, a second hole is formed in each trench to penetrate the stacked structure, and the second insulating layer in the third hole is removed, wherein the second hole exposes the sidewall of the sacrificial layer of the word line area but does not expose the sidewall of the sacrificial layer of the memory cell area; a plurality of fourth grooves are formed by laterally etching the sacrificial layer of the word line area through each second hole and the third hole, the fourth grooves being disposed between the second hole and the third hole and communicating with the second hole and the third hole;

[0047] A second conductive film is deposited and filled in the plurality of fourth grooves to form a connection electrode, the connection electrode being connected to the gate electrode, and the plurality of connection electrodes distributed along the second direction are connected through the plurality of gate electrodes distributed along the second direction to form a word line.

[0048] This disclosure provides an electronic device, including the semiconductor device described in any of the above embodiments, or the semiconductor device formed by the semiconductor device manufacturing method described in any of the above embodiments.

[0049] This application includes a semiconductor device and a method for manufacturing the same, as well as an electronic device. The semiconductor device includes: a plurality of transistors stacked in different layers along a direction perpendicular to a substrate; a bit line connected to the plurality of transistors in the different layers and extending along a direction perpendicular to the substrate; each transistor includes a gate electrode and a semiconductor layer, the semiconductor layer including a first semiconductor sublayer extending in a direction parallel to the substrate and a second semiconductor sublayer extending in a direction perpendicular to the substrate, the first semiconductor sublayer including a strip-shaped portion extending in a first direction, the second semiconductor sublayer being connected to the bit line, and the gate electrode extending in a direction parallel to the substrate and surrounding the strip-shaped portion. This embodiment provides a ring-gate semiconductor device that is easy to stack, which can simplify the process and improve gate control capability.

[0050] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0051] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0052] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0053] Figure 1A A plan view of a semiconductor device provided for an exemplary embodiment; Figure 1B For along Figure 1A Cross-sectional view along the aa' direction; Figure 1C For along Figure 1A Cross-sectional view in the bb' direction; Figure 1D This is a cross-sectional view along the cc' direction in 1A; Figure 1E For along Figure 1A Cross-sectional view in the dd' direction;

[0054] Figure 2A and Figure 2BCross-sectional views of a semiconductor device along the aa' direction and the dd' direction, respectively, provided in another exemplary embodiment;

[0055] Figures 3A to 3D Cross-sectional views along the aa', bb', cc', and dd' directions after the stacked structure is formed, respectively, provided in an exemplary embodiment;

[0056] Figures 4A to 4D These are cross-sectional views along the aa', bb', cc', and dd' directions after forming a first preset shape, provided in an exemplary embodiment. Figure 4E This is a schematic diagram showing the planar location of the first trench;

[0057] Figures 5A to 5D Cross-sectional views along the aa', bb', cc', and dd' directions after the formation of the third insulating layer are provided in an exemplary embodiment.

[0058] Figures 6A to 6D Cross-sectional views along the aa', bb', cc', and dd' directions after the formation of the first hole are provided in an exemplary embodiment; Figure 6E This is a schematic diagram showing the planar position of the first hole;

[0059] Figures 7A to 7D Cross-sectional views along the aa', bb', cc', and dd' directions after the sacrificial layer of the etched word line region is provided in an exemplary embodiment;

[0060] Figures 8A to 8D These are cross-sectional views along the aa', bb', cc', and dd' directions after forming a word line structure layer, respectively, provided in an exemplary embodiment.

[0061] Figures 9A to 9D These are cross-sectional views along the aa', bb', cc', and dd' directions after forming a word line, respectively, provided in an exemplary embodiment. Figure 9E This is a schematic diagram showing the planar position of the second hole;

[0062] Figures 10A to 10D Cross-sectional views along the aa', bb', cc', and dd' directions after the formation of the fourth insulating layer are provided in an exemplary embodiment.

[0063] Figures 11A to 11D The images are cross-sectional views along the aa', bb', cc', and dd' directions after the formation of the third hole, provided in an exemplary embodiment. Figure 11E This is a schematic diagram showing the planar location of the third hole;

[0064] Figures 12A to 12DCross-sectional views along the aa', bb', cc', and dd' directions after the formation of the first groove are provided in an exemplary embodiment;

[0065] Figures 13A to 13D Cross-sectional views along the aa', bb', cc', and dd' directions after the gate electrode is formed, respectively, provided in an exemplary embodiment;

[0066] Figures 14A to 14D Cross-sectional views along the aa', bb', cc', and dd' directions after disconnecting the gate electrodes of different layers, respectively, provided in an exemplary embodiment;

[0067] Figures 15A to 15D Cross-sectional views along the aa', bb', cc', and dd' directions after the formation of the fifth and sixth insulating layers, respectively, are provided in an exemplary embodiment.

[0068] Figures 16A to 16D Cross-sectional views along the aa', bb', cc', and dd' directions after the second trench is formed, respectively, provided in an exemplary embodiment;

[0069] Figures 17A to 17D These are cross-sectional views along the aa', bb', cc', and dd' directions after the second groove is formed, respectively, provided in an exemplary embodiment.

[0070] Figures 18A to 18D Cross-sectional views along the aa', bb', cc', and dd' directions after etching the gate electrode, respectively, provided in an exemplary embodiment;

[0071] Figures 19A to 19D Cross-sectional views along the aa', bb', cc', and dd' directions after the formation of the seventh insulating layer are provided in an exemplary embodiment.

[0072] Figures 20A to 20D Cross-sectional views along the aa', bb', cc', and dd' directions after etching away the fifth, sixth, and seventh insulating layers, respectively, according to an exemplary embodiment;

[0073] Figures 21A to 21D Cross-sectional views along the aa', bb', cc', and dd' directions after the formation of the gate insulating layer are provided in an exemplary embodiment.

[0074] Figures 22A to 22D Cross-sectional views along the aa', bb', cc', and dd' directions after the formation of the semiconductor layer and bit lines are provided in an exemplary embodiment.

[0075] Figures 23A to 23DCross-sectional views along the aa', bb', cc', and dd' directions after etching the first portion, respectively, provided in an exemplary embodiment;

[0076] Figures 24A to 24D Cross-sectional views along the aa', bb', cc', and dd' directions respectively, after etching the first portion, semiconductor layer, and gate insulating layer, as provided in an exemplary embodiment;

[0077] Figures 25A to 25D Cross-sectional views along the aa', bb', cc', and dd' directions after the second portion is formed, respectively, provided in an exemplary embodiment;

[0078] Figures 26A to 26D Cross-sectional views along the aa', bb', cc', and dd' directions after the second part of different layers is disconnected, respectively, according to an exemplary embodiment.

[0079] Figures 27A to 27D Cross-sectional views along the aa', bb', cc', and dd' directions after the dielectric layer is formed, respectively, provided in an exemplary embodiment;

[0080] Figures 28A to 28D Cross-sectional views along the aa', bb', cc', and dd' directions after the formation of the second pole are provided in an exemplary embodiment;

[0081] Figures 29A to 29D Cross-sectional views along the aa', bb', cc', and dd' directions after removing the eighth insulating layer, respectively, provided in an exemplary embodiment;

[0082] Figures 30A to 30D These are cross-sectional views along the aa', bb', cc', and dd' directions after forming the second preset pattern, respectively, provided in an exemplary embodiment.

[0083] Figures 31A to 31D Cross-sectional views along the aa', bb', cc', and dd' directions after the formation of the third insulating layer are provided in an exemplary embodiment.

[0084] Figures 32A to 32D Cross-sectional views along the aa', bb', cc', and dd' directions respectively, provided in an exemplary embodiment after the formation of the first hole and the second hole;

[0085] Figures 33A to 33D Cross-sectional views along the aa', bb', cc', and dd' directions after the sacrificial layer of the etched word line region is provided in an exemplary embodiment;

[0086] Figures 34A to 34DThese are cross-sectional views along the aa', bb', cc', and dd' directions after forming a word line structure layer, respectively, provided in an exemplary embodiment.

[0087] Figures 35A to 35D These are cross-sectional views along the aa', bb', cc', and dd' directions after the word lines have been formed, respectively, provided in an exemplary embodiment.

[0088] Figures 36A to 36D Cross-sectional views along the aa', bb', cc', and dd' directions after etching the third insulating layer, respectively, provided in an exemplary embodiment;

[0089] Figure 37 A cross-sectional view along the cc' direction after forming a word line structure layer, provided as an exemplary embodiment.

[0090] Figures 38A to 38D Cross-sectional views along the aa', bb', cc', and dd' directions after the fourth hole is formed, respectively, provided in an exemplary embodiment; Figure 38E This is a schematic diagram showing the planar location of the fourth hole;

[0091] Figures 39A to 39D These are cross-sectional views along the aa', bb', cc', and dd' directions after etching the sacrificial layer, respectively, provided in an exemplary embodiment.

[0092] Figures 40A to 40D Cross-sectional views along the aa', bb', cc', and dd' directions after forming a dummy layer, respectively, provided in an exemplary embodiment;

[0093] Figure 41 A cross-sectional view along the cc' direction after etching the dummy layer, provided as an exemplary embodiment.

[0094] Figure 42 A cross-sectional view along the cc' direction after the formation of the tenth insulating layer, provided as an exemplary embodiment.

[0095] Figures 43A to 43D These are cross-sectional views along the aa', bb', cc', and dd' directions after the formation of the third hole, provided in an exemplary embodiment.

[0096] Figures 44A to 44D Cross-sectional views along the aa', bb', cc', and dd' directions after the formation of the first sub-groove, respectively, are provided in an exemplary embodiment.

[0097] Figure 45 A cross-sectional view along the aa' direction after the formation of the second sub-groove, provided as an exemplary embodiment;

[0098] Figures 46A to 46DCross-sectional views along the aa', bb', cc', and dd' directions after the gate electrode is formed, respectively, provided in an exemplary embodiment;

[0099] Figures 47A to 47D Cross-sectional views along the aa', bb', cc', and dd' directions after the second trench is formed, respectively, provided in an exemplary embodiment;

[0100] Figures 48A to 48D Cross-sectional views along the aa', bb', cc', and dd' directions after etching the gate electrode, respectively, provided in an exemplary embodiment;

[0101] Figures 49A to 49D Cross-sectional views along the aa', bb', cc', and dd' directions after etching away the fifth and sixth insulating layers, respectively, according to an exemplary embodiment;

[0102] Figures 50A to 50D Cross-sectional views along the aa', bb', cc', and dd' directions after the formation of the second pole are provided in an exemplary embodiment;

[0103] Figures 51A to 51D These are cross-sectional views along the aa', bb', cc', and dd' directions after forming a word line, respectively, provided in an exemplary embodiment.

[0104] Figures 52A to 52D Cross-sectional views along the aa', bb', cc', and dd' directions after the formation of the fourth insulating layer are provided in an exemplary embodiment.

[0105] Figures 53A to 53D These are cross-sectional views along the aa', bb', cc', and dd' directions after forming a word line structure layer, respectively, provided in an exemplary embodiment.

[0106] Figures 54A to 54D These are cross-sectional views along the aa', bb', cc', and dd' directions after forming a word line structure layer, respectively, provided in an exemplary embodiment.

[0107] Figures 55A to 55D Cross-sectional views along the aa', bb', cc', and dd' directions after the second portion is formed, respectively, provided in an exemplary embodiment;

[0108] Figures 56A to 56D Cross-sectional views along the aa', bb', cc', and dd' directions after the second part of different layers is disconnected, respectively, according to an exemplary embodiment.

[0109] Figures 57A to 57DThese are cross-sectional views along the aa', bb', cc', and dd' directions after exposing the second portion, respectively, provided in an exemplary embodiment.

[0110] Figures 58A to 58D Cross-sectional views along the aa', bb', cc', and dd' directions after the formation of the second pole are provided in an exemplary embodiment;

[0111] Figures 59A to 59D These are cross-sectional views along the aa', bb', cc', and dd' directions after forming a word line, respectively, provided in an exemplary embodiment.

[0112] Figures 60A to 60D These are cross-sectional views along the aa', bb', cc', and dd' directions after the formation of the fourth insulating layer, respectively, provided in an exemplary embodiment. Detailed Implementation

[0113] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0114] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0115] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0116] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0117] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0118] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0119] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0120] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0121] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0122] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0123] The term "co-layered A and B" as used in this disclosure includes film layers formed of the same material or different materials located on the same film layer. For example, A and B are formed by forming the same film layer with the same material and then undergoing the same patterning process or different patterning processes. Co-layered A and B may be located on the same horizontal plane but not necessarily on the same film layer, or they may be located in different regions of the same film layer but not necessarily on the same horizontal plane.

[0124] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0125] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0126] Figure 1A A schematic plan view of a semiconductor device provided as an exemplary embodiment. Figures 1B to 1E respectively along Figure 1A Cross-sectional views along the aa', bb', cc', and dd' directions. (Example) Figures 1A to 1E As shown, this disclosure provides a semiconductor device, which may include a multilayer memory cell array vertically stacked on a substrate 1; the multilayer memory cell array may be distributed along a third direction Z. The third direction Z may be perpendicular to the substrate 1.

[0127] Each layer of the memory cell array may include multiple bit lines 30, multiple word lines 40, and multiple memory cells. The multiple memory cells of the memory cell array may be distributed along a first direction X and a second direction Y. The word lines 40 may be conductive lines extending along the second direction Y parallel to the substrate 1. Multiple word lines 40 of the same layer of the memory cell array may be spaced apart from each other, and the multiple word lines 40 may be distributed spaced apart along the first direction X parallel to the substrate 1. Word lines 40 of different layers of memory cell arrays may be stacked on the substrate 1, with word lines 40 at the same position in different layers spaced apart from each other.

[0128] The bit line 30 can extend along a third direction Z, and the bit line 30 can be arrayed on the substrate 1 along a first direction X and a second direction Y.

[0129] The memory cell may include a transistor and a capacitor connected to the transistor. The transistor may include a gate electrode 26, a first electrode 51, and a second electrode 52. The second electrode 52 may be part of a bit line 30, and the second electrodes 52 of transistors at the same location on different layers may be part of the same bit line 30. The gate electrodes 26 of memory cells in the same column of the same memory cell array may be connected to the same word line 40. The capacitor may include a first electrode 41 and a second electrode 42, which are insulated from each other by a dielectric layer 43.

[0130] In some embodiments, the word line 40 may include a plurality of independent connection electrodes distributed along a second direction Y. The plurality of connection electrodes of the same word line 40 are connected via the gate electrodes 26 of transistors distributed in the same column along the second direction Y.

[0131] In some embodiments, the plurality of connection electrodes can be connected to form a linear word line 40. The solution provided in this embodiment can make the semiconductor device compact and the process simple, but the embodiments disclosed herein are not limited thereto. The positions of the plurality of connection electrodes can be staggered, and the word line 40 formed by the connection does not have to be a straight line.

[0132] In some embodiments, the connection electrode may be connected to the region of the gate electrode 26 near the bit line 30.

[0133] The following description uses a semiconductor device comprising a group of memory cells stacked vertically at the same location as an example.

[0134] like Figures 1A to 1E As shown, this disclosure provides a semiconductor device, which may include:

[0135] Multiple transistors are stacked in different layers along the direction perpendicular to substrate 1;

[0136] Bit line 30 is connected to the plurality of transistors in the different layers and extends along a direction perpendicular to the substrate 1;

[0137] The transistor includes a gate electrode 26 and a semiconductor layer 23. The semiconductor layer 23 may include a first semiconductor sublayer 231 extending in a direction parallel to the substrate 1 and a second semiconductor sublayer 232 extending in a direction perpendicular to the substrate 1. The first semiconductor sublayer 231 may include a strip-shaped portion 2311 extending in a first direction X. The second semiconductor sublayer 232 is connected to the bit line 30. The gate electrode 26 extends in a direction parallel to the substrate 1 and surrounds the strip-shaped portion.

[0138] This embodiment provides a semiconductor device including a surrounding gate electrode, which can improve gate control capability and facilitate stacking.

[0139] In some embodiments, the second semiconductor sublayer 232 may surround the bit line 30. The surrounding may be a full surround, completely surrounding the sidewalls of the bit line 30, that is, the cross-section of the second semiconductor sublayer 232 may be a closed loop on a plane parallel to the substrate 1.

[0140] In some embodiments, on a plane perpendicular to the substrate 1 and the first direction X, the orthographic projection of the strip-shaped portion lies within the orthographic projection of the second semiconductor sublayer 232; the orthographic projection of the gate electrode 26 on the substrate 1 lies outside the orthographic projection of the second semiconductor sublayer 232 on the substrate 1. In this embodiment, the orthographic projection of the second semiconductor sublayer 232 lies outside the orthographic projection of the gate electrode 26. The second semiconductor layer 232 is the semiconductor layer 23 at the end of the transistor. The semiconductor layer 23 at the end is widened, which can form a structure similar to CAA, thereby improving the gate control capability.

[0141] In some embodiments, the first semiconductor sublayer 231 may further include an end portion 2312 disposed at one end of the strip portion 2311 away from the bit line 30. On a plane perpendicular to the substrate 1 and the first direction X, the orthographic projection of the strip portion 2311 lies within the orthographic projection of the end portion 2312, and the orthographic projection of the gate electrode 26 onto the substrate 1 lies outside the orthographic projection of the end portion 2312 onto the substrate 1. In this embodiment, the end portion 2312 of the semiconductor layer 23 is wider than the strip portion 2311, which can form a structure similar to a channel all around (CAA), improving gate control capability.

[0142] In some embodiments, the orthogonal projection of the gate electrode 26 onto the substrate 1 is located outside the orthogonal projection of the second semiconductor sublayer 232 onto the substrate 1.

[0143] In some embodiments, the end portion 2312 is provided with a first groove that opens away from the bit line 30, and the transistor further includes a first source / drain electrode 51, which fills the first groove. The solution provided in this embodiment can increase the contact area between the first source / drain electrode 51 and the semiconductor layer 23.

[0144] In some embodiments, the first source / drain electrode 51 may include a first portion 511 filling the first groove and a second portion 512 disposed on the side of the first groove opposite to the bit line 30, the second portion 512 overlapping the first portion 511. In this embodiment, the first source / drain electrode 51 may be divided into two parts, the first portion 511 and the second portion 512 may be manufactured separately, the first portion 511 may be deposited sequentially with the semiconductor layer 23 without needing to be formed after etching the semiconductor layer 23, thereby not damaging the contact surface between the first portion 511 and the semiconductor layer 23 and improving device performance.

[0145] In some embodiments, the semiconductor layers 23 of the plurality of transistors at the same location on different layers can be connected to form a single integrated structure. The solution provided in this embodiment can form a single vertically stacked semiconductor layer 23 of multiple transistors, simplifying the process, reducing costs, and facilitating the stacking of semiconductor devices with a large number of layers. In this case, the semiconductor layer 23 may include a longitudinal extension extending perpendicular to the substrate 1 and a plurality of lateral extensions extending horizontally from the longitudinal extension to multiple layers; the lateral extensions are the first semiconductor sublayer 231. The semiconductor layers 23 are formed into a single integrated structure by connecting them with second semiconductor sublayers 232.

[0146] In some embodiments, the transistors and capacitors of the same memory cell are arranged parallel to the first direction X. In memory cells of the same layer, the transistors and capacitors of adjacent memory cells along the first direction are arranged in opposite directions. The semiconductor layers 23 of memory cells that are adjacent along the first direction and whose transistors are close to each other are connected to form an integral structure. That is, two memory cells that are adjacent along the first direction are grouped together. The transistors of the memory cells in this group are close to each other, and the capacitors are away from each other. The semiconductor layers of the memory cells in this group can be formed at one time, thereby simplifying the process. Since the semiconductor layers 23 of the multiple transistors (referred to as a vertical column of transistors, which is different from a column of transistors in the same layer; in this disclosure, unless otherwise specified as a vertical column, they are all columns in the same layer) at the same position in different layers can be connected to form an integral structure, the semiconductor layers 23 of two vertical columns of transistors that are adjacent along the first direction X can form an integral structure.

[0147] In some embodiments, the semiconductor layer 23 of the integrated structure can be connected to the same bit line 30 and surround the connected bit line 30. In this case, a semiconductor thin film and a conductive thin film can be deposited sequentially in a hole to form the semiconductor layer 23 of multiple memory cells and the bit line 30 connected to the multiple memory cells at one time. In this embodiment, a portion of the bit line 30 serves as the second source / drain electrode 52 of the transistor.

[0148] In some embodiments, the transistor may further include a gate insulating layer 24 disposed between the gate electrode 26 and the semiconductor layer 23, wherein the gate electrode 26 and the semiconductor layer 23 are insulated from each other by the gate insulating layer 24.

[0149] In some embodiments, the gate insulating layers 24 of the plurality of transistors at the same location on different layers can be connected to form a single structure. In this embodiment, the gate insulating layers 24 of the stacked transistors can be formed in a single manufacturing process, simplifying the manufacturing process of devices with multiple transistor stacks.

[0150] In some embodiments, the gate insulating layers 24 of two adjacent vertical columns of transistors along the first direction X can be formed as a single structure. This embodiment can further simplify the manufacturing process of devices with multiple transistor stacks.

[0151] In some embodiments, the bit line 30 may extend along a direction perpendicular to the substrate 1, either in a straight line or a curved line. In some embodiments, the bit line 30 may be a straight line. The cross-section of the straight bit line 30 along the direction parallel to the substrate 1 may be the same everywhere or not exactly the same. This application does not limit the characteristics of the cross-section of the straight line.

[0152] In some embodiments, the cross-section of the bit line 30 in a plane parallel to the substrate 1 can be circular, square, elliptical, etc.

[0153] In some embodiments, the second portion 512 of the first source / drain electrode 51 also serves as the first electrode 41 of the capacitor. The second portion 512 of the first source / drain electrode 51 may be provided with a second groove with an opening away from the bit line 30. The second electrode 42 is insulated from the first source / drain electrode 51 through a dielectric layer 43 and fills the second groove.

[0154] In some embodiments, the second poles 42 of the capacitors of a plurality of vertical columns of memory cells arranged along the second direction can be connected to form an integral structure, and the second poles 42 of the integral structure may include a longitudinal sub-electrode that fills the trench between adjacent memory cells along the second direction and extends in a direction perpendicular to the substrate 1, and a plurality of lateral sub-electrodes that extend from the longitudinal sub-electrode to the second groove of each layer, each lateral sub-electrode corresponding to a memory cell.

[0155] In some embodiments, the second portion 512 of the first source / drain electrode 51 may not have a second groove and may be a block electrode. The second electrode 42 is provided with a third groove with an opening facing the bit line 30. The second portion 512 of the first source / drain electrode 51 is insulated from the second electrode 42 by a dielectric layer 43 and fills the third groove. Figure 2A and 2B As shown, Figure 2A A cross-sectional view of a semiconductor device along the aa' direction, provided for another exemplary embodiment. Figure 2BA cross-sectional view of a semiconductor device along the dd' direction is provided for another exemplary embodiment. In this embodiment, the transistor structure can refer to the previous embodiment and will not be repeated. The solution provided in this embodiment can increase the electrode area of ​​the capacitor, improve capacitance, and not increase the area occupied by the capacitor. In this embodiment, the second electrodes 42 of the capacitors of a plurality of vertical columns of memory cells arranged along the second direction can be connected to form an integral structure, and this integral structure fills the trenches between adjacent memory cells along the second direction to form a planar electrode. This planar electrode has a plurality of grooves, and the second portion 512 of the first source / drain electrode 51 is disposed in the groove and insulated from the planar electrode by the dielectric layer 43.

[0156] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. The "patterning process" mentioned in this embodiment includes deposition of a film layer, coating with photoresist, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of a film layer, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0157] In one exemplary embodiment, the fabrication process of the semiconductor device may include:

[0158] 101) Forming a stacked structure;

[0159] The formation of the stacked structure may include: sequentially and alternately depositing a first insulating film and a sacrificial layer film on the substrate 1 to form a stacked structure, such as... Figure 3A , Figure 3B , Figure 3C and Figure 3D As shown, where, Figure 3A A cross-sectional view along the aa' direction after forming a stacked structure, provided as an exemplary embodiment; Figure 3B This is a cross-sectional view along the bb' direction after the stacked structure has been formed. Figure 3C This is a cross-sectional view along the cc' direction after the stacked structure has been formed. Figure 3DThis is a cross-sectional view along the dd' direction after the stacked structure is formed. The stacked structure may include multiple stacks of alternating first insulating layers 10 and sacrificial layers 11.

[0160] In some embodiments, substrate 1 may be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate may be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material.

[0161] In some embodiments, the first insulating film and the sacrificial layer film can be deposited using a chemical vapor deposition method.

[0162] In some embodiments, the first insulating film may be a low-K dielectric layer, that is, a dielectric layer with a dielectric constant K not greater than 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2).

[0163] In some embodiments, the sacrificial layer film may be an insulating material different from the first insulating film, such as silicon nitride (SiN).

[0164] Figure 3A The stacked structure shown includes four first insulating layers 10 and three sacrificial layers 11. This is merely an example; in other embodiments, the stacked structure may include more or fewer alternating layers of first insulating layers 10 and sacrificial layers 11. The topmost first insulating layer 10 may use a different material than the other first insulating layers 10 as a hard mask layer.

[0165] 102) Etch the stacked structure to form a first preset pattern;

[0166] The etching of the plurality of stacked structures to form a first preset pattern may include:

[0167] A second insulating film is deposited to form a second insulating layer 13;

[0168] Using a mask with a first preset pattern, the stacked structure is etched to form the first preset pattern between the first insulating layer 10 and the sacrificial layer 11. The first preset pattern may include a memory cell region 100 and a word line region 200; the memory cell region 100 may extend along a first direction X, and the word line region 200 may extend along a second direction Y; the memory cell region 100 may include a capacitor region 101 and a transistor region 102, the capacitor region 101 being disposed on the side of the transistor region 102 away from the word line region 200, subsequently forming a capacitor in the capacitor region 101, forming a semiconductor layer 23, a gate electrode 26, etc., in the transistor region 102, and forming word lines 40 and bit lines 30 in the word line region 200. Figure 4A , Figure 4B, Figure 4C , Figure 4D and Figure 4E As shown, where, Figure 4A A cross-sectional view along the aa' direction after forming a first preset pattern, provided as an exemplary embodiment; Figure 4B This is a cross-sectional view along the bb' direction after the first preset shape has been formed. Figure 4C To form a cross-sectional view along the cc' direction after the first preset shape is formed. Figure 4D To form a cross-sectional view along the dd' direction after the first preset shape is formed. Figure 4E This is a schematic diagram showing the planar position of the first trench T1. (Example) Figure 4E As shown, the film layer in the first trench T1 is etched away, while the film layer in the remaining area is retained, forming the first preset pattern.

[0169] In some embodiments, the second insulating film may be an insulating material different from the first insulating film, including but not limited to SiN.

[0170] 103) Forming a third insulating layer 14;

[0171] The formation of the third insulating layer 14 may include: depositing a third insulating film on the substrate 1 on which the aforementioned structure is formed and polishing it to form a third insulating layer 14 filling the first trench T1; the third insulating layer 14 may be flush with the second insulating layer 13. Figure 5A , Figure 5B , Figure 5C and Figure 5D As shown, where, Figure 5A A cross-sectional view along the aa' direction after the formation of the third insulating layer 14, provided as an exemplary embodiment. Figure 5B The diagram shows a cross-sectional view along the bb' direction after the formation of the third insulating layer 14. Figure 5C This is a cross-sectional view along the cc' direction after the third insulating layer 14 has been formed. Figure 5D This is a cross-sectional view along the dd' direction after the formation of the third insulating layer 14. The third insulating layer 14 isolates the subsequently formed multiple memory cells.

[0172] In some embodiments, the third insulating film may be an insulating material different from the second insulating film, such as SiO2.

[0173] 104) Form the first hole K1;

[0174] The formation of the first hole K1 may include: forming a first hole K1 penetrating the third insulating layer 14 along a direction perpendicular to the substrate 1, wherein the sidewall of the first hole K1 exposes the sacrificial layer 11 of the word line region 200 but does not expose the sacrificial layer 11 of the memory cell region 100, such as... Figure 6A , Figure 6B , Figure 6C , Figure 6D and Figure 6E As shown, where, Figure 6A A cross-sectional view along the aa' direction after the formation of the first hole K1 is provided as an exemplary embodiment. Figure 6B To form the cross-sectional view along the bb' direction after the first hole K1 is formed, Figure 6C To form a cross-sectional view along the cc' direction after the first hole K1 is formed, Figure 6D To form a cross-sectional view along the dd' direction after the first hole K1 is formed, Figure 6E This is a schematic diagram showing the planar position of the first hole K1. (See diagram below.) Figure 6C As shown, the third insulating layer 14 is retained on both sides of the sacrificial layer 11 in the cc' direction. The sacrificial layer 11 is protected by the retained third insulating layer 14 to prevent it from being etched away when the sacrificial layer 11 of the word line area 200 is etched later.

[0175] 105) Sacrificial layer 11 in the etched letter line area 200;

[0176] The sacrificial layer 11 of the etched word line region 200 may include: introducing etching solution into the first hole K1, laterally etching away the sacrificial layer 11 of the word line region 200, but not removing all of the sacrificial layer 11 of the word line region 200, and not removing the sacrificial layer 11 located in the extension direction of the memory cell region 100, and the sacrificial layer 11 of the word line region 200 forming multiple segments spaced along the second direction Y, such as Figure 7A , Figure 7B , Figure 7C and Figure 7D As shown, where, Figure 7A A cross-sectional view along the aa' direction of the sacrificial layer 11 after etching the word line region 200, provided as an exemplary embodiment. Figure 7B This is a cross-sectional view along the bb' direction after the sacrificial layer 11 of the etched word line area 200 is formed. Figure 7C This is a cross-sectional view along the cc' direction after etching the sacrificial layer 11 of the word line area 200. Figure 7D This is a cross-sectional view along the dd' direction after the sacrificial layer 11 of the word line region 200 has been etched. It can be seen that in the aa' direction, the sacrificial layer 11 of the word line region 200 has not been etched away (the sacrificial layer 11 extends continuously along the first direction X).

[0177] 106) Forming a character line structure layer 40';

[0178] The formation of the word line structure layer 40' may include: depositing a first conductive thin film on the substrate 1 on which the aforementioned structure is formed to form the word line structure layer 40', wherein the word line structure layer 40' fills the area where the first hole K1 and the sacrificial layer 11 of the word line region 200 are laterally etched, such as Figure 8A , Figure 8B , Figure 8C and Figure 8D As shown, where, Figure 8AA cross-sectional view along the aa' direction after forming the word line structure layer 40', provided as an exemplary embodiment. Figure 8B This is a cross-sectional view along the bb' direction after forming the word line structure layer 40'. Figure 8C To form a cross-sectional view along the cc' direction after the word line structure layer 40' is formed, Figure 8D This is a cross-sectional view along the dd' direction after forming the word line structure layer 40'.

[0179] In some embodiments, the first conductive film may be one or more of the following different types of materials:

[0180] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can also be a metal alloy containing these metals.

[0181] Alternatively, it can be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); or metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0182] Alternatively, it could be polycrystalline silicon, conductive doped semiconductor materials, such as conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium, etc.; or other materials that exhibit conductivity.

[0183] The subsequent second to fifth conductive films are similar to the first conductive film and will not be described in detail.

[0184] 107) Forming character lines 40;

[0185] The formation of the word line 40 may include: etching away the word line structure layer 40' in the first hole K1, and forming a plurality of second holes K2 penetrating the word line structure layer 40' and the first insulating layer 10 along a direction perpendicular to the substrate 1, wherein the plurality of second holes K2 disconnect the word line structure layer 40' to form two independent word lines 40, such as... Figure 9A , Figure 9B , Figure 9C , Figure 9D and Figure 9E As shown, where, Figure 9A A cross-sectional view along the aa' direction after forming the word line 40, provided as an exemplary embodiment. Figure 9B To form a cross-sectional view along the bb' direction after the character line 40, Figure 9C To form a cross-sectional view along the cc' direction after word line 40, Figure 9D To form a cross-sectional view along the dd' direction after word line 40, Figure 9EThis is a schematic diagram showing the planar position of the second hole K2. The word line 40 includes multiple segments distributed along the second direction Y, and these segments are subsequently connected by the gate electrodes 26 of multiple transistors distributed along the second direction Y.

[0186] In some embodiments, the cross-section of the second hole K2 on a plane parallel to the substrate 1 is, for example, square.

[0187] 108) Forming the fourth insulating layer 15;

[0188] The formation of the fourth insulating layer 15 may include: depositing a fourth insulating film on the substrate 1 on which the aforementioned structure is formed, thereby forming the fourth insulating layer 15, wherein the fourth insulating layer 15 fills the first hole K1 and the second hole K2; as shown in the example. Figure 10A , Figure 10B , Figure 10C and Figure 10D As shown, where, Figure 10A A cross-sectional view along the aa' direction after the formation of the fourth insulating layer 15, provided as an exemplary embodiment. Figure 10B The diagram shows a cross-sectional view along the bb' direction after the fourth insulating layer 15 has been formed. Figure 10C This is a cross-sectional view along the cc' direction after the fourth insulating layer 15 has been formed. Figure 10D This is a cross-sectional view along the dd' direction after the fourth insulating layer 15 is formed.

[0189] In some embodiments, the fourth insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as SiO2.

[0190] 109) Formation of the third hole K3;

[0191] The formation of the third hole K3 may include: forming a third hole K3 that penetrates the stacked structure along a direction perpendicular to the substrate 1, such as... Figure 11A , Figure 11B , Figure 11C , Figure 11D and Figure 11E As shown, where, Figure 11A A cross-sectional view along the aa' direction after the formation of the third hole K3, provided as an exemplary embodiment. Figure 11B The cross-sectional view along the bb' direction after forming the third hole K3 is shown in the figure. Figure 11C To form a cross-sectional view along the cc' direction after forming the third hole K3, Figure 11D To form a cross-sectional view along the dd' direction after forming the third hole K3, Figure 11E This is a schematic diagram showing the planar location of the third hole K3. The third hole K3 can be located in the word line area 200, and it penetrates the first insulating layer 10 and the sacrificial layer 11. A bit line 30 can subsequently be formed within the third hole K3.

[0192] In some embodiments, the cross-section of the third hole K3 on a plane parallel to the substrate 1 can be square, circular, elliptical, etc.

[0193] 110) Form the first groove A1;

[0194] The formation of the first groove A1 may include: removing the sacrificial layer 11 of the transistor region 102 by lateral etching through the third hole K3 to form the first groove A1; at this time, the sacrificial layer 11 of the capacitor region 101 is retained, such as Figure 12A , Figure 12B , Figure 12C and Figure 12D As shown, where, Figure 12A A cross-sectional view along the aa' direction after the formation of the first groove A1, provided as an exemplary embodiment. Figure 12B The cross-sectional view along the bb' direction after the first groove A1 is formed. Figure 12C This is a cross-sectional view along the cc' direction after the first groove A1 is formed. Figure 12D This is a cross-sectional view along the dd' direction after the first groove A1 is formed. A gate electrode 26 is subsequently formed in the first groove A1.

[0195] In some embodiments, the sacrificial layer 11 can be removed by dry lateral etching, for example, by using free radicals generated by long-distance plasma to remove the sacrificial layer 11 of the transistor region 102 by long-distance dry lateral etching. The solution provided in this embodiment forms the semiconductor layer region in one step, reducing the number of photolithography and etching steps. However, this embodiment is not limited to this; the first groove A1 can be formed by other methods. However, this embodiment is not limited to this; the sacrificial layer 11 can be removed by wet lateral etching. Compared with wet etching, dry etching is faster and has better process controllability.

[0196] 111) Form gate electrode 26;

[0197] The gate electrode 26 may include: depositing a second conductive film on the substrate 1 forming the aforementioned structure to form a gate electrode 26 covering the inner wall of the first groove A1 and the inner wall of the third hole K3 (including the bottom wall and side wall of the third hole K3), such as Figure 13A , Figure 13B , Figure 13C and Figure 13D As shown, where, Figure 13A A cross-sectional view along the aa' direction after forming the gate electrode 26 is provided as an exemplary embodiment. Figure 13B This is a cross-sectional view along the bb' direction after the gate electrode 26 is formed. Figure 13C This is a cross-sectional view along the cc' direction after the gate electrode 26 is formed. Figure 13D This is a cross-sectional view along the dd' direction after the gate electrode 26 is formed.

[0198] In some embodiments, the gate electrode 26 can be formed using a high-temperature process to improve the electron mobility of the gate electrode 26. The solution provided in this embodiment forms the gate electrode 26 before forming the semiconductor layer 23. Compared to forming the gate electrode 26 after forming the semiconductor layer 23, this eliminates the need to consider damage to the semiconductor layer 23 caused by the high-temperature process. Therefore, the range of selectable materials and processes for the gate electrode 26 is wider, allowing for the selection of materials with better conductivity and the use of high-temperature processes to obtain a better crystal phase, thereby improving the conductivity of the gate electrode 26.

[0199] 112) Disconnect the gate electrodes 26 of different layers;

[0200] The process of disconnecting the gate electrodes 26 of different layers may include: etching away the gate electrode 26 located in the third hole K3 to disconnect the gate electrodes 26 of different layers, such as... Figure 14A , Figure 14B , Figure 14C and Figure 14D As shown, where, Figure 14A A cross-sectional view along the aa' direction after disconnecting the gate electrodes 26 of different layers, provided as an exemplary embodiment. Figure 14B This is a cross-sectional view along the bb' direction after disconnecting the gate electrodes 26 of different layers. Figure 14C This is a cross-sectional view along the cc' direction after the gate electrodes 26 of different layers are disconnected. Figure 14D This is a cross-sectional view along the dd' direction after the gate electrodes 26 of different layers are disconnected. At this time, the gate electrodes 26 are only distributed in the first groove A1.

[0201] In some embodiments, the gate electrode 26 in the third hole K3 can be removed by dry etching.

[0202] 113) Form the fifth insulating layer 16 and the sixth insulating layer 17;

[0203] After depositing a fifth insulating film on the substrate 1 that forms the aforementioned structure, the substrate is polished to form a fifth insulating layer 16 that fills the first groove A1 and the third hole K3.

[0204] A sixth insulating film is deposited to form a sixth insulating layer 17, as shown in the figure. Figure 15A , Figure 15B , Figure 15C and Figure 15D As shown, where, Figure 15A A cross-sectional view along the aa' direction provided for an exemplary embodiment after the formation of the fifth insulating layer 16 and the sixth insulating layer 17. Figure 15B The diagram shows a cross-sectional view along the bb' direction after the formation of the fifth insulating layer 16 and the sixth insulating layer 17. Figure 15C This is a cross-sectional view along the cc' direction after the fifth insulating layer 16 and the sixth insulating layer 17 have been formed. Figure 15DA cross-sectional view along the dd' direction after the formation of the fifth insulating layer 16 and the sixth insulating layer 17.

[0205] In some embodiments, the fifth insulating film may be a film layer with a higher etching selectivity than the first insulating film, such as SiN.

[0206] In some embodiments, the sixth insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as SiO2.

[0207] 114) Formation of the second trench T2;

[0208] The formation of the second trench T2 may include: forming a second trench T2 extending through the stacked structure in a direction perpendicular to the substrate 1 at one end of the capacitor region 101 away from the bit line 30, wherein the sidewalls of the second trench T2 expose the sacrificial layer 11 so that the sacrificial layer 11 of the capacitor region 101 can be subsequently removed, such as... Figure 16A , Figure 16B , Figure 16C and Figure 16D As shown, where, Figure 16A A cross-sectional view along the aa' direction after the formation of the second trench T2, provided as an exemplary embodiment. Figure 16B The diagram shows a cross-sectional view along the bb' direction after the formation of the second trench T2. Figure 16C This is a cross-sectional view along the cc' direction after the second trench T2 is formed. Figure 16D This is a cross-sectional view along the dd' direction after the formation of the second trench T2.

[0209] 115) Forming the second groove A2;

[0210] The formation of the second groove A2 may include: removing the sacrificial layer 11 of the capacitor region 101 by lateral etching of the second trench T2 to form the second groove A2, such as... Figure 17A , Figure 17B , Figure 17C and Figure 17D As shown, where, Figure 17A A cross-sectional view along the aa' direction after the formation of the second groove A2, provided as an exemplary embodiment. Figure 17B This is a cross-sectional view along the bb' direction after the second groove A2 has been formed. Figure 17C This is a cross-sectional view along the cc' direction after the second groove A2 has been formed. Figure 17D This is a cross-sectional view along the dd' direction after the second groove A2 is formed.

[0211] 116) Etch gate electrode 26;

[0212] The etching of the gate electrode 26 may include: etching away the sidewalls of the gate electrode 26 extending perpendicular to the substrate 1 (i.e., the bottom wall of the first groove A1), such that the gate electrode 26 forms a double-sided open annular film (previously a single-sided open annular film), as shown below. Figure 18A , Figure 18B , Figure 18C and Figure 18D As shown, where, Figure 18A A cross-sectional view along the aa' direction after etching the gate electrode 26, provided as an exemplary embodiment. Figure 18B This is a cross-sectional view along the bb' direction after etching the gate electrode 26. Figure 18C This is a cross-sectional view along the cc' direction after etching the gate electrode 26. Figure 18D This is a cross-sectional view along the dd' direction after etching the gate electrode 26.

[0213] In some embodiments, the sidewalls of the gate electrode 26 extending in a direction perpendicular to the substrate 1 can be removed by wet etching.

[0214] 117) Forming the seventh insulating layer 18;

[0215] The formation of the seventh insulating layer 18 may include: depositing a seventh insulating film on the substrate 1 on which the aforementioned structure is formed, thereby forming the seventh insulating layer 18, wherein the seventh insulating layer 18 fills the second trench T2 and the second recess A2, as shown below. Figure 19A , Figure 19B , Figure 19C and Figure 19D As shown, where, Figure 19A A cross-sectional view along the aa' direction after the formation of the seventh insulating layer 18, provided as an exemplary embodiment. Figure 19B The diagram shows a cross-sectional view along the bb' direction after the formation of the seventh insulating layer 18. Figure 19C This is a cross-sectional view along the cc' direction after the formation of the seventh insulating layer 18. Figure 19D This is a cross-sectional view along the dd' direction after the formation of the seventh insulating layer 18.

[0216] In some embodiments, the seventh insulating film may be a material with a high etching selectivity to the gate electrode 26, such as SiN, carbon, aluminum oxide (Al2O3), etc.

[0217] 118) Etching removes the fifth insulating layer 16, the sixth insulating layer 17, and the seventh insulating layer 18;

[0218] The etching removal of the fifth insulating layer 16, the sixth insulating layer 17 and the seventh insulating layer 18 may include: grinding or dry etching to remove the sixth insulating layer 17 to expose the fifth insulating layer 16;

[0219] The fifth insulating layer 16 (i.e., the fifth insulating layer 16 filling the first groove A1 and the third hole K3) and the seventh insulating layer 18 are removed by etching, as follows: Figure 20A , Figure 20B , Figure 20C and Figure 20D As shown, where, Figure 20A A cross-sectional view along the aa' direction after etching away the fifth insulating layer 16, the sixth insulating layer 17, and the seventh insulating layer 18, as provided in an exemplary embodiment. Figure 20B This is a cross-sectional view along the bb' direction after etching away the fifth insulating layer 16, the sixth insulating layer 17, and the seventh insulating layer 18. Figure 20C This is a cross-sectional view along the cc' direction after etching away the fifth insulating layer 16, the sixth insulating layer 17, and the seventh insulating layer 18. Figure 20D This is a cross-sectional view along the dd' direction after etching away the fifth insulating layer 16, the sixth insulating layer 17, and the seventh insulating layer 18. At this point, the third hole K3, the first groove A1, the second groove A2, and the second trench T2 are connected, facilitating the subsequent one-time formation of the bit line 30 and the semiconductor layer 23. In some embodiments, the fifth insulating layer 16 can be removed by wet etching.

[0220] 119) Forming a gate insulating layer 24;

[0221] The formation of the gate insulating layer 24 may include: depositing a gate insulating film on the substrate 1 on which the above structure is formed to form the gate insulating layer 24, such as... Figure 21A , Figure 21B , Figure 21C and Figure 21D As shown, where, Figure 21A A cross-sectional view along the aa' direction after the formation of the gate insulating layer 24 is provided as an exemplary embodiment. Figure 21B This is a cross-sectional view along the bb' direction after the gate insulating layer 24 has been formed. Figure 21C This is a cross-sectional view along the cc' direction after the gate insulating layer 24 has been formed. Figure 21D This is a cross-sectional view along the dd' direction after the gate insulating layer 24 is formed.

[0222] In some embodiments, the gate insulating film may comprise one or more high-K dielectric materials, such as dielectric materials with a dielectric constant K > 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following high-K materials: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc.

[0223] 120) Forming a first portion 511 of a semiconductor layer 23, a bit line 30, and a first source / drain electrode 51;

[0224] The formation of the first portion 511 of the semiconductor layer 23, bit line 30, and first source / drain electrode 51 may include: sequentially depositing a semiconductor thin film and a third conductive thin film on the substrate 1 forming the aforementioned structure to form the semiconductor layer 23, bit line 30, and the first portion 511 of the first source / drain electrode 51; wherein, the semiconductor layer 23 covers the surface of the gate insulating layer 24 and fills the first groove A1, the bit line 30 fills the third hole K3, the semiconductor layer 23 surrounds the bit line 30, the gate insulating layer 24 surrounds the semiconductor layer 23, the gate electrode 26 surrounds the gate insulating layer 24, and the first portion 511 of the first source / drain electrode 51 fills the second groove A2 and the second trench T2, and is disconnected from the bit line 30 (separated by the semiconductor layer 23), as shown. Figure 22A , Figure 22B , Figure 22C and Figure 22D As shown, where, Figure 22A A cross-sectional view along the aa' direction after the formation of semiconductor layer 23 and bit line 30, provided as an exemplary embodiment. Figure 22B A cross-sectional view along the bb' direction after the formation of semiconductor layer 23 and bit line 30. Figure 22C A cross-sectional view along the cc' direction after the formation of semiconductor layer 23 and bit line 30. Figure 22D A cross-sectional view along the dd' direction after the formation of semiconductor layer 23 and bit line 30.

[0225] In this embodiment, the thickness of the gate electrode 26 can be controlled so that the semiconductor layer 23 can fill the first groove A1 during the deposition of the semiconductor thin film.

[0226] In some embodiments, the semiconductor layer 23 widens at the end of the transistor (the end of the transistor region 102 near the capacitor region 101) to form a structure similar to a channel all around (CAA), ensuring the gate control capability at the end of the transistor.

[0227] In some embodiments, the material of the semiconductor layer 23 may be silicon or polycrystalline silicon with a band gap of less than 1.65 eV, or it may be a wide band gap material, such as a metal oxide material with a band gap of greater than 1.65 eV.

[0228] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0229] In some embodiments, the material of the metal oxide semiconductor layer or channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO4). Materials such as IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.

[0230] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0231] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0232] 121) Etch the first portion 511 of the first source / drain electrode 51;

[0233] The first portion 511 of the etched first source / drain electrode 51 may include:

[0234] An eighth insulating film is deposited to form an eighth insulating layer 19, which covers the stacked structure to protect the film layer in the third hole K3;

[0235] The first portion 511 in the second trench T2 is removed by dry etching, which facilitates subsequent lateral etching of the film layer in the second groove A2; as... Figure 23A , Figure 23B , Figure 23C and Figure 23D As shown, where, Figure 23A A cross-sectional view along the aa' direction after etching the first portion 511, provided as an exemplary embodiment. Figure 23B This is a cross-sectional view along the bb' direction after etching the first part 511. Figure 23CThis is a cross-sectional view along the cc' direction after etching the first part 511. Figure 23D This is a cross-sectional view along the dd' direction after etching the first part 511.

[0236] 122) Etch the first portion 511, the semiconductor layer 23, and the gate insulating layer 24;

[0237] The etching of the first portion 511, the semiconductor layer 23, and the gate insulating layer 24 may include: etching away the semiconductor layer 23 and the gate insulating layer 24 in the second trench T2, and etching a predetermined length of the first portion 511, the semiconductor layer 23, and the gate insulating layer 24 in the second groove A2, retaining a portion of the first portion 511, the semiconductor layer 23, and the gate insulating layer 24, such as... Figure 24A , Figure 24B , Figure 24C and Figure 24D As shown, where, Figure 24A A cross-sectional view along the aa' direction after etching the first portion 511, the semiconductor layer 23, and the gate insulating layer 24, provided as an exemplary embodiment. Figure 24B This is a cross-sectional view along the bb' direction after etching the first part 511, the semiconductor layer 23, and the gate insulating layer 24. Figure 24C This is a cross-sectional view along the cc' direction after etching the first portion 511, the semiconductor layer 23, and the gate insulating layer 24. Figure 24D This is a cross-sectional view along the dd' direction after etching the first part 511, the semiconductor layer 23 and the gate insulating layer 24.

[0238] The first source / drain electrode 51 contacts the semiconductor layer 23 through a first portion 511. Therefore, retaining the first portion 511 can improve the contact performance between the semiconductor layer 23 and the first source / drain electrode 51. If the first portion 511 is not retained, the semiconductor layer 23 is easily etched and damaged, and the semiconductor layer 23 directly contacts the subsequently formed first source / drain electrode 51, resulting in poorer contact performance compared to the contact performance between the first portion 511 and the semiconductor layer 23. The retained first portion 511 should be as small as possible to leave more space for the subsequent formation of the capacitor.

[0239] 123) Forming the second part 512 of the first source / drain electrode 51;

[0240] The formation of the second portion 512 of the first source / drain electrode 51 may include: depositing a fourth conductive thin film on the substrate 1 forming the aforementioned structure to form the second portion 512 of the first source / drain electrode 51, such as... Figure 25A , Figure 25B , Figure 25C and Figure 25D As shown, where, Figure 25A A cross-sectional view along the aa' direction after forming the second portion 512, provided as an exemplary embodiment. Figure 25B To form the cross-sectional view along the bb' direction after the second part 512, Figure 25C To form the cross-sectional view along the cc' direction after the second part 512, Figure 25D This is a cross-sectional view along the dd' direction after the second portion 512 is formed. The second portion 512 covers the inner wall of the second groove A2, connects to the first portion 511, and connects to the semiconductor layer 23, and is insulated from the gate electrode 26 through the gate insulating layer 24. The second portion 512 also covers the sidewall of the second trench T2, so that the second portions 512 of different layers are connected together at this time.

[0241] 124) Disconnect the second part 512 from the different layers;

[0242] The process of disconnecting the second portion 512 of different layers may include: etching away the second portion 512 located in the second trench T2 to disconnect the second portion 512 of different layers, such as... Figure 26A , Figure 26B , Figure 26C and Figure 26D As shown, where, Figure 26A A cross-sectional view along the aa' direction after disconnecting the second portion 512 of different layers, as provided in an exemplary embodiment. Figure 26B This is a cross-sectional view along the bb' direction after the second part 512 of different layers has been disconnected. Figure 26C This is a cross-sectional view along the cc' direction after the second part 512 of different layers has been disconnected. Figure 26D This is a cross-sectional view along the dd' direction after the second portion 512 of the different layers has been disconnected. The second portion 512 of the first source / drain electrode 51 also serves as the first electrode 41 of a capacitor.

[0243] 125) Forming a dielectric layer 43;

[0244] The formation of dielectric layer 43 may include: depositing a dielectric thin film on the substrate 1 on which the aforementioned structure is formed to form dielectric layer 43, such as... Figure 27A , Figure 27B , Figure 27C and Figure 27D As shown, where, Figure 27A A cross-sectional view along the aa' direction after the formation of dielectric layer 43, provided for an exemplary embodiment. Figure 27B This is a cross-sectional view along the bb' direction after the dielectric layer 43 has been formed. Figure 27C This is a cross-sectional view along the cc' direction after the dielectric layer 43 has been formed. Figure 27D This is a cross-sectional view along the dd' direction after the dielectric layer 43 is formed. The dielectric layer 43 covers the surface of the second portion 512 of the first source / drain electrode 51 away from the semiconductor layer 23, and covers the sidewalls and bottom wall of the second trench T2.

[0245] In some embodiments, the dielectric film may be a Low-K material, such as silicon oxide. Alternatively, it may be a High-K material. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0246] 126) Formation of the second pole 42;

[0247] The formation of the second electrode 42 may include: depositing a fifth conductive thin film on the substrate 1 on which the aforementioned structure is formed to form the second electrode 42, wherein the second electrode 42 fills the second trench T2 and the second recess A2, as shown below. Figure 28A , Figure 28B , Figure 28C and Figure 28D As shown, where, Figure 28A A cross-sectional view along the aa' direction after the formation of the second pole 42, provided as an exemplary embodiment. Figure 28B The diagram shows a cross-sectional view along the bb' direction after the formation of the second pole 42. Figure 28C To form a cross-sectional view along the cc' direction after the second pole 42 is formed, Figure 28D This is a cross-sectional view along the dd' direction after the formation of the second pole 42.

[0248] 127) Remove the eighth insulation layer 19;

[0249] The removal of the eighth insulating layer 19 may include: removing the eighth insulating layer 19 by grinding or etching to expose the bit line 30, facilitating the connection of other devices to the memory cell, such as... Figure 29A , Figure 29B , Figure 29C and Figure 29D As shown, where, Figure 29A A cross-sectional view along the aa' direction after removing the eighth insulating layer 19, provided as an exemplary embodiment. Figure 29B The diagram shows a cross-sectional view along the bb' direction after the eighth insulating layer 19 has been removed. Figure 29C This is a cross-sectional view along the cc' direction after the eighth insulating layer 19 has been removed. Figure 29D This is a cross-sectional view along the dd' direction after the eighth insulating layer 19 has been removed. However, the embodiments disclosed herein are not limited to this, and the eighth insulating layer 19 may not be removed depending on the needs of subsequent manufacturing processes.

[0250] In another exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0251] 201), same as 101), forming as Figures 3A to 3D The stacked structure shown.

[0252] 202) Etch the stacked structure to form a second preset pattern;

[0253] The etching of the plurality of stacked structures to form the second preset pattern may include:

[0254] A second insulating film is deposited to form a second insulating layer 13;

[0255] The stacked structure is etched to form a first trench T1 and a second hole K2 penetrating the stacked structure; the first trench T1 causes the first insulating layer 10 and the sacrificial layer 11 to form a second predetermined pattern; the first trench T1 defines a memory cell region 100 and a word line region 200, and the second hole K2 is disposed in the word line region 200, breaking the region where two adjacent word lines are located; the memory cell region 100 can extend along a first direction X, and the word line region 200 can extend along a second direction Y; as Figure 30A , Figure 30B , Figure 30C and Figure 30D As shown, where, Figure 30A A cross-sectional view along the aa' direction after forming a second preset pattern, provided as an exemplary embodiment; Figure 30B This is a cross-sectional view along the bb' direction after the second preset shape has been formed. Figure 30C To form a cross-sectional view along the cc' direction after the second preset shape is formed. Figure 30D This is a cross-sectional view along the dd' direction after forming the second preset shape.

[0256] 203) Forming a third insulating layer 14;

[0257] The formation of the third insulating layer 14 may include: depositing a third insulating film on the substrate 1 on which the aforementioned structure is formed and polishing it to form a third insulating layer 14 that fills the first trench T1 and the second hole K2; the third insulating layer 14 may be flush with the second insulating layer 13. Figure 31A , Figure 31B , Figure 31C and Figure 31D As shown, where, Figure 31A A cross-sectional view along the aa' direction after the formation of the third insulating layer 14, provided as an exemplary embodiment. Figure 31B The diagram shows a cross-sectional view along the bb' direction after the formation of the third insulating layer 14. Figure 31C This is a cross-sectional view along the cc' direction after the third insulating layer 14 has been formed. Figure 31D This is a cross-sectional view along the dd' direction after the formation of the third insulating layer 14. The third insulating layer 14 isolates the subsequently formed multiple memory cells.

[0258] 204) Form the first hole K1 and the second hole K2;

[0259] The formation of the first hole K1 and the second hole K2 may include: forming a first hole K1 and a second hole K2 penetrating the third insulating layer 14 along a direction perpendicular to the substrate 1, wherein the sidewall of the first hole K1 exposes the sacrificial layer 11 of the word line region 200 but does not expose the sacrificial layer 11 of the memory cell region 100, such as... Figure 32A , Figure 32B , Figure 32C and Figure 32D As shown, where, Figure 32A A cross-sectional view along the aa' direction after forming the first hole K1 and the second hole K2, provided as an exemplary embodiment. Figure 32B The diagram shows the cross-sectional view along the bb' direction after forming the first hole K1 and the second hole K2. Figure 32C To form a cross-sectional view along the cc' direction after forming the first hole K1 and the second hole K2, Figure 32D This is a cross-sectional view along the dd' direction after the formation of the first hole K1 and the second hole K2. (See diagram below.) Figure 32C As shown, the sacrificial layer 11 in the cc' direction is protected by the third insulating layer 14 and is not exposed, thus preventing the sacrificial layer 11 of the memory cell area 100 from being etched away when the sacrificial layer 11 of the word line area 200 is etched later.

[0260] 205) Sacrificial layer 11 in the etched letter line area 200;

[0261] The sacrificial layer 11 of the etched word line area 200 may include: introducing etching solution into the first hole K1, and laterally etching away the sacrificial layer located between the first hole K1 and the second hole K2, such as... Figure 33A , Figure 33B , Figure 33C and Figure 33D As shown, at this time, part of the sacrificial layer 11 of the word line region 200 is removed, and part of the sacrificial layer is not removed. That is, the sacrificial layer 11 located in the extension direction of the memory cell region 100 is not removed, and the sacrificial layer 11 of the word line region 200 forms multiple segments spaced along the second direction Y (similar to...). Figure 33C and Figure 33D The sacrificial layer 11 shown in the figure, wherein, Figure 33A A cross-sectional view along the aa' direction of the sacrificial layer 11 after etching the word line region 200, provided as an exemplary embodiment. Figure 33B This is a cross-sectional view along the bb' direction after the sacrificial layer 11 of the etched word line area 200 is formed. Figure 33C This is a cross-sectional view along the cc' direction after etching the sacrificial layer 11 of the word line area 200. Figure 33D This is a cross-sectional view along the dd' direction after the sacrificial layer 11 of the word line region 200 has been etched. It can be seen that in the aa' direction, the sacrificial layer 11 of the word line region 200 has not been etched away (in the aa' direction, the sacrificial layer 11 extends continuously along the first direction X).

[0262] 206) Forming a character line structure layer 40';

[0263] The formation of the word line structure layer 40' may include: depositing a first conductive thin film on the substrate 1 on which the aforementioned structure is formed to form the word line structure layer 40'. In this embodiment, the word line structure layer 40' fills the area where the first hole K1, the second hole K2, and the sacrificial layer 11 of the word line region 200 are laterally etched, such as... Figure 34A , Figure 34B , Figure 34C and Figure 34D As shown, where, Figure 34A A cross-sectional view along the aa' direction after forming the word line structure layer 40', provided as an exemplary embodiment. Figure 34B This is a cross-sectional view along the bb' direction after forming the word line structure layer 40'. Figure 34C To form a cross-sectional view along the cc' direction after the word line structure layer 40' is formed, Figure 34D This is a cross-sectional view along the dd' direction after forming the word line structure layer 40'.

[0264] 207) Forms a character line 40;

[0265] The formation of the word line 40 may include: etching away the word line structure layer 40' in the first hole K1 and the second hole K2 to form two independent word lines 40, such as Figure 35A , Figure 35B , Figure 35C and Figure 35D As shown, where, Figure 35A A cross-sectional view along the aa' direction after forming the word line 40, provided as an exemplary embodiment. Figure 35B To form a cross-sectional view along the bb' direction after the character line 40, Figure 35C To form a cross-sectional view along the cc' direction after word line 40, Figure 35D This is a cross-sectional view along the dd' direction after word line 40 is formed. Each word line 40 includes multiple segments distributed along the second direction Y, and these segments are subsequently connected by gate electrodes 26 of multiple transistors distributed along the second direction Y. Compared to the previous embodiment, the solution provided in this embodiment eliminates the need to etch the stack of metal and insulating film layers at the location of the second hole K2; direct metal etching is sufficient. This reduces the process difficulty compared to etching the stack of metal and insulating film layers. Furthermore, compared to the subsequent two embodiments, damage to the gate electrode can be avoided during word line truncation.

[0266] 208)~227), same as 108)~127), will not be repeated here.

[0267] The solution provided in this embodiment uses an alternative method to form the word line 40, which can avoid etching the metal insulating layer stack.

[0268] In another exemplary embodiment, the manufacturing process of a semiconductor device may include:

[0269] 301)~305), same as steps 101~105, to form as follows Figures 7A to 7D The structure shown;

[0270] 306) Etch the third insulating layer 14 to enlarge the first hole K1, so that the sidewalls of the first hole K1 expose the sacrificial layer 11 of the memory cell region 100, that is, etch away the third insulating layer 14 retained on both sides of the sacrificial layer 11 in the cc' direction in step 304, such as Figure 36A , Figure 36B , Figure 36C and Figure 36D As shown, where, Figure 36A A cross-sectional view along the aa' direction after etching the third insulating layer 14, provided as an exemplary embodiment. Figure 36B This is a cross-sectional view along the bb' direction after etching the third insulating layer 14. Figure 36C This is a cross-sectional view along the cc' direction after etching the third insulating layer 14. Figure 36D This is a cross-sectional view along the dd' direction after etching the third insulating layer 14.

[0271] 307) Forming a character line structure layer 40';

[0272] The formation of the word line structure layer 40' may include: depositing a first conductive thin film on the substrate 1 on which the aforementioned structure is formed to form the word line structure layer 40', wherein the word line structure layer 40' fills the area where the first hole K1 (the enlarged first hole K1 in step 306) and the sacrificial layer 11 of the word line region 200 is laterally etched, such as Figure 37 As shown, where, Figure 37 A cross-sectional view along the cc' direction after forming the word line structure layer 40' is provided for an exemplary embodiment. Cross-sectional views in the aa', bb', and dd' directions can be referenced. Figure 8A , Figure 8B and Figure 8D (The rest is omitted.)

[0273] 308) Formation of the fourth hole K4;

[0274] The formation of the fourth hole K4 may include: forming a fourth hole K4 penetrating the third insulating layer 14 along a direction perpendicular to the substrate 1, wherein the sidewalls of the fourth hole K4 expose the sacrificial layer 11 of the transistor region 102 but do not expose the sacrificial layer 11 of the capacitor region 101, and exposing the word line structure layer 40', such as Figure 38A , Figure 38B , Figure 38C , Figure 38D and Figure 38E As shown, where, Figure 38AA cross-sectional view along the aa' direction after the formation of the fourth hole K4, provided as an exemplary embodiment. Figure 38B The diagram shows the cross-sectional view along the bb' direction after the formation of the fourth hole K4. Figure 38C To form a cross-sectional view along the cc' direction after forming the fourth hole K4, Figure 38D To form a cross-sectional view along the dd' direction after forming the fourth hole K4, Figure 38E This is a schematic diagram showing the planar position of the fourth hole, K4.

[0275] 309) Etching the sacrificial layer 11;

[0276] The etched sacrificial layer 11 may include: the sacrificial layer 11 exposed by the sidewall of the fourth hole K4 through lateral etching via the fourth hole K4, such as... Figure 39A , Figure 39B , Figure 39C and Figure 39D As shown, where, Figure 39A A cross-sectional view along the aa' direction after etching the sacrificial layer 11, provided as an exemplary embodiment. Figure 39B This is a cross-sectional view along the bb' direction after etching the sacrificial layer 11. Figure 39C This is a cross-sectional view along the cc' direction after etching the sacrificial layer 11. Figure 39D This is a cross-sectional view along the dd' direction after etching the sacrificial layer 11.

[0277] 310) Forming a virtual layer 9;

[0278] The formation of the dummy layer 9 may include: depositing a dummy layer thin film on the substrate 1 on which the aforementioned structure is formed to form the dummy layer 9, wherein the dummy layer 9 fills the area where the fourth hole K4 and the sacrificial layer 11 etched away in step 309 are located, such as Figure 40A , Figure 40B , Figure 40C and Figure 40D As shown, where, Figure 40A A cross-sectional view along the aa' direction after forming the dummy layer 9, provided as an exemplary embodiment. Figure 40B To create a cross-sectional view along the bb' direction after establishing a dummy layer 9, Figure 40C To create a cross-sectional view along the cc' direction after creating the dummy layer 9, Figure 40D To form a cross-sectional view along the dd' direction after creating the dummy layer 9.

[0279] In some embodiments, the dummy layer film can be a material with a high etching selectivity ratio to the sacrificial layer film, such as polysilicon, spin-on carbon (SOC), etc.

[0280] 311) Etch to remove the dummy layer 9 in the fourth hole K4, such as Figure 41 As shown, Figure 41A cross-sectional view along the cc' direction after etching the dummy layer 9, provided for an exemplary embodiment. Cross-sectional views along the aa', bb', and dd' directions can be referenced. Figure 40A , Figure 40B and Figure 40D (The rest is omitted.)

[0281] 312) Form the tenth insulating layer 20;

[0282] The formation of the fourth insulating layer 20 may include: depositing a tenth insulating film to form a tenth insulating layer 20 that fills the fourth hole K4, such as... Figure 42 As shown, Figure 42 A cross-sectional view along the cc' direction after the formation of the tenth insulating layer 20 is provided for an exemplary embodiment. Cross-sectional views along the aa', bb', and dd' directions can be referenced. Figure 40A , Figure 40B and Figure 40D (The rest is omitted.)

[0283] 313) Formation of the third hole K3;

[0284] The formation of the third hole K3 may include: forming a third hole K3 that penetrates the stacked structure along a direction perpendicular to the substrate 1, such as... Figure 43A , Figure 43B , Figure 43C and Figure 43D As shown, where, Figure 43A A cross-sectional view along the aa' direction after the formation of the third hole K3, provided as an exemplary embodiment. Figure 43B The cross-sectional view along the bb' direction after forming the third hole K3 is shown in the figure. Figure 43C To form a cross-sectional view along the cc' direction after forming the third hole K3, Figure 43D This is a cross-sectional view along the dd' direction after the third hole K3 is formed. The third hole K3 can be located in the word line region 200, and the third hole K3 penetrates the first insulating layer 10 and the sacrificial layer 11. Subsequently, a bit line 30 can be formed within the third hole K3.

[0285] 314) Form the first sub-groove A11;

[0286] The formation of the first sub-groove A11 may include: removing the sacrificial layer 11 of the transistor region 102 by lateral etching through the third hole K3 to form the first sub-groove A1; at this time, the dummy layer 9 of the transistor region 102 is retained, and the sacrificial layer 11 of the capacitor region 101 is retained, as shown below. Figure 44A , Figure 44B , Figure 44C and Figure 44D As shown, where, Figure 44A A cross-sectional view along the aa' direction after the formation of the first sub-groove A11, provided as an exemplary embodiment. Figure 44BThis is a cross-sectional view along the bb' direction after the first sub-groove A11 has been formed. Figure 44C This is a cross-sectional view along the cc' direction after the formation of the first sub-groove A11. Figure 44D This is a cross-sectional view along the dd' direction after the formation of the first sub-groove A11.

[0287] In some embodiments, the sacrificial layer 11 can be removed by wet lateral etching.

[0288] 315) Forming the second sub-groove A12;

[0289] The formation of the second sub-groove A12 may include: laterally etching away the dummy layer 9 to form the second sub-groove A12. The first sub-groove A11 and the second sub-groove A12 are connected, and their combination constitutes the first groove A1. Figure 45 As shown, Figure 45 A cross-sectional view along the aa' direction after forming the second sub-groove A12, provided for an exemplary embodiment. Cross-sectional views along the bb', cc', and dd' directions can be referenced. Figure 44B , Figure 44C and Figure 44D (Details omitted here.) A gate electrode 26 can be formed subsequently in the first groove A1.

[0290] In some embodiments, the dummy layer 9 can be removed by wet etching.

[0291] The solution provided in this embodiment forms the first groove A1 through two-step selective etching. By utilizing the different etching rates of the sacrificial layer film and the dummy layer film, they act as barrier layers for each other. Compared with the solution of forming the first groove A1 through one-step etching, the dimensional uniformity of the device can be improved.

[0292] 316) Form gate electrode 26;

[0293] The gate electrode 26 may include: depositing a second conductive film on the substrate 1 that forms the aforementioned structure to form a gate electrode 26 covering the inner wall of the first groove A1 and the inner wall of the third hole K3 (including the bottom wall and side wall of the third hole K3);

[0294] Etching removes the gate electrode 26 located in the third hole K3 to disconnect the gate electrodes 26 in different layers; such as Figure 46A , Figure 46B , Figure 46C and Figure 46D As shown, where, Figure 46A A cross-sectional view along the aa' direction after forming the gate electrode 26 is provided as an exemplary embodiment. Figure 46B This is a cross-sectional view along the bb' direction after the gate electrode 26 is formed. Figure 46C This is a cross-sectional view along the cc' direction after the gate electrode 26 is formed. Figure 46DThis is a cross-sectional view along the dd' direction after the gate electrode 26 is formed.

[0295] 317) Forming the fifth insulating layer 16, the sixth insulating layer 17, and the second trench T2;

[0296] The formation of the fifth insulating layer 16, the sixth insulating layer 17 and the second trench T2 may include: depositing a fifth insulating film on the substrate 1 on which the aforementioned structure is formed and then grinding it flat to form a fifth insulating layer 16 that fills the first trench A1 and the third hole K3;

[0297] A sixth insulating film is deposited to form a sixth insulating layer 17 covering the stacked structure;

[0298] A second trench T2 is formed at one end of the capacitor region 101 away from the bit line 30, penetrating the stacked structure in a direction perpendicular to the substrate 1. The sidewalls of the second trench T2 expose the sacrificial layer 11 so that the sacrificial layer 11 of the capacitor region 101 can be subsequently removed, such as... Figure 47A , Figure 47B , Figure 47C and Figure 47D As shown, where, Figure 47A A cross-sectional view along the aa' direction after the formation of the second trench T2, provided as an exemplary embodiment. Figure 47B The diagram shows a cross-sectional view along the bb' direction after the formation of the second trench T2. Figure 47C This is a cross-sectional view along the cc' direction after the second trench T2 is formed. Figure 47D This is a cross-sectional view along the dd' direction after the formation of the second trench T2.

[0299] 318) Form the second groove A2 and etch the gate electrode 26;

[0300] The process of forming the second groove A2 and etching the gate electrode 26 may include: removing the sacrificial layer 11 of the capacitor region 101 by lateral etching through the second trench T2 to form the second groove A2.

[0301] Etching removes the sidewalls of the gate electrode 26 extending perpendicular to the substrate 1 (i.e., the bottom wall of the first groove A1), so that the gate electrode 26 forms a double-sided open annular film (previously a single-sided open annular film), as shown. Figure 48A , Figure 48B , Figure 48C and Figure 48D As shown, where, Figure 48A A cross-sectional view along the aa' direction after etching the gate electrode 26, provided as an exemplary embodiment. Figure 48B This is a cross-sectional view along the bb' direction after etching the gate electrode 26. Figure 48C This is a cross-sectional view along the cc' direction after etching the gate electrode 26. Figure 48D This is a cross-sectional view along the dd' direction after etching the gate electrode 26.

[0302] In some embodiments, the sidewalls of the gate electrode 26 extending in a direction perpendicular to the substrate 1 can be removed by wet etching.

[0303] 318) Etching removes the fifth insulating layer 16 and the sixth insulating layer 17;

[0304] The etching removal of the fifth insulating layer 16 and the sixth insulating layer 17 may include: depositing a seventh insulating film on the substrate 1 that forms the aforementioned structure to form a seventh insulating layer 18, wherein the seventh insulating layer 18 fills the second trench T2 and the second groove A2; the seventh insulating layer 18 is used to protect the gate electrode 26 when the sixth insulating layer 17 is subsequently removed.

[0305] The sixth insulating layer 17 is removed by grinding or dry etching to expose the fifth insulating layer 16;

[0306] The fifth insulating layer 16 (i.e., the fifth insulating layer 16 filling the first groove A1 and the third hole K3) and the seventh insulating layer 18 are removed by etching, as follows: Figure 49A , Figure 49B , Figure 49C and Figure 49D As shown, where, Figure 49A A cross-sectional view along the aa' direction after etching away the fifth insulating layer 16 and the sixth insulating layer 17, provided as an exemplary embodiment. Figure 49B This is a cross-sectional view along the bb' direction after etching away the fifth insulating layer 16 and the sixth insulating layer 17. Figure 49C This is a cross-sectional view along the cc' direction after etching away the fifth insulating layer 16 and the sixth insulating layer 17. Figure 49D This is a cross-sectional view along the dd' direction after etching away the fifth insulating layer 16 and the sixth insulating layer 17. At this point, the third hole K3, the first groove A1, the second groove A2, and the second trench T2 are connected, facilitating the subsequent one-time formation of the bit line 30 and the semiconductor layer 23.

[0307] Figures 49A to 49D The seventh insulating layer 18 is not shown; please refer to [reference needed]. Figures 19A to 19D The location of the seventh insulating layer 18 is shown in the figure.

[0308] Steps 319) to 327) are the same as steps 119) to 127), forming bit line 30, gate insulating layer 24, semiconductor layer 23, first source / drain electrode 51, dielectric layer 43, and second electrode 42, as follows. Figure 50A , Figure 50B , Figure 50C and Figure 50D As shown, Figure 50A A cross-sectional view along the aa' direction after the formation of the second pole 42, provided as an exemplary embodiment. Figure 50B The diagram shows a cross-sectional view along the bb' direction after the formation of the second pole 42. Figure 50C To form a cross-sectional view along the cc' direction after the second pole 42 is formed, Figure 50D This is a cross-sectional view along the dd' direction after etching away the fifth insulating layer 16 and the sixth insulating layer 17.

[0309] 328) Forms a character line 40;

[0310] The formation of the word line 40 may include: etching away the word line structure layer 40' in the first hole K1, and forming a plurality of second holes K2 penetrating the word line structure layer 40' and the first insulating layer 10 along a direction perpendicular to the substrate 1, wherein the plurality of second holes K2 disconnect the word line structure layer 40' to form two independent word lines 40, such as... Figure 51A , Figure 51B , Figure 51C and Figure 51D As shown, where, Figure 51A A cross-sectional view along the aa' direction after forming the word line 40, provided as an exemplary embodiment. Figure 51B To form a cross-sectional view along the bb' direction after the character line 40, Figure 51C To form a cross-sectional view along the cc' direction after word line 40, Figure 51D This is a cross-sectional view along the dd' direction after word line 40 is formed. The word line 40 includes multiple segments distributed along the second direction Y, and these segments are subsequently connected by the gate electrodes 26 of multiple transistors distributed along the second direction Y.

[0311] In some embodiments, the cross-section of the second hole K2 on a plane parallel to the substrate 1 is, for example, square.

[0312] 329) Forming the fourth insulating layer 15;

[0313] The formation of the fourth insulating layer 15 may include: depositing a fourth insulating film on the substrate 1 on which the aforementioned structure is formed, thereby forming the fourth insulating layer 15, wherein the fourth insulating layer 15 fills the first hole K1 and the second hole K2; as shown in the example. Figure 52A , Figure 52B , Figure 52C and Figure 52D As shown, where, Figure 52A A cross-sectional view along the aa' direction after the formation of the fourth insulating layer 15, provided as an exemplary embodiment. Figure 52B The diagram shows a cross-sectional view along the bb' direction after the fourth insulating layer 15 has been formed. Figure 52C This is a cross-sectional view along the cc' direction after the fourth insulating layer 15 has been formed. Figure 52D This is a cross-sectional view along the dd' direction after the fourth insulating layer 15 is formed.

[0314] In another exemplary embodiment, the manufacturing process of a semiconductor device may include:

[0315] Steps 401) to 407) are the same as steps 301) to 307), forming the following: Figure 53A , Figure 53B , Figure 53C and Figure 53D The structure shown, wherein, Figure 53A A cross-sectional view along the aa' direction after forming the word line structure layer 40', provided as an exemplary embodiment. Figure 53B This is a cross-sectional view along the bb' direction after forming the word line structure layer 40'. Figure 53C To form a cross-sectional view along the cc' direction after the word line structure layer 40' is formed, Figure 53D This is a cross-sectional view along the dd' direction after forming the word line structure layer 40'.

[0316] Steps 408) to 421), and steps 109) to 122), form bit line 30, gate electrode 26, gate insulating layer 24, semiconductor layer 23, and the first portion 511 of the first source / drain electrode 51, as shown. Figure 54A , Figure 54B , Figure 54C and Figure 54D ,in, Figure 54A A cross-sectional view along the aa' direction after forming the word line structure layer 40', provided as an exemplary embodiment. Figure 54B This is a cross-sectional view along the bb' direction after forming the word line structure layer 40'. Figure 54C To form a cross-sectional view along the cc' direction after the word line structure layer 40' is formed, Figure 54D This is a cross-sectional view along the dd' direction after forming the word line structure layer 40'.

[0317] 422) Forming the second part 512 of the first source / drain electrode 51;

[0318] The formation of the second portion 512 of the first source / drain electrode 51 may include: depositing a fourth conductive film on the substrate 1 forming the aforementioned structure to form the second portion 512 of the first source / drain electrode 51, wherein the second portion 512 fills the second groove A2, such as... Figure 55A , Figure 55B , Figure 55C and Figure 55D As shown, where, Figure 55A A cross-sectional view along the aa' direction after forming the second portion 512, provided as an exemplary embodiment. Figure 55B To form the cross-sectional view along the bb' direction after the second part 512, Figure 55C To form the cross-sectional view along the cc' direction after the second part 512, Figure 55DThis is a cross-sectional view along the dd' direction after the formation of the second portion 512. The second portion 512 is connected to the first portion 511, and to the semiconductor layer 23, and is insulated from the gate electrode 26 through the gate insulating layer 24. The second portion 512 also covers the sidewalls of the second trench T2, so that the second portions 512 of different layers are connected together at this time.

[0319] 423) Disconnect the second part of the different layers 512;

[0320] The process of disconnecting the second portion 512 of different layers may include: etching away the second portion 512 located in the second trench T2 to disconnect the second portion 512 of different layers, such as... Figure 56A , Figure 56B , Figure 56C and Figure 56D As shown, where, Figure 56A A cross-sectional view along the aa' direction after disconnecting the second portion 512 of different layers, as provided in an exemplary embodiment. Figure 56B This is a cross-sectional view along the bb' direction after the second part 512 of different layers has been disconnected. Figure 56C This is a cross-sectional view along the cc' direction after the second part 512 of different layers has been disconnected. Figure 56D This is a cross-sectional view along the dd' direction after the second portion 512 of the different layers has been disconnected. The second portion 512 of the first source / drain electrode 51 also serves as the first electrode 41 of a capacitor.

[0321] 424) Expose the second portion 512 of the first source / drain electrode 51;

[0322] The second portion 512 of the exposed first source / drain electrode 51 may include:

[0323] Etching removes the eighth insulating layer 19;

[0324] Etching removes the first insulating layer 10 and the third insulating layer 14 of the capacitor region 101, exposing the upper and lower surfaces of the second portion 512, as well as the three sidewalls extending perpendicular to the substrate 1 (i.e., the sidewalls other than the sidewall facing the semiconductor layer 23), such as... Figure 57A , Figure 57B , Figure 57C and Figure 57D As shown, where, Figure 57A A cross-sectional view along the aa' direction after exposing the second portion 512, provided as an exemplary embodiment. Figure 57B To expose the cross-sectional view along the bb' direction after the second part 512 is shown. Figure 57C To expose the cross-sectional view along the cc' direction after the second part 512 is exposed. Figure 57D This is a cross-sectional view along the dd' direction after exposing the second part 512.

[0325] 425) Forming a dielectric layer 43 and a second electrode 42;

[0326] The formation of dielectric layer 43 and second electrode 42 may include: depositing a dielectric thin film on substrate 1 on which the aforementioned structure is formed to form dielectric layer 43, wherein dielectric layer 43 covers the sidewall of the second portion 512 of the first source / drain electrode 51 away from the semiconductor layer 23, and covers the sidewall of the second portion 512 of the first source / drain electrode 51 extending in a direction perpendicular to substrate 1, and the upper and lower surfaces of the second portion 512 of the first source / drain electrode 51.

[0327] A fifth conductive film is deposited on the substrate 1 forming the aforementioned structure to form a second electrode 42. The second electrode 42 fills the region between the second trench T2 and the adjacent second portion 512 along the direction perpendicular to the substrate 1 (i.e., the region where the first insulating layer 10 was etched away in the previous step). Figure 58A , Figure 58B , Figure 58C and Figure 58D As shown, where, Figure 58A A cross-sectional view along the aa' direction after the formation of the second pole 42, provided as an exemplary embodiment. Figure 58B The diagram shows a cross-sectional view along the bb' direction after the formation of the second pole 42. Figure 58C To form a cross-sectional view along the cc' direction after the second pole 42 is formed, Figure 58D This is a cross-sectional view along the dd' direction after the formation of the second pole 42.

[0328] The solution provided in this embodiment forms an external capacitor. Compared with the internal capacitors of the aforementioned embodiments, the capacitor has a larger electrode area and a larger capacitance value while maintaining the same area occupied by the capacitor, thus improving the area utilization rate.

[0329] 426) Forms character line 40;

[0330] The formation of the word line 40 may include: etching away the word line structure layer 40' in the first hole K1, and forming a plurality of second holes K2 penetrating the word line structure layer 40' and the first insulating layer 10 along a direction perpendicular to the substrate 1, wherein the plurality of second holes K2 disconnect the word line structure layer 40' to form two independent word lines 40, such as... Figure 59A , Figure 59B , Figure 59C and Figure 59D As shown, where, Figure 59A A cross-sectional view along the aa' direction after forming the word line 40, provided as an exemplary embodiment. Figure 59B To form a cross-sectional view along the bb' direction after the character line 40, Figure 59C To form a cross-sectional view along the cc' direction after word line 40, Figure 59DThis is a cross-sectional view along the dd' direction after word line 40 is formed. The word line 40 includes multiple segments distributed along the second direction Y, and these segments are subsequently connected by the gate electrodes 26 of multiple transistors distributed along the second direction Y.

[0331] 427) Forming the fourth insulating layer 15;

[0332] The formation of the fourth insulating layer 15 may include: depositing a fourth insulating film on the substrate 1 on which the aforementioned structure is formed, thereby forming the fourth insulating layer 15, wherein the fourth insulating layer 15 fills the first hole K1 and the second hole K2; as shown in the example. Figure 60A , Figure 60B , Figure 60C and Figure 60D As shown, where, Figure 60A A cross-sectional view along the aa' direction after the formation of the fourth insulating layer 15, provided as an exemplary embodiment. Figure 60B The diagram shows a cross-sectional view along the bb' direction after the fourth insulating layer 15 has been formed. Figure 60C This is a cross-sectional view along the cc' direction after the fourth insulating layer 15 has been formed. Figure 60D This is a cross-sectional view along the dd' direction after the fourth insulating layer 15 is formed.

[0333] This disclosure provides a method for manufacturing a semiconductor device, the semiconductor device comprising: a plurality of transistors stacked in different layers along a direction perpendicular to a substrate; and bit lines, wherein the transistors include gate electrodes and semiconductor layers, including:

[0334] A stacked structure of alternating first insulating layers and sacrificial layers is formed on the substrate;

[0335] The stacked structure is patterned to form a word line area extending along a second direction and a plurality of memory cell areas extending along a first direction and spaced apart along the second direction; a trench extending along the first direction through the stacked structure is provided between any two adjacent memory cell areas.

[0336] A first hole is formed in the word line area, penetrating the stacked structure; a portion of each sacrificial layer is removed to form a plurality of first grooves communicating with the first hole;

[0337] A gate electrode is formed that covers the sidewall of the first groove;

[0338] A gate insulating film and a semiconductor film are sequentially deposited in the first groove and the first hole to form the gate insulating layer and the semiconductor layer of the transistor. The semiconductor layer fills the first groove and covers the bottom wall and side wall of the first hole. The gate insulating layer surrounds the semiconductor layer, and the gate electrode surrounds the gate insulating layer.

[0339] The bit line is formed by depositing a first conductive thin film within the first hole in which the semiconductor layer is formed.

[0340] In some embodiments, the method may further include:

[0341] The sacrificial layer of the storage cell area is removed to form a second groove that communicates with the first groove. The second groove is located on the side of the first groove away from the first hole.

[0342] The process of sequentially depositing a gate insulating film and a semiconductor film in the first groove and the first hole to form the gate insulating layer and the semiconductor layer of the transistor, wherein the semiconductor layer fills the first groove and covers the bottom wall and sidewall of the first hole, the gate insulating layer surrounds the semiconductor layer, and the gate electrode surrounds the gate insulating layer; and depositing a first conductive film in the first hole where the semiconductor layer is formed to form the bit line includes:

[0343] A gate insulating film, a semiconductor film, and a first conductive film are sequentially deposited in the second groove, the first groove, and the first hole, with the semiconductor film filling the first groove. The gate insulating film, the semiconductor film, and the first conductive film in the second groove are etched to a predetermined length to form the gate insulating layer, the semiconductor layer, and the bit line. The first conductive film retained in the second groove forms the first part of the first source / drain electrode of the transistor.

[0344] A second portion of the first source / drain electrode is formed within the second groove, and the second portion of the first source / drain electrode overlaps with the first portion of the first source / drain electrode.

[0345] In some embodiments, a second portion of the first source / drain electrode covers the bottom and sidewalls of the second groove; the method further includes: forming a second electrode that fills the second groove, and a dielectric layer disposed between the second electrode and the first source / drain electrode.

[0346] In some embodiments, a second portion of the first source / drain electrode fills the second groove; the method further includes exposing an outer wall of the second portion of the first source / drain electrode, the outer wall including an end face of the second portion of the first source / drain electrode facing away from the first portion of the first source / drain electrode, and each sidewall connected to the end face; forming a second pole surrounding the outer wall; and forming a dielectric layer disposed between the outer wall and the second pole.

[0347] In some embodiments, removing a portion of each of the sacrificial layers to form a plurality of first grooves communicating with the first hole includes:

[0348] Lateral etching is performed through the first hole to remove a portion of each of the sacrificial layers, forming a plurality of first grooves communicating with the first hole;

[0349] Alternatively, before forming the first hole, the first part of the sacrificial layer of each sacrificial layer is replaced with a dummy layer, and a second sacrificial layer exists between the dummy layer and the first hole; after etching away the second part of the sacrificial layer, the dummy layer is then etched away to form a plurality of first grooves communicating with the first hole.

[0350] In some embodiments, the method further includes:

[0351] A second hole is formed in each of the trenches, penetrating the stacked structure. The second hole exposes the sidewall of the sacrificial layer of the word line region but does not expose the sidewall of the sacrificial layer of the memory cell region. A plurality of third grooves are formed by laterally etching the sacrificial layer of the word line region through each of the second holes. The third grooves connect two adjacent second holes along a first direction.

[0352] A second conductive film is deposited and filled in the plurality of third grooves, and a third hole is formed in the word line area to penetrate the stacked structure. The third hole disconnects the second conductive film in each of the third grooves to form two disconnected connection electrodes. The connection electrodes are connected to the gate electrode. A plurality of connection electrodes distributed along the second direction are connected to form word lines through a plurality of gate electrodes distributed along the second direction.

[0353] Alternatively, a second hole is formed in each of the trenches, penetrating the stacked structure. The second hole exposes the sidewall of the sacrificial layer in the word line region but does not expose the sidewall of the sacrificial layer in the memory cell region. A plurality of third grooves are formed by laterally etching the sacrificial layer in the word line region through each of the second holes. The third grooves connect two adjacent second holes along a first direction. The second holes are enlarged along a second direction to expose the sidewall of the sacrificial layer located in the memory cell region.

[0354] A second conductive film is deposited and filled in the plurality of third grooves, and a third hole is formed in the word line region to penetrate the stacked structure. The third hole disconnects the second conductive film in each of the third grooves to form two disconnected connection electrodes. The connection electrodes are connected to the gate electrode. The plurality of connection electrodes distributed along the second direction are connected to form word lines through the plurality of gate electrodes distributed along the second direction.

[0355] In some embodiments, the method further includes:

[0356] When the stacked structure is patterned, multiple third holes that penetrate the stacked structure are also formed in the letter line area;

[0357] After the third hole and the trench are filled with a second insulating layer, a second hole is formed in each trench to penetrate the stacked structure, and the second insulating layer in the third hole is removed, wherein the second hole exposes the sidewall of the sacrificial layer of the word line area but does not expose the sidewall of the sacrificial layer of the memory cell area; a plurality of fourth grooves are formed by laterally etching the sacrificial layer of the word line area through each second hole and the third hole, the fourth grooves being disposed between the second hole and the third hole and communicating with the second hole and the third hole;

[0358] A second conductive film is deposited and filled in the plurality of fourth grooves to form a connection electrode, the connection electrode being connected to the gate electrode, and the plurality of connection electrodes distributed along the second direction are connected through the plurality of gate electrodes distributed along the second direction to form a word line.

[0359] This disclosure also provides an electronic device, including a semiconductor device formed by the manufacturing method of any of the foregoing embodiments or the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0360] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Multiple memory cells are stacked along the vertical substrate direction, distributed across different layers; Bit lines are connected to a plurality of memory cells in different layers and extend along a direction perpendicular to the substrate; The memory cell includes a capacitor and a transistor arranged parallel to a first direction. The transistor includes a gate electrode and a semiconductor layer. The semiconductor layer includes a first semiconductor sublayer extending parallel to the substrate and a second semiconductor sublayer connected to the first semiconductor sublayer and extending perpendicular to the substrate. The first semiconductor sublayer includes a strip-shaped portion extending parallel to the first direction of the substrate. The second semiconductor sublayer is connected to the bit line. The gate electrode extends parallel to the substrate and surrounds the strip-shaped portion. The bit line is disposed on the side of the first semiconductor sublayer away from the capacitor.

2. The semiconductor device according to claim 1, characterized in that, The second semiconductor sublayer surrounds the bit line.

3. The semiconductor device according to claim 1, characterized in that, On a plane perpendicular to the substrate and the first direction, the orthographic projection of the strip portion lies within the orthographic projection of the second semiconductor sublayer, and the orthographic projection of the gate electrode on the substrate lies outside the orthographic projection of the second semiconductor sublayer on the substrate.

4. The semiconductor device according to claim 1, characterized in that, The first semiconductor sublayer further includes an end portion disposed away from the bit line of the strip portion. On a plane perpendicular to the substrate and the first direction, the orthographic projection of the strip portion is located within the orthographic projection of the end portion, and the orthographic projection of the gate electrode on the substrate is located outside the orthographic projection of the end portion on the substrate.

5. The semiconductor device according to claim 4, characterized in that, The end is provided with a first groove with an opening away from the bit line, and the transistor further includes: a first source / drain electrode, the first source / drain electrode filling the first groove.

6. The semiconductor device according to claim 5, characterized in that, The first source / drain electrode includes a first portion that fills the first groove and a second portion disposed on the side of the first groove away from the bit line, the second portion overlapping the first portion.

7. The semiconductor device according to claim 6, characterized in that, The second portion of the first source / drain electrode is provided with a second groove with an opening opposite to the bit line. The capacitor includes a second electrode, which is insulated from the first source / drain electrode by a dielectric layer and fills the second groove.

8. The semiconductor device according to claim 6, characterized in that, The second part of the first source / drain electrode is a block electrode. The capacitor includes a second electrode with a third groove that opens toward the bit line. The second part of the first source / drain electrode is insulated from the second electrode by a dielectric layer and fills the third groove.

9. The semiconductor device according to claim 8, characterized in that, The semiconductor device includes a multilayer memory cell array distributed along a direction perpendicular to the substrate, wherein each layer of the memory cell array includes multiple rows and columns of memory cells distributed along a first direction and a second direction parallel to the substrate, multiple word lines extending along the second direction and spaced apart along a direction perpendicular to the substrate, and multiple bit lines extending along a direction perpendicular to the substrate and spaced apart along the second direction; the plurality of transistors are located on different layers and arranged in an array; the same word line includes multiple connection electrodes distributed along the second direction; the multiple connection electrodes of the same word line are connected through the gate electrodes of transistors in the same column distributed along the second direction; each bit line is connected to a transistor in at least one column of memory cells arranged perpendicular to the substrate.

10. The semiconductor device according to claim 9, characterized in that, The connecting electrode is connected to the region of the gate electrode near the bit line.

11. The semiconductor device according to claim 9, characterized in that, The semiconductor layers of the multiple transistors at the same location on different layers are connected to form an integral structure.

12. The semiconductor device according to claim 11, characterized in that, In the same layer of memory cells, the transistors and capacitors of adjacent memory cells along the first direction are arranged in opposite directions; the semiconductor layers of memory cells that are adjacent along the first direction and whose transistors are close to each other are connected to form an integrated structure.

13. The semiconductor device according to claim 12, characterized in that, The semiconductor layer of the monolithic structure is connected to the same bit line and surrounds the connected bit line.

14. A method for manufacturing a semiconductor device, characterized in that, The semiconductor device includes: a plurality of memory cells stacked on different layers along a direction perpendicular to the substrate, and bit lines; each memory cell includes a capacitor and a transistor arranged parallel to a first direction; the transistor includes a gate electrode and a semiconductor layer, comprising: A stacked structure of alternating first insulating layers and sacrificial layers is formed on the substrate; The stacked structure is patterned to form a word line region extending along a second direction parallel to the substrate and a plurality of memory cell regions extending along a first direction parallel to the substrate and spaced apart along the second direction; a trench extending along the first direction through the stacked structure is provided between any two adjacent memory cell regions. A first hole is formed in the word line area, penetrating the stacked structure; a portion of each sacrificial layer is removed to form a plurality of first grooves communicating with the first hole; A gate electrode is formed that covers the sidewall of the first groove; A gate insulating film and a semiconductor film are sequentially deposited in the first groove and the first hole to form the gate insulating layer and the semiconductor layer of the transistor. The semiconductor layer fills the first groove and covers the bottom wall and side wall of the first hole. The gate insulating layer surrounds the semiconductor layer, and the gate electrode surrounds the gate insulating layer. The bit line is formed by depositing a first conductive thin film within the first hole in which the semiconductor layer is formed.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that, The method further includes: The sacrificial layer of the storage cell area is removed to form a second groove that communicates with the first groove. The second groove is located on the side of the first groove away from the first hole. The process of sequentially depositing a gate insulating film and a semiconductor film in the first groove and the first hole to form the gate insulating layer and the semiconductor layer of the transistor, wherein the semiconductor layer fills the first groove and covers the bottom wall and sidewall of the first hole, the gate insulating layer surrounds the semiconductor layer, and the gate electrode surrounds the gate insulating layer; and depositing a first conductive film in the first hole where the semiconductor layer is formed to form the bit line includes: A gate insulating film, a semiconductor film, and a first conductive film are sequentially deposited in the second groove, the first groove, and the first hole, with the semiconductor film filling the first groove. The gate insulating film, the semiconductor film, and the first conductive film in the second groove are etched to a predetermined length to form the gate insulating layer, the semiconductor layer, and the bit line. The first conductive film retained in the second groove forms the first part of the first source / drain electrode of the transistor. A second portion of the first source / drain electrode is formed within the second groove, and the second portion of the first source / drain electrode overlaps with the first portion of the first source / drain electrode.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that, The second portion of the first source / drain electrode covers the bottom wall and sidewall of the second groove; the method further includes: forming a second electrode that fills the second groove, and a dielectric layer disposed between the second electrode and the first source / drain electrode.

17. The method for manufacturing a semiconductor device according to claim 15, characterized in that, The second portion of the first source / drain electrode fills the second groove; the method further includes exposing an outer wall of the second portion of the first source / drain electrode, the outer wall including an end face of the second portion of the first source / drain electrode facing away from the first portion of the first source / drain electrode, and each sidewall connected to the end face; forming a second pole surrounding the outer wall; and forming a dielectric layer disposed between the outer wall and the second pole.

18. The method for manufacturing a semiconductor device according to claim 14, characterized in that, The removal of the portion of each of the sacrificial layers to form a plurality of first grooves communicating with the first hole includes: Lateral etching is performed through the first hole to remove a portion of each of the sacrificial layers, forming a plurality of first grooves communicating with the first hole; Alternatively, before forming the first hole, the first part of the sacrificial layer of each sacrificial layer is replaced with a dummy layer, and a second part of the sacrificial layer exists between the dummy layer and the first hole; after etching away the second part of the sacrificial layer, the dummy layer is then etched away to form a plurality of first grooves communicating with the first hole.

19. The method for manufacturing a semiconductor device according to claim 14, characterized in that, The method further includes: A second hole is formed in each of the trenches, penetrating the stacked structure. The second hole exposes the sidewall of the sacrificial layer of the word line region but does not expose the sidewall of the sacrificial layer of the memory cell region. A plurality of third grooves are formed by laterally etching the sacrificial layer of the word line region through each of the second holes. The third grooves connect two adjacent second holes along a first direction. A second conductive film is deposited and filled in the plurality of third grooves, and a third hole is formed in the word line area to penetrate the stacked structure. The third hole disconnects the second conductive film in each of the third grooves to form two disconnected connection electrodes. The connection electrodes are connected to the gate electrode. A plurality of connection electrodes distributed along the second direction are connected to form word lines through a plurality of gate electrodes distributed along the second direction. Alternatively, a second hole is formed in each of the trenches, penetrating the stacked structure. The second hole exposes the sidewall of the sacrificial layer in the word line region but does not expose the sidewall of the sacrificial layer in the memory cell region. A plurality of third grooves are formed by laterally etching the sacrificial layer in the word line region through each of the second holes. The third grooves connect two adjacent second holes along a first direction. The second holes are enlarged along a second direction to expose the sidewall of the sacrificial layer located in the memory cell region. A second conductive film is deposited and filled in the plurality of third grooves, and a third hole is formed in the word line region to penetrate the stacked structure. The third hole disconnects the second conductive film in each of the third grooves to form two disconnected connection electrodes. The connection electrodes are connected to the gate electrode. The plurality of connection electrodes distributed along the second direction are connected to form word lines through the plurality of gate electrodes distributed along the second direction.

20. The method for manufacturing a semiconductor device according to claim 14, characterized in that, The method further includes: When the stacked structure is patterned, multiple third holes that penetrate the stacked structure are also formed in the letter line area; After the third hole and the trench are filled with a second insulating layer, a second hole is formed in each trench to penetrate the stacked structure, and the second insulating layer in the third hole is removed, wherein the second hole exposes the sidewall of the sacrificial layer of the word line area but does not expose the sidewall of the sacrificial layer of the memory cell area; a plurality of fourth grooves are formed by laterally etching the sacrificial layer of the word line area through each second hole and the third hole, the fourth grooves being disposed between the second hole and the third hole and communicating with the second hole and the third hole; A second conductive film is deposited and filled in the plurality of fourth grooves to form a connection electrode, the connection electrode being connected to the gate electrode, and the plurality of connection electrodes distributed along the second direction are connected through the plurality of gate electrodes distributed along the second direction to form a word line.

21. An electronic device, characterized in that, This includes the semiconductor device as described in any one of claims 1 to 13, or the semiconductor device formed by the semiconductor device manufacturing method as described in any one of claims 14 to 20.

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