Semiconductor device and method for manufacturing the same

Abstract

The present application relates to a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device includes: providing a substrate, on which a mask layer is formed, the mask layer exposing an area in the substrate where a high-resistance structure needs to be formed; using an ion implantation process to implant ions in the area; removing the mask layer and performing an annealing process to form an insulating buried layer in the area, and forming a crystalline layer on the insulating buried layer to form a high-resistance structure including the insulating buried layer and the crystalline layer. The semiconductor device includes a substrate and a high-resistance structure, and the high-resistance structure includes an insulating buried layer located in the substrate and a crystalline layer located on the insulating buried layer. The present application improves the uniformity of the resistance value of the high-resistance structure by forming a high-resistance structure in the substrate, helps to reduce the thickness of the interlayer dielectric layer formed subsequently, and reduces the parasitic capacitance and device power consumption of the semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In the general polysilicon gate process, the high resistor (HIR) is a resistor structure formed directly on polysilicon by ion doping. However, the resistance of the high resistor layer is easily affected by the critical dimension (CD) of polysilicon (poly) and the lightly doped drain structure (LDD), N+ plasma doping or P+ plasma doping, resulting in a large resistance variation of the high resistor layer.

[0003] In the existing high-k metal gate manufacturing process, after the high-k metal gate replaces the polysilicon gate, a high-resistance structure composed of oxide, titanium nitride (TiN) and silicon nitride (SiN) is deposited (depo), and then an inter-layer dielectric layer (ILD) is deposited to achieve the function of current shunting and voltage limiting. However, the above method will increase the thickness of the inter-layer dielectric layer formed, thereby increasing the parasitic capacitance and resistance of the semiconductor device. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor device and a manufacturing method thereof to improve the resistance uniformity of the high-resistance structure and reduce parasitic capacitance and power consumption of the semiconductor device.

[0005] In a first aspect, the present application provides a method for manufacturing a semiconductor device, comprising:

[0006] Providing a substrate, on which a mask layer is formed, the mask layer exposing an area in the substrate where a high-resistance structure needs to be formed;

[0007] Implanting ions into the region using an ion implantation process;

[0008] The mask layer is removed and an annealing process is performed to form an insulating buried layer in the region, and a crystal layer is formed on the insulating buried layer to form a high resistance structure including the insulating buried layer and the crystal layer.

[0009] In one embodiment, the ion implantation process includes at least one of a first ion implantation process and a second ion implantation process; wherein,

[0010] Performing the first ion implantation process at a first implantation angle to form a first ion implantation region in the region;

[0011] Performing the second ion implantation process at a second implantation angle to form a second ion implantation region in the region;

[0012] The inclination directions of the first ion implantation process and the second ion implantation process are opposite, and the first implantation angle is the angle formed by the implantation direction of the first ion implantation process and the surface direction of the substrate vertically injected, and the second implantation angle is the angle formed by the implantation direction of the second ion implantation process and the surface direction of the substrate vertically injected.

[0013] In one embodiment, a cross-sectional width of the region in a direction perpendicular to the surface of the substrate is the sum of a width of the first ion implantation region and a width of the second ion implantation region.

[0014] In one of the embodiments, when the implantation energy and the implantation dose of the ion implantation process remain unchanged, the resistance value of the high-resistance structure is adjusted by adjusting the implantation angle of the ion implantation process, and the implantation angle includes the first implantation angle and the second implantation angle.

[0015] In one of the embodiments, when the first implantation angle α is zero, the ion implantation process includes the first ion implantation process;

[0016] At the first injection angle α, In the case of , the ion implantation process includes the second ion implantation process;

[0017] At the first injection angle α, In the case of, the ion implantation process includes the first ion implantation process and the second ion implantation process, and the second implantation angle β satisfies the following condition:

[0018] ;

[0019] Wherein, L is the cross-sectional width of the region in a direction perpendicular to the surface of the substrate, H is the thickness of the mask layer, H1 is the implantation depth of the first ion implantation process, and H2 is the implantation depth of the second ion implantation process.

[0020] In one of the embodiments, the resistance of the high-resistance structure decreases as the first injection angle increases.

[0021] In one of the embodiments, when the implantation angle of the ion implantation process remains unchanged, the implantation depth of the ion implantation process is adjusted by adjusting the implantation energy and implantation dose of the ion implantation process, and the resistance value of the high-resistance structure decreases as the implantation depth increases.

[0022] In one embodiment, after forming the high resistance structure, the method for manufacturing the semiconductor device further includes:

[0023] forming a gate structure on the substrate at both sides of the high resistance structure;

[0024] forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the gate structure and the region;

[0025] A gate connector and a high resistance connector are formed in the interlayer dielectric layer. The gate connector penetrates the interlayer dielectric layer and connects the gate structure. The high resistance connector penetrates the interlayer dielectric layer and connects the high resistance structure.

[0026] In a second aspect, the present application further provides a semiconductor device, comprising:

[0027] substrate;

[0028] The high resistance structure comprises an insulating buried layer and a crystal layer, wherein the insulating buried layer is located in the substrate and the crystal layer is located on the insulating buried layer.

[0029] In one embodiment, the semiconductor device further includes:

[0030] A gate structure, disposed on the substrate at both sides of the high resistance structure;

[0031] An interlayer dielectric layer, disposed on the substrate and the gate structure;

[0032] A gate connector, penetrating the interlayer dielectric layer and connecting the gate structure;

[0033] A high resistance connecting piece penetrates the interlayer dielectric layer and connects the high resistance structure.

[0034] The unexpected effect of the present application is that by forming a high-resistance structure in the substrate, the uniformity of the resistance value of the high-resistance structure is improved, which helps to reduce the thickness of the interlayer dielectric layer formed subsequently, and reduces the parasitic capacitance and device power consumption of the semiconductor device.

[0035] Furthermore, the present application achieves resistance control of the subsequently formed high-resistance structure by controlling at least one of the implantation angle, implantation energy and implantation dose of the ion implantation process, thereby meeting the different resistance requirements of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 It is a structural schematic diagram of a high resistance structure in the related art.

[0038] Figure 2 A flowchart of a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0039] Figure 3 A structural schematic diagram corresponding to the step of providing a substrate in a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0040] Figure 4 A schematic structural diagram corresponding to the step of implanting ions into a substrate using an ion implantation process in a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0041] Figure 5 A structural schematic diagram corresponding to the step of forming a high-resistance structure in a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0042] Figure 6 A structural schematic diagram corresponding to the step of forming a gate structure in a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0043] Figure 7 A structural schematic diagram corresponding to the step of forming an interlayer dielectric layer in a method for manufacturing a semiconductor device provided in one of the embodiments of the present application.

[0044] Explanation of the reference numerals: 100 - semiconductor substrate; 110 - gate; 120 - interlayer dielectric structure; 130 - high resistance layer; 200 - substrate; 201 - region where a high resistance structure needs to be formed; 210 - mask layer; 220 - high resistance structure; 221 - buried insulating layer; 222 - crystalline layer; 230 - gate structure; 240 - interlayer dielectric layer; 241 - gate connector; 242 - high resistance connector. DETAILED DESCRIPTION

[0045] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0047] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0048] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0049] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0050] See also Figure 1 In a general high-k metal gate manufacturing process, after a gate 110 is formed on a semiconductor substrate 100, an interlayer dielectric structure 120 is formed on the semiconductor substrate 100 and the gate 110, and a high-resistance layer 130 (High Resistor, HIR) is formed in the interlayer dielectric structure 120 to achieve the purpose of current shunting and voltage limiting.

[0051] However, the method of forming the high resistance layer 130 in the interlayer dielectric structure 120 will increase the thickness of the interlayer dielectric structure, thereby increasing the parasitic capacitance and resistance of the semiconductor device.

[0052] In order to solve the above problems, the present application provides a semiconductor device and a manufacturing method thereof to improve the resistance uniformity of the high-resistance structure and reduce parasitic capacitance and power consumption of the semiconductor device.

[0053] Figure 2 A flowchart of a method for manufacturing a semiconductor device provided in one embodiment of the present application. Figure 2 One embodiment of the present application provides a method for manufacturing a semiconductor device, including steps S01 to S03.

[0054] Step S01: providing a substrate, on which a mask layer is formed, wherein the mask layer exposes a region of the substrate where a high-resistance structure needs to be formed.

[0055] Step S02: using an ion implantation process to implant ions into the region.

[0056] See also Figure 4 In one of the embodiments, the resistance value of the subsequently formed high-resistance structure can be controlled by adjusting the ion implantation conditions of the ion implantation process to meet the resistance value requirements under different process conditions.

[0057] Step S03: removing the mask layer and performing an annealing process to form an insulating buried layer in the region, and forming a crystalline layer on the insulating buried layer to form a high resistance structure including the insulating buried layer and the crystalline layer.

[0058] It should be noted that since the high-resistance structure is formed in the substrate, the ion implantation process or other related processes performed on other semiconductor structures on the surface of the substrate in the subsequent process flow has little effect on the resistance value of the high-resistance structure, thereby helping to improve the uniformity of the resistance value of the high-resistance structure in the semiconductor device.

[0059] The method for manufacturing a semiconductor device as described above improves the uniformity of the resistance value of the high-resistance structure by forming a high-resistance structure in the substrate, helps to reduce the thickness of the interlayer dielectric layer formed subsequently, and reduces the parasitic capacitance and device power consumption of the semiconductor device.

[0060] See also Figure 3 In one embodiment, the material of the substrate 200 includes silicon material, and the material of the mask layer 210 includes silicon nitride. In other embodiments of the present application, the material of the substrate 200 and the material of the mask layer 210 can be adjusted according to actual needs, and it is only necessary to ensure that the material selected for the substrate 200 can react with the ions injected in step S02 to generate a high-resistance structure, and the present application does not limit this.

[0061] See also Figure 4 In one embodiment, the ion implantation process includes at least one of a first ion implantation process and a second ion implantation process; wherein the first ion implantation process is performed at a first implantation angle to form a first ion implantation region in the region 201 where a high resistance structure is required to be formed; and the second ion implantation process is performed at a second implantation angle to form a second ion implantation region in the region 201. Optionally, oxygen ions are implanted in the region 201 during the ion implantation process.

[0062] It should be noted that the first ion implantation process and the second ion implantation process have opposite inclination directions so as to form adjacent first ion implantation regions and second ion implantation regions. The first implantation angle is the angle α formed by the implantation direction of the first ion implantation process and the surface direction of the substrate 200 vertically injected, and the second implantation angle is the angle β formed by the implantation direction of the second ion implantation process and the surface direction of the substrate 200 vertically injected.

[0063] Continue reading Figure 4 In one embodiment, according to common sense of mathematical geometry, the cross-sectional width L of the region 201 where the high-resistance structure needs to be formed along the surface direction perpendicular to the substrate 200 is the sum of the width L1 of the first ion implantation region and the width L2 of the second ion implantation region, that is, L=L1+L2.

[0064] In one of the embodiments, when the implantation energy (Energy) and implantation dose (Dosage) of the ion implantation process remain unchanged, the resistance value of the subsequently formed high-resistance structure is adjusted by adjusting the implantation angle of the ion implantation process, and the implantation angle includes a first implantation angle and a second implantation angle.

[0065] See also Figure 4 In one embodiment, when the first implantation angle α is zero (ie, α=0), the ion implantation process includes a first ion implantation process; when the first implantation angle α satisfies In the case where the ion implantation process includes a second ion implantation process; in the first implantation angle α satisfies In the case of , the ion implantation process includes a first ion implantation process and a second ion implantation process, and the second implantation angle β satisfies the following conditions:

[0066] ;

[0067] Wherein, L is the cross-sectional width of the region 201 in a direction perpendicular to the surface of the substrate 200 , H is the thickness of the mask layer 210 , H1 is the implantation depth of the first ion implantation process, and H2 is the implantation depth of the second ion implantation process.

[0068] Continue reading Figure 4 In one embodiment, since the implantation depth H1 of the first ion implantation region is less than the implantation depth H2 of the second ion implantation region, the resistance value of the subsequently formed high-resistance structure decreases as the first implantation angle increases. Exemplarily, when the first implantation angle α increases from zero to satisfy During the process, the resistance of the high-resistance structure decreases as the first injection angle α increases.

[0069] In one embodiment, when the implantation angle of the ion implantation process remains unchanged, the implantation depth of the ion implantation process is adjusted by adjusting the implantation energy and implantation dose of the ion implantation process, and the resistance value of the high-resistance structure decreases as the implantation depth increases. That is, the thickness and depth of the buried insulating layer are inversely correlated with the resistance value of the subsequently formed high-resistance structure.

[0070] It should be noted that since the resistance of the subsequently formed high-resistance structure is jointly determined by the insulating buried layer and the crystallization layer formed after the first ion implantation process and / or the second ion implantation process, the high-resistance structure is composed of a partial high-resistance structure formed in the first ion implantation area and a partial high-resistance structure formed in the second ion implantation area connected in series. Therefore, the resistance R of the high-resistance structure is the sum of the resistance R1 of the partial high-resistance structure formed in the first ion implantation area and the resistance R2 of the partial high-resistance structure formed in the second ion implantation area, that is, R=R1+R2.

[0071] Accordingly, the resistance of the high-resistance structure can be adjusted within a certain range by adjusting the injection angle in the above-mentioned ion injection process while other parameters remain unchanged. The resistance of the high-resistance structure can also be adjusted within a certain range by adjusting the injection dose and / or injection energy in the above-mentioned ion injection process while other parameters remain unchanged, thereby meeting different resistance requirements of the high-resistance structure.

[0072] At the same time, it should be emphasized that the resistance adjustment method of the high-resistance structure provided above is implemented under the premise that the cross-sectional width L of the region 201 where the high-resistance structure needs to be formed is fixed, so as to reduce the negative impact of the change of the cross-sectional width L of the region 201 in the subsequent process on the resistance uniformity of the high-resistance structure.

[0073] See also Figure 5 In one embodiment, a wet cleaning process is used to remove the mask layer 210, and then a high temperature annealing process is performed to make the oxygen ions implanted in the ion implantation process react with the silicon in the substrate 200, thereby forming an insulating buried layer 221 and a crystalline layer 222 to form a high resistance structure 220. The depth and thickness of the insulating buried layer 221 are determined by the implantation energy and implantation dose of the ion implantation process, and the crystalline layer 222 is formed in the substrate 200 and is located above the insulating buried layer 221.

[0074] In one embodiment, the buried insulating layer is a silicon dioxide layer, the crystal layer is a silicon material layer doped with oxygen ions, and the silicon material in a part of the crystal layer is combined with the oxygen ions to form silicon dioxide. That is, all silicon materials in the region where the buried insulating layer is located are combined with the oxygen ions to form silicon dioxide, so that the silicon dioxide distribution in the buried insulating layer is relatively uniform; while only part of the silicon material in the region where the crystal layer is located is combined with the oxygen ions, so that the silicon dioxide distribution in the crystal layer is uneven.

[0075] See also Figure 6 and Figure 7 In one embodiment, after forming the high resistance structure 220, the manufacturing method of the semiconductor device further includes: forming a gate structure 230 on the substrate 200 on both sides of the high resistance structure 220; forming an interlayer dielectric layer 240 on the substrate 200, the interlayer dielectric layer 240 covering the region 201 where the gate structure 230 and the high resistance structure 220 are located; forming a gate connector 241 and a high resistance connector 242 in the interlayer dielectric layer 240, the gate connector 241 penetrates the interlayer dielectric layer 240 and connects to the gate structure 230, and the high resistance connector 242 penetrates the interlayer dielectric layer 240 and connects to the high resistance structure 220.

[0076] In one embodiment, after the high resistance structure is formed, during the etching process of the metal silicide barrier layer, the oxide in the region where the high resistance structure is located is retained, and during the subsequent formation of silicide, no silicide is formed in the region where the high resistance structure is located.

[0077] In one embodiment, the gate structure 230 includes a metal gate (not labeled in the figure) and a high dielectric constant material layer covering the sidewalls of the metal gate to reduce or avoid the influence of the gate structure 230 on the resistance uniformity of the high resistance structure 220 .

[0078] Continue reading Figure 7 One embodiment of the present application further provides a semiconductor device, comprising: a substrate 200 and a high resistance structure 220; wherein the high resistance structure 220 comprises an insulating buried layer 221 and a crystal layer 222, wherein the insulating buried layer 221 is located in the substrate 200, and the crystal layer 222 is located on the insulating buried layer 221. In one embodiment, the insulating buried layer is a silicon dioxide layer, the crystal layer is a silicon material layer doped with oxygen ions, and silicon dioxide is formed in a partial region of the crystal layer.

[0079] See also Figure 7 In one embodiment, the semiconductor device further includes a gate structure 230, an interlayer dielectric layer 240, a gate connector 241 and a high-resistance connector 242, wherein the gate structure 230 is arranged on the substrate 200 on both sides of the high-resistance structure 220, the interlayer dielectric layer 240 is arranged on the substrate 200 and the gate structure 230, the gate connector 241 penetrates the interlayer dielectric layer 240 and connects the gate structure 230, and the high-resistance connector 242 penetrates the interlayer dielectric layer 240 and connects the high-resistance structure 220.

[0080] The unexpected effect of the present application is that by forming a high-resistance structure in the substrate, the uniformity of the resistance of the high-resistance structure is improved, which helps to reduce the thickness of the interlayer dielectric layer formed subsequently, and reduces the parasitic capacitance and device power consumption of the semiconductor device. Furthermore, the present application controls the resistance of the subsequently formed high-resistance structure by controlling at least one of the injection angle, injection energy and injection dose of the ion injection process, thereby meeting the different resistance requirements of the semiconductor device.

[0081] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0082] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0083] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the application. It should be noted that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, on which a mask layer is formed, the mask layer exposing an area in the substrate where a high-resistance structure needs to be formed; Implanting ions into the region using an ion implantation process, and adjusting the ion implantation conditions of the ion implantation process to achieve resistance control of the high-resistance structure; Removing the mask layer and performing an annealing process to form an insulating buried layer in the region, and forming a crystalline layer on the insulating buried layer to form a high resistance structure including the insulating buried layer and the crystalline layer; forming a gate structure on the substrate at both sides of the high resistance structure; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the gate structure and the region; A gate connector and a high resistance connector are formed in the interlayer dielectric layer. The gate connector penetrates the interlayer dielectric layer and connects the gate structure. The high resistance connector penetrates the interlayer dielectric layer and connects the high resistance structure.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The ion implantation process includes at least one of a first ion implantation process and a second ion implantation process; wherein, Performing the first ion implantation process at a first implantation angle to form a first ion implantation region in the region; Performing the second ion implantation process at a second implantation angle to form a second ion implantation region in the region; The inclination directions of the first ion implantation process and the second ion implantation process are opposite, and the first implantation angle is the angle formed by the implantation direction of the first ion implantation process and the surface direction of the substrate vertically injected, and the second implantation angle is the angle formed by the implantation direction of the second ion implantation process and the surface direction of the substrate vertically injected.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The cross-sectional width of the region in a direction perpendicular to the surface of the substrate is the sum of the width of the first ion implantation region and the width of the second ion implantation region.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: When the implantation energy and the implantation dose of the ion implantation process remain unchanged, the resistance value of the high-resistance structure is adjusted by adjusting the implantation angle of the ion implantation process, and the implantation angle includes the first implantation angle and the second implantation angle.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: At the first injection angle α When is zero, the ion implantation process includes the first ion implantation process; At the first injection angle α satisfy In the case of , the ion implantation process includes the second ion implantation process; At the first injection angle α satisfy In the case of, the ion implantation process includes the first ion implantation process and the second ion implantation process, and the second implantation angle β The following conditions must be met: ； in, L is the cross-sectional width of the region in a direction perpendicular to the surface of the substrate, H is the thickness of the mask layer, H 1 is the implantation depth of the first ion implantation process, H 2 is the implantation depth of the second ion implantation process.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The resistance value of the high-resistance structure decreases as the first injection angle increases.

7. The method for manufacturing a semiconductor device according to claim 3, wherein: When the implantation angle of the ion implantation process remains unchanged, the implantation depth of the ion implantation process is adjusted by adjusting the implantation energy and the implantation dose of the ion implantation process, and the resistance value of the high-resistance structure decreases as the implantation depth increases.

8. A semiconductor device, characterized in that: include: substrate; A high resistance structure, comprising an insulating buried layer and a crystal layer, wherein the insulating buried layer is located in the substrate, and the crystal layer is located on the insulating buried layer; A gate structure, disposed on the substrate at both sides of the high resistance structure; An interlayer dielectric layer, disposed on the substrate and the gate structure; A gate connector, penetrating the interlayer dielectric layer and connecting the gate structure; A high resistance connecting piece penetrates the interlayer dielectric layer and connects the high resistance structure.

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