Chip packaging structure and method for preparing chip packaging structure

Abstract

The present application relates to a chip packaging structure and a preparation method thereof, belonging to the technical field of chip packaging. The chip packaging structure includes a substrate, a support glue layer, a sensing chip, a wiring layer, a processing chip, a plastic package, and a first conductive pillar. The processing chip is mounted on the wiring layer and connected to a second pad, realizing electrical connection with the sensing chip. The sensing chip and the processing chip can be directly stacked, and the processing chip can be directly connected to the wiring layer. The wiring layer can be directly connected to the sensing chip through a stepped groove. Therefore, there is no need to re-wire outside the plastic package, reducing the transmission path between chips, improving the transmission speed, and further enhancing the chip performance. Moreover, the stepped groove also improves the bonding force between the wiring layer, the plastic package, and the sensing chip, avoiding warping and delamination.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology. Specifically, it relates to a chip packaging structure and a method for manufacturing the chip packaging structure. Background Art

[0002] The types and structures of sensing chips of sensors are constantly updated, and sensing chips such as charge-coupled devices (CCD: charge couple device), CMOS chips, and contact image sensors (CIS: contact image sensor) have been developed. Generally, in practical applications, the sensing chips need to be packaged to form sensor devices for use. Usually, the photosensitive chips need to be packaged together with the processor chips to meet the high performance of the sensor chips and achieve miniaturization. The packaged products have small sizes, excellent product performance, and fast signal processing speeds. The products are mainly applied to miniaturized and thin graphic processing terminal products.

[0003] Through research by the inventor, it is found that in the stacked structure formed by the sensor chip and the processing chip in the prior art, it usually needs to re-wire outside the plastic package. Both the sensor chip and the processing chip are connected to the external wiring layer through conductive posts, which results in a long transmission path between the sensor chip and the processing chip, and it is easy to have processing delays, which is not conducive to the improvement of device performance. Summary of the Invention

[0004] The purpose of this application is to provide a chip packaging structure and a method for manufacturing the chip packaging structure. The chip packaging structure and the method for manufacturing the chip packaging structure can form stacked chips, reduce the transmission path between the chips, improve the transmission speed, and thus improve the chip performance.

[0005] To achieve the above purpose, the present invention is realized through the following solutions:

[0006] In a first aspect, the present invention provides a chip packaging structure, including:

[0007] A substrate;

[0008] A support glue layer, which is disposed on the substrate and is provided with an induction groove;

[0009] A sensing chip, which is disposed on the support glue layer, and a sensing area and an electrical bump are provided on the front surface of the sensing chip. The electrical bump is bonded to the support glue layer, and the sensing area is correspondingly bonded to the induction groove;

[0010] A wiring layer, which is disposed on the back surface of the sensing chip and is electrically connected to the electrical bump, and a first pad and a second pad are provided on the wiring layer;

[0011] A processing chip, which is mounted on the wiring layer and connected to the second pad;

[0012] A plastic package, which is disposed on the wiring layer and covers the processing chip;

[0013] A first conductive pillar, which is embedded in the plastic package, connected to the first pad, spaced apart from the processing chip, and exposed from the plastic package;

[0014] Wherein, a stepped groove is provided on the back surface of the sensing chip, the stepped groove exposes the electrical bump, and the wiring layer extends to the side wall and the bottom wall of the stepped groove.

[0015] In an optional embodiment, the stepped groove has a first step and a second step, the distance between the first step and the substrate is greater than the distance between the second step and the substrate, and an opening exposing the electrical bump is further provided on the second step. The wiring layer covers the first step and the second step and extends into the opening to make electrical contact with the electrical bump.

[0016] In an optional embodiment, the second pad is disposed on the back surface of the sensing chip and spaced apart from the stepped groove, and the first pad is disposed on the first step and / or the second step so that the first conductive pillar is bonded to the first step and / or the second step.

[0017] In an optional embodiment, the first conductive pillars are disposed on at least two sides of the sensing chip, and one end of the first conductive pillar is bonded to the first step.

[0018] In an optional embodiment, a solder ball is further provided at the end of the first conductive pillar exposed from the plastic package.

[0019] In an optional embodiment, the wiring layer includes a first dielectric layer, a conductive layer, and a second dielectric layer. The first dielectric layer is disposed on the back surface of the sensing chip, the conductive layer is disposed on the first dielectric layer and makes electrical contact with the electrical bump, the second dielectric layer is disposed on the first dielectric layer and covers the conductive layer, and the first pad and the second pad are both disposed on the second dielectric layer and connected to the conductive layer.

[0020] In an optional embodiment, the second pad is disposed on the first step, the processing chip is flip-chip bonded to the back surface of the sensing chip, and a second conductive pillar is provided at the edge of the processing chip. The second conductive pillar is embedded in the plastic package and connected to the second pad.

[0021] In an alternative embodiment, the first pad is disposed on the back surface of the sensing chip and is spaced apart from the stepped groove, and the first conductive pillar is embedded in the plastic package and connected to the first pad.

[0022] In an alternative embodiment, an adhesive layer is further disposed on the area of the back surface of the sensing chip where no stepped groove is provided, and the processing chip is fixed to the back surface of the sensing chip through the adhesive layer.

[0023] In an alternative embodiment, a third conductive pillar is further disposed on the edge of the processing chip, a third pad is disposed on the wiring layer on the second step, and the third conductive pillar is embedded in the plastic package and connected to the third pad.

[0024] In an alternative embodiment, support pillars are disposed on the wiring layer on the first step and / or the second step, the support pillars extend in a direction away from the substrate, and are in clearance fit with the surface of the processing chip close to the substrate.

[0025] In an alternative embodiment, protection pillars are further disposed on the wiring layer on the first step and / or the second step, the protection pillars extend in a direction away from the substrate, are located outside the processing chip, and the protection pillars are in clearance fit with the side wall of the processing chip.

[0026] In a second aspect, the present invention provides a method for manufacturing a chip package structure for manufacturing the chip package structure as described in the foregoing embodiments, the manufacturing method comprising:

[0027] Providing a substrate;

[0028] Forming a support glue layer on the substrate and forming a sensing groove on the support glue layer;

[0029] Bonding a wafer on the support glue layer, wherein the wafer includes a plurality of sensing chips, a sensing area and electrical bumps are disposed on the front surface of the sensing chip, the electrical bumps are bonded to the support glue layer, and the sensing area is correspondingly bonded to the sensing groove;

[0030] Etching the wafer and forming a stepped groove on the back surface of the sensing chip, wherein the stepped groove exposes the electrical bumps;

[0031] Forming a wiring layer on the wafer, wherein the wiring layer extends to the side wall and the bottom wall of the stepped groove, and a first pad and a second pad are disposed on the wiring layer;

[0032] Mounting a processing chip on the wiring layer, wherein the processing chip is connected to the second pad;

[0033] A molding body is formed on the wiring layer, wherein the molding body encapsulates the processing chip;

[0034] A first conductive pillar is formed in the molding body, wherein the first conductive pillar is connected to the first pad, and the first conductive pillar is spaced apart from the processing chip and exposed from the molding body.

[0035] Through the above technical solution, the chip packaging structure and its manufacturing method provided by the embodiments of the present invention form a support glue layer on the substrate. The support glue layer is provided with an induction groove. At the same time, the induction chip is arranged on the support glue layer, and the induction area corresponds to the induction groove. The electrical bumps are joined downward to the support glue block. At the same time, a step groove is formed on the back surface of the induction chip, and the step groove can expose the electrical bumps. In addition, a wiring layer is further arranged on the back surface of the induction chip. The wiring layer extends to the side wall and the bottom wall of the step groove and is in electrical contact with the electrical bumps to achieve electrical connection with the induction chip. The first conductive pillar is embedded in the molding body and connected to the first pad on the wiring layer, so as to achieve electrical connection with the wiring layer. The processing chip is mounted on the wiring layer and connected to the second pad, realizing electrical connection with the induction chip. Compared with the prior art, the embodiments of the present invention can directly stack the induction chip and the processing chip, and the processing chip can be directly connected to the wiring layer. The wiring layer can be directly connected to the induction chip through the step groove arrangement. Therefore, there is no need to re-wire outside the molding body, reducing the transmission path between the chips, improving the transmission speed, and further improving the chip performance. Moreover, the step groove arrangement also improves the bonding force between the wiring layer, the molding body, and the induction chip, avoiding warping and delamination.

[0036] Other features and advantages of the present application will be described in detail in the subsequent specific implementation part. Brief Description of the Drawings

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0038] Figure 1 A front view of the chip packaging structure provided by the first embodiment of the present application;

[0039] Figure 2 A top view of the chip packaging structure provided by the first embodiment of the present application;

[0040] Figures 3 to 9 A process flow chart of the manufacturing method of the chip packaging structure provided by the first embodiment of the present application;

[0041] Figure 10 The front view of the chip packaging structure provided by the second embodiment of the present application;

[0042] Figure 11 The top view of the chip packaging structure provided by the second embodiment of the present application;

[0043] Figure 12 The schematic diagram of the chip packaging structure provided by the third embodiment of the present application;

[0044] Figure 13 The schematic diagram of the chip packaging structure provided by the fourth embodiment of the present application.

[0045] Icon:

[0046] 100 - Chip packaging structure; 110 - Substrate; 120 - Support glue layer; 121 - Induction groove; 130 - Induction chip; 131 - Induction area; 132 - Electrical bump; 133 - Adhesive glue layer; 140 - Wiring layer; 141 - First dielectric layer; 142 - Conductive layer; 143 - Second dielectric layer; 150 - Processing chip; 151 - Second pad; 152 - Second conductive column; 153 - Third conductive column; 154 - Support column; 155 - Protection column; 156 - Third pad; 160 - Plastic package; 170 - First conductive column; 171 - First pad; 172 - Solder ball; 180 - Step groove; 181 - First step; 182 - Second step. Detailed implementation manners

[0047] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and illustrated herein can be arranged and designed in various different configurations.

[0048] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of this application is usually placed during use. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to the present application. In addition, terms such as "first", "second", etc. are only used for descriptive distinction and cannot be construed as indicating or implying relative importance.

[0049] In the description of the present application, it should also be noted that unless otherwise clearly specified and defined, the terms "arrangement" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium, and can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0050] As disclosed in the background art, in the existing induction packaging structure, it usually requires re-wiring outside the plastic package body. Both the sensor chip and the processing chip are connected to the external wiring layer through conductive posts, which results in a relatively long transmission path between the sensor chip and the processing chip passing through the conductive posts twice, and it is easy to have processing delays, which is not conducive to the improvement of device performance.

[0051] Furthermore, in the existing technology, the wiring layer and the plastic package body are in planar contact, resulting in a poor bonding force between the two, and the plastic package body or the wafer is prone to warping, which in turn leads to delamination between the wiring layer and the plastic package body, affecting the structural stability of the device. Moreover, the stacked structure of the processing chip and the induction chip in the existing technology has poor structural stability.

[0052] To solve the above problems, the embodiments of the present invention provide a novel chip packaging structure and a preparation method of the chip packaging structure. It should be noted that, without conflict, the features in the embodiments of the present application can be combined with each other.

[0053] First Embodiment

[0054] See Figure 1 and Figure 2 The chip packaging structure 100 provided by the embodiments of the present invention can form stacked chips, and can reduce the transmission path between the chips, improve the transmission speed, and thus improve the chip performance.

[0055] The chip packaging structure 100 provided by the embodiment of the present invention includes a substrate 110, a support glue layer 120, a sensing chip 130, a wiring layer 140, a processing chip 150, a plastic package 160, and a first conductive column 170. The support glue layer 120 is disposed on the substrate 110 and is provided with a sensing groove 121; the sensing chip 130 is disposed on the support glue layer 120, and a sensing area 131 and an electrical bump 132 are provided on the front surface of the sensing chip 130. The electrical bump 132 is bonded to the support glue layer 120, and the sensing area 131 is correspondingly bonded to the sensing groove 121; the wiring layer 140 is disposed on the back surface of the sensing chip 130 and is electrically connected to the electrical bump 132, and a first pad 171 and a second pad 151 are provided on the wiring layer 140; the processing chip 150 is mounted on the wiring layer 140 and is connected to the second pad 151; the plastic package 160 is disposed on the wiring layer 140 and covers the processing chip 150; the first conductive column 170 is embedded in the plastic package 160 and is connected to the first pad 171, and the first conductive column 170 is spaced from the processing chip 150 and exposed from the plastic package 160; wherein, a stepped groove 180 is provided on the back surface of the sensing chip 130, the stepped groove 180 exposes the electrical bump 132, and the wiring layer 140 extends to the side wall and the bottom wall of the stepped groove 180.

[0056] In this embodiment, the substrate 110 may be glass, silicon, a polymer composite material, a metal material, etc. The sensing chip 130 may be an image sensing chip, and its sensing area 131 corresponds to the sensing groove 121 on the support glue layer 120. At this time, the substrate 110 needs to be made of a transparent material. Or, the sensing chip 130 may also be a gyroscope, a capacitive sensing chip 130, etc. At this time, the substrate 110 may be made of an opaque material. Among them, the support glue layer 120 may be a thermosetting glue layer, and a polymer composite material such as epoxy resin, polyimide, or benzocyclobutene is used. The support glue layer 120 can fix the wafer, and multiple sensing chips 130 may be distributed on the wafer. The embodiment of the present invention can directly stack the sensing chip 130 and the processing chip 150, and the processing chip 150 can be directly connected to the wiring layer 140. The wiring layer 140 can be directly connected to the sensing chip 130 through the stepped groove. Therefore, there is no need to re-wire outside the plastic package 160, reducing the transmission path between the chips, improving the transmission speed, and thus improving the chip performance. Moreover, the stepped groove setting also improves the bonding force between the wiring layer 140, the plastic package 160, and the sensing chip 130, avoiding warping and delamination.

[0057] In this embodiment, the stepped groove 180 has a first step 181 and a second step 182. The distance between the first step 181 and the substrate 110 is greater than the distance between the second step 182 and the substrate 110. An opening for exposing the electrical bump 132 is further provided on the second step 182. The wiring layer 140 covers the first step 181 and the second step 182 and extends into the opening to make electrical contact with the electrical bump 132. Specifically, the first step 181 and the second step 182 can be formed by two grooving processes, and the notch sizes in the two grooving processes are different, so that the staggeredly arranged first step 181 and second step 182 can be formed. At the same time, the second step 182 can be further grooved to expose the electrical bump 132, so as to ensure that the wiring layer 140 is laid on the first step 181 and the second step 182 and realizes electrical contact with the electrical bump 132. Among them, the setting of the first step 181 and the second step 182 adopts two grooving processes with different sizes, which reduces the grooving difficulty and ensures the grooving accuracy. At the same time, the staggered arrangement between the first step 181 and the second step 182, and the wiring layer 140 can be distributed on the first step 181 and the second step 182, which can further increase the pairwise contact area among the encapsulant 160, the wiring layer 140 and the sensing chip 130, thereby improving the bonding force among the three and avoiding the warping and delamination of the encapsulant 160 or the wafer.

[0058] In this embodiment, the second pad 151 is arranged on the wiring layer 140 on the back of the sensing chip 130 and is spaced from the stepped groove 180. The first pad 171 is arranged on the first step 181 and / or the second step 182 so that the first conductive pillar 170 is bonded to the first step 181 and / or the second step 182. Preferably, the first pad 171 is arranged on the first step 181 so that the first conductive pillar 170 can be bonded to the first step 181. Among them, a convex table surface is formed in the middle of the back of the sensing chip 130, and the stepped groove is arranged at the edge of the convex table surface. The convex table surface is the area on the back of the sensing chip 130 that is not grooved, and the processing chip 150 is arranged on the convex table surface. And the horizontal dimension of the processing chip 150 is less than or equal to the horizontal dimension of the convex table surface, so as to improve the density of the processing chip 150. For example, a plurality of processing chips 150 can be arranged. In addition, by bonding the first conductive pillar 170 to the relatively higher first step 181, the transmission path between the wiring layer 140 and the outside can be further shortened.

[0059] In this embodiment, the first conductive pillars 170 are arranged on at least two sides of the sensing chip 130, and one end of the first conductive pillar 170 is bonded to the first step 181. Specifically, the first conductive pillars 170 can be arranged around the sensing chip 130 and are arranged in a rectangle around the convex table surface. A solder ball 172 is further arranged at one end of each first conductive pillar 170 exposed from the encapsulant 160, so as to realize the connection with an external circuit board.

[0060] In this embodiment, the wiring layer 140 includes a first dielectric layer 141, a conductive layer 142, and a second dielectric layer 143. The first dielectric layer 141 is disposed on the back surface of the sensing chip 130. The conductive layer 142 is disposed on the first dielectric layer 141 and is in electrical contact with the electrical bump 132. The second dielectric layer 143 is disposed on the first dielectric layer 141 and covers the conductive layer 142. The first pad 171 and the second pad 151 are both disposed on the second dielectric layer 143 and are connected to the conductive layer 142. Specifically, both the first dielectric layer 141 and the second dielectric layer 143 are dielectric materials, such as high molecular composite materials like epoxy resin, polyimide, benzocyclobutene, etc. At the same time, the conductive layer 142 can be a conductive metal layer, such as a copper layer, which has better conductivity.

[0061] This embodiment also provides a method for manufacturing a chip packaging structure 100 for manufacturing the aforementioned chip packaging structure 100. The manufacturing method includes the following steps:

[0062] S1: Provide a substrate 110.

[0063] Specifically, a wafer can be taken for standby first, and then a substrate 110 is taken. The substrate 110 can also be a carrier. The substrate 110 can be made of materials such as glass, silicon, high molecular composite materials, metal, etc. The substrate 110 can be determined according to the specific type of the sensing chip 130. When the sensing chip 130 is an image sensing chip, it is necessary to ensure that the substrate 110 has transparent characteristics. If the sensing chip 130 is other sensing chips, such as a gyroscope or a capacitive sensing chip 130, the substrate 110 can also use opaque materials.

[0064] S2: Form a support glue layer 120 on the substrate 110 and form an induction groove 121 on the support glue layer 120.

[0065] See Figure 3 , specifically, a liquid glue layer can be first coated on the surface of the substrate 110 by a coater in a spin coating manner, and then soft baked and shaped into a film via a hot plate to form the support glue layer 120. Then, the induction groove 121 can be formed on the support glue layer 120 through an etching process. The induction groove 121 penetrates through the support glue layer 120 and partially exposes the substrate 110.

[0066] S3: Attach the wafer to the support glue layer 120.

[0067] See Figure 4, wherein the wafer includes a plurality of sensing chips 130. On the front surface of the sensing chip 130, there are provided a sensing area 131 and electrical bumps 132. The electrical bumps 132 are bonded to the support adhesive layer 120, and the sensing area 131 is correspondingly bonded to the sensing groove 121. Specifically, the electrical bumps 132 are located on at least two sides of the sensing area 131. When mounting the wafer, through an alignment process, the sensing area 131 of the sensing chip 130 can be aligned with the sensing groove 121, and the electrical bumps 132 can be bonded to the support adhesive layer 120 on both sides of the sensing groove 121. The support adhesive layer 120 can be used to fix the wafer, and finally, the support adhesive layer 120 is cured by baking.

[0068] S4: Etch the wafer and form a step groove 180 on the back surface of the sensing chip 130.

[0069] See Figure 5 , wherein the step groove 180 exposes the electrical bumps 132. The etching of the step groove 180 can be divided into three etching processes. First, use plasma etching technology (using a plasma dry etching O 2 and SF 6 mixed plasma gas) or chemical etching technology (using a mixed reagent of phosphoric acid, acetic acid, hydrogen chloride, sulfuric acid, etc. for etching) to etch the back surface of the wafer, or in combination with a grinding method, thin the back surface of the wafer. First, etch to form a first step 181, then etch again to form a second step 182, and finally etch to expose the electrical bumps 132 of the wafer. Among them, the slot width of the first step 181 is greater than the slot width of the second step 182. After three times of etching, the electrical bumps 132 of the wafer can be exposed.

[0070] S5: Form a wiring layer 140 on the wafer.

[0071] See Figure 6 , wherein the wiring layer 140 extends to the side wall and bottom wall of the step groove 180, and a first pad 171 and a second pad 151 are provided on the wiring layer 140. Specifically, after the back surface of the wafer is etched, first, use a spin coating process to coat the first dielectric layer 141 on the back surface of the wafer, then cover the first dielectric layer 141 with a photomask, form a pattern layer opening through an exposure and development process, then use an electroplating process to electroplate a conductive layer 142, and finally use a spin coating process again to form a second dielectric layer 143. Both the first dielectric layer 141 and the second dielectric layer 143 can be polymer composite materials such as epoxy resin, polyimide, benzocyclobutene, etc. Finally, cover the second dielectric layer 143 with a photomask again, then use an exposure and development process to form a pattern layer opening, and then use an electroplating process to electroplate a metal pad in the pattern layer opening, thereby forming the first pad 171 and the second pad 151. The first pad 171 is located on the first step 181, and the second pad 151 is located on the convex surface of the back of the wafer.

[0072] S6: Mount the processing chip 150 on the wiring layer 140.

[0073] See Figure 7 , where the processing chip 150 is connected to the second pad 151. Specifically, using the flip-chip process, the processing chip 150 is mounted on the wiring layer 140, and the bumps of the processing chip 150 are correspondingly connected to the second pad 151, and then fixed by reflow soldering to complete the stacking, thereby realizing the electrical connection between the processing chip 150 and the wiring layer 140.

[0074] S7: Form a molding compound 160 on the wiring layer 140.

[0075] See Figure 8 , where the molding compound 160 covers the processing chip 150. Specifically, the molding compound 160 can be prepared on the wiring layer 140 using the molding process. The molding compound 160 can act as a protective layer, and the molding material can be a polymer composite such as epoxy resin, polyimide, or benzocyclobutene.

[0076] S8: Form a first conductive pillar 170 in the molding compound 160.

[0077] See Figure 9 , where the first conductive pillar 170 is connected to the first pad 171, and the first conductive pillar 170 is spaced from the processing chip 150 and exposed from the molding compound 160. Specifically, the plasma etching technology or the laser drilling technology can be used again to open a hole in the molding compound 160 and expose the first pad 171 on the first step 181, and then fill the metal by electroplating to form the first conductive pillar 170, and then form a metal layer on the first conductive pillar 170 by electroplating, and finally complete the ball planting to form solder balls 172 on the first conductive pillar 170. The metal layer can be a nickel-vanadium layer or a titanium-nickel-vanadium layer, and the material of the solder balls 172 can be SnAg or SnAgCu. Finally, through the cutting process, single products are formed.

[0078] In summary, for the chip packaging structure 100 and its manufacturing method provided by the embodiments of the present invention, a support glue layer 120 is formed on the substrate 110. The support glue layer 120 is provided with an induction groove 121. At the same time, the induction chip 130 is disposed on the support glue layer 120, and the induction area 131 corresponds to the induction groove 121. The electrical bumps 132 are joined downward to the support glue block. At the same time, a step groove 180 is formed on the back surface of the induction chip 130, and the step groove 180 can expose the electrical bumps 132. In addition, a wiring layer 140 is further disposed on the back surface of the induction chip 130. The wiring layer 140 extends to the side wall and the bottom wall of the step groove 180 and is in electrical contact with the electrical bumps 132 to achieve electrical connection with the induction chip 130. The first conductive column 170 is embedded in the plastic package 160 and connected to the first pad 171 on the wiring layer 140, thereby achieving electrical connection with the wiring layer 140. The processing chip 150 is mounted on the wiring layer 140 and connected to the second pad 151, achieving electrical connection with the induction chip 130. Compared with the prior art, the embodiments of the present invention can directly stack the induction chip 130 and the processing chip 150, and the processing chip 150 can be directly connected to the wiring layer 140. The wiring layer 140 can be directly connected to the induction chip 130 through the step groove. Therefore, there is no need to re-wire outside the plastic package 160, reducing the transmission path between the chips, improving the transmission speed, and further improving the chip performance. Moreover, the setting of the step groove also improves the bonding force between the wiring layer 140, the plastic package 160, and the induction chip 130, avoiding warping and delamination.

[0079] Second Embodiment

[0080] Refer to Figure 10 and Figure 11 , this embodiment provides a chip packaging structure 100, whose basic structure, principle, and the resulting technical effects are the same as those of the first embodiment. For a brief description, for the parts not mentioned in this embodiment, reference can be made to the corresponding content in the first embodiment.

[0081] In this embodiment, the chip packaging structure 100 includes a substrate 110, a support glue layer 120, a sensing chip 130, a wiring layer 140, a processing chip 150, a plastic package 160, and a first conductive post 170. The support glue layer 120 is disposed on the substrate 110 and is provided with a sensing groove 121. The sensing chip 130 is disposed on the support glue layer 120, and a sensing area 131 and an electrical bump 132 are provided on the front surface of the sensing chip 130. The electrical bump 132 is bonded to the support glue layer 120, and the sensing area 131 is correspondingly bonded to the sensing groove 121. The wiring layer 140 is disposed on the back surface of the sensing chip 130 and is electrically connected to the electrical bump 132, and a first pad 171 and a second pad 151 are provided on the wiring layer 140. The processing chip 150 is mounted on the wiring layer 140 and is connected to the second pad 151. The plastic package 160 is disposed on the wiring layer 140 and covers the processing chip 150. The first conductive post 170 is embedded in the plastic package 160 and is connected to the first pad 171, and the first conductive post 170 is spaced apart from the processing chip 150 and exposed from the plastic package 160. Wherein, a stepped groove 180 is provided on the back surface of the sensing chip 130, the stepped groove 180 exposes the electrical bump 132, and the wiring layer 140 extends to the side wall and the bottom wall of the stepped groove 180.

[0082] In this embodiment, the stepped groove 180 has a first step 181 and a second step 182. The distance between the first step 181 and the substrate 110 is greater than the distance between the second step 182 and the substrate 110. An opening exposing the electrical bump 132 is further provided on the second step 182. The wiring layer 140 covers the first step 181 and the second step 182 and extends into the opening to make electrical contact with the electrical bump 132. The second pad 151 is disposed on the first step 181. The processing chip 150 is attached to the back surface of the sensing chip 130, and a second conductive post 152 is provided at the edge of the processing chip 150. The second conductive post 152 is embedded in the plastic package 160 and is connected to the second pad 151.

[0083] In this embodiment, a convex table surface is formed in the middle of the back surface of the sensing chip 130, and the stepped groove is provided at the edge of the convex table surface. The horizontal width of the processing chip 150 is greater than the horizontal width of the convex table surface, and the edge of the processing chip 150 extends out of the convex table edge. The second conductive post 152 is located outside the edge of the convex table surface and is connected to the second pad 151.

[0084] In this embodiment, the first pad 171 is disposed on the back surface of the sensing chip 130 and is spaced apart from the stepped groove 180. The first conductive pillar 170 is embedded in the encapsulant 160 and is connected to the first pad 171. Specifically, the first pad 171 is spaced apart from the mounting area of the processing chip 150. By disposing the first pad 171 on the convex surface, the distance of the first conductive pillar 170 can be further shortened, thereby shortening the transmission path between the wiring layer 140 and the external circuit and improving the performance.

[0085] Furthermore, an adhesive layer 133 is also disposed in the area of the back surface of the sensing chip 130 where the stepped groove 180 is not provided. The processing chip 150 is flip-chip fixed to the back surface of the sensing chip 130 through the adhesive layer 133. Specifically, the adhesive layer 133 is coated and disposed in the mounting area of the convex surface and is a non-conductive material. The front surface of the processing chip 150 can be fixed to the convex surface through the adhesive layer 133 to achieve fixation. Particularly importantly, through the fixing effect of the adhesive layer 133 on the processing chip 150, the weldability between the second conductive pillar 152 and the second pad 151 during welding of the processing chip 150 can be better, and the occurrence of de-soldering or cracks at the welding point can be avoided (in the case of conventional flip-chip direct welding without a fixing effect, de-soldering or cracks are likely to occur).

[0086] It should be noted that in this embodiment, the processing chip 150 is connected to the second pad 151 through the second conductive pillar 152. The second pad 151 is located on the first step 181, so that the second conductive pillar 152 not only plays an electrical connection role, but also can improve the edge capillary action, prompting the encapsulant to fill the gap between the processing chip 150 and the first step 181, and ensuring the filling and fixing effect of the encapsulant 160. Moreover, when the encapsulant fills between the edge of the processing chip 150 and the first step 181, the bonding force between the encapsulant 160 and the processing chip 150 can be further improved, thereby further ensuring the stable and reliable structure.

[0087] Third Embodiment

[0088] See Figure 12 , this embodiment provides a chip packaging structure 100, whose basic structure, principle, and the resulting technical effects are the same as those of the second embodiment. For a brief description, for the parts not mentioned in this embodiment, reference can be made to the corresponding content in the second embodiment.

[0089] In this embodiment, a third conductive post 153 is further provided at the edge of the processing chip 150, and a third pad 156 is provided on the wiring layer 140 on the second step 182. The third conductive post 153 is embedded in the plastic package 160 and connected to the third pad 156. Specifically, an electrical connection is achieved between the third conductive post 153 and the third pad 156, so that the electrical connection effect between the processing chip 150 and the wiring layer 140 is better, and the third conductive post 153 can also play a role in structural support, improving the structural stability.

[0090] Further, support posts 154 are provided on the wiring layer 140 on the first step 181 and / or the second step 182. The support posts 154 extend in a direction away from the substrate 110 and are in clearance fit with the surface of the processing chip 150 close to the substrate 110. Specifically, support posts 154 are provided on the wiring layer 140 of the second step 182. The support posts 154 extend toward the front edge of the processing chip 150 and are in clearance fit with the front surface of the processing chip 150. By providing the support posts 154, it can play a role in mounting and positioning the processing chip 150 during the actual mounting process, and through the capillary action of the support posts 154, it can further ensure the filling effect of the encapsulant and improve the stability of the overall structure. Further, by providing a plurality of support posts 154, a surrounding blocking wall structure can be formed around the edge of the sensing chip 130, and the support posts 154 are made of a metal material, which can block external optoelectronic signals (such as visible light), avoiding adverse interference of external signals on the sensing area (with the setting of the step groove 180 and the thinning of the sensing chip 130, optoelectronic signals will enter or exit from the thinning area, which will affect the normal function of the sensing area 131), improving the performance of the sensing chip 130.

[0091] Of course, in other preferred embodiments of the present invention, the support posts 154 can also be provided on the first step 181.

[0092] Fourth Embodiment

[0093] See Figure 13 , this embodiment provides a chip package structure 100, whose basic structure, principle, and the resulting technical effects are the same as those of the second embodiment. For a brief description, for the parts not mentioned in this embodiment, reference can be made to the corresponding content in the second embodiment.

[0094] In this embodiment, a protection pillar 155 is further disposed on the wiring layer 140 on the first step 181 and / or the second step 182. The protection pillar 155 extends away from the substrate 110 and is located outside the processing chip 150, and the protection pillar 155 is in clearance fit with the side wall of the processing chip 150. Specifically, the protection pillar 155 is disposed on the wiring layer 140 of the first step 181, and the protection pillar 155 extends upward and does not penetrate through the encapsulant 160. The height of the protection pillar 155 relative to the first step 181 is greater than the height of the back surface of the processing chip 150 relative to the first step 181, so that the protection pillar 155 can protrude from the back surface of the processing chip 150.

[0095] In this embodiment, a support pillar 154 may further be disposed on the wiring layer 140 of the first step 181. The support pillar 154 extends upward and is in clearance fit with the front surface of the processing chip 150.

[0096] It should be noted that by providing the support pillar 154 in this embodiment, it can play a role in mounting and positioning the processing chip 150 during the actual mounting process. And through the capillary action of the support pillar 154, the filling effect of the encapsulant can be further ensured, and the stability of the overall structure can be improved. At the same time, by providing the protection pillar 155, on the one hand, the capillary action of the encapsulant can be further enhanced to ensure the filling effect, and on the other hand, it can protect the processing chip 150 and the second conductive pillar 152, avoiding the displacement of the second conductive pillar 152 and the second pad 151 caused by the mold flow impact. At the same time, when mounting the processing chip 150, the protection pillar 155 can also play a preliminary positioning role, enabling the processing chip 150 to be quickly and accurately positioned. Further, a plurality of protection pillars 155 can form a wall structure, which can surround the sensing area. And the protection pillar 155 is also made of a metal material, which can block external optoelectronic signals (such as visible light), avoiding adverse interference of external signals on the sensing area (with the setting of the step groove 180 and the thinning of the sensing chip 130, optoelectronic signals will enter or exit from the thinning part, which will affect the normal function of the sensing area 131), and improving the performance of the sensing chip 130.

[0097] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip packaging structure, characterized in that: include: substrate; A supporting adhesive layer, the supporting adhesive layer is disposed on the substrate and is provided with a sensing groove; A sensing chip, wherein the sensing chip is arranged on the supporting adhesive layer, and a sensing area and an electrical bump are arranged on the front side of the sensing chip, the electrical bump is bonded to the supporting adhesive layer, and the sensing area is correspondingly bonded to the sensing groove; A wiring layer, the wiring layer is arranged on the back side of the sensing chip and is electrically connected to the electrical bump, and a first pad and a second pad are arranged on the wiring layer; a processing chip mounted on the wiring layer and connected to the second pad; A plastic package, the plastic package being disposed on the wiring layer and covering the processing chip; A first conductive column, wherein the first conductive column is embedded in the plastic package and connected to the first pad, and the first conductive column is spaced apart from the processing chip and exposed from the plastic package; Wherein, a step groove is provided at the edge position of the back side of the sensing chip, the step groove exposes the electrical bump, and the wiring layer extends to the side wall and the bottom wall of the step groove; The step groove has a first step and a second step, the distance between the first step and the substrate is greater than the distance between the second step and the substrate, the second step is also provided with an opening exposing the electrical bump, the wiring layer covers the first step and the second step, and extends into the opening to electrically contact the electrical bump; the second pad is provided on the first step, the processing chip is flip-chip attached to the back of the sensing chip, and a second conductive column is provided at the edge of the processing chip, the second conductive column is embedded in the plastic package and connected to the second pad; an adhesive layer is also provided in the area on the back of the sensing chip where the step groove is not provided, and the processing chip is fixed to the back of the sensing chip through the adhesive layer.

2. The chip packaging structure according to claim 1, characterized in that: The second pad is disposed on the wiring layer on the back side of the sensing chip, and the first pad is disposed on the first step and / or the second step, so that the first conductive column is bonded to the first step and / or the second step.

3. The chip packaging structure according to claim 2, characterized in that: The first conductive pillar is disposed on at least two sides of the sensing chip, and one end of the first conductive pillar is connected to the first step.

4. The chip packaging structure according to claim 1, characterized in that: A solder ball is also disposed on one end of the first conductive column exposed from the plastic package body.

5. The chip packaging structure according to claim 1, characterized in that: The wiring layer includes a first dielectric layer, a conductive layer, and a second dielectric layer. The first dielectric layer is arranged on the back side of the sensing chip. The conductive layer is arranged on the first dielectric layer and is in electrical contact with the electrical bump. The second dielectric layer is arranged on the first dielectric layer and covers the conductive layer. The first pad and the second pad are both arranged on the second dielectric layer and are connected to the conductive layer.

6. The chip packaging structure according to claim 1, characterized in that: The first pad is arranged on the back side of the sensing chip and is spaced apart from the step groove. The first conductive column is embedded in the plastic package and connected to the first pad.

7. The chip packaging structure according to claim 1, characterized in that: A third conductive column is also arranged at the edge of the processing chip, a third pad is arranged on the wiring layer on the second step, and the third conductive column is embedded in the plastic package and connected to the third pad.

8. The chip packaging structure according to claim 1, characterized in that: A support column is provided on the wiring layer on the first step and / or the second step. The support column extends in a direction away from the substrate and is gap-matched with a surface of the processing chip on one side close to the substrate.

9. The chip packaging structure according to claim 8, characterized in that: A protection column is further provided on the wiring layer on the first step and / or the second step. The protection column extends in a direction away from the substrate and is located outside the processing chip. The protection column is gap-matched with the sidewall of the processing chip.

10. A method for preparing a chip packaging structure, used for preparing the chip packaging structure as claimed in claim 1, characterized in that: The preparation method comprises: providing a substrate; forming a supporting adhesive layer on the substrate, and forming a sensing groove on the supporting adhesive layer; A wafer is attached to the supporting adhesive layer, wherein the wafer includes a plurality of sensing chips, a sensing area and an electrical bump are provided on the front of the sensing chip, the electrical bump is bonded to the supporting adhesive layer, and the sensing area is correspondingly bonded to the sensing groove; Etching the wafer and forming a step groove on the back side of the sensor chip, wherein the step groove exposes the electrical bump; forming a wiring layer on the wafer, wherein the wiring layer extends to the side wall and the bottom wall of the step groove, and a first pad and a second pad are disposed on the wiring layer; mounting a processing chip on the wiring layer, wherein the processing chip is connected to the second pad; forming a plastic package on the wiring layer, wherein the plastic package covers the processing chip; A first conductive column is formed in the plastic package, wherein the first conductive column is connected to the first pad, and the first conductive column is spaced apart from the processing chip and exposed from the plastic package.

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