A gate driving circuit, display panel and display device

Abstract

The application provides a gate drive circuit, a display panel and a display device, and relates to the technical field of display. The gate drive circuit comprises a plurality of cascaded shift registers, and each shift register comprises a first input unit, a second input unit, a first output unit, a second output unit, a first reset unit and an off unit. The first reset unit is configured to write an off voltage to a first node. The first reset unit comprises a first reset transistor, a gate of the first reset transistor is connected to a first clock signal end or a third clock signal end, a first electrode of the first reset transistor is connected to the first node, a control end of the off unit is connected to the first node, a first end of the off unit is connected to a second electrode of the first reset transistor, and the off unit is configured to write an on voltage to the second electrode of the first reset transistor when the off unit is turned on under the control of the first node. The embodiment of the application can reduce the leakage of the shift register and the leakage of the gate drive circuit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a gate driving circuit, a display panel, and a display device. Background Technology

[0002] Display panels typically include display areas and non-display areas. The display area is equipped with multiple pixel driving circuits and light-emitting elements. The pixel driving circuits are used to drive the light-emitting elements to emit light in order to display images. The non-display area is equipped with gate driving circuits, which are used to provide control signals to the pixel driving circuits so that the light-emitting elements are lit up line by line under the drive of the pixel driving circuits.

[0003] In related technologies, the gate drive circuit suffers from leakage current. Summary of the Invention

[0004] The present invention provides a gate driving circuit, a display panel, and a display device to reduce leakage current in the shift register and the gate driving circuit.

[0005] In a first aspect, embodiments of the present invention provide a gate driving circuit, including a plurality of cascaded shift registers, wherein the shift registers include a first input unit, a second input unit, a first output unit, a second output unit, a first reset unit, and a shutdown unit;

[0006] The output terminal of the first input unit and the control terminal of the first output unit are connected to the first node, and the output terminal of the second input unit and the control terminal of the second output unit are connected to the third node;

[0007] The first reset unit is used to write a shutdown voltage to the first node, the shutdown voltage being a voltage that controls the first output unit to turn off; the first reset unit includes a first reset transistor, the gate of the first reset transistor being connected to a first clock signal terminal or a third clock signal terminal; the first terminal of the first reset transistor is connected to the first node;

[0008] The control terminal of the shutdown unit is connected to the first node, and the first terminal of the shutdown unit is connected to the second terminal of the first reset transistor. When the first node controls the shutdown unit to be turned on, the shutdown unit is used to write the turn-on voltage to the second terminal of the first reset transistor. The turn-on voltage is the voltage that controls the first output unit to be turned on.

[0009] In a second aspect, embodiments of the present invention provide a display panel including the gate driving circuit described in the first aspect.

[0010] Thirdly, embodiments of the present invention provide a display device including the display panel described in the second aspect.

[0011] In the gate driving circuit provided in this embodiment of the invention, a turn-off unit is provided, and the control terminal of the turn-off unit is connected to the first node. When the voltage of the first node is the on-state voltage, the turn-off unit is turned on, writing the on-state voltage to the second terminal of the first reset transistor. Both the first and second terminals of the first reset transistor are on-state voltages. The gate of the first reset transistor is the turn-off voltage. The on-state voltage applied to the second terminal of the first reset transistor turns off the first reset transistor more completely, reducing leakage current through the first reset transistor and reducing leakage current in the circuit branch where the first node and the first reset unit are located. Here, leakage current refers to leakage current in the off state, or voltage change caused by leakage current. Attached Figure Description

[0012] Figure 1 A circuit diagram of a gate driving circuit provided in an embodiment of the present invention;

[0013] Figure 2 A circuit diagram of a shift register provided in an embodiment of the present invention;

[0014] Figure 3 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0015] Figure 4 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0016] Figure 5 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0017] Figure 6 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0018] Figure 7 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0019] Figure 8 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0020] Figure 9 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0021] Figure 10 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0022] Figure 11 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0023] Figure 12A timing diagram for driving a shift register provided in an embodiment of the present invention;

[0024] Figure 13 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0025] Figure 14 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0026] Figure 15 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0027] Figure 16 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0028] Figure 17 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0029] Figure 18 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0030] Figure 19 A timing diagram for driving another shift register provided in an embodiment of the present invention;

[0031] Figure 20 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0032] Figure 21 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0033] Figure 22 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0034] Figure 23 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0035] Figure 24 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0036] Figure 25 A timing diagram for driving another shift register provided in an embodiment of the present invention;

[0037] Figure 26 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0038] Figure 27 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0039] Figure 28 A circuit diagram of another shift register provided in an embodiment of the present invention;

[0040] Figure 29 A circuit diagram of another gate driving circuit provided in an embodiment of the present invention;

[0041] Figure 30 A circuit diagram of another gate driving circuit provided in an embodiment of the present invention;

[0042] Figure 31 A schematic diagram of a display panel provided in an embodiment of the present invention;

[0043] Figure 32 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0044] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0045] Figure 1 This is a circuit diagram of a gate driving circuit provided in an embodiment of the present invention. Figure 2 This is a circuit diagram of a shift register provided in an embodiment of the present invention, with reference to... Figure 1 and Figure 2 The gate drive circuit includes multiple cascaded shift registers 100. Each shift register 100 includes a first input unit 110, a second input unit 120, a first output unit 130, a second output unit 140, a first reset unit 150, and a shutdown unit 160. The output terminal of the first input unit 110 and the control terminal of the first output unit 130 are connected to a first node Q1. The output terminal of the first input unit 110 is coupled to the first node Q1, and the control terminal of the first output unit 130 is coupled to the first node Q1. The output terminal of the second input unit 120 and the control terminal of the second output unit 140 are connected to a third node QB.

[0046] The first reset unit 150 is used to write a shutdown voltage to the first node Q1. The shutdown voltage is the voltage that controls the first output unit 130 to turn off. The shutdown voltage can also be the voltage that controls the second output unit 140 to turn off. The first reset unit 150 includes a first reset transistor T7, the gate of which is connected to either a first clock signal terminal CK1 or a third clock signal terminal CK3. The first reset transistor T7 is turned on or off under the control of the first clock signal terminal CK1. Alternatively, the first reset transistor T7 is turned on or off under the control of the third clock signal terminal CK3. The first clock signal terminal CK1 and the third clock signal terminal CK3 provide clock signals. The first terminal of the first reset transistor T7 is connected to the first node Q1.

[0047] The control terminal of the shutdown unit 160 is connected to the first node Q1, and the first terminal of the shutdown unit 160 is connected to the second terminal of the first reset transistor T7. When the first node Q1 controls the shutdown unit 160 to be turned on, the shutdown unit 160 writes an on-state voltage to the second terminal of the first reset transistor T7. This on-state voltage is the voltage that controls the first output unit 130 to be turned on. The on-state voltage can also be the voltage that controls the second output unit 140 to be turned on.

[0048] In the gate driving circuit provided in this embodiment of the invention, a turn-off unit 160 is provided, and the control terminal of the turn-off unit 160 is connected to the first node Q1. When the voltage of the first node Q1 is the on-state voltage, the turn-off unit 160 is turned on, writing the on-state voltage to the second terminal of the first reset transistor T7. Both the first and second terminals of the first reset transistor T7 are on-state voltages. The gate of the first reset transistor T7 is the turn-off voltage. The on-state voltage applied to the second terminal of the first reset transistor T7 turns off the first reset transistor T7 more completely, reducing the leakage current through the first reset transistor T7 and reducing the leakage current in the circuit branch where the first node Q1 and the first reset unit 150 are located. Here, leakage current refers to the leakage current in the off state, or the voltage change caused by leakage current.

[0049] For example, the gate drive circuit includes a plurality of thin-film transistors, at least one of which is an oxide transistor. The semiconductor layer of the oxide transistor includes a metal oxide. The metal oxide may, for example, include indium gallium zinc oxide (IGZO).

[0050] Exemplarily, the thin-film transistor includes an N-type transistor. The gate of the N-type transistor is turned on under a positive voltage (including a high voltage) and turned off under a negative voltage. For the N-type transistor, the turn-off voltage is a negative voltage (including a low voltage), and the turn-on voltage is a positive voltage. In other embodiments, the thin-film transistor includes a P-type transistor. The gate of the P-type transistor is turned off under a positive voltage and turned on under a negative voltage. For the P-type transistor, the turn-off voltage is a positive voltage, and the turn-on voltage is a negative voltage. The positive voltage is greater than the negative voltage. For simplicity, the various embodiments of the present invention are explained using an N-type transistor as an example, but are not limited thereto.

[0051] For example, the first reset transistor T7 is an N-type transistor. The turn-off voltage is negative, and the turn-on voltage is positive. Both the first and second terminals of the first reset transistor T7 are positive, while the gate of the first reset transistor T7 is negative. The gate-source voltage difference of the first reset transistor T7 is a very negative value, allowing the first reset transistor T7 to be turned off more completely, thus reducing leakage current through the first reset transistor T7.

[0052] Figure 3 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 3 The turn-off unit 160 includes a turn-off transistor T9. The gate of the turn-off transistor T9 is connected to the first node Q1, and the first terminal of the turn-off transistor T9 is connected to the second terminal of the first reset transistor T7. When the turn-off transistor T9 is turned on, a turn-on voltage is written to the second terminal of the first reset transistor T7.

[0053] Optionally, refer to Figure 3 The second terminal of the turn-off transistor T9 is connected to the first power supply voltage terminal VGH, which provides the turn-on voltage. During the period when the turn-off transistor T9 is on, the turn-on voltage of the first power supply voltage terminal VGH can be written to the second terminal of the first reset transistor T7, increasing the time for completely turning off the first reset transistor T7 and further improving the effect of reducing leakage current in the gate drive circuit.

[0054] For example, refer to Figure 4 When the first node Q1 is positive, the positive voltage of the first node Q1 controls the turn-off transistor T9 to turn on, writing the positive voltage of the first power supply voltage terminal VGH to the second terminal of the first reset transistor T7. In one embodiment, the voltage of the first power supply voltage terminal VGH is a high voltage, for example, greater than or equal to 8V. In other embodiments, the voltage of the first power supply voltage terminal VGH can also be a low voltage, less than or equal to -8V.

[0055] Figure 4 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 4 The second terminal of the turn-off transistor T9 is connected to the first clock signal terminal CK1. During the period when the clock signal provided by the first clock signal terminal CK1 is the on-state voltage, the on-state voltage can be written to the second terminal of the first reset transistor T7.

[0056] Figure 5 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 5 The second terminal of the turn-off transistor T9 is connected to the second clock signal terminal 220. During the period when the clock signal provided by the second clock signal terminal 220 is the on-state voltage, the on-state voltage can be written to the second terminal of the first reset transistor T7.

[0057] Figure 6 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 1 and Figure 6 The shift register 100 also includes an isolation transistor T4. The gate of the isolation transistor T4 is connected to the first clock signal terminal CK1, the first terminal of the isolation transistor T4 is connected to the first node Q1, and the second terminal of the isolation transistor T4 and the control terminal of the first output unit 130 are connected to the second node Q2.

[0058] For example, refer to Figure 6 The isolation transistor T4 is an N-type transistor. Its turn-off voltage is negative, and its turn-on voltage is positive. During the period when the clock signal provided by the first clock signal terminal CK1 is positive, the isolation transistor T4 is turned on, and the first node Q1 and the second node Q2 have the same voltage. During the period when the clock signal provided by the first clock signal terminal CK1 is negative, the isolation transistor T4 is turned off, and the first node Q1 and the second node Q2 have the same or different voltages.

[0059] Figure 7 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 7 The first output unit 130 includes a first output transistor T5 and a first capacitor C1. The gate of the first output transistor T5 is connected to the second node Q2, the first terminal of the first output transistor T5 is connected to the second clock signal terminal 220, and the second terminal of the first output transistor T5 is connected to the output signal terminal 210. The second node Q2 has a different voltage than the first node Q1. Due to the bootstrap effect of the first capacitor C1, the voltage of the second node Q2 is set to more thoroughly turn on the first output unit 130, thereby improving the voltage transmission capability of the first output unit 130 and improving the driving capability of the enable voltage output from the output signal terminal 210.

[0060] For example, refer to Figure 7 The first output transistor T5 is an N-type transistor. Its turn-off voltage is negative, and its turn-on voltage is positive. Due to the bootstrap effect of the first capacitor C1, the voltage of the second node Q2 is coupled to a higher potential by the first capacitor C1. The higher the gate voltage of the first output transistor T5, the more completely the first output transistor T5 is turned on, and the stronger its voltage transmission capability, thus improving the driving capability of the enable voltage output at the output signal terminal 210.

[0061] Figure 8 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 1 and Figure 8 The shift register 100 also includes a second capacitor C2. The first plate of the second capacitor C2 is connected to the first node Q1, and the second plate of the second capacitor C2 is connected to the second power supply voltage terminal 230. The second power supply voltage terminal 230 provides a turn-off voltage. The capacitance value of the second capacitor C2 is greater than that of the first capacitor C1. Therefore, when the isolation transistor T4 is turned on, the second capacitor C2, with its larger capacitance value, shifts the voltage of the second node Q2 towards the voltage of the first node Q1. For example, if the voltage of the first node Q1 is less than the voltage of the second node Q2, when the isolation transistor T4 is turned on, the second capacitor C2, with its larger capacitance value, pulls the voltage of the second node Q2 down to the voltage of the first node Q1. This achieves the effect of resetting the voltage of the second node Q2.

[0062] For example, refer to Figure 8 The second output unit 140 includes a third output transistor T6 and a third capacitor C3. The gate of the third output transistor T6 is connected to the third node QB, and the first terminal of the third output transistor T6 is connected to the second power supply voltage terminal 230, which provides a turn-off voltage. For example, the voltage at the second power supply voltage terminal 230 is a low voltage, such as less than or equal to -8V. In other embodiments, the voltage at the second power supply voltage terminal 230 can also be a high voltage, greater than or equal to 8V. The second terminal of the third output transistor T6 is connected to the output signal terminal 210. The first plate of the third capacitor C3 is connected to the third node QB, and the second plate of the third capacitor C3 is connected to the second power supply voltage terminal 230. The third capacitor C3 is used to maintain the voltage at the third node QB.

[0063] Figure 9 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 9The second clock signal terminal 220 includes a second clock first sub-signal terminal CK2 and a second clock second sub-signal terminal BCK2. The second clock first sub-signal terminal CK2 and the second clock second sub-signal terminal BCK2 provide voltages with the same timing but different voltage values. Same timing means that the second clock first sub-signal terminal CK2 and the second clock second sub-signal terminal BCK2 simultaneously have on-voltage and off-voltage during the same time period. The output signal terminal 210 includes a first output signal terminal OUT and a second output signal terminal CR. The first terminal of the first output transistor T5 is connected to the second clock first sub-signal terminal CK2, and the second terminal of the first output transistor T5 is connected to the first output signal terminal OUT. The first output unit 130 also includes a second output transistor T10. The gate of the second output transistor T10 is connected to the second node Q2, the first terminal of the second output transistor T10 is connected to either the second clock first sub-signal terminal CK2 or the second clock second sub-signal terminal BCK2, and the second terminal of the second output transistor T10 is connected to the second output signal terminal CR.

[0064] For example, refer to Figure 9 The voltage of the second sub-signal terminal BCK2 of the second clock when it is low is less than the voltage of the first sub-signal terminal CK2 of the second clock when it is low.

[0065] Figure 10 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 10 The first reset unit 150 further includes a second reset transistor T8. The gate of the second reset transistor T8 is connected to the third node QB, the first terminal of the second reset transistor T8 is connected to the second terminal of the first reset transistor T7, and the second terminal of the second reset transistor T8 is connected to the second power supply voltage terminal 230. The second power supply voltage terminal 230 provides a turn-off voltage. The turn-on voltage applied to the second terminal of the first reset transistor T7 more completely turns off the first reset transistor T7, reducing the leakage current through the first reset transistor T7 and reducing the leakage current in the circuit branch where the first node Q1—first reset transistor T7—second reset transistor T8—second power supply voltage terminal 230 is located.

[0066] Figure 11 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 11The first input unit 110 includes a first input transistor T1. The gate of the first input transistor T1 is connected to the cascaded signal input terminal STV, and the first terminal of the first input transistor T1 is connected to the first power supply voltage terminal VGH. The first power supply voltage terminal VGH provides a turn-on voltage, and the second terminal of the first input transistor T1 is connected to the first node Q1. When the turn-on voltage provided by the cascaded signal input terminal STV turns on the first input transistor T1, the turn-on voltage provided by the first power supply voltage terminal VGH is transmitted to the first node Q1. The turn-on voltage of the first node Q1 turns on the turn-off transistor T9. The turn-off transistor T9 transmits the turn-on voltage provided by the first power supply voltage terminal VGH to the second terminal of the first reset transistor T7, thus turning off the first reset transistor T7 more thoroughly and reducing leakage current through the first reset transistor T7.

[0067] For example, refer to Figure 11 The second input unit 120 includes a second input transistor T2, the gate of which is connected to a third clock signal terminal CK3. The first terminal of the second input transistor T2 is connected to a first power supply voltage terminal VGH, and the second terminal is connected to a third node QB. During the period when the third clock signal terminal CK3 provides a conduction voltage, the second input transistor T2 is turned on, transmitting the conduction voltage provided by the first power supply voltage terminal VGH to the third node QB.

[0068] For example, refer to Figure 1 and Figure 11 The second output signal terminal CR of the current stage shift register 100 is connected to the cascade signal input terminal STV of the next stage shift register 100.

[0069] For example, refer to Figure 1 and Figure 8 The first output signal terminal OUT of the current stage shift register 100 is connected to the cascade signal input terminal STV of the next stage shift register 100.

[0070] Optionally, refer to Figure 1 and Figure 11The shift register 100 includes a second power supply voltage terminal 230 that provides a turn-off voltage. The second power supply voltage terminal 230 includes a first sub-voltage terminal VGL and a second sub-voltage terminal LVGL. The voltage provided by the first sub-voltage terminal VGL is greater than the voltage provided by the second sub-voltage terminal LVGL. The second output unit 140 includes a third output transistor T6, the gate of which is connected to a third node QB, the first terminal of which is connected to the second sub-voltage terminal LVGL, and the second terminal of which is connected to the output signal terminal 210. The shift register 100 also includes a third reset transistor T3, the gate of which is connected to a first node Q1, the first terminal of which is connected to the third node QB, and the second terminal of which is connected to the second sub-voltage terminal LVGL.

[0071] For example, refer to Figure 11 The second terminal of the third output transistor T6 is connected to the second output signal terminal CR. The second output unit 140 also includes a fourth output transistor T11. The gate of the fourth output transistor T11 is connected to the third node QB, the first terminal of the fourth output transistor T11 is connected to the first sub-voltage terminal VGL of the second power supply, and the second terminal of the fourth output transistor T11 is connected to the first output signal terminal OUT. When the first node Q1 is positive, the third reset transistor T3 is turned on. The voltage provided by the second sub-voltage terminal LVGL of the second power supply is transmitted to the third node QB through the third reset transistor T3. When the voltage of the first output signal terminal OUT is high, the gate-source voltage difference of the fourth output transistor T11 is negative. Even if the threshold voltage of the fourth output transistor T11 is negatively drifted, the fourth output transistor T11 can be turned off, improving the working stability of the shift register 100. As an example, the voltage provided by the first sub-voltage terminal VGL of the second power supply is, for example, -8V, and the voltage provided by the second sub-voltage terminal LVGL of the second power supply is, for example, -10V.

[0072] For example, refer to Figure 11The low voltage of the first sub-signal terminal CK2 of the second clock is equal to the voltage provided by the second sub-voltage terminal LVGL of the second power supply, and the low voltage of the second sub-signal terminal BCK2 of the second clock is equal to the voltage provided by the first sub-voltage terminal VGL of the second power supply. Therefore, the low voltage transmitted to the second output signal terminal CR through the first output transistor T5 is equal to the low voltage transmitted to the second output signal terminal CR through the third output transistor T6. The low voltage transmitted to the first output signal terminal OUT through the second output transistor T10 is equal to the low voltage transmitted to the first output signal terminal OUT through the fourth output transistor T11. This reduces both the race conditions caused by voltage differences and the leakage current in the two circuit branches. These two circuit branches include: the first sub-signal terminal CK2 of the second clock – the first output transistor T5 – the third output transistor T6 – the second sub-voltage terminal LVGL of the second power supply; and the second sub-signal terminal BCK2 of the second clock – the second output transistor T10 – the fourth output transistor T11 – the first sub-voltage terminal VGL of the second power supply.

[0073] Figure 12 A timing diagram for driving a shift register provided in an embodiment of the present invention is shown below. Figure 11 and Figure 12 During the first time period t1, the voltage at the cascaded signal input terminal STV is high, the first input transistor T1 is turned on, and the first node Q1 becomes high. The voltage at the first clock signal terminal CK1 is high, the isolation transistor T4 is turned on, and the second node Q2 becomes high. When the first node Q1 is high, the turn-off transistor T9 is turned on, transferring the high voltage of the first power supply voltage terminal VGH to the second terminal of the first reset transistor T7, turning off the first reset transistor T7 more completely and reducing leakage current through the first reset transistor T7. The high voltage at the first node Q1 charges the second capacitor C2. The second capacitor C2 maintains the high potential of the first node Q1. When the first node Q1 is high, the third reset transistor T3 is turned on, and the low voltage of the second sub-voltage terminal LVGL of the second power supply is transferred to the third node QB, making the third node QB low. When the third node QB is low, the third output transistor T6, the second reset transistor T8, and the fourth output transistor T11 are turned off. When the high voltage at the second node Q2, the first output transistor T5 and the second output transistor T10 are turned on. When the first sub-signal terminal CK2 of the second clock is low, the second output signal terminal CR is low. When the second sub-signal terminal BCK2 of the second clock is low, the first output signal terminal OUT is low. When the third clock signal terminal CK3 is low, the second input transistor T2 and the first reset transistor T7 are turned off.

[0074] During the second time period t2, the voltage at the cascaded signal input terminal STV is low, and the first input transistor T1 is off. The first node Q1 remains at a high voltage. When the first node Q1 is high, the turn-off transistor T9 is turned on, transferring the high voltage of the first power supply voltage terminal VGH to the second terminal of the first reset transistor T7, thus turning off the first reset transistor T7 more completely and reducing leakage current through the first reset transistor T7. When the first node Q1 is high, the third reset transistor T3 is turned on, and the low voltage at the second sub-voltage terminal LVGL of the second power supply is transferred to the third node QB, making the third node QB low. When the third node QB is low, the third output transistor T6, the second reset transistor T8, and the fourth output transistor T11 are off. The voltage at the first clock signal terminal CK1 is low, the isolation transistor T4 is off, and the second node Q2 remains high. When the second node Q2 is high, the first output transistor T5 is turned on, the first sub-signal terminal CK2 of the second clock becomes high, and the second output signal terminal CR is high. The second output transistor T10 is turned on, the second clock sub-signal terminal BCK2 is at a high voltage, and the first output signal terminal OUT is at a high voltage. During the second time period t2, shift register 100 outputs an enable voltage. Due to the bootstrap effect of the first capacitor C1, the voltage of the second node Q2 is coupled to a higher potential by the first capacitor C1. The higher the gate voltage of the first output transistor T5 and the second output transistor T10, the more thoroughly they are turned on, and the stronger their voltage transmission capability, thus improving the driving capability of the enable voltage output by the first output signal terminal OUT and the second output signal terminal CR. The third clock signal terminal CK3 is at a low voltage, and the second input transistor T2 and the first reset transistor T7 are turned off. During the first time period t1 and the second time period t2, the high voltage of the first power supply voltage terminal VGH is transmitted to the second terminal of the first reset transistor T7, turning it off more completely.

[0075] During the third time period t3, the voltage at the cascaded signal input terminal STV is low, and the first input transistor T1 is off. The voltage at the first clock signal terminal CK1 is low, and the isolation transistor T4 is off. The third clock signal terminal CK3 becomes high, the second input transistor T2 turns on, and the third node QB becomes high. When the third clock signal terminal CK3 and the third node QB are high, the first reset transistor T7 and the second reset transistor T8 turn on, and the low voltage at the second sub-voltage terminal LVGL of the second power supply is transmitted to the first node Q1, making the first node Q1 low. When the first node Q1 is low, the third reset transistor T3 and the turn-off transistor T9 are off. When the second node Q2 is high, the first output transistor T5 and the second output transistor T10 turn on. The first sub-signal terminal CK2 of the second clock is low, and this low voltage is transmitted to the second output signal terminal CR via the first output transistor T5, making the second output signal terminal CR low. When the second clock sub-signal terminal BCK2 is at a low voltage, this low voltage is transmitted to the first output signal terminal OUT via the second output transistor T10, resulting in a low voltage at OUT. When the third node QB is at a high voltage, the third output transistor T6 and the fourth output transistor T11 are turned on. The low voltage of the second power supply sub-voltage terminal LVGL is transmitted to the second output signal terminal CR via the third output transistor T6, making the voltage at LVGL equal to the low voltage at the second clock sub-signal terminal BCK2. Similarly, the low voltage of the second power supply first sub-voltage terminal VGL is transmitted to the first output signal terminal OUT via the fourth output transistor T11, making the voltage at VGL equal to the low voltage at the second clock first sub-signal terminal CK2. This reduces both the race conditions caused by voltage differences and leakage current in both circuit branches. The two circuit branches include: the second clock first sub-signal terminal CK2 – first output transistor T5 – third output transistor T6 – second power supply second sub-voltage terminal LVGL; and the second clock second sub-signal terminal BCK2 – second output transistor T10 – fourth output transistor T11 – second power supply first sub-voltage terminal VGL. During the third time period t3, when the voltage at the first output signal terminal OUT is high, the gate-source voltage difference of the fourth output transistor T11 is negative. Even if the threshold voltage of the fourth output transistor T11 drifts negatively, it can still turn off the fourth output transistor T11, improving the operational stability of the shift register 100.

[0076] During the fourth time period t4, the voltage at the cascaded signal input terminal STV is low, and the first input transistor T1 is off. The first node Q1 maintains a low voltage. The voltage at the first clock signal terminal CK1 is low, and the isolation transistor T4 is off. The second node Q2 maintains a high voltage, and the first output transistor T5 and the second output transistor T10 are on. The low voltage at the first sub-signal terminal CK2 of the second clock is transmitted to the second output signal terminal CR via the first output transistor T5, making CR low. The low voltage at the second sub-signal terminal BCK2 of the second clock is transmitted to the first output signal terminal OUT via the second output transistor T10, making OUT low. The third node QB maintains a high voltage, and the third output transistor T6 and the fourth output transistor T11 are on. The low voltage at the second sub-voltage terminal LVGL of the second power supply is transmitted to the second output signal terminal CR via the third output transistor T6, and the low voltage at the first sub-voltage terminal VGL of the second power supply is transmitted to the first output signal terminal OUT via the fourth output transistor T11.

[0077] During the fifth time period t5, the voltage at the cascaded signal input terminal STV is low, the first input transistor T1 is off, and the first node Q1 maintains a low voltage. The voltage at the first clock signal terminal CK1 is high, the isolation transistor T4 is on, and the voltage at the second node Q2 is pulled down by the low voltage of the first node Q1, causing the second node Q2 to become low. When the first node Q1 is low, the shutdown transistor T9 is off. When the second node Q2 is high, the first output transistor T5 and the second output transistor T10 are off. That is, the potential of the second node Q2 will be reset to low when the first clock signal terminal CK1 becomes high again. When the first node Q1 is low, the third reset transistor T3 is off. The third node QB maintains a high voltage, the third output transistor T6 and the fourth output transistor T11 are on, the low voltage at the second sub-voltage terminal LVGL of the second power supply is transmitted to the second output signal terminal CR via the third output transistor T6, and the low voltage at the first sub-voltage terminal VGL of the second power supply is transmitted to the first output signal terminal OUT via the fourth output transistor T11.

[0078] Figure 13 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 13 The first output signal terminal OUT of the current stage shift register 100 is connected to the cascade signal input terminal STV of the next stage shift register 100. Figure 13 The circuit of the shift register shown is suitable for Figure 12 The driving timing is shown.

[0079] Figure 14 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 14The first terminal of the first output transistor T5 is connected to the first sub-signal terminal CK2 of the second clock, and the first terminal of the second output transistor T10 is connected to the first sub-signal terminal CK2 of the second clock. Figure 14 The circuit of the shift register shown is suitable for Figure 12 The driving timing is shown.

[0080] Figure 15 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 15 The second terminal of the turn-off transistor T9 is connected to the second clock signal terminal 220. Figure 15 The circuit of the shift register shown is suitable for Figure 12 The driving timings are shown below. (Reference) Figure 12 and Figure 15 During the second time period t2, the clock signal provided by the second clock signal terminal 220 is a high voltage, turning on the off transistor T9. This transmits the high voltage of the first power supply voltage terminal VGH to the second terminal of the first reset transistor T7, turning off the first reset transistor T7 more completely and reducing leakage current through the first reset transistor T7. It should be noted that the voltage of the second node Q2 is pulled high by coupling during the second time period t2, making it more prone to leakage current. Therefore, turning off the first reset transistor T7 more completely during the second time period t2 can more significantly reduce the leakage current of the shift register and the gate drive circuit.

[0081] Figure 16 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 16 The gate of the first reset transistor T7 is connected to the first clock signal terminal CK1, and the second terminal of the first reset transistor T7 is connected to the output terminal of the first input unit 110. When the voltage of the first node Q1 is the on-state voltage, the turn-off unit 160 is turned on, writing the on-state voltage to the second terminal of the first reset transistor T7. Both the first and second terminals of the first reset transistor T7 are on-state voltages. The gate of the first reset transistor T7 is the turn-off voltage. The on-state voltage applied to the second terminal of the first reset transistor T7 turns off the first reset transistor T7 more completely, reducing leakage current through the first reset transistor T7 and reducing leakage current in the circuit branch where the first node Q1 and the first reset unit 150 are located.

[0082] Figure 17 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 17The first input unit 110 includes a first input transistor T1. The gate of the first input transistor T1 is connected to the first clock signal terminal CK1, the first terminal of the first input transistor T1 is connected to the cascaded signal input terminal STV, and the second terminal of the first input transistor T1 is connected to the second terminal of the first reset transistor T7. When the conduction voltage provided by the first clock signal terminal CK1 turns on the first input transistor T1, the voltage of the cascaded signal input terminal STV is transmitted to the second terminal of the first reset transistor T7. And when the first reset unit 150 is turned on, the voltage of the cascaded signal input terminal STV is transmitted to the first node Q1.

[0083] For example, refer to Figure 17 The second input unit 120 includes a second input transistor T2, the gate of which is connected to the first clock signal terminal CK1. The first terminal of the second input transistor T2 is connected to the first power supply voltage terminal VGH, and the second terminal is connected to the third node QB. During the period when the first clock signal terminal CK1 provides a conduction voltage, the second input transistor T2 is turned on, transmitting the conduction voltage provided by the first power supply voltage terminal VGH to the third node QB.

[0084] Figure 18 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 18 The shutdown unit 160 includes a shutdown transistor T9. The gate of the shutdown transistor T9 is connected to the first node Q1, and the first terminal of the shutdown transistor T9 is connected to the second terminal of the first reset transistor T7. When the shutdown transistor T9 is turned on, a conduction voltage is written to the second terminal of the first reset transistor T7, thereby turning off the first reset transistor T7 more completely.

[0085] For example, refer to Figure 18 The first terminal of the first reset transistor T7 is connected to the first node Q1. When the conduction voltage provided by the first clock signal terminal CK1 turns on the first input transistor T1 and the first reset transistor T7, the voltage of the cascaded signal input terminal STV is transmitted to the first node Q1 through the first input transistor T1 and the first reset transistor T7. The second terminal of the third reset transistor T3 is connected to the first clock signal terminal CK1.

[0086] Figure 19 For another shift register driving timing diagram provided in an embodiment of the present invention, refer to... Figure 18 and Figure 19During the first time period t1, the voltage at the first clock signal terminal CK1 is high, and the first input transistor T1 and the first reset transistor T7 are turned on. The voltage at the cascade signal input terminal STV is high, and this high voltage is transmitted to the first node Q1. When the first node Q1 is high, the third reset transistor T3 is turned on, and the high voltage at the first clock signal terminal CK1 is transmitted to the third node QB. With the first clock signal terminal CK1 high, the second input transistor T2 is turned on, and the high voltage at the first power supply voltage terminal VGH is transmitted to the third node QB via the second input transistor T2, making the third node QB high. When the first node Q1 is high, the first output transistor T5 is turned on, transmitting the low voltage at the first sub-signal terminal CK2 of the second clock to the first output signal terminal OUT. When the third node QB is high, the third output transistor T6 is turned on, transmitting the low voltage at the first sub-signal terminal VGL of the second power supply to the first output signal terminal OUT. The first output signal terminal OUT is low.

[0087] During the second time period t2, the voltage at the first clock signal terminal CK1 is low, and the first input transistor T1, the second input transistor T2, and the first reset transistor T7 are off. The first node Q1 maintains a high voltage, the third reset transistor T3 is on, and the low voltage at the first clock signal terminal CK1 is transmitted to the third node QB. The third node QB then becomes low. The third output transistor T6 is off. The second node Q2 maintains a high voltage, the first output transistor T5 is on, and the second clock signal terminal 220 becomes high. The high voltage at the second clock signal terminal 220 is transmitted to the first output signal terminal OUT through the first output transistor T5, making the first output signal terminal OUT high. With the first node Q1 high, the turn-off transistor T9 is on, transmitting the high voltage at the first power supply voltage terminal VGH through the turn-off transistor T9 to the second terminal of the first reset transistor T7, thus turning off the first reset transistor T7 more completely, reducing leakage current through the first reset transistor T7, and reducing leakage current in the circuit branch containing the first node Q1 – first reset transistor T7 – first input transistor T1 – cascaded signal input terminal STV. The voltage at the first clock signal terminal CK1 is low, and the isolation transistor T4 is off. Due to the bootstrap effect of the first capacitor C1, the voltage at the second node Q2 is coupled to a higher potential by the first capacitor C1. The higher the gate voltage of the first output transistor T5, the more thoroughly the first output transistor T5 is turned on, and the stronger the voltage transmission capability of the first output transistor T5, thus improving the driving capability of the enable voltage output at the first output signal terminal OUT.

[0088] During the third time period t3, the voltage at the first clock signal terminal CK1 is high, and the first input transistor T1 and the first reset transistor T7 are turned on. The voltage at the cascade signal input terminal STV is low, and this low voltage is transmitted to the first node Q1. The first node Q1 becomes low. When the first node Q1 is low, the third reset transistor T3 is turned off. The voltage at the first clock signal terminal CK1 is high, the isolation transistor T4 is turned on, and the voltage at the second node Q2 is pulled low by the low voltage at the first node Q1, causing the second node Q2 to become low. The first output transistor T5 is turned off. The voltage at the first clock signal terminal CK1 is high, the second input transistor T2 is turned on, and the high voltage at the first power supply voltage terminal VGH is transmitted to the third node QB through the second input transistor T2, causing the third node QB to become high. When the third node QB is high, the third output transistor T6 is turned on, transmitting the low voltage at the first sub-voltage terminal VGL of the second power supply to the first output signal terminal OUT. The first output signal terminal OUT becomes low.

[0089] Figure 20 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 1 and Figure 20 The first terminal of the first output transistor T5 is connected to the first sub-signal terminal CK2 of the second clock, and the first terminal of the second output transistor T10 is connected to the first sub-signal terminal CK2 of the second clock. Figure 20 The circuit of the shift register shown is suitable for Figure 19 The driving timing is shown. The second output signal terminal CR of the current stage shift register 100 is connected to the cascade signal input terminal STV of the next stage shift register 100.

[0090] Figure 21 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 21 The first terminal of the first output transistor T5 is connected to the first sub-signal terminal CK2 of the second clock, and the first terminal of the second output transistor T10 is connected to the second sub-signal terminal BCK2 of the second clock. Figure 21 The circuit of the shift register shown is suitable for Figure 19 The driving timing is shown.

[0091] Figure 22 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 1 and Figure 22The shift register 100 also includes a second reset unit 170, which is used to write a turn-off voltage to the second node Q2. The second reset unit 170 includes a fourth reset transistor T12, the gate of which is connected to the third clock signal terminal CK3. The first terminal of the fourth reset transistor T12 is connected to the second node Q2. The first terminal of the turn-off unit 160 is connected to the second terminal of the fourth reset transistor T12, and is used to write a conduction voltage to the second terminal of the fourth reset transistor T12 when the first node Q1 controls the turn-off unit 160 to be turned on. When the voltage of the first node Q1 is the conduction voltage, the turn-off unit 160 is turned on, writing the conduction voltage to the second terminal of the fourth reset transistor T12. Both the first and second terminals of the fourth reset transistor T12 are conduction voltages. The gate of the fourth reset transistor T12 is at the turn-off voltage. The turn-on voltage applied to the second terminal of the fourth reset transistor T12 turns it off more completely, reducing leakage current through the fourth reset transistor T12 and reducing leakage current in the circuit branch where the second node Q2 and the second reset unit 170 are located. On the other hand, the second reset unit 170 is used to write the turn-off voltage to the second node Q2, thereby resetting the second node Q2.

[0092] Figure 23 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 23 The second reset unit 170 also includes a fifth reset transistor T13. The gate of the fifth reset transistor T13 is connected to the third clock signal terminal CK3, the first terminal of the fifth reset transistor T13 is connected to the second terminal of the fourth reset transistor T12, and the second terminal of the fifth reset transistor T13 is connected to the second power supply voltage terminal 230. The second power supply voltage terminal 230 provides a turn-off voltage. The turn-on voltage applied to the second terminal of the fourth reset transistor T12 more completely turns off the fourth reset transistor T12, reducing leakage current through the fourth reset transistor T12 and reducing leakage current in the circuit branch containing the second node Q2—fourth reset transistor T12—fifth reset transistor T13—second power supply voltage terminal 230.

[0093] For example, refer to Figure 23 The same shutdown unit 160 can both shut down the first reset transistor T7 more thoroughly, reducing leakage current through the first reset transistor T7, and shut down the fourth reset transistor T12 more thoroughly, reducing leakage current through the fourth reset transistor T12.

[0094] Figure 24 This is a circuit diagram of another shift register provided in an embodiment of the present invention. Figure 25 This is a timing diagram for driving another shift register provided in an embodiment of the present invention. Figure 25 and Figure 12 The same process will not be repeated here. (See reference) Figure 24 and Figure 25 During the first time period t1, the first node Q1 becomes high voltage, and the second node Q2 becomes high voltage. When the first node Q1 is high voltage, the turn-off transistor T9 turns on, transmitting the high voltage to the second terminal of the first reset transistor T7, thus turning off the first reset transistor T7 more completely. The third clock signal terminal CK3 is low voltage, and the fourth reset transistor T12 turns off. The turn-off transistor T9 turns on, transmitting the high voltage to the second terminal of the fourth reset transistor T12, thus turning off the fourth reset transistor T12 more completely.

[0095] During the second time period t2, the first node Q1 maintains a high voltage. When the first node Q1 is high, transistor T9 is turned off, transferring the high voltage to the second terminal of the first reset transistor T7, thus turning off T7 more completely. The third clock signal terminal CK3 is low, and the fourth reset transistor T12 is turned off. Transistor T9 is then turned on, transferring the high voltage to the second terminal of the fourth reset transistor T12, thus turning off T12 more completely.

[0096] During the third time period t3, the first clock signal terminal CK1 is at a low voltage, and the isolation transistor T4 is off. The third clock signal terminal CK3 is at a high voltage, the second input transistor T2 is on, and the third node QB becomes high. When the third clock signal terminal CK3 and the third node QB are high, the first reset transistor T7 and the second reset transistor T8 are on, and the low voltage of the second sub-voltage terminal LVGL of the second power supply is transmitted to the first node Q1, making the first node Q1 low. When the first node Q1 is low, the third reset transistor T3 and the turn-off transistor T9 are off. When the third clock signal terminal CK3 is high, the fourth reset transistor T12 is on, and the low voltage of the second sub-voltage terminal LVGL of the second power supply is transmitted to the second node Q2 through the second reset transistor T8 and the fourth reset transistor T12, pulling the second node Q2 from high voltage to low voltage. This achieves the reset of the second node Q2. During the third time period t3, when the second node Q2 is low, the first output transistor T5 and the second output transistor T10 are off. When the third node QB is at a high voltage, the third output transistor T6 and the fourth output transistor T11 are turned on. The low voltage of the second sub-voltage terminal LVGL of the second power supply is transmitted to the second output signal terminal CR through the third output transistor T6, and the low voltage of the first sub-voltage terminal VGL of the second power supply is transmitted to the first output signal terminal OUT through the fourth output transistor T11.

[0097] Figure 26 This is a circuit diagram of another shift register provided in an embodiment of the present invention. Figure 26 The circuit of the shift register shown is suitable for Figure 25The drive timing shown is for reference. Figure 25 and Figure 26 The second reset unit 170 further includes a fifth reset transistor T13. The gate of the fifth reset transistor T13 is connected to the third clock signal terminal CK3, the first terminal of the fifth reset transistor T13 is connected to the second terminal of the fourth reset transistor T12, and the second terminal of the fifth reset transistor T13 is connected to the second sub-voltage terminal LVGL of the second power supply. During the third time period t3, the third node QB is at a high voltage, and the second reset transistor T8 is turned on. The third clock signal terminal CK3 is at a high voltage, and the fourth reset transistor T12 and the fifth reset transistor T13 are turned on. The low voltage of the second sub-voltage terminal LVGL of the second power supply is transmitted to the second node Q2 through the second reset transistor T8 and the fourth reset transistor T12, and the low voltage of the second sub-voltage terminal LVGL of the second power supply is transmitted to the second node Q2 through the fifth reset transistor T13 and the fourth reset transistor T12, thus resetting the second node Q2.

[0098] Figure 27 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 1 and Figure 27 The first output signal terminal OUT of the current stage shift register 100 is connected to the cascade signal input terminal STV of the next stage shift register 100. Figure 27 The circuit of the shift register shown is suitable for Figure 25 The driving timing is shown.

[0099] Figure 28 This is a circuit diagram of another shift register provided in an embodiment of the present invention, referred to... Figure 28 The second terminal of the turn-off transistor T9 is connected to the second clock signal terminal 220. Figure 28 The circuit of the shift register shown is suitable for Figure 25 The driving timing is shown.

[0100] Figure 29 This is a circuit diagram of another gate driving circuit provided in an embodiment of the present invention, referred to... Figure 29The gate drive circuit also includes a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, and a fourth clock signal line CLK4. The first clock signal line CLK1 is electrically connected to the first clock signal terminal CK1 of the i-th shift register 100, the third clock signal terminal CK3 of the (i+2)-th shift register 100, and the second clock signal terminal 220 of the (i+3)-th shift register 100. The second clock signal line CLK2 is electrically connected to the second clock signal terminal 220 of the i-th shift register 100, the first clock signal terminal CK1 of the (i+1)-th shift register 100, and the third clock signal terminal CK3 of the (i+3)-th shift register 100. The third clock signal line CLK3 is electrically connected to the third clock signal terminal CK3 of the i-th shift register 100, the second clock signal terminal 220 of the (i+1)-th shift register 100, and the first clock signal terminal CK1 of the (i+3)-th shift register 100. The fourth clock signal line CLK4 is electrically connected to the third clock signal terminal CK3 of the (i+1)th shift register 100, the second clock signal terminal 220 of the (i+2)th shift register 100, and the first clock signal terminal CK1 of the (i+3)th shift register 100. The first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4 provide corresponding clock signals to the connected clock signal terminals. i is a positive integer.

[0101] For example, refer to Figure 29 The cascaded shift registers 100 include a first shift register VSR1, a second shift register VSR2, a third shift register VSR3, and a fourth shift register VSR4. A first clock signal line CLK1 is electrically connected to the first clock signal terminal CK1 of the first shift register VSR1, the third clock signal terminal CK3 of the third shift register VSR3, and the second clock signal terminal 220 of the fourth shift register VSR4. A second clock signal line CLK2 is electrically connected to the second clock signal terminal 220 of the first shift register VSR1, the first clock signal terminal CK1 of the second shift register VSR2, and the third clock signal terminal CK3 of the fourth shift register VSR4. A third clock signal line CLK3 is electrically connected to the third clock signal terminal CK3 of the first shift register VSR1, the second clock signal terminal 220 of the second shift register VSR2, and the first clock signal terminal CK1 of the third shift register VSR3. The fourth clock signal line CLK4 is electrically connected to the third clock signal terminal CK3 of the second shift register VSR2, the second clock signal terminal 220 of the third shift register VSR3, and the first clock signal terminal CK1 of the fourth shift register VSR4.

[0102] For example, refer to Figure 29The gate drive circuit also includes an initial signal line STVL, which is electrically connected to the cascaded signal input terminal STV of the first shift register VSR1.

[0103] For example, refer to Figure 12 and Figure 29 , Figure 12 The driving timing shown can be the driving timing for the first shift register VSR1. The first clock signal line CLK1 is electrically connected to the first clock signal terminal CK1 of the first shift register VSR1, providing a clock signal to CK1. The second clock signal line CLK2 is electrically connected to the second clock signal terminal 220 of the first shift register VSR1, providing a clock signal to CK1. The third clock signal line CLK3 is electrically connected to the third clock signal terminal CK3 of the first shift register VSR1, providing a clock signal to CK3.

[0104] Figure 30 This is a circuit diagram of another gate driving circuit provided in an embodiment of the present invention, referred to... Figure 30 The gate drive circuit also includes a first clock signal line CLK1 and a second clock signal line CLK2. The first clock signal line CLK1 is electrically connected to the first clock signal terminal CK1 of the i-th shift register 100 and the second clock signal terminal 220 of the (i+1)-th shift register 100. The second clock signal line CLK2 is electrically connected to the second clock signal terminal 220 of the i-th shift register 100 and the first clock signal terminal CK1 of the (i+1)-th shift register 100. The first clock signal line CLK1 and the second clock signal line CLK2 provide corresponding clock signals to the clock signal terminals connected to them. i is a positive integer.

[0105] For example, refer to Figure 30 The cascaded shift registers 100 include a first shift register VSR1, a second shift register VSR2, and a third shift register VSR3. A first clock signal line CLK1 is electrically connected to the first clock signal terminal CK1 of the first shift register VSR1 and the second clock signal terminal 220 of the second shift register VSR2. A second clock signal line CLK2 is electrically connected to the second clock signal terminal 220 of the first shift register VSR1 and the first clock signal terminal CK1 of the second shift register VSR2.

[0106] For example, refer to Figure 19 and Figure 30 , Figure 19The driving timing shown can be the driving timing for the first shift register VSR1. The first clock signal line CLK1 is electrically connected to the first clock signal terminal CK1 of the first shift register VSR1, providing a clock signal to the first clock signal terminal CK1 of the first shift register VSR1. The second clock signal line CLK2 is electrically connected to the second clock signal terminal 220 of the first shift register VSR1, providing a clock signal to the second clock signal terminal 220 of the first shift register VSR1.

[0107] Figure 31 This is a schematic diagram of a display panel provided in an embodiment of the present invention, with reference to... Figure 31 The display panel includes the gate driving circuit 200 in the above embodiments. Since the display panel provided in this embodiment includes the gate driving circuit 200 in the above embodiments, the shift register 100 in the gate driving circuit 200 can have a small leakage current.

[0108] For example, refer to Figure 31 The display panel includes a display area AA and a non-display area NAA. A gate driving circuit 200 is located in the non-display area NAA, and a pixel driving circuit 330 is located in the display area AA. Multiple pixel driving circuits 330 are arranged in an array along a first direction X and a second direction Y. The display panel also includes multiple scan lines 121, which extend along the first direction X and are arranged along the second direction Y. The first output signal terminal OUT of the shift register 100 is electrically connected to one scan line 121. The pixel driving circuit 330 can be, for example, a 2T1C or 7T1C pixel driving circuit, which are well-known in the art and will not be described in detail here.

[0109] Figure 32 This is a schematic diagram of a display device provided in an embodiment of the present invention. (Reference) Figure 32 The display device includes any of the display panels provided in the embodiments of the present invention. Specifically, the display device can be a mobile phone, tablet computer, in-vehicle display device, or smart wearable device, etc.

[0110] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A gate driving circuit, comprising a plurality of cascaded shift registers, characterized in that, The shift register includes a first input unit, a second input unit, a first output unit, a second output unit, a first reset unit, and a shutdown unit; The output terminal of the first input unit and the control terminal of the first output unit are connected to the first node, the output terminal of the second input unit and the control terminal of the second output unit are connected to the third node, and the third node is connected to the first reset unit; The first reset unit is used to write a shutdown voltage to the first node, the shutdown voltage being a voltage that controls the first output unit to turn off; the first reset unit includes a first reset transistor, the gate of the first reset transistor being connected to a first clock signal terminal or a third clock signal terminal; the first terminal of the first reset transistor is connected to the first node; The control terminal of the shutdown unit is connected to the first node, and the first terminal of the shutdown unit is connected to the second terminal of the first reset transistor. When the first node controls the shutdown unit to be turned on, the shutdown unit is used to write the turn-on voltage to the second terminal of the first reset transistor. The turn-on voltage is the voltage that controls the first output unit to be turned on.

2. The gate driving circuit according to claim 1, characterized in that, The shutdown unit includes a shutdown transistor, the gate of which is connected to the first node, and the first terminal of which is connected to the second terminal of the first reset transistor.

3. The gate driving circuit according to claim 2, characterized in that, The second terminal of the turn-off transistor is connected to a first power supply voltage terminal, which provides the turn-on voltage.

4. The gate driving circuit according to claim 2, characterized in that, The second terminal of the turn-off transistor is connected to either the first clock signal terminal or the second clock signal terminal.

5. The gate driving circuit according to claim 1, characterized in that, The shift register further includes an isolation transistor, the gate of which is connected to the first clock signal terminal, the first terminal of which is connected to the first node, and the second terminal of which, along with the control terminal of the first output unit, is connected to the second node.

6. The gate driving circuit according to claim 5, characterized in that, The first output unit includes a first output transistor and a first capacitor. The gate of the first output transistor is connected to the second node, the first terminal of the first output transistor is connected to the second clock signal terminal, and the second terminal of the first output transistor is connected to the output signal terminal.

7. The gate driving circuit according to claim 6, characterized in that, The shift register further includes a second capacitor, the first plate of which is connected to the first node, and the second plate of which is connected to a second power supply voltage terminal, which provides the turn-off voltage. The capacitance value of the second capacitor is greater than the capacitance value of the first capacitor.

8. The gate driving circuit according to claim 6, characterized in that, The second clock signal terminal includes a second clock first sub-signal terminal and a second clock second sub-signal terminal. The second clock first sub-signal terminal and the second clock second sub-signal terminal provide voltages with the same timing but different voltage values. The output signal terminal includes a first output signal terminal and a second output signal terminal; the first terminal of the first output transistor is connected to the first sub-signal terminal of the second clock, and the second terminal of the first output transistor is connected to the first output signal terminal; The first output unit further includes a second output transistor, the gate of which is connected to the second node, the first terminal of which is connected to the first sub-signal terminal of the second clock or the second sub-signal terminal of the second clock, and the second terminal of which is connected to the second output signal terminal.

9. The gate driving circuit according to claim 1, characterized in that, The first reset unit further includes a second reset transistor, the gate of which is connected to the third node, the first terminal of which is connected to the second terminal of the first reset transistor, and the second terminal of which is connected to a second power supply voltage terminal, which provides the turn-off voltage.

10. The gate driving circuit according to claim 9, characterized in that, The first input unit includes a first input transistor, the gate of which is connected to a cascaded signal input terminal, the first terminal of which is connected to a first power supply voltage terminal, the first power supply voltage terminal providing the turn-on voltage, and the second terminal of which is connected to the first node.

11. The gate driving circuit according to claim 1, characterized in that, The shift register includes a second power supply voltage terminal that provides the turn-off voltage. The second power supply voltage terminal includes a second power supply first sub-voltage terminal and a second power supply second sub-voltage terminal. The voltage provided by the second power supply first sub-voltage terminal is greater than the voltage provided by the second power supply second sub-voltage terminal. The second output unit includes a third output transistor, the gate of which is connected to the third node, the first terminal of which is connected to the second sub-voltage terminal of the second power supply, and the second terminal of which is connected to the output signal terminal. The shift register further includes a third reset transistor, the gate of which is connected to the first node, the first terminal of which is connected to the third node, and the second terminal of which is connected to the second sub-voltage terminal of the second power supply.

12. The gate driving circuit according to claim 1, characterized in that, The gate of the first reset transistor is connected to the first clock signal terminal, and the second terminal of the first reset transistor is connected to the output terminal of the first input unit.

13. The gate driving circuit according to claim 12, characterized in that, The first input unit includes a first input transistor, the gate of the first input transistor is connected to the first clock signal terminal, the first terminal of the first input transistor is connected to the cascaded signal input terminal, and the second terminal of the first input transistor is connected to the second terminal of the first reset transistor.

14. The gate driving circuit according to claim 5, characterized in that, The shift register further includes a second reset unit, which is used to write the turn-off voltage to the second node; The second reset unit includes a fourth reset transistor, the gate of which is connected to the third clock signal terminal; The first terminal of the fourth reset transistor is connected to the second node; The first terminal of the shutdown unit is connected to the second terminal of the fourth reset transistor, and is used to write the turn-on voltage to the second terminal of the fourth reset transistor when the first node controls the shutdown unit to be turned on.

15. The gate driving circuit according to claim 14, characterized in that, The second reset unit further includes a fifth reset transistor; The gate of the fifth reset transistor is connected to the third clock signal terminal, the first terminal of the fifth reset transistor is connected to the second terminal of the fourth reset transistor, the second terminal of the fifth reset transistor is connected to the second power supply voltage terminal, and the second power supply voltage terminal provides the turn-off voltage.

16. The gate driving circuit according to claim 1, characterized in that, It also includes a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; The first clock signal line is electrically connected to the first clock signal terminal of the i-th shift register, the third clock signal terminal of the (i+2)-th shift register, and the second clock signal terminal of the (i+3)-th shift register. The second clock signal line is electrically connected to the second clock signal terminal of the i-th shift register, the first clock signal terminal of the (i+1)-th shift register, and the third clock signal terminal of the (i+3)-th shift register. The third clock signal line is electrically connected to the third clock signal terminal of the i-th shift register, the second clock signal terminal of the (i+1)-th shift register, and the first clock signal terminal of the (i+2)-th shift register. The fourth clock signal line is electrically connected to the third clock signal terminal of the (i+1)th shift register, the second clock signal terminal of the (i+2)th shift register, and the first clock signal terminal of the (i+3)th shift register; i is a positive integer.

17. The gate driving circuit according to claim 1, characterized in that, It also includes a first clock signal line and a second clock signal line; The first clock signal line is electrically connected to the first clock signal terminal of the i-th shift register and the second clock signal terminal of the (i+1)-th shift register; The second clock signal line is electrically connected to the second clock signal terminal of the i-th shift register and the first clock signal terminal of the (i+1)-th shift register; i is a positive integer.

18. A display panel, characterized in that, Includes the gate drive circuit according to any one of claims 1-17.

19. A display device, characterized in that, Includes the display panel as described in claim 18.

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