MIM capacitor and its manufacturing method

Abstract

This invention provides a MIM capacitor and its fabrication method. The method includes: forming an interconnect layer on a substrate on which a front-end semiconductor device has been formed; the interconnect layer includes: a metal interconnect layer located in the device region, which is connected to the front-end semiconductor device through contact holes in the substrate, including multiple interconnect metal layers and interconnect vias connecting adjacent interconnect metal layers; and a first MIM capacitor lower electrode located in the edge region, including multiple lower electrode metal layers and lower electrode vias connecting adjacent lower electrode metal layers; forming a waterproof trench of a predetermined depth in the edge region of the interconnect layer, wherein the first MIM capacitor lower electrode is located outside at least one sidewall of the waterproof trench; depositing a waterproof layer on the surface of the interconnect layer; and forming a first MIM upper electrode metal layer on the surface of the waterproof trench. This invention utilizes the waterproof layer as the capacitor dielectric layer, fabricating an additional MIM capacitor at the waterproof trench without adding a photomask.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a MIM capacitor and its fabrication method. Background Technology

[0002] With the development of integrated circuits, the requirements for capacitor capacitance are getting higher and higher, especially for MIM capacitors used in RF front-end modules. MIM capacitors not only need to have large capacitance, but also need to have high Q value under high frequency application conditions.

[0003] Currently, the industry typically increases the capacitance of MIM capacitors by increasing capacitance density, increasing the area of ​​MIM capacitors, and designing composite structures with double or multi-layer MIM capacitors connected in parallel.

[0004] However, the above methods suffer from significant waste of wafer area and increased costs due to the addition of photomasks. How to achieve high capacitance density MIM capacitors without increasing the number of photomasks or wasting wafer area has become a pressing technical problem for the industry. Summary of the Invention

[0005] This invention provides a MIM capacitor device and its fabrication method, solving the technical problem of how to realize a MIM capacitor device without increasing the number of photomasks or wasting wafer area.

[0006] According to a first aspect of the present invention, an embodiment of the present invention provides a method for manufacturing a MIM capacitor, comprising:

[0007] A substrate is provided on which a front-end semiconductor device and a first interlayer dielectric layer are formed, and a contact hole is formed in the first interlayer dielectric layer; wherein, the substrate includes a device region and an edge region, and the front-end semiconductor device is formed in the device region;

[0008] An interconnect layer is formed on the first interlayer dielectric layer; the interconnect layer includes a metal interconnect layer located in the device region and a first MIM capacitor lower electrode located in the edge region; the metal interconnect layer is electrically connected to the contact hole, and the metal interconnect layer includes multiple interconnect metal layers and interconnect vias electrically connected to adjacent interconnect metal layers; the first MIM capacitor lower electrode includes multiple lower electrode metal layers and lower electrode vias electrically connected to adjacent lower electrode metal layers;

[0009] A waterproof trench of a predetermined depth is formed in the edge region of the interconnect layer; the lower electrode of the first MIM capacitor is located on the outside of at least one side wall of the waterproof trench;

[0010] A waterproof layer is deposited on the surface of the interconnect layer, the waterproof layer covering the surface of the interconnect layer, as well as the bottom and sidewalls of the waterproof layer trench;

[0011] A first MIM upper electrode metal layer is formed at the bottom and sidewall of the waterproof layer trench. The first MIM capacitor lower electrode, the waterproof layer, and the first MIM upper electrode metal layer constitute the first MIM capacitor.

[0012] Optionally, an interconnect layer is formed on the first interlayer dielectric layer, including:

[0013] A first interconnect dielectric layer is formed on the first interlayer dielectric layer, and a first interconnect metal layer and a first lower electrode metal layer are formed in the first interconnect dielectric layer.

[0014] At least one barrier layer and at least one second interconnect dielectric layer are sequentially formed on the first interconnect dielectric layer. The second interconnect dielectric layer has a first interconnect via, a second interconnect metal layer, a first lower electrode via, and a second lower electrode metal layer. The first interconnect via penetrates the barrier layer and is electrically connected to the second interconnect metal layer and the first interconnect metal layer. The first lower electrode via penetrates the barrier layer and is electrically connected to the second lower electrode metal layer and the first lower electrode metal layer.

[0015] Optionally, the barrier layer and the second interconnect dielectric layer are multiple layers, with multiple barrier layers and multiple second interconnect dielectric layers spaced apart. Each second interconnect dielectric layer has a first interconnect via, a second interconnect metal layer, a first lower electrode via, and a second lower electrode metal layer.

[0016] The first interconnect via is also electrically connected to the second interconnect metal layer adjacent to the second interconnect dielectric layer;

[0017] The first lower electrode through-hole is also electrically connected to the second lower electrode metal layer of the adjacent second interconnect dielectric layer.

[0018] Optionally, the materials of the interconnect vias, the interconnect metal layer, and the lower electrode vias are the same as the material of the lower electrode metal layer.

[0019] Optionally, a waterproof trench of a predetermined depth is formed in the edge region of the interconnect layer, including:

[0020] A mask layer is formed on the interconnect layer, the mask layer including a waterproof layer pattern located in the edge region;

[0021] The interconnect layer is etched using the mask layer as a mask to form a waterproof trench of a predetermined depth.

[0022] Optionally, the bottom of the waterproof layer trench is lower than the bottom of the interconnect metal layer in the first interconnect dielectric layer.

[0023] Optionally, the method further includes:

[0024] When forming the top interconnect metal layer in the multilayer interconnect metal layers, the lower electrode metal layer of the second MIM capacitor is formed;

[0025] When a first MIM upper electrode metal layer is formed at the bottom and sidewall of the waterproof layer trench, a second MIM upper electrode metal layer is formed on the lower electrode metal layer of the second MIM capacitor.

[0026] The second MIM capacitor consists of the lower electrode plate, the waterproof layer, and the metal layer of the upper electrode plate.

[0027] Optionally, forming a first MIM upper electrode metal layer and a second MIM upper electrode metal layer includes:

[0028] A metal layer for the upper electrode is deposited on the waterproof layer;

[0029] A mask layer is formed on the upper electrode metal layer, the mask layer including a first MIM capacitor upper electrode metal layer pattern opening and a second MIM capacitor upper electrode metal layer pattern opening;

[0030] Using the mask layer as a mask, the upper electrode metal layer is etched to form the first MIM upper electrode metal layer and the second MIM upper electrode metal layer.

[0031] According to a second aspect of the present invention, an embodiment of the present invention provides a MIM capacitor device, comprising:

[0032] A substrate on which a front-end semiconductor device and a first interlayer dielectric layer have been formed, and a contact hole has been formed in the first interlayer dielectric layer; wherein, the substrate includes a device region and an edge region, and the front-end semiconductor device is formed in the device region;

[0033] An interconnect layer is located on the first interlayer dielectric layer, wherein the interconnect layer includes a metal interconnect layer located in the device region, a first MIM capacitor lower electrode located in the edge region, and a waterproof layer trench located in the edge region of the interconnect layer; the metal interconnect layer is electrically connected to the contact hole, and the metal interconnect layer includes multiple interconnect metal layers and interconnect vias electrically connected to adjacent interconnect metal layers; the first MIM capacitor lower electrode is located outside at least one sidewall of the waterproof layer trench, and includes multiple lower electrode metal layers and lower electrode vias electrically connected to adjacent lower electrode metal layers;

[0034] A waterproof layer is located on the surface of the interconnect layer, the waterproof layer covering the surface of the interconnect layer, as well as the bottom and sidewalls of the waterproof layer trench;

[0035] A first MIM upper electrode metal layer is formed at the bottom and sidewall of the waterproof layer trench; wherein, the first MIM capacitor lower electrode, the waterproof layer, and the first MIM upper electrode metal layer constitute the first MIM capacitor.

[0036] Optionally, the MIM capacitor further includes a second MIM capacitor, the second MIM capacitor comprising:

[0037] The lower electrode metal layer of the second MIM capacitor is formed simultaneously with the top interconnect metal layer in the multilayer interconnect metal layer.

[0038] The second MIM upper electrode metal layer is formed on the waterproof layer and covers the first part of the second MIM capacitor lower electrode metal layer, and the second MIM upper electrode metal layer and the first MIM capacitor upper electrode metal layer are formed simultaneously.

[0039] The second MIM capacitor is composed of the lower electrode plate of the second MIM capacitor, the waterproof layer, and the metal layer of the upper electrode plate of the second MIM capacitor.

[0040] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0041] The MIM capacitor and its fabrication method provided by this invention involve forming a first MIM capacitor lower electrode plate on at least one sidewall of a waterproof layer trench, using the waterproof layer as the capacitor dielectric layer, and forming a first MIM upper electrode plate metal layer on the bottom and sidewall of the waterproof layer trench. The first MIM capacitor lower electrode plate, the waterproof layer, and the first MIM upper electrode plate metal layer constitute a first MIM capacitor. Since the waterproof layer is an inherent structure in existing semiconductor devices, and its fabrication method is also an inherent procedure in existing semiconductor devices, this method ingeniously achieves the formation of a first MIM capacitor during the formation of the waterproof layer. This allows for the fabrication of an additional MIM capacitor at the waterproof layer trench without adding a photomask, efficiently utilizing the wafer area. Furthermore, because the waterproof layer trench is a deep trench, the area of ​​the first MIM capacitor is significantly increased compared to conventional MIM capacitors, thereby greatly improving the capacitance of the MIM capacitor.

[0042] Furthermore, the materials of the interconnect vias, the interconnect metal layer, and the lower electrode via are the same as the material of the lower electrode metal layer. This allows the lower electrode of the first MIM capacitor to be fabricated simultaneously with the interconnect layer, eliminating the need for additional processes, reducing the number of photomasks, and further saving costs. Furthermore, since the materials of the interconnect vias and the interconnect metal layer are copper, the resistance of the lower electrode of the first MIM capacitor is significantly reduced, thereby improving the Q value of the capacitor.

[0043] Furthermore, during the formation of the top interconnect metal layer in the multilayer interconnect metal layers, a second MIM capacitor lower electrode metal layer is also formed simultaneously. Conversely, during the formation of the first MIM upper electrode metal layer, a second MIM upper electrode metal layer is formed on the second MIM capacitor lower electrode metal layer. Thus, a second MIM capacitor is formed using the second MIM capacitor lower electrode metal layer, the waterproof layer, and the second MIM upper electrode metal layer. The second MIM capacitor and the first MIM capacitor can be connected in parallel, thereby further increasing the capacitance of the MIM capacitor. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a flowchart of a method for manufacturing a MIM capacitor provided in one embodiment of the present invention;

[0046] Figures 2 to 20 This is a schematic diagram of the device structure corresponding to each step of the fabrication method of the MIM capacitor provided in an embodiment of the present invention.

[0047] Explanation of reference numerals in the attached figures:

[0048] 10-Substrate;

[0049] 101 - Top layer silicon;

[0050] 102 - Insulation layer;

[0051] 103 - Bottom substrate;

[0052] 104 - First interlayer dielectric layer;

[0053] 105 - Front-end semiconductor devices;

[0054] 106 - Contact hole barrier layer;

[0055] 107 - Contact hole;

[0056] 108 - First barrier layer;

[0057] 109 - Device Area;

[0058] 110 - Edge Zone;

[0059] 20 - Interconnect layer;

[0060] 201 - First interconnect dielectric layer;

[0061] 202 - First oxide layer;

[0062] 203 - First hard mask layer;

[0063] 204 - Second barrier layer;

[0064] 205 - Metallic material layer;

[0065] 206 - Second interconnect dielectric layer;

[0066] 207 - Second hard mask layer;

[0067] 208 - Waterproof layer;

[0068] 210 - Metal interconnect layer;

[0069] 211 - First interconnect metal layer;

[0070] 212 - First interconnect via;

[0071] 213 - Second interconnect metal layer;

[0072] 220 - Lower plate of the first MIM capacitor;

[0073] 221 - First lower electrode metal layer;

[0074] 222 - First lower electrode plate through hole;

[0075] 223 - Second lower electrode metal layer;

[0076] 230 - Second MIM lower electrode metal layer;

[0077] 240 - First MIM upper electrode metal layer;

[0078] 241 - Third barrier material layer;

[0079] 242 - Second MIM upper electrode metal layer;

[0080] 243 - Third barrier layer;

[0081] 301 - Photoresist layer;

[0082] 401 - Third interconnect dielectric layer;

[0083] 402 - Through hole;

[0084] 403 - Fourth interconnect dielectric layer;

[0085] 404 - Second metal interconnect layer;

[0086] 405 - Fourth barrier layer;

[0087] 406 - Fifth interconnect dielectric layer;

[0088] 407 - Contact metal layer;

[0089] 408 - Buffer layer;

[0090] 409 - Passivation layer. Detailed Implementation

[0091] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0092] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0093] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0094] Prior to filing this application, the applicant conducted thorough research on MIM capacitors. MIM capacitors are widely used in the electronics field as charge storage, coupling, and filtering devices, and their fabrication is a crucial step in the semiconductor integrated circuit manufacturing process. With increasingly stringent requirements for semiconductor chip integration and performance, there is a pressing need to improve the overall performance of semiconductor devices to achieve faster processing speeds, larger data storage capacities, and more functions, leading to increasingly higher capacitance requirements for capacitors. In particular, MIM capacitors used in RF front-end modules not only require large capacitance but also high Q values ​​under high-frequency applications to meet the demands of 5G, Sub-6G, and millimeter-wave technologies.

[0095] The quality factor Q reflects the capacitor's losses. A higher quality factor indicates lower distortion and better capacitor performance. The formula for calculating the quality factor Q is as follows:

[0096] Q = 2πfL / R

[0097] Where f is the resonant frequency of the capacitor, L is the inductance value, and R is the resistance value of the resonant circuit. The resistance values ​​of the upper and lower plates of the MIM capacitor also affect its Q value. Lower resistance of the upper and lower plates of the MIM capacitor helps reduce capacitor losses, thereby improving the capacitor's Q value and making it perform better in high-frequency applications.

[0098] The ratio of the charge on a capacitor to the voltage U across its terminals is called the capacitance. The capacitance of a capacitor can be calculated using the following formula:

[0099] C=ε·A / d

[0100] Where C represents the capacitance value, ε represents the dielectric constant, A represents the area of ​​the capacitor plates facing each other, and d represents the dielectric thickness of the capacitor.

[0101] In view of the three methods for increasing the capacitance of capacitors in RF chips studied by the applicant in the background art and their inherent defects, the applicant, in conjunction with the inherent procedures of chip manufacturing, has conducted in-depth research on how to fabricate high-capacitance-density MIM capacitors without increasing the number of photomasks or wasting wafer area, and has found a breakthrough to solve the corresponding technical problems, as follows:

[0102] The applicant discovered that in high-frequency applications, radio frequency (RF) chips typically employ discontinuous die seal rings to ensure proper signal reception and transmission. However, this allows moisture to easily penetrate the chip, affecting its reliability. Therefore, RF chips have extremely high requirements for water resistance. The RFSOI process usually adds an additional photomask to create a water block layer (WBL) to protect the circuitry and improve chip reliability. Specifically, the water block layer is located around the periphery of the RF chip body. The formation of the water block layer requires first creating a deep trench, which is then filled with the water block layer.

[0103] In view of this, the present invention proposes a method for manufacturing a MIM capacitor, which may include:

[0104] A substrate is provided on which a front-end semiconductor device and a first interlayer dielectric layer are formed, and a contact hole is formed in the first interlayer dielectric layer; wherein the substrate includes a device region and an edge region, and the front-end semiconductor device is formed in the device region.

[0105] An interconnect layer is formed on the first interlayer dielectric layer; the interconnect layer includes a metal interconnect layer located in the device region and a first MIM capacitor lower electrode located in the edge region; the metal interconnect layer is electrically connected to the contact hole, and the metal interconnect layer includes multiple interconnect metal layers and interconnect vias electrically connected to adjacent interconnect metal layers; the first MIM capacitor lower electrode includes multiple lower electrode metal layers and lower electrode vias electrically connected to adjacent lower electrode metal layers.

[0106] A waterproof trench of a predetermined depth is formed in the edge region of the interconnect layer; the lower electrode of the first MIM capacitor is located on the outside of at least one side wall of the waterproof trench.

[0107] A waterproof layer is deposited on the surface of the interconnect layer, the waterproof layer covering the surface of the interconnect layer, as well as the bottom and sidewalls of the waterproof layer trench.

[0108] A first MIM upper electrode metal layer is formed at the bottom and sidewall of the waterproof layer trench. The first MIM capacitor lower electrode, the waterproof layer, and the first MIM upper electrode metal layer constitute the first MIM capacitor.

[0109] As can be seen, the method for fabricating a MIM capacitor provided by the technical solution of the present invention utilizes the inherent waterproof layer and the corresponding waterproof trench fabrication process in the radio frequency chip fabrication process. By using the waterproof layer as the capacitor dielectric layer, an additional first MIM capacitor is fabricated at the waterproof trench without adding a photomask, thus making efficient use of the wafer area. Furthermore, since the waterproof trench is a deep trench, the area of ​​the MIM capacitor is greatly increased compared to conventional MIM capacitors, thereby greatly improving the capacitance of the MIM capacitor.

[0110] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings.

[0111] Figure 1 This is a flowchart of a method for manufacturing a MIM capacitor provided in one embodiment of the present invention; Figures 2 to 19 This is a schematic diagram of the device structure corresponding to each step of the fabrication method of the MIM capacitor provided in an embodiment of the present invention.

[0112] Please refer to Figure 1 and in conjunction with references Figures 2 to 19 In this embodiment, the number of interconnect layers is three, which is used as an example for illustration. The method for fabricating the MIM capacitor provided in this embodiment of the invention may include:

[0113] S1: A substrate 10 is provided, on which a front-end semiconductor device and a first interlayer dielectric layer 104 are formed, and a contact hole 107 is formed in the first interlayer dielectric layer 104; wherein, the substrate 10 includes a device region 109 and an edge region 110, and the front-end semiconductor device is formed in the device region 109; Figure 2 As shown.

[0114] The substrate 10 can be an SOI substrate. Specifically, the SOI substrate is a silicon-on-insulator substrate, that is, an insulating layer 102 is added between the top silicon layer 101 and the bottom substrate 103. SOI substrates are widely used in CMOS devices, radio frequency devices, and silicon photonics devices. Of course, the present invention is not limited thereto, and the substrate in the embodiments of the present invention can also be other types of substrates, such as germanium-on-insulator substrates.

[0115] In one embodiment, the substrate 10 may include a plurality of device regions 109, each of which can be used to form a corresponding semiconductor device; the edge region 110 may be a region located on the periphery of the device region 109 and surrounding the device region 109. Specifically, for example, the outer side of the device region 109 is typically a sealing ring, the outer side of the sealing ring is a dicing strip, and the edge region 110 is located between the device region 109 and the sealing ring.

[0116] As a preferred method, in Figure 2 In the example, the sidewalls and bottom surfaces of the contact hole 107 also have a contact hole blocking layer 106 to prevent the metal material in the contact hole 107 from diffusing into the first interlayer dielectric layer 104.

[0117] Please continue to refer to this. Figure 2 In a preferred embodiment, a first barrier layer 108 is further formed on the first interlayer dielectric layer 104. The first barrier layer 108 is used to prevent the metal material in the contact hole 107 from diffusing into the subsequently formed interconnect layer.

[0118] As an example, the first barrier layer 108 can be formed on the first interlayer dielectric layer 104 by chemical vapor deposition (CVD). Of course, the present invention is not limited to this, and it can also be formed by physical vapor deposition, heat treatment, etc. Those skilled in the art can choose a suitable formation method as needed.

[0119] In one embodiment, the material of the first barrier layer 108 may be carbon nitride (NDC) or other nitride / carbide-based composite material layers.

[0120] S2: An interconnect layer is formed on the first interlayer dielectric layer; the interconnect layer includes a metal interconnect layer located in the device region and a first MIM capacitor lower electrode located in the edge region; the metal interconnect layer is electrically connected to the contact hole, and the metal interconnect layer includes multiple interconnect metal layers and interconnect vias electrically connected to adjacent interconnect metal layers; the first MIM capacitor lower electrode includes multiple lower electrode metal layers and lower electrode vias electrically connected to adjacent lower electrode metal layers.

[0121] As one implementation, the method of forming an interconnect layer on the first interlayer dielectric layer 104 in step S2 specifically includes, for example:

[0122] S21: A first interconnect dielectric layer is formed on the first interlayer dielectric layer 104, and a first interconnect metal layer and a first lower electrode metal layer are formed in the first interconnect dielectric layer.

[0123] Please refer to the following: Figures 3-7 The specific formation process of step S21 is described.

[0124] exist Figure 3 In the example, the first interconnect dielectric layer 201 is formed on the first barrier layer 108.

[0125] The first interconnect dielectric layer 201 may be silicon oxide, silicon nitride, aluminum oxide, LK material, ULK material, HK (high dielectric constant) material, etc. LK material may include organosilicon, silicon fluoride, polyimide, etc.

[0126] Preferably, the first interconnect dielectric layer 201 can use LK material or ULK material, thereby reducing the dielectric constant K of the insulating layer between metal interconnect layers, and thus avoiding the increase of RC delay time, crosstalk noise and power consumption.

[0127] Please continue to refer to this. Figure 3 After the first interconnect dielectric layer 201 is formed, a first oxide layer 202, a first hard mask layer 203 and a photoresist layer 301 can be formed sequentially on the first interconnect dielectric layer 201.

[0128] In this embodiment, the first hard mask layer 203 is used to protect the functional layers beneath it. The present invention does not specifically limit the material of the first hard mask layer; it can be any metal compound material that provides protection. In one specific embodiment, the material of the first hard mask layer 203 can be TiN.

[0129] In this embodiment, please refer to Figure 4 The photoresist layer 301 can be exposed and developed using a photomask to form a patterned photoresist layer 301, which is a mask layer 302.

[0130] In this embodiment, the mask layer 302 includes a photolithographic pattern, which includes a first interconnect metal layer pattern and a first lower electrode metal layer pattern. The first interconnect metal layer pattern is located in the device region and corresponds to the contact hole; the first lower electrode metal layer pattern is located in the edge region.

[0131] In this embodiment, please refer to Figure 5 Using the mask layer 302 as a mask and the surface of the first interlayer dielectric layer 104 as an etching stop layer, the first hard mask layer 203, the first oxide layer 202, the first interconnect dielectric layer 201 and the first barrier layer 108 are etched sequentially to form the first interconnect metal groove and the first lower electrode metal groove.

[0132] In this embodiment, the first interconnect metal recess is located in the device region and exposes the top surface of the contact hole and a portion of the surface of the first interlayer dielectric layer 104. The first lower electrode metal recess is located in the edge region and exposes a portion of the surface of the first interlayer dielectric layer 104.

[0133] In this embodiment, after etching is completed, the remaining mask layer 302 is removed.

[0134] In this embodiment, please refer to Figure 6A second barrier layer 204 is deposited on the surface of the substrate 10. The second barrier layer 204 conformally covers the ground and sidewalls of the first interconnect metal recess and the first lower electrode metal recess, as well as the surface covering the remaining first hard mask layer 203.

[0135] In this embodiment, reference continues to be made to Figure 6 Metal material can be filled into the first interconnecting metal groove and the first lower electrode plate metal groove to form a metal material layer 205.

[0136] In one embodiment, the metal material can be copper (Cu), which can improve chip speed and reduce resistance. In other embodiments, the metal material is not limited, and it can be other metals, such as aluminum, etc.

[0137] In one embodiment, when the metal material is copper (Cu), the material of the second barrier layer 204 can be tantalum (Ta), tantalum nitride (TaN), or a combination of tantalum (Ta) and tantalum nitride (TaN), serving as an adhesion layer for copper and a barrier layer to prevent copper diffusion.

[0138] In this embodiment, please refer to Figure 7 Using the first interconnect dielectric layer 201 as a stop layer, the metal material layer 205 is ground until the first hard mask layer 203 and the first oxide layer 202 are removed, forming the first interconnect metal layer 211 and the first lower electrode metal layer 221, wherein the surface of the first interconnect metal layer 211 and the surface of the first lower electrode metal layer 221 are flush with the surface of the first interconnect dielectric layer 201.

[0139] As an example, the grinding method is chemical mechanical polishing (CMP). In other embodiments, the invention is not limited thereto, and other grinding methods are also within the scope of protection of the invention.

[0140] For ease of description, the second barrier layer 204 is omitted in the following figures.

[0141] S22: At least one barrier layer and at least one second interconnect dielectric layer are sequentially formed on the first interconnect dielectric layer 201. The second interconnect dielectric layer has a first interconnect via, a second interconnect metal layer, a first lower electrode via, and a second lower electrode metal layer. The first interconnect via penetrates the barrier layer and is electrically connected to the second interconnect metal layer and the first interconnect metal layer. The first lower electrode via penetrates the barrier layer and is electrically connected to the second lower electrode metal layer and the first lower electrode metal layer.

[0142] Please refer to Figures 8-9The following describes step S21 by taking the sequential formation of two barrier layers and two second interconnect layers on the first interconnect dielectric layer 201 as an example.

[0143] Please refer to Figure 8 A barrier layer 209 and a second interconnect dielectric layer 206 are sequentially formed on the first interconnect dielectric layer 201. The second interconnect dielectric layer 206 has a first interconnect via 212, a second interconnect metal layer 213, a first lower electrode via 222, and a second lower electrode metal layer 223. The first interconnect via 212 penetrates the barrier layer 209 and is electrically connected to the second interconnect metal layer 213 and the first interconnect metal layer 211. The first lower electrode via 222 penetrates the barrier layer 209 and is electrically connected to the second lower electrode metal layer 223 and the first lower electrode metal layer 221.

[0144] In this embodiment, the barrier layer 209 may be made of SiN. This invention does not limit this, and those skilled in the art can choose a suitable barrier layer material as needed.

[0145] In this embodiment, a barrier layer 209 and a second interconnect dielectric layer 206 can be formed first. After forming the second interconnect dielectric layer 206, a first interconnect via groove, a second interconnect metal groove, a first lower electrode via groove, and a second lower electrode metal groove are formed in the second interconnect dielectric layer 206. Then, metal material is deposited and polished. The specific preparation process is the same as the preparation process of the first interconnect metal layer and the first lower electrode metal layer described above, and will not be repeated here.

[0146] In this embodiment, the metals forming the first interconnect via 212, the second interconnect metal layer 213, the first lower electrode via 222, and the second lower electrode metal layer 223 can be the same as those of the first interconnect metal layer and the first lower electrode metal layer, and the material of the second interconnect dielectric layer 206 can also be the same as that of the first interconnect dielectric layer 201.

[0147] In this embodiment, the barrier layer and the second interconnect dielectric layer are multiple layers. In this case, the multiple barrier layers and the multiple second interconnect dielectric layers are spaced apart, and each second interconnect dielectric layer has a first interconnect via, a second interconnect metal layer, a first lower electrode via, and a second lower electrode metal layer formed therein.

[0148] The first interconnect via is also electrically connected to the second interconnect metal layer adjacent to the second interconnect dielectric layer.

[0149] The first lower electrode through-hole is also electrically connected to the second lower electrode metal layer of the adjacent second interconnect dielectric layer.

[0150] For details, please refer to Figure 9 A second barrier layer 209 and a second second interconnect dielectric layer 206 are sequentially formed on the second interconnect dielectric layer 206. A first interconnect via 212, a second interconnect metal layer 213, a first lower electrode via 222, and a second lower electrode metal layer 223 are formed in the second interconnect dielectric layer 206.

[0151] The first interconnect via 212 is electrically connected to the second interconnect metal layer 213 of the adjacent second interconnect dielectric layer 206, and the first lower electrode via 222 is also electrically connected to the second lower electrode metal layer 223 of the adjacent second interconnect dielectric layer 206.

[0152] It can be seen that, in Figure 9 In the example, an interconnect layer 20 is formed on the first interlayer dielectric layer 104; wherein, the interconnect layer 20 includes the metal interconnect layer 210 and the lower electrode 220 of the first MIM capacitor; wherein, the metal interconnect layer 210 is used for electrical connection with the contact hole 107; the lower electrode 220 of the first MIM capacitor is located in the edge region 110; the metal interconnect layer includes multiple interconnect metal layers and interconnect vias electrically connecting adjacent interconnect metal layers; the lower electrode 220 of the first MIM capacitor includes multiple lower electrode metal layers and lower electrode vias electrically connecting adjacent lower electrode metal layers. Of course, it should be understood that the number of metal interconnect layers and the number of lower electrode metal layers in this embodiment are merely examples. Depending on the actual situation, the number of metal interconnect layers and the number of lower electrode metal layers can also be other values, such as four layers, five layers, etc., all of which are within the protection scope of this invention.

[0153] In addition, by Figure 9 As can be seen from the example, the number of lower plates 220 of the first MIM capacitor in this embodiment is two. In practical applications, the number of lower plates 220 of the first MIM capacitor can also be one.

[0154] In the fabrication process of this invention, the height of the interconnect metal layer within each interconnect dielectric layer is the same as the height of the lower electrode metal layer, and the height of the interconnect via within each interconnect dielectric layer is the same as the height of the lower electrode via. It should be understood that this invention does not limit the width of the interconnect metal layer, the lower electrode metal layer, the interconnect via, or the lower electrode via within each interconnect dielectric layer.

[0155] In a preferred embodiment, the materials of the interconnect vias, the interconnect metal layer, and the lower electrode vias are the same as the material of the lower electrode metal layer.

[0156] Therefore, the lower electrode of the first MIM capacitor of the present invention can be fabricated simultaneously with the formation of the interconnect layer, without the need for additional processes, saving the number of photomasks and further reducing costs. Furthermore, since the materials of the interconnect vias and the interconnect metal layer are copper, the resistance of the lower electrode of the first MIM capacitor is greatly reduced, thereby improving the Q value of the subsequently obtained first MIM capacitor.

[0157] In a preferred embodiment, when performing the fabrication process corresponding to step S22, during the formation of the top interconnect metal layer in the multilayer interconnect metal layer, the fabrication method of the MIM capacitor may further include:

[0158] S221: When forming the top interconnect metal layer in the multilayer interconnect metal layers, the lower electrode metal layer 230 of the second MIM capacitor is formed; as shown Figure 9 As shown.

[0159] In a preferred embodiment, the material of the lower electrode metal layer 230 of the second MIM capacitor is the same as the material of the interconnect metal layer, thereby reducing the difficulty of the fabrication process and also greatly reducing the resistance value of the lower electrode of the second MIM capacitor, thus improving the Q value of the subsequently obtained second MIM capacitor.

[0160] In one embodiment, after forming the top interconnect metal layer in the multilayer interconnect metal layers, the following may be further included:

[0161] A second hard mask layer 207 is formed on the interconnect layer, such as Figure 10 As shown.

[0162] Specifically, the material of the second hard mask layer can be one of SiN / SiO2 or a combination of both. In this embodiment of the invention, the material of the second hard mask layer can also be set to be the same as that of the waterproof layer. The second hard mask layer mainly serves a protective function, protecting the functional layers beneath it.

[0163] Please continue to refer to this. Figure 1 Step S3 is executed: a waterproof trench of a preset depth is formed in the edge region 110 of the interconnect layer; wherein, the lower electrode 220 of the first MIM capacitor is located on the outside of at least one side wall of the waterproof trench.

[0164] As one implementation, the method of forming a waterproof trench of a predetermined depth at the edge region 110 of the interconnect layer in step S3 may specifically include:

[0165] S31: A mask layer 303 is formed on the interconnect layer, the mask layer 303 including a waterproof layer pattern, the waterproof layer pattern being located in the edge region; as shown Figure 11 As shown.

[0166] Specifically, a mask layer 303 is formed on the interconnect layer 20 after photolithography and development.

[0167] It should be noted that, since there are two lower electrodes 220 of the first MIM capacitor in this embodiment, the waterproof layer pattern is located between the two lower electrodes 220. It should also be noted that if there is only one lower electrode of the first MIM capacitor, the waterproof layer pattern can be located on one side of that lower electrode.

[0168] It should be understood that, Figure 11 The example is based on the formation of a second hard mask layer 207 on the interconnect layer. In actual implementation, other methods can also be used to form the mask layer 303 on the interconnect layer. That is, the second hard mask layer 207 may not be included or other functional layers may be added. The present invention does not impose any limitations.

[0169] S32: Using the mask layer 303 as a mask, the interconnect layer is etched to form waterproof trenches of a predetermined depth; such as Figure 12 As shown.

[0170] The bottom of the waterproof trench is lower than the bottom of the interconnect metal layer in the first interconnect dielectric layer. However, this invention is not limited to this. In actual fabrication, the interface between the substrate 10 and the first interlayer dielectric layer 104 can be used as an etching stop layer, and etching can be performed on the edge region 110 of the interconnect layer to form the waterproof trench, meaning the bottom of the waterproof trench can contact the surface of the substrate 10.

[0171] exist Figure 12 In the example, the two lower electrodes 220 of the first MIM capacitor are respectively located on the outer sides of the two side walls of the waterproof layer trench. During fabrication, the lower electrodes 220 of the first MIM capacitor should be in close contact with the waterproof layer trench, and the distance between the lower electrodes 220 of the first MIM capacitor and the waterproof layer trench is greater than or equal to 0 micrometers and less than or equal to 0.5 micrometers.

[0172] Please continue to refer to this. Figure 13 Remove the mask layer 303.

[0173] exist Figure 13 Based on this, please continue to refer to Figure 1 Step S4: Deposit a waterproof layer 208 on the surface of the interconnect layer, the waterproof layer 208 covering the surface of the interconnect layer 20, as well as the bottom and sidewalls of the waterproof layer trench; the device after depositing the waterproof layer 208 is as follows: Figure 14 As shown.

[0174] In one specific embodiment, the waterproof layer 208 can be deposited using a plasma-enhanced chemical vapor deposition (PECVD) process. In this embodiment of the invention, the waterproof layer 208 also serves as the dielectric layer of the MIM, and its thickness can range from tens of angstroms to thousands of angstroms.

[0175] As an example, the material of the waterproof layer 208 can be silicon nitride (SIN). Of course, the present invention does not limit this to it, and it can also be a dense layer of other materials, such as hafnium dioxide (HfO2), aluminum oxide, etc.

[0176] Please continue to refer to this. Figure 1 Step S5: Form a first MIM upper electrode metal layer 240 located at the bottom and sidewall of the waterproof layer trench, wherein the first MIM capacitor lower electrode 220, the waterproof layer 208, and the first MIM upper electrode metal layer 240 constitute a first MIM capacitor.

[0177] Since the metal material forming the first MIM upper electrode metal layer 240 is prone to diffusion, a third barrier layer 243 needs to be formed on the surface of the first MIM upper electrode metal layer 240 to prevent the diffusion of metal material in subsequent processes.

[0178] Based on this, as a specific implementation method, step S5 may specifically include:

[0179] S511: A metal material layer for the upper electrode of the MIM, a third barrier material layer 241, and a photoresist layer are sequentially formed on the surface of the substrate 10.

[0180] S512: Pattern the photoresist layer to form a mask layer 304.

[0181] S513: Using the mask layer 304 as a mask, etch the first portion of the MIM upper electrode metal material layer and the first portion of the third barrier material layer 241 to form the first MIM upper electrode metal layer 240, as shown. Figure 15 As shown.

[0182] S514: Remove the mask layer 304.

[0183] S515: Deposit a third barrier layer material on the surface of the substrate 10 to form the third barrier layer 243 covering the surface and sidewalls of the upper electrode metal layer 240 of the first MIM, such as... Figure 16 As shown.

[0184] In a preferred embodiment, if the material of the first MIM upper electrode metal layer 240 is aluminum, then for the through holes connecting the MIM upper electrode formed in subsequent processes, aluminum has a lower migration rate than the metal copper in the through holes and is not easy to diffuse. Therefore, it is not necessary to deposit a third barrier layer 243 on the surface of the first MIM upper electrode metal layer 240.

[0185] exist Figure 16 In the example, the first MIM upper electrode metal layer 240 in the waterproof layer trench extends to the surface of the areas on both sides of the waterproof layer trench. Of course, the first MIM upper electrode metal layer 240 can be formed only at the bottom and sidewalls of the waterproof layer trench, such as... Figure 17 As shown, its formation process is existing technology and will not be described in detail here.

[0186] Therefore, the method provided in this embodiment of the invention forms a first MIM capacitor lower electrode plate on the outside of the sidewall of the waterproof layer trench, uses the waterproof layer as the capacitor dielectric layer, and forms a first MIM upper electrode plate metal layer at the bottom and sidewall of the waterproof layer trench. The first MIM capacitor lower electrode plate, the waterproof layer, and the first MIM upper electrode plate metal layer constitute a first MIM capacitor. Since the fabrication of the waterproof layer is an inherent procedure of existing semiconductor devices, this method ingeniously achieves the formation of a first MIM capacitor during the formation of the waterproof layer, realizing the fabrication of an additional MIM capacitor at the waterproof layer trench without adding a photomask, thus efficiently utilizing the wafer area. Furthermore, since the waterproof layer trench is a deep trench, the area of ​​the MIM capacitor is greatly increased compared to conventional MIM capacitors, thereby significantly improving the capacitance of the MIM capacitor.

[0187] Please continue to refer to this. Figure 16 In a preferred embodiment, where a second MIM capacitor lower electrode metal layer 230 is further formed within the interconnect layer, the method may further include:

[0188] When the first MIM upper electrode metal layer 240 is formed at the bottom and sidewall of the waterproof layer trench, the second MIM upper electrode metal layer 242 is formed on the second MIM capacitor lower electrode metal layer 230.

[0189] The second MIM capacitor consists of the lower electrode 230, the waterproof layer 208, and the metal layer 242 of the upper electrode 242.

[0190] Specifically, the method for forming the first MIM upper electrode metal layer 240 and the second MIM upper electrode metal layer 242 may include:

[0191] S521: Deposit an upper electrode metal layer on the waterproof layer.

[0192] S522: A mask layer is formed on the upper electrode metal layer, wherein the mask layer includes a first MIM capacitor upper electrode metal layer pattern and a second MIM capacitor upper electrode metal layer pattern.

[0193] S523: Using the mask layer as a mask, the upper electrode metal layer is etched to form the first MIM upper electrode metal layer 240 and the second MIM upper electrode metal layer 242; as Figure 16 As shown.

[0194] In this case, the second MIM capacitor and the first MIM capacitor can be connected in parallel, thereby further increasing the capacitance of the MIM capacitor. The plate area of ​​the MIM capacitor is increased without reducing the number of crystals, thus realizing a high capacitance value MIM capacitor.

[0195] It should be understood that the present invention does not limit the material of the first MIM upper electrode metal layer 240 or the second MIM upper electrode metal layer 242, and the material can be titanium Ti, titanium nitride TiN, aluminum Al, tantalum nitride TaN, etc.

[0196] As can be seen, in a processing area (shot), the proportion of the layout area consumed by the MIM capacitor formed in the embodiment of the present invention is <0.008%, while the effective area (or plate area) of the MIM capacitor is increased by about 220,000 square micrometers, which is much larger than the effective area (or plate area) of ordinary MIM capacitors formed in the prior art (about several hundred square micrometers to 10 square millimeters).

[0197] Of course, the fabrication process of semiconductor devices also includes other processes, such as forming... Figure 17 Following the description of the MIM capacitor, please refer to [link / reference]. Figures 18-20 Please provide an explanation.

[0198] Please refer to Figure 18 A third interconnect dielectric layer 401 is deposited on the surface of the substrate 10; the third interconnect dielectric layer 401 is then subjected to surface planarization.

[0199] Specifically, the third interconnect dielectric layer 401 can be silicon oxide, silicon nitride, aluminum oxide, LK material, ULK material, etc. Preferably, since RF chips need to increase speed and reduce parasitic capacitance to improve their performance, LK material or ULK material is often used as the interconnect dielectric layer. Among them, LK materials include organosilicon, silicon fluoride, polyimide, etc.

[0200] Please refer to Figure 19 A via 402 is formed at a predetermined position in the third interconnect dielectric layer 401 to connect the metal interconnect layer 210, the first MIM capacitor, and the second MIM capacitor.

[0201] Please refer to Figure 20 A new barrier layer 410 and a fourth interconnect dielectric layer 403 are sequentially formed on the third interconnect dielectric layer 401. The fourth interconnect dielectric layer 403 includes a second metal interconnect layer 404, which is electrically connected to a corresponding via 402. A fourth barrier layer 405 and a fifth interconnect dielectric layer 406 are sequentially formed on the fourth interconnect dielectric layer 403. Using the interface between the fourth barrier layer 405 and the second metal interconnect layer 404 as an etch stop layer, the fifth interconnect dielectric layer 406 and the fourth barrier layer 405 are sequentially etched to form a second recess. Metal material is filled into the second recess to form a contact metal layer 407, which extends to the surface of the fifth interconnect dielectric layer 406. A buffer layer 408 and a passivation layer 409 are sequentially formed on the surface of the substrate 10.

[0202] In summary, the embodiments of the present invention cleverly utilize the waterproof layer 208 as the capacitor dielectric layer, and fabricate additional MIM capacitors in the trenches of the waterproof layer without adding a photomask, thus making efficient use of the wafer area and improving the capacitance.

[0203] In addition, please continue to refer to Figure 15 The present invention also provides a MIM capacitor device, which may include:

[0204] A substrate 10 has a front-end semiconductor device 105 and a first interlayer dielectric layer 104 formed thereon, and a contact hole 107 is formed in the first interlayer dielectric layer 104; wherein, the substrate 10 includes a device region 109 and an edge region 110, and the front-end semiconductor device 105 is formed in the device region 109.

[0205] An interconnect layer 20 is located on the first interlayer dielectric layer 104. The interconnect layer 20 includes a metal interconnect layer 210 located in the device region, a first MIM capacitor lower electrode 220 located in the edge region, and a waterproof trench located in the edge region 110 of the interconnect layer 20. The metal interconnect layer 210 is electrically connected to the contact hole 107. The metal interconnect layer 210 includes multiple interconnect metal layers and interconnect vias electrically connecting adjacent interconnect metal layers. The first MIM capacitor lower electrode 220 is located outside at least one sidewall of the waterproof trench and includes multiple lower electrode metal layers and lower electrode vias electrically connecting adjacent lower electrode metal layers.

[0206] A waterproof layer 208 is located on the surface of the interconnect layer 20, and the waterproof layer 208 covers the surface of the interconnect layer 20, as well as the bottom and sidewalls of the waterproof layer trench.

[0207] A first MIM upper electrode metal layer 240 is formed at the bottom and sidewall of the waterproof layer trench; wherein, the first MIM capacitor lower electrode 220, the waterproof layer 208, and the first MIM upper electrode metal layer 240 constitute the first MIM capacitor.

[0208] The bottom of the waterproof layer trench is lower than the bottom of the interconnect metal layer in the first interconnect dielectric layer 201.

[0209] As can be seen, the present invention utilizes the waterproof layer 208 as the capacitor dielectric layer, and fabricates an additional MIM capacitor in the trench of the waterproof layer without adding a photomask, which makes efficient use of the wafer area and improves the capacitance.

[0210] In a preferred embodiment, the materials of the interconnect vias, the interconnect metal layer, and the lower electrode vias are the same as the material of the lower electrode metal layer.

[0211] Therefore, this invention eliminates the need for additional steps in forming the lower electrode metal layer. By using the existing bottom metal as the lower electrode of the additional MIM capacitor, it not only reduces the resistance value and increases the Q value of the capacitor, but also saves on the number of photomasks and reduces costs.

[0212] In a preferred embodiment, please refer to [link / reference needed]. Figure 15 The MIM capacitor may further include a second MIM capacitor, which may include:

[0213] The lower electrode metal layer 230 of the second MIM capacitor is formed simultaneously with the top interconnect metal layer in the multilayer interconnect metal layer.

[0214] The second MIM upper electrode metal layer 242 is formed on the waterproof layer and covers the first part of the second MIM capacitor lower electrode metal layer 230. The second MIM upper electrode metal layer 242 and the first MIM capacitor upper electrode metal layer 240 are formed simultaneously.

[0215] The second MIM capacitor consists of the lower electrode 230 of the second MIM capacitor, the waterproof layer 208, and the metal layer 242 of the upper electrode of the second MIM capacitor.

[0216] As can be seen, the additional MIM capacitors fabricated in the waterproof layer trenches of this invention do not occupy the original positions of the MIM capacitors, thus making efficient use of the wafer area and improving the capacitance.

[0217] Preferably, the material of the lower electrode metal layer 230 of the second MIM capacitor is the same as the material of the interconnect metal layer, which reduces the difficulty of the manufacturing process.

[0218] In summary, this embodiment of the invention forms a first MIM capacitor lower electrode plate on at least one sidewall of the waterproof layer trench, uses the waterproof layer as the capacitor dielectric layer, and forms a first MIM upper electrode plate metal layer on the bottom and sidewall of the waterproof layer trench. The first MIM capacitor lower electrode plate, the waterproof layer, and the first MIM upper electrode plate metal layer constitute a first MIM capacitor. Since the fabrication of the waterproof layer is an inherent procedure in existing semiconductor devices, this method ingeniously achieves the formation of a first MIM capacitor during the formation of the waterproof layer, realizing the fabrication of an additional MIM capacitor at the waterproof layer trench without adding a photomask, efficiently utilizing the wafer area, and also improving the capacitance.

[0219] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a MIM capacitor, characterized in that, include: A substrate is provided on which a front-end semiconductor device and a first interlayer dielectric layer are formed, and a contact hole is formed in the first interlayer dielectric layer; wherein, the substrate includes a device region and an edge region, and the front-end semiconductor device is formed in the device region; An interconnect layer is formed on the first interlayer dielectric layer; the interconnect layer includes a metal interconnect layer located in the device region and a first MIM capacitor lower electrode located in the edge region; the metal interconnect layer is electrically connected to the contact hole, and the metal interconnect layer includes multiple interconnect metal layers and interconnect vias electrically connected to adjacent interconnect metal layers; the first MIM capacitor lower electrode includes multiple lower electrode metal layers and lower electrode vias electrically connected to adjacent lower electrode metal layers; A waterproof trench of a predetermined depth is formed in the edge region of the interconnect layer; the lower electrode of the first MIM capacitor is located on the outside of at least one side wall of the waterproof trench; A waterproof layer is deposited on the surface of the interconnect layer, the waterproof layer covering the surface of the interconnect layer, as well as the bottom and sidewalls of the waterproof layer trench; A first MIM upper electrode metal layer is formed at the bottom and sidewall of the waterproof layer trench. The first MIM capacitor lower electrode, the waterproof layer, and the first MIM upper electrode metal layer constitute the first MIM capacitor.

2. The method for manufacturing a MIM capacitor as described in claim 1, characterized in that, An interconnect layer is formed on the first interlayer dielectric layer, including: A first interconnect dielectric layer is formed on the first interlayer dielectric layer, and a first interconnect metal layer and a first lower electrode metal layer are formed in the first interconnect dielectric layer. At least one barrier layer and at least one second interconnect dielectric layer are sequentially formed on the first interconnect dielectric layer. The second interconnect dielectric layer has a first interconnect via, a second interconnect metal layer, a first lower electrode via, and a second lower electrode metal layer. The first interconnect via penetrates the barrier layer and is electrically connected to the second interconnect metal layer and the first interconnect metal layer. The first lower electrode via penetrates the barrier layer and is electrically connected to the second lower electrode metal layer and the first lower electrode metal layer.

3. The method for manufacturing a MIM capacitor as described in claim 2, characterized in that, The barrier layer and the second interconnect dielectric layer are multiple layers, and the multiple layers of the barrier layer and the multiple layers of the second interconnect dielectric layer are spaced apart. Each second interconnect dielectric layer has a first interconnect via, a second interconnect metal layer, a first lower electrode via, and a second lower electrode metal layer. The first interconnect via is also electrically connected to the second interconnect metal layer adjacent to the second interconnect dielectric layer; The first lower electrode through-hole is also electrically connected to the second lower electrode metal layer of the adjacent second interconnect dielectric layer.

4. The method for manufacturing a MIM capacitor as described in claim 1, characterized in that, The materials of the interconnect vias, the interconnect metal layer, and the lower electrode vias are the same as the materials of the lower electrode metal layer.

5. The method for manufacturing a MIM capacitor as described in claim 1, characterized in that, A waterproof trench of a predetermined depth is formed in the edge region of the interconnect layer, including: A mask layer is formed on the interconnect layer, the mask layer including a waterproof layer pattern located in the edge region; The interconnect layer is etched using the mask layer as a mask to form a waterproof trench of a predetermined depth.

6. The method for manufacturing a MIM capacitor as described in claim 5, characterized in that, The bottom of the waterproof layer trench is lower than the bottom of the interconnect metal layer in the first interconnect dielectric layer.

7. The method for manufacturing a MIM capacitor as described in claim 1, characterized in that, The method further includes: When forming the top interconnect metal layer in the multilayer interconnect metal layers, the lower electrode metal layer of the second MIM capacitor is formed; When a first MIM upper electrode metal layer is formed at the bottom and sidewall of the waterproof layer trench, a second MIM upper electrode metal layer is formed on the lower electrode metal layer of the second MIM capacitor. The second MIM capacitor consists of the lower electrode plate, the waterproof layer, and the metal layer of the upper electrode plate.

8. The method for manufacturing a MIM capacitor as described in claim 7, characterized in that, Forming a first MIM upper electrode metal layer and a second MIM upper electrode metal layer includes: A metal layer for the upper electrode is deposited on the waterproof layer; A mask layer is formed on the upper electrode metal layer, the mask layer including a first MIM capacitor upper electrode metal layer pattern opening and a second MIM capacitor upper electrode metal layer pattern opening; Using the mask layer as a mask, the upper electrode metal layer is etched to form the first MIM upper electrode metal layer and the second MIM upper electrode metal layer.

9. A MIM capacitor device, characterized in that, include: A substrate on which a front-end semiconductor device and a first interlayer dielectric layer have been formed, and a contact hole has been formed in the first interlayer dielectric layer; wherein, the substrate includes a device region and an edge region, and the front-end semiconductor device is formed in the device region; An interconnect layer is located on the first interlayer dielectric layer, wherein the interconnect layer includes a metal interconnect layer located in the device region, a first MIM capacitor lower electrode located in the edge region, and a waterproof layer trench located in the edge region of the interconnect layer; the metal interconnect layer is electrically connected to the contact hole, and the metal interconnect layer includes multiple interconnect metal layers and interconnect vias electrically connected to adjacent interconnect metal layers; the first MIM capacitor lower electrode is located outside at least one sidewall of the waterproof layer trench, and includes multiple lower electrode metal layers and lower electrode vias electrically connected to adjacent lower electrode metal layers; A waterproof layer is located on the surface of the interconnect layer, the waterproof layer covering the surface of the interconnect layer, as well as the bottom and sidewalls of the waterproof layer trench; A first MIM upper electrode metal layer is formed at the bottom and sidewall of the waterproof layer trench; wherein, the first MIM capacitor lower electrode, the waterproof layer, and the first MIM upper electrode metal layer constitute the first MIM capacitor.

10. The MIM capacitor device as claimed in claim 9, characterized in that, The MIM capacitor further includes a second MIM capacitor, the second MIM capacitor comprising: The lower electrode metal layer of the second MIM capacitor is formed simultaneously with the top interconnect metal layer in the multilayer interconnect metal layer. The second MIM upper electrode metal layer is formed on the waterproof layer and covers the first part of the second MIM capacitor lower electrode metal layer, and the second MIM upper electrode metal layer and the first MIM capacitor upper electrode metal layer are formed simultaneously. The second MIM capacitor is composed of the lower electrode plate of the second MIM capacitor, the waterproof layer, and the metal layer of the upper electrode plate of the second MIM capacitor.

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