Fast control prototyping system and method for power systems

Abstract

The embodiment of the present application relates to the technical field of semi-physical simulation, and discloses a kind of fast control prototype test system and method of power system.The system in the present application includes: host computer, for establishing CPU model and FPGA model, and its control algorithm, and conversion is the control information to simulation machine;Simulation machine is used to carry and run CPU model and FPGA model, wherein, CPU model utilizes static synchronous compensator STATCOM model to adjust level output, FPGA model integrates Aurora communication IP core, Aurora communication IP core is used for data exchange with simulation machine;Simulation machine is also used to control CPU model and FPGA model to run according to control information, collects operating state information, and feeds back operating state information to host computer.To realize all-around debugging verification from fast control prototype RCP to communication protocol.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of hardware-in-the-loop simulation technology, and in particular to a rapid control prototype testing system and method for power systems. Background Technology

[0002] The Rapid Control Prototype (RCP) development method combines a rapid prototyping controller with a real controlled object. Researchers only need to build and debug a simulation model containing the required control algorithm in the commercial software MATLAB / Simulink. Then, the control algorithm can be used to control the simulator through the rapid prototyping controller to verify the control algorithm in a real-time environment. This method can effectively overcome the difficulties of programming and developing complex control systems and improve R&D efficiency.

[0003] Currently, the rapid control prototypes simulate the voltage environment of two-level inverters. However, with the development of the power industry, power systems need to achieve higher output voltage and power to meet the needs of medium- and high-voltage, high-power applications. The current rapid control prototypes simulating two-level inverters cannot meet the higher voltage requirements in the test scenario, i.e., they cannot simulate the Aurora protocol verification of SVG cascaded multilevel controllers. Summary of the Invention

[0004] The purpose of this invention is to provide a rapid control prototype testing system and method for power systems, so as to achieve comprehensive debugging and verification from rapid control prototype (RCP) to communication protocol.

[0005] To address the aforementioned technical problems, embodiments of the present invention provide a rapid control prototype testing system for a power system, comprising: a host computer for establishing a CPU model and an FPGA model, their control algorithms, and converting them into control information for a simulator; a simulator for carrying and running the CPU model and the FPGA model, wherein the CPU model uses a STATCOM model to adjust the level output, the FPGA model integrates an Aurora communication IP core, and the Aurora communication IP core is used for data exchange with the simulator; the simulator is also used to control the operation of the CPU model and the FPGA model according to the control information, collect operating status information, and feed the operating status information back to the host computer.

[0006] An embodiment of the present invention also provides a rapid control prototype testing method for a power system, applied to the aforementioned rapid control prototype testing system for a power system. The method includes: establishing a CPU model and an FPGA model, along with their control algorithms, using system modeling software in a host computer; converting the control algorithms into control information for a simulator using a control module in the system modeling software; the simulator controlling the CPU model and the FPGA model it carries according to the control information; collecting the operating status information of the CPU model and the FPGA model; and feeding back the operating status information to the host computer to obtain test results.

[0007] Compared to existing technologies, this invention establishes a CPU model and an FPGA model within the system to achieve hardware and software compatibility. A STATCOM (Static Synchronous Compensator) model is built into the CPU model, and the STATCOM model is used to adjust the output level. An Aurora communication IP core is integrated into the FPGA model to simulate the communication protocol of a real controller. By detecting the operating status of the CPU model and FPGA model in a simulated environment, comprehensive debugging and verification from the rapid control prototype RCP to the communication protocol are achieved.

[0008] In addition, the STATCOM model is a three-phase system model composed of a single-phase modular multilevel converter (MMC) model; wherein the voltage and current phases of each phase of the three-phase system model are 120 degrees out of phase.

[0009] In addition, the FPGA model also includes an I / O interface; the I / O interface is used to realize data interaction between the FPGA model and the simulator.

[0010] In addition, the CPU model includes a data frame parsing model; the data frame parsing model is used to generate and parse the communication data frames exchanged between the Aurora communication IP core and the simulator.

[0011] In addition, the communication data frame includes at least: a pulse width modulation (PWM) signal and capacitor voltage information.

[0012] In addition, the CPU model includes: a power grid model; the power grid model is used to simulate the voltage, frequency and load characteristics of the power grid.

[0013] In addition, the CPU model includes a transformer model; the transformer model is used to simulate voltage transformation and power transfer between the power grid and the STATCOM model.

[0014] In addition, the CPU model includes a load model, which is used to simulate the load conditions on the power grid.

[0015] In addition, the CPU model includes a fault model; the fault model is used to simulate fault conditions that occur in the power grid. Attached Figure Description

[0016] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0017] Figure 1 This is a schematic diagram of the structure of a rapid control prototype test system for a power system according to an embodiment of the present invention;

[0018] Figure 2 This is an equivalent circuit diagram of a single-phase MMC model of a rapid control prototype testing system for a power system according to an embodiment of the present invention.

[0019] Figure 3 This is a schematic diagram of the CPU model of a rapid control prototype testing system for a power system according to an embodiment of the present invention;

[0020] Figure 4 This is a schematic diagram of the structure of an FPGA model of a rapid control prototype testing system for a power system according to an embodiment of the present invention;

[0021] Figure 5 This is a schematic diagram of the structure of another rapid control prototype test system for a power system according to an embodiment of the present invention;

[0022] Figure 6 This is a schematic diagram of the structure of a simulator for a rapid control prototype testing system for a power system according to an embodiment of the present invention;

[0023] Figure 7 This is a schematic diagram of the simulation results of the optical port CH00 transmission and CH01 reception delay test of a fast control prototype test system for a power system according to an embodiment of the present invention.

[0024] Figure 8 This is a schematic diagram of the simulation results of the CH00 data transmission number verification test of a rapid control prototype test system for a power system according to an embodiment of the present invention;

[0025] Figure 9 This is a schematic diagram of the simulation results of the CH00 data transmission validity verification test of a rapid control prototype test system for a power system according to an embodiment of the present invention.

[0026] Figure 10 This is a flowchart of a rapid control prototype testing method for a power system according to an embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0028] The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined with and referenced by each other without contradiction.

[0029] This invention relates to a rapid control prototype testing system for power systems, comprising: a host computer for establishing CPU and FPGA models and their control algorithms, and converting them into control information for a simulator; a simulator for hosting and running the CPU and FPGA models, wherein the CPU model uses a STATCOM model to adjust the level output, and the FPGA model integrates an Aurora communication IP core for data exchange with the simulator; the simulator is also used to control the operation of the CPU and FPGA models according to the control information, collect operating status information, and feed the operating status information back to the host computer. This achieves comprehensive debugging and verification from the rapid control prototype (RCP) to the communication protocol. The implementation details of the rapid control prototype testing system for power systems according to this embodiment are described below. These details are provided for ease of understanding and are not essential for implementing this solution.

[0030] The rapid control prototype test system for the power system in this embodiment is as follows: Figure 1 As shown, it specifically includes: a host computer 10, used to establish the CPU model 21 and the FPGA model 22, and their control algorithms, and convert them into control information for the simulator 20; a simulator 20, used to carry and run the CPU model 21 and the FPGA model 22, wherein the CPU model 21 uses a STATCOM model to adjust the level output, and the FPGA model 22 integrates an Aurora communication IP core, which is used to exchange data with the simulator 20; the simulator 20 is also used to control the operation of the CPU model 21 and the FPGA model 22 according to the control information, collect the operation status information, and feed the operation status information back to the host computer 10.

[0031] Compared to existing technologies, this invention establishes a CPU model and an FPGA model within the system to achieve hardware and software compatibility. A STATCOM (Static Synchronous Compensator) model is built into the CPU model, and the STATCOM model is used to adjust the output level. An Aurora communication IP core is integrated into the FPGA model to simulate the communication protocol of a real controller. By detecting the operating status of the CPU model and FPGA model in a simulated environment, comprehensive debugging and verification from the rapid control prototype RCP to the communication protocol are achieved.

[0032] The following is a detailed introduction to the different subsystems in the rapid control prototype testing system for power systems:

[0033] The host computer can be a computer, server, or other similar device. The underlying software installed on the host computer includes MATLAB / Simulink, and simulation toolkits based on MATLAB / Simulink such as easyPSST, SCILAB, RTLAB, dSPACE, RTDS, CCS, and Keil. MATLAB / Simulink is used to build mathematical models, including CPU and FPGA models. RTLAB is used for managing the semi-physical simulation interface. After the mathematical models (CPU and FPGA models) are compiled and converted by the software, they are downloaded to the semi-physical CPU and FPGA development boards of the simulator, core by core. Additionally, the host computer also has the VIVADO software design suite installed. VIVADO is used for data packet capture, and the host computer connects to the slave computer via a Joint Test Action Group (JTAG) cable for operation.

[0034] The simulator contains both a CPU model and an FPGA model. The CPU model includes a STATCOM model, which is used to adjust the output levels. The STATCOM model is a three-phase system model composed of single-phase modular multilevel converter (MMC) models; in this three-phase system model, the voltage and current phases of each phase are 120 degrees out of phase. The single-phase MMC model is a mathematical model, and its equivalent circuit diagram is shown below. Figure 2 As shown, controlled voltage source 1 is connected to signal Vsp; controlled voltage source 2 is connected to signal Vsn. The driving voltage of the controlled voltage source is calculated using control pulses, and the magnitude of its DC current is determined by a coefficient k. The specific calculation logic is as follows:

[0035] Vsp=Vsn=kVdc+Iac*Ron*2; k=1,g=[1,0,0,1]; k=-1,g=[0,1,1,0]

[0036] Vsp=Vsn=Iac*Ron*2; k=0,g=[1,0,1,0]||g=[0,1,0,1]

[0037] Vsp=kVdc+Iac*Ron*2; Vsn=-kVdc+Iac*Ron*2; k=1; g=[0,0,0,0]&Iac≥0

[0038] Vsp=kVdc+Iac*Ron*2; Vsn=-kVdc+Iac*Ron*2; k=-1; g=[0,0,0,0]&Iac≥0

[0039] Vdc represents DC voltage, Iac represents AC current, Ron represents on-resistance, and the coefficient k represents the relationship between DC current and AC current: Idc = k * Iac. Idc represents DC current.

[0040] By combining single-phase MMC models into three-phase parallel combinations, the single-phase models are connected according to the corresponding topology to form a complete three-phase system. The voltage and current phases of each phase are 120 degrees out of phase to achieve a balanced three-phase power system.

[0041] In addition, such as Figure 3 As shown, CPU model 21 includes: a power grid model 211, used to simulate the voltage, frequency, and load characteristics of the power grid; a transformer model 212, used to simulate voltage transformation and power transfer between the power grid and STATCOM; a load model 213, used to simulate various loads on the power grid, including qualitative and quantitative load characteristics; a data frame parsing model 214, used to generate and parse communication data frames, including information such as PWM signals and SM capacitor voltage; and a fault model 215, used to simulate various fault conditions that may occur in the power grid, such as short circuits and open circuits. STATCOM model 216 is defined as the mathematical model and control algorithm for the STATCOM valve body.

[0042] In addition, such as Figure 4 As shown, FPGA model 22 includes: Aurora communication IP core 221, which integrates and configures a high-performance Aurora communication IP core for high-speed data exchange with the simulator; and IO interface 222, which designs the simulator's input / output interfaces to ensure data interaction and synchronization with the FPGA.

[0043] After the sub-models in the CPU and FPGA models mentioned above are converted into their corresponding software code, they are divided into cores and downloaded to the hardware-in-the-loop CPU and FPGA development boards to achieve parallel operation and collaborative work.

[0044] After downloading the CPU and FPGA models to the simulator, the internal structure of the simulator is as follows: Figure 5As shown, the STATCOM cascaded multilevel system outputs level signals based on control information sent by the host computer. The output signals are sent to the analog output (AO) and digital output (DO) interfaces of the FPGA model. Analog signals generated by the I / O configuration module in the CPU model are then used by the analog current transformer (PT) and voltage transformer (CT) to acquire the current and voltage signals of the power system, converting them into digital signals for FPGA processing. The processed signals are then returned to the STATCOM digital controller via the analog input (AI) and digital input (DI) interfaces. Simultaneously, the data frame parsing model in the CPU model (…) Figure 5 The protocol parsing shown is used to generate communication data frames and send them to the Aurora communication IP core, such as... Figure 5 The diagram shows six data transmission channels: CH00, CH01, CH02, CH03, CH04, and CH05. These channels communicate via the Aurora protocol through the fiber optic interface for high-speed data exchange. A signal monitoring module analyzes the communication data to determine normal operating conditions, abnormal signal states, data loss, or error states, verifying the performance of the framing and unframing modules under various conditions. Furthermore, the dynamic response speed, stability, and responsiveness to power grid faults and changes of the STATCOM rapid control prototype are evaluated to assess its performance and effectiveness.

[0045] Simulation model of rapid control prototype test system for power system, such as Figure 6 As shown, the power grid is connected to the STATCOM via a transformer. The STATCOM changes the output level of the power grid to control the voltage Vcap input to the fiber optic communication protocol frame. The fiber optic communication protocol frame forms a closed-loop control with the STATCOM through the CH00 transmit and receive interfaces. A load model (load) and a fault model (fault simulation) are connected between the power grid and the transformer. Different loads are controlled by load switches, and different fault conditions are simulated. Furthermore, the CH01 transmit and receive interfaces of the fiber optic communication protocol frame form a closed-loop control with the STATCOM simulation controller.

[0046] The following examples illustrate the simulation results of several network-related functional tests performed by the rapid control prototype testing system in this embodiment of the invention:

[0047] The simulation results for the delay test of optical port CH00 transmission and CH01 reception are as follows: Figure 7 As shown, the simulation results for the verification test of the number of data transmitted by the optical port CH00 are as follows: Figure 8 As shown, the simulation results of the data transmission validity verification test for the optical port CH00 are as follows: Figure 9 As shown.

[0048] The following is a detailed explanation of the control information sent by the host computer:

[0049] A control module was built on the host computer, specifically within the Simulink environment, adding various control modules. These modules could include PI controllers, filters, modulators, etc., to implement the multi-layered control strategy of STATCOM. Precise parameter settings and debugging of each control module ensured system stability and response speed.

[0050] The above control modules can be used to control various working environments of the system:

[0051] 1. Achieve multi-level control of capacitor voltage:

[0052] For example: Global voltage control: used to maintain the overall voltage level of the entire system, ensuring normal system operation. Global voltage control achieves voltage stability across the entire system by monitoring and adjusting capacitor voltages. Interphase voltage equalization control: used to balance the voltage between different phases. Interphase voltage equalization control ensures voltage balance in the three-phase system by adjusting the voltage difference between the capacitors of each phase, avoiding harmonics and power losses caused by voltage imbalance. Intra-phase voltage equalization control: used to further refine control, achieving voltage equalization within each phase. Intra-phase voltage equalization control ensures voltage consistency for each module by adjusting the voltage difference between modules within a single phase, improving system stability and efficiency.

[0053] 2. Achieve current control on the AC side:

[0054] For example, on the AC side, a current control strategy is adopted, including inner loop current control and outer loop voltage control. Through the coordinated control of the inner and outer loops, fast dynamic response and high-precision steady-state control are achieved.

[0055] 3. Implement carrier phase-shift modulation strategy:

[0056] For example, cascaded STATCOMs employ a carrier phase-shift modulation strategy. This strategy effectively reduces system switching losses, minimizes electromagnetic interference, and improves the quality of the output voltage waveform by shifting the phase of multiple carrier signals.

[0057] In addition to controlling the STATCOM model, the host computer also controls and verifies the FPGA model. Specifically, a framing module for communication data formats is built in Simulink to manage and parse various control signals and feedback information. The specific design is as follows:

[0058] Data Frame Structure Design: A data frame structure for transmitting various control and feedback information was designed in Simulink. This data includes PWM signal transmission and reception, and capacitor voltage transmission and reception information for each submodule (SM). The format of each data frame is designed according to the requirements of the communication protocol, including a frame header, data segments, and checksums to ensure data integrity and correctness.

[0059] Data Packaging and Unpacking: This module implements data packaging (framing) and unpacking (parsing) functions. The PWM signal sent by the controller and the received SM capacitor voltage, among other data, are packaged into data frames conforming to the communication protocol requirements by the framing module. At the receiving end, the received data frames are unpacked, and the valid data is extracted and parsed.

[0060] Data parsing: The received data frames are unpacked to extract the capacitor voltage value of each submodule. The unpacking process includes steps such as frame header identification, data segment extraction, and checksum verification to ensure the accuracy and integrity of the data.

[0061] Design various test cases, including normal working state, abnormal signal state, data loss or error state, etc., to verify the performance of the framing and unpacking modules under various conditions.

[0062] All modules involved in this embodiment are logical modules. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this invention, this embodiment does not introduce units that are not closely related to solving the technical problem proposed by this invention; however, this does not mean that other units are absent from this embodiment.

[0063] Embodiments of the present invention also relate to a rapid control prototype testing method for a power system, applied to the aforementioned rapid control prototype testing system for a power system, such as... Figure 10 As shown, the method includes the following steps:

[0064] Step 1001: In the host computer, use system modeling software to build CPU and FPGA models and their control algorithms, and use the control module in the system modeling software to convert the control algorithms into control information for the simulator.

[0065] Step 1002: The simulator controls the operation of the CPU model and FPGA model it carries according to the control information, and collects the running status information of the CPU model and FPGA model, and feeds the running status information back to the host computer to obtain the test results.

[0066] Compared to existing technologies, this invention establishes a CPU model and an FPGA model within the system to achieve hardware and software compatibility. A STATCOM (Static Synchronous Compensator) model is built into the CPU model, and the STATCOM model is used to adjust the output level. An Aurora communication IP core is integrated into the FPGA model to simulate the communication protocol of a real controller. By detecting the operating status of the CPU model and FPGA model in a simulated environment, comprehensive debugging and verification from the rapid control prototype RCP to the communication protocol are achieved.

[0067] In addition, the rapid control prototype testing method for the power system in this embodiment is implemented by the rapid control prototype testing system for the power system in the above embodiments. That is, the implementation method mentioned in the above system embodiments is also applicable to the method implementation in this embodiment. To avoid repetition, it will not be described again here.

[0068] The steps of the various methods described above are only for clarity. In practice, they can be combined into one step or some steps can be split into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, but without changing the core design of the algorithm and process, are also within the scope of protection of this patent.

[0069] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present invention, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present invention.

Claims

1. A rapid control prototype testing system for a power system, characterized in that, include: The host computer is used to build CPU and FPGA models and their control algorithms, and convert them into control information for the simulator; after the CPU and FPGA models are converted into software code, they are downloaded to the hardware-in-the-loop CPU and FPGA development board of the simulator, respectively. The simulator is used to support and run the CPU model and the FPGA model through the hardware-in-the-loop CPU and the FPGA development board. The CPU model uses a STATCOM model to adjust the level output, and the FPGA model integrates an Aurora communication IP core, which is used to exchange data with the simulator. The simulator is also used to control the operation of the CPU model and the FPGA model according to the control information, collect the operation status information, and feed the operation status information back to the host computer; The CPU model includes: a data frame parsing model; The data frame parsing model is used to generate and parse the communication data frames exchanged between the Aurora communication IP core and the simulator, and to send the communication data frames to the Aurora communication IP core. The communication data frame includes at least: a pulse width modulation (PWM) signal and capacitor voltage information; The STATCOM model is a three-phase system model composed of a single-phase modular multilevel converter (MMC) model; wherein, the voltage and current phases of each phase of the three-phase system model are 120 degrees out of phase. The single-phase modular multilevel converter (MMC) model includes: a first controlled voltage source connected to signal Vsp, and a second controlled voltage source connected to signal Vsn, where Vsp represents the bridge arm equivalent voltage corresponding to the forward current and Vsn represents the bridge arm equivalent voltage corresponding to the reverse current. The driving voltages of the first and second controlled voltage sources are calculated using control pulses, and the magnitude of the DC current is determined by a coefficient k. The calculation formula is as follows: Vsp=Vsn=kVdc+Iac Ron 2;k=1,g=[1,0,0,1];k=-1,g=[0,1,1,0] Vsp=Vsn=Iac Ron 2;k=0,g=[1,0,1,0]||g=[0,1,0,1] Vsp=kVdc+Iac Ron 2;Vsn=-kVdc+Iac Ron 2;k=1;g=[0,0,0,0]&Iac≥0 Vsp=kVdc+Iac Ron 2;Vsn=-kVdc+Iac Ron 2;k=-1;g=[0,0,0,0]&Iac≥0 Vdc represents the DC voltage, Iac represents the AC current, Ron represents the on-resistance, and the coefficient k represents the relationship between the DC current and the AC current: Idc = k Iac and Idc represent DC current, g represents control pulse, and each element in array g represents the state of each switch, where an element of 0 represents that the switch is open and an element of 1 represents that the switch is closed.

2. The rapid control prototype testing system for power systems according to claim 1, characterized in that, The FPGA model also includes: I / O interfaces; The I / O interface is used to enable data interaction between the FPGA model and the simulator.

3. The rapid control prototype testing system for a power system according to any one of claims 1 to 2, characterized in that, The CPU model includes: a power grid model; The power grid model is used to simulate the voltage, frequency, and load characteristics of the power grid.

4. The rapid control prototype testing system for power systems according to claim 3, characterized in that, The CPU model Includes: transformer model; The transformer model is used to simulate voltage transformation and power transfer between the power grid and the STATCOM model.

5. The rapid control prototype testing system for power systems according to claim 3, characterized in that, The CPU model includes: a load model; The load model is used to simulate the load conditions on the power grid.

6. The rapid control prototype testing system for power systems according to claim 3, characterized in that, The CPU model includes: a fault model; The fault model is used to simulate fault conditions that occur in the power grid.

7. A rapid control prototype testing method for a power system, characterized in that, The method of applying a rapid control prototype testing system for a power system as described in any one of claims 1 to 6 includes: In the host computer, CPU and FPGA models and their control algorithms are established using system modeling software, and the control algorithms are converted into control information for the simulator using the control module in the system modeling software. The simulator controls the operation of the CPU model and the FPGA model it carries according to the control information, and collects the running status information of the CPU model and the FPGA model, and feeds the running status information back to the host computer to obtain the test results.

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