PCIe system debug device and method

Abstract

The application provides a PCIe system debugging device and method, the PCIe system comprises a PCIe device and a central processor, and a control service component; the debugging device comprises a plurality of data acquisition points and an operation terminal; the plurality of data acquisition points are respectively arranged at different data flow nodes on a data transmission path between the PCIe device and the central processor, each data acquisition point is used for acquiring state information of a data flow at a position thereof; the operation terminal is electrically connected with the plurality of data acquisition points and the PCIe device, the operation terminal comprises a configuration module and a storage module, the configuration module is used for customizing configuration of an excitation data packet provided to the PCIe device, and the storage module is used for acquiring and storing state information fed back by the data acquisition points. The PCIe system debugging device provided by the application can customize and send excitation data packets to simulate various transmission scenes, so that the accuracy, effectiveness and flexibility of a debugging process are effectively enhanced, and active testing capability which is not possessed by a traditional analyzer is provided.

Description

Technical Field

[0001] This invention relates to the field of computer-related system debugging technology, and in particular to a PCIe system debugging device and method. Background Technology

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard widely used in modern computer systems to meet the demands of high-bandwidth data transmission. However, with the continuous improvement of computing device performance and the increasing complexity of application scenarios, the requirements for data transmission stability and performance are also constantly increasing. In practical applications, factors such as transmission quality, transmission distance, and transmission environment all affect PCIe data transmission. This impact often leads to transient inconsistencies during data transmission, thereby increasing the difficulty of debugging and maintenance.

[0003] Existing debugging tools, such as PCIe protocol analyzers, primarily function to capture and analyze packets within the PCIe channel. While these tools can help engineers understand certain aspects of data transmission, they have several limitations. First, these analyzers typically cannot accurately generate the PCIe packet stimuli needed for testing. This means that engineers are limited by the tool's functionality when they need to simulate specific data flow scenarios to test system behavior. Furthermore, traditional debugging methods are relatively simple and passive, relying mainly on the analysis of existing data, lacking flexibility and making fine-grained debugging and real-time control of specific nodes in the transmission path difficult. Summary of the Invention

[0004] The purpose of this invention is to provide a PCIe system debugging device and method that can accurately generate PCIe stimulus data packets and has flexible debugging methods.

[0005] To achieve the above objectives, the present invention provides a PCIe system debugging apparatus, wherein the PCIe system includes a PCIe device and a central processing unit, and a control service component disposed between the PCIe device and the central processing unit, the control service component being used to control the communication between the PCIe device and the central processing unit;

[0006] The debugging device includes several data acquisition points and an operation terminal;

[0007] The data acquisition points are respectively set at different data flow nodes on the data transmission path between the PCIe device and the central processing unit.

[0008] Each of the aforementioned data acquisition points is used to obtain the status information of the data stream at its location;

[0009] The operating terminal is electrically connected to several data acquisition points and the PCIe device. The operating terminal includes a configuration module and a storage module. The configuration module is used to customize the stimulus data packets provided to the PCIe device, and the storage module is used to acquire and store the status information fed back by the data acquisition points.

[0010] Preferably, the configuration module is further configured to configure the data acquisition point to be started, wherein the data acquisition point to be started is a part or all of the set data acquisition points.

[0011] Preferably, the control service component includes a PCIe controller, a memory management unit, a cache coherency controller, and an interrupt controller;

[0012] The PCIe controller is electrically connected to the PCIe device, the memory management unit is electrically connected to the PCIe controller, the cache coherence controller is electrically connected to the memory management unit, and the interrupt controller is electrically connected to both the cache coherence controller and the central processing unit.

[0013] Preferably, the data transmission path between the PCIe device and the central processing unit includes an uplink data channel and a downlink data channel, and the data acquisition point is provided in both the uplink data channel and the downlink data channel;

[0014] The uplink data transmission channel is a data channel through which data flows from the PCIe device to the central processing unit, and the downlink data transmission channel is a data channel through which data flows from the central processing unit to the PCIe device.

[0015] Preferably, the data acquisition points include a first acquisition point, a second acquisition point, a third acquisition point, a fourth acquisition point, a fifth acquisition point, and a sixth acquisition point located in the uplink data channel, and a seventh acquisition point, an eighth acquisition point, and a ninth acquisition point located in the downlink data channel;

[0016] The first acquisition point and the ninth acquisition point are located between the PCIe device and the PCIe controller;

[0017] The second acquisition point is located between the PCIe controller and the memory management unit;

[0018] The third acquisition point is located between the memory management unit and the cache consistency controller;

[0019] The fourth acquisition point is located between the cache consistency controller and the interrupt controller;

[0020] The fifth acquisition point is located between the interrupt controller and the central processing unit;

[0021] The sixth and seventh acquisition points are located between the cache coherence controller and the central processing unit;

[0022] The eighth acquisition point is located between the cache coherence controller and the PCIe controller.

[0023] The present invention also provides a PCIe system debugging method, wherein the PCIe system includes a PCIe device and a central processing unit (CPU), and a control service component disposed between the PCIe device and the CPU, the control service component being used to control communication between the PCIe device and the CPU; the debugging method includes:

[0024] A user terminal can be used to customize and configure an incentive data packet that is compatible with the current PCIe device, and then send the incentive data packet to the PCIe device.

[0025] Collect and store the status information of the data flow at different data flow nodes on the data transmission path between the PCIe device and the central processing unit to obtain test data;

[0026] When the test data shows that there is an error in the data transmission between the PCIe device and the central processing unit, the configuration of the PCIe device is adjusted according to the test data, and the test data is obtained again until the data transmission between the PCIe device and the central processing unit meets expectations.

[0027] Preferably, data acquisition points are set at different data flow nodes on the data transmission path between the PCIe device and the central processing unit, and the status information at the corresponding location is obtained through the data acquisition points; the operation terminal is also used to configure the data acquisition points to be started, and the data acquisition points to be started are some or all of the set data acquisition points.

[0028] Preferably, the control service component includes a PCIe controller, a memory management unit, a cache coherency controller, and an interrupt controller;

[0029] The PCIe controller is electrically connected to the PCIe device, the memory management unit is electrically connected to the PCIe controller, the cache coherence controller is electrically connected to the memory management unit, and the interrupt controller is electrically connected to both the cache coherence controller and the central processing unit.

[0030] Preferably, the data transmission path between the PCIe device and the central processing unit includes an uplink data channel and a downlink data channel, and the data acquisition point is provided in both the uplink data channel and the downlink data channel;

[0031] The uplink data transmission channel is a data channel through which data flows from the PCIe device to the central processing unit, and the downlink data transmission channel is a data channel through which data flows from the central processing unit to the PCIe device.

[0032] Preferably, the data acquisition points include a first acquisition point, a second acquisition point, a third acquisition point, a fourth acquisition point, a fifth acquisition point, and a sixth acquisition point located in the uplink data channel, and a seventh acquisition point, an eighth acquisition point, and a ninth acquisition point located in the downlink data channel;

[0033] The first acquisition point and the ninth acquisition point are located between the PCIe device and the PCIe controller;

[0034] The second acquisition point is located between the PCIe controller and the memory management unit;

[0035] The third acquisition point is located between the memory management unit and the cache consistency controller;

[0036] The fourth acquisition point is located between the cache consistency controller and the interrupt controller;

[0037] The fifth acquisition point is located between the interrupt controller and the central processing unit;

[0038] The sixth and seventh acquisition points are located between the cache coherence controller and the central processing unit;

[0039] The eighth acquisition point is located between the cache coherence controller and the PCIe controller.

[0040] Compared with existing technologies, the PCIe system debugging device provided by this invention achieves fine control and monitoring of the data transmission process through several data acquisition points between the PCIe device and the central processing unit. The configuration module in the operating terminal allows engineers to customize the configuration of stimulus data packets, sending different quantities, types, and contents of stimulus data packets to simulate various transmission scenarios. This effectively enhances the accuracy, effectiveness, and flexibility of the debugging process, providing proactive testing capabilities not available in traditional analyzers. Secondly, the multi-point data acquisition configuration enables real-time acquisition of the status information of each data flow node, allowing engineers to identify transmission bottlenecks and problem nodes, and quickly diagnose potential connection inconsistencies. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the PCIe system debugging device in an embodiment of the present invention.

[0042] Figure 2 This is a distribution diagram of data acquisition points in the PCIe system in an embodiment of the present invention.

[0043] Figure 3 This is an execution flowchart of the PCIe system debugging device in an embodiment of the present invention. Detailed Implementation

[0044] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0045] This embodiment discloses a PCIe system debugging device for debugging a PCIe system so that the data transmission therein meets expectations.

[0046] The PCIe system includes PCIe devices and a central processing unit (CPU), as well as a control service component located between the PCIe devices and the CPU. The control service component is used to control the communication between the PCIe devices and the CPU.

[0047] In this embodiment, the PCIe (Peripheral Component Interconnect Express) device refers to a hardware component connected to the computer motherboard. PCIe is a high-speed serial computer expansion bus standard that can be used to connect various external devices, such as graphics cards, solid-state drives (SSDs), and network interface cards. These devices communicate with the CPU via the PCIe bus to achieve high-speed data transmission.

[0048] Therefore, the goal of the debugging device in this embodiment is to optimize the data transmission related to the PCIe protocol in the PCIe device, especially the stability and performance of data transmission, as well as the capture and analysis of errors.

[0049] like Figure 1 and Figure 2 The debugging device includes several data acquisition points J and an operation terminal.

[0050] Several data acquisition points J are respectively set at different data flow nodes on the data transmission path between the PCIe device and the CPU. Each data acquisition point J is used to obtain the status information of the data flow at its location. Specifically, the status information includes error information output by the functional module with data analysis capabilities in the control service component.

[0051] The operating terminal is electrically connected to several data acquisition points J and PCIe devices. The operating terminal includes a configuration module and a storage module. The configuration module is used to customize the stimulus data packets provided to the PCIe devices, and the storage module is used to acquire and store the status information fed back by the data acquisition points J.

[0052] It should be noted that several data acquisition points J can be constructed using a data acquisition card or a data stream analyzer.

[0053] For example, you might need to debug the data transfer behavior of a PCIe device when sending an MSI-X (Extended Message Signal Interrupt) packet to the CPU. The goal of the debugging is to ensure that the packet is successfully sent and correctly triggers a CPU response. Figure 3 The debugging workflow is as follows:

[0054] S10: Configure the stimulus data packet to be compatible with the current PCIe device through the operation terminal.

[0055] The data packet includes the following information:

[0056] Data packet type: MSI-X;

[0057] Data packet content includes information such as Request ID and Event ID;

[0058] Number of data packets: Set to 1;

[0059] PCIe Function Configuration: Enable MSI-X function, and configure message address and message data.

[0060] S11: Send the stimulus packet to the PCIe device.

[0061] S12: Collect and store the status information of the data flow at different data flow nodes on the data transmission path between the PCIe device and the CPU to obtain test data. This test data can be stored on the operating terminal in the form of a log.

[0062] S13: Determine whether there is an error in the data transmission between the current PCIe device and the CPU based on the test data. If yes, proceed to S14. If no, it means that the data transmission between the current PCIe device and the CPU is as expected, then proceed to S15.

[0063] S14: Adjust the configuration of the PCIe device based on the test data and return to step S10.

[0064] S15: End the current debugging session.

[0065] On the other hand, the configuration module is also used to configure the data acquisition point J to be activated. The data acquisition point J to be activated can be a part or all of the set data acquisition points J. In this embodiment, the number and objects of the data acquisition points J to be activated can be configured as needed to achieve rational utilization of resources.

[0066] On the other hand, such as Figure 2 The control service components include the PCIe controller, memory management unit, cache coherency controller, and interrupt controller.

[0067] The PCIe controller is electrically connected to the PCIe device, the memory management unit is electrically connected to the PCIe controller, the cache coherence controller is electrically connected to the memory management unit, and the interrupt controller is electrically connected to both the cache coherence controller and the CPU.

[0068] PCIe controller: Responsible for managing data transmission on the PCIe bus, including sending, receiving, routing, and error handling of data packets.

[0069] The Memory Management Unit (MMU) is responsible for managing PCIe device access to system memory. It maps the physical addresses of PCIe devices to virtual addresses in system memory, enabling device access to memory.

[0070] Cache consistency controller: Responsible for ensuring the consistency of cached data shared across different devices. It prevents conflicts when different devices modify the same data, thus ensuring data consistency.

[0071] Interrupt Controller: Responsible for managing interrupt signals from PCIe devices. When a PCIe device needs to send a signal to the CPU, it sends an interrupt request through the interrupt controller, thereby notifying the CPU to handle the corresponding event.

[0072] To address this, the data transmission path between the PCIe device and the CPU includes an uplink data channel and a downlink data channel. Data acquisition points J are set up in both the uplink and downlink data channels to enable comprehensive monitoring of the data flow between the PCIe device and the CPU.

[0073] The uplink data transmission channel is the data channel through which data flows from the PCIe device to the CPU, while the downlink data transmission channel is the data channel through which data flows from the CPU to the PCIe device.

[0074] Additionally, it should be noted that data acquisition point J utilizes the error monitoring functions within modules such as the PCIe controller, memory management unit, and interrupt controller to generate status information. This includes the RAS function of the PCIe controller, the error event recording queue of the memory management unit, the PMU function, and the pending and active states of the interrupt controller. The pending state indicates that an interrupt event has occurred but has not yet been processed; the active state indicates that the interrupt event is being processed.

[0075] Specifically, when data flows to the PCIe controller, the RAS function in the PCIe controller is enabled. The RAS function is an error detection and repair mechanism built into the PCIe bus standard. It can detect hardware faults, such as memory errors and data transmission errors, and perform corresponding processing.

[0076] When a PCIe system encounters a PCIe-related error, such as a data transmission error or link failure, the RAS function records the error information (e.g., error type, error location). This error information is the status information collected by data acquisition point J. By analyzing this error information, debugging personnel can quickly locate the problem.

[0077] When data flows to the memory management unit, the PMU function is used to monitor performance data, and the RAS function of the memory management unit, such as the error queue, is enabled to output specific error information.

[0078] The PMU is a functional component used to track and count low-level hardware events in a PCIe system, such as data transfer volume and instruction execution count.

[0079] When a PCIe system experiences performance issues, such as slow data transfer speeds or low system efficiency, debugging personnel can analyze the PCIe system's operation using the status information output by the PMU function. This includes observing data transfer rates and instruction execution frequencies to identify performance bottlenecks and pinpoint the problem.

[0080] When data flows to the interrupt controller, if the PCIe system encounters interrupt-related problems, such as untimely interrupt handling or delayed interrupt response, the debugging personnel can observe the pending and active states generated by the interrupt controller to understand the occurrence time and processing of the interrupt event, thereby analyzing the cause of the problem.

[0081] On the other hand, the data acquisition point J includes the first acquisition point J1, the second acquisition point J2, the third acquisition point J3, the fourth acquisition point J4, the fifth acquisition point J5 and the sixth acquisition point J6 located in the uplink data channel, and the seventh acquisition point J7, the eighth acquisition point J8 and the ninth acquisition point J9 located in the downlink data channel.

[0082] The first acquisition point J1 and the ninth acquisition point J9 are located between the PCIe device and the PCIe controller;

[0083] The second acquisition point J2 is located between the PCIe controller and the memory management unit;

[0084] The third acquisition point J3 is located between the memory management unit and the cache consistency controller;

[0085] The fourth acquisition point J4 is located between the cache coherency controller and the interrupt controller;

[0086] The fifth acquisition point J5 is located between the interrupt controller and the central processing unit;

[0087] The sixth acquisition point J6 and the seventh acquisition point J7 are located between the cache coherence controller and the central processing unit; the eighth acquisition point J8 is located between the cache coherence controller and the PCIe controller.

[0088] Table 1

[0089]

[0090]

[0091] During debugging, the corresponding data acquisition points J can be configured and enabled according to the current functions of the PCIe device. For example, when debugging the data transmission situation when the PCIe device sends an MSI-X (Extended Message Signal Interrupt) data packet to the CPU, only the first acquisition point J1, the second acquisition point J2, the third acquisition point J3, the fourth acquisition point J4, and the fifth acquisition point J5 need to be enabled.

[0092] In summary, the PCIe system debugging device disclosed in the above embodiments of the present invention achieves fine control and monitoring of the data transmission process through several data acquisition points J between the PCIe device and the CPU. The configuration module in the operating terminal allows engineers to customize the configuration of stimulus data packets, and can send stimulus data packets of different quantities, types, and contents to simulate various transmission scenarios. This effectively enhances the accuracy, effectiveness, and flexibility of the debugging process, providing active testing capabilities that traditional analyzers do not possess. Secondly, the configuration of multi-point data acquisition enables real-time acquisition of the status information of each data flow node, allowing engineers to identify transmission bottlenecks and problem nodes, and quickly diagnose potential connection inconsistencies.

[0093] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A PCIe system debugging device, characterized in that, The PCIe system includes a PCIe device and a central processing unit (CPU), and a control service component disposed between the PCIe device and the CPU, the control service component being used to control the communication between the PCIe device and the CPU; The debugging device includes several data acquisition points and an operation terminal; The data acquisition points are respectively set at different data flow nodes on the data transmission path between the PCIe device and the central processing unit. Each data acquisition point is used to acquire the status information of the data flow at its location. The status information includes error information output by the functional module with data analysis function in the control service component. The operating terminal is electrically connected to several data acquisition points and the PCIe device. The operating terminal includes a configuration module and a storage module. The configuration module is used to customize the stimulus data packets provided to the PCIe device, and the storage module is used to acquire and store the status information fed back by the data acquisition points. The control service component includes a PCIe controller, a memory management unit, a cache coherency controller, and an interrupt controller. The PCIe controller is electrically connected to the PCIe device, the memory management unit is electrically connected to the PCIe controller, the cache coherence controller is electrically connected to the memory management unit, and the interrupt controller is electrically connected to both the cache coherence controller and the central processing unit. The data transmission path between the PCIe device and the central processing unit includes an uplink data channel and a downlink data channel, and the data acquisition point is provided in both the uplink data channel and the downlink data channel; The uplink data channel is a data channel through which data flows from the PCIe device to the central processing unit, and the downlink data channel is a data channel through which data flows from the central processing unit to the PCIe device; The data acquisition points include the first acquisition point, the second acquisition point, the third acquisition point, the fourth acquisition point, the fifth acquisition point, and the sixth acquisition point located in the uplink data channel, and the seventh acquisition point, the eighth acquisition point, and the ninth acquisition point located in the downlink data channel; The first acquisition point and the ninth acquisition point are located between the PCIe device and the PCIe controller; The second acquisition point is located between the PCIe controller and the memory management unit; The third acquisition point is located between the memory management unit and the cache consistency controller; The fourth acquisition point is located between the cache consistency controller and the interrupt controller; The fifth acquisition point is located between the interrupt controller and the central processing unit; The sixth and seventh acquisition points are located between the cache coherence controller and the central processing unit; The eighth acquisition point is located between the cache coherence controller and the PCIe controller.

2. The PCIe system debugging device according to claim 1, characterized in that, The configuration module is also used to configure the data acquisition point to be started, which is a part or all of the set data acquisition points.

3. A PCIe system debugging method, characterized in that, The PCIe system includes a PCIe device and a central processing unit (CPU), and a control service component disposed between the PCIe device and the CPU, the control service component being used to control the communication between the PCIe device and the CPU; The debugging method includes: A user terminal can be used to customize and configure an incentive data packet that is compatible with the current PCIe device, and then send the incentive data packet to the PCIe device. Collect and store the status information of the data flow at different data flow nodes on the data transmission path between the PCIe device and the central processing unit to obtain test data; the status information includes error information output by the functional module with data analysis function in the control service component. When the test data shows that there is an error in the data transmission between the PCIe device and the central processing unit, the configuration of the PCIe device is adjusted according to the test data, and the test data is obtained again until the data transmission between the PCIe device and the central processing unit meets the expectations. The control service components include a PCIe controller, a memory management unit, a cache coherency controller, and an interrupt controller; The PCIe controller is electrically connected to the PCIe device, the memory management unit is electrically connected to the PCIe controller, the cache coherence controller is electrically connected to the memory management unit, and the interrupt controller is electrically connected to both the cache coherence controller and the central processing unit. The data transmission path between the PCIe device and the central processing unit includes an uplink data channel and a downlink data channel, and data acquisition points are provided in both the uplink data channel and the downlink data channel; The uplink data channel is a data channel through which data flows from the PCIe device to the central processing unit, and the downlink data channel is a data channel through which data flows from the central processing unit to the PCIe device; The data acquisition points include the first acquisition point, the second acquisition point, the third acquisition point, the fourth acquisition point, the fifth acquisition point, and the sixth acquisition point located in the uplink data channel, and the seventh acquisition point, the eighth acquisition point, and the ninth acquisition point located in the downlink data channel; The first acquisition point and the ninth acquisition point are located between the PCIe device and the PCIe controller; The second acquisition point is located between the PCIe controller and the memory management unit; The third acquisition point is located between the memory management unit and the cache consistency controller; The fourth acquisition point is located between the cache consistency controller and the interrupt controller; The fifth acquisition point is located between the interrupt controller and the central processing unit; The sixth and seventh acquisition points are located between the cache coherence controller and the central processing unit; The eighth acquisition point is located between the cache coherence controller and the PCIe controller.

4. The PCIe system debugging method according to claim 3, characterized in that, Data acquisition points are set at different data flow nodes on the data transmission path between the PCIe device and the central processing unit, and the status information at the corresponding location is obtained through the data acquisition points; the operation terminal is also used to configure the data acquisition points to be started, and the data acquisition points to be started are some or all of the set data acquisition points.

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