A method for manufacturing a semiconductor device and a semiconductor device

CN119698057BActive Publication Date: 2026-08-28SHANGHAI INTEGRATED CIRCUIT EQUIPMENT & MATERIALS INDUSTRY INNOVATION CENTER CO LTD
View PDF 1 Cites 0 Cited by

Patent Information

Application Number
CN202311218591.5
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2023-09-20
Publication Date
2026-08-28
Estimated Expiration
2043-09-20

AI Technical Summary

Technical Problem

但通过对栅极金属填充前的形貌进行优化,进而实现栅极金属完全填充的相关研究却不多

Benefits of technology

[0003]本发明的目的是提供一种半导体器件的制备方法,可以通过对栅极金属填充前的形貌进行优化,实现栅极金属完全填充;本发明的另一目的在于提供一种半导体器件,可以栅极金属可以完全填充,具有高的良品率。

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN119698057B_ABST
    Figure CN119698057B_ABST
Patent Text Reader

Abstract

The application discloses a preparation method of a semiconductor device and the semiconductor device, and applies to the technical field of semiconductor devices, and comprises the following steps: obtaining a semiconductor structure; etching a photoresist to expose a side wall with a preset height; etching the semiconductor structure with the exposed side wall according to a preset etching time, so that part of a hard mask is left on the top of a pseudo gate of a second type transistor; performing a back etching process based on the etched semiconductor structure, and grinding the surface of the semiconductor structure after the back etching process is completed, so that the top of the pseudo gate of the second type transistor has a non-arch structure. By reducing the etching time, the arch degree of the top of the gate of the second type transistor is effectively reduced; in combination with a subsequent grinding process, the top of the pseudo gate of the second type transistor can have a non-arch structure, the hole after the pseudo gate is removed has a sufficient size to realize complete filling of the gate metal, and the semiconductor device has a high yield.
Need to check novelty before this filing date? Find Prior Art

Citation Information

Patent Citations

  • Method for etching back hard mask layer on top of polycrystalline silicon pseudo gate in gate-last process

    CN114334824A