Etching liquid and method for manufacturing semiconductor device

Abstract

This application discloses an etching solution and a method for fabricating semiconductor devices. The etching solution is used to etch silicon nitride and includes a phosphoric acid solution and an organic solvent, wherein the organic solvent is one of allyltrimethoxysilane and vinyltrimethoxysilane. The yield and performance of semiconductor devices fabricated using the etching solution provided in this application are significantly improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to an etching solution and a method for preparing semiconductor devices. Background Technology

[0002] In the transistor structure of semiconductor devices, sidewall structures are typically incorporated. These sidewalls are usually made of materials with low dielectric constants to isolate the gate and source / drain electrodes, thereby reducing parasitic capacitance within the transistor structure. Air is considered the most ideal material for low dielectric constant. Therefore, using air sidewalls can significantly reduce device parasitic capacitance and effectively improve device and circuit operating speed. However, during fabrication, air sidewalls can easily cause over-etching of other structures within the semiconductor device, thus affecting the yield and performance of the semiconductor device. Summary of the Invention

[0003] The purpose of this application is to at least address the problem of how to improve the performance of semiconductor devices. This purpose is achieved through the following technical solutions:

[0004] A first aspect of this application provides an etching solution for etching silicon nitride, the etching solution comprising:

[0005] Phosphoric acid solution and organic solvent, said organic solvent including one of allyltrimethoxysilane organic solvent and vinyltrimethoxysilane organic solvent.

[0006] In the above embodiments, the etching solution is used to etch silicon nitride. The etching solution has high selectivity for etching silicon nitride and silicon dioxide, and also has high selectivity for etching silicon nitride and hafnium dioxide. This can reduce the etching rate of silicon dioxide and hafnium dioxide while removing silicon nitride, thereby reducing the adverse effects on silicon dioxide and hafnium dioxide and helping to maintain the film thickness using silicon dioxide or hafnium dioxide materials.

[0007] A second aspect of this application also provides a method for fabricating a semiconductor device, comprising:

[0008] Provide a base;

[0009] A transistor structure is formed on one side of the substrate. The transistor structure includes a sidewall sacrificial structure, a first functional part, and a second functional part located on one side of the substrate. At least a portion of the sidewall sacrificial structure is located between the first functional part and the second functional part.

[0010] The etching solution provided in the first aspect of this application is brought into contact with the sidewall sacrificial structure to remove the sidewall sacrificial structure. Attached Figure Description

[0011] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0012] Figure 1 This is a flowchart of a method for fabricating a semiconductor device provided in this application;

[0013] Figure 2 This is a schematic diagram of the transistor structure in a method for fabricating a semiconductor device provided in this application;

[0014] Figure 3 yes Figure 2 Cross-sectional view along the N-N' axis;

[0015] Figure 4 yes Figure 2 Cross-sectional view along the middle M-M';

[0016] Figure 5 This is a cross-sectional view of the transistor structure during the etching process in a semiconductor device fabrication method provided in this application, taken from an N-N' perspective.

[0017] Figure 6 This is a cross-sectional view of the transistor structure during the etching process in a semiconductor device fabrication method provided in this application, taken from the M-M' perspective.

[0018] Figures 7 to 9 This is a schematic diagram illustrating the structural changes of the transistor structure during the fabrication process of a semiconductor device fabrication method provided in this application.

[0019] Figures 10 to 19 yes Figure 9 A schematic diagram of the structural changes of the cross section along P-P' in steps 412 to 421;

[0020] Figures 20 to 29 yes Figure 9 A schematic diagram of the structural changes of the cross section along Q-Q' in steps 412 to 421;

[0021] Figure 30 yes Figure 5 The cross-section shown is a schematic diagram of the structure after removing the sidewall sacrificial structure;

[0022] Figure 31 yes Figure 6 The cross-section shown is a schematic diagram of the structure after removing the sidewall sacrificial structure;

[0023] Figure 32 yes Figure 9A schematic diagram of the structure after removing the sidewall sacrificial structure in another semiconductor device fabrication method provided in this application, with the cross section along P-P' as shown.

[0024] Figures 33 to 34 This is a top view schematic diagram of the structural changes in another semiconductor device fabrication method provided in this application;

[0025] Figure 35 yes Figure 9 A schematic diagram of the structure after removing the sidewall sacrificial structure in another semiconductor device fabrication method provided in this application, with the cross section along P-P' as shown.

[0026] Figures 36 to 37 This is a schematic diagram illustrating the structural changes of the transistor structure in another method for fabricating a semiconductor device provided in this application.

[0027] The attached figures are labeled as follows:

[0028] 1. Substrate; 10. Substrate; 101. First section; 102. Second section; 11. Source region; 12. Drain region; 13. Channel region; 14. Shallow trench isolation structure; 2. Transistor structure; 21. Sidewall sacrificial structure; 211. First sidewall sacrificial structure; 212. Second sidewall sacrificial structure; 22. First functional part; 23. Second functional part; 24. Channel layer stack section; 241. Channel layer; 242. Sacrificial layer; x, First direction; y, Second direction; z, Third direction; 25. Source-drain power 251, Source; 252, Drain; 26, Gate functional section; 27, Gate dielectric layer; 28, First dielectric layer; 29, First channel; 30, Second dielectric layer; 31, Second channel; 32, Sacrificial layer; 33, Dummy gate; 34, Sidewall sacrificial periphery structure; B1, First surface; B2, Second surface; 1021, Source formation region; 1022, Drain formation region; L1, First gap; L2, Second gap; 35, Inner sidewall sacrificial structure; 36, Air sidewall; k, Fourth direction. Detailed Implementation

[0029] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0030] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0031] Although terms such as first, second, third, etc., may be used in this document to describe multiple elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or segment from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and other numerical terms used herein do not imply order or sequence. Therefore, the first element, component, region, layer, or segment discussed below may be referred to as the second element, component, region, layer, or segment without departing from the teachings of the exemplary embodiments.

[0032] For ease of description, spatial relative terms may be used in the text to describe the relationship of one element or feature relative to another element or feature, as shown in the figure. These relative terms include, for example, "inside," "outside," "middle," "outer," "below," "below," "above," "over," etc. Such spatial relative terms are intended to include different orientations of the device in use or operation, other than those depicted in the figure. For example, if the device in the figure is flipped, an element described as "below other elements or features" or "below other elements or features" would subsequently be oriented as "above other elements or features" or "above other elements or features." Therefore, the example term "below" can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or in other directions), and the spatial relative descriptors used in the text will be interpreted accordingly.

[0033] This application provides an etching solution for etching silicon nitride, the etching solution comprising:

[0034] Phosphoric acid solution and organic solvent, the organic solvent being one of allyltrimethoxysilane organic solvent and vinyltrimethoxysilane organic solvent.

[0035] In the above embodiments, the etching solution is used to etch silicon nitride. The etching solution has high selectivity for etching silicon nitride and silicon dioxide, and also has high selectivity for etching silicon nitride and hafnium dioxide. This can reduce the etching rate of silicon dioxide and hafnium dioxide while removing silicon nitride, thereby reducing the adverse effects on silicon dioxide and hafnium dioxide and helping to maintain the film thickness using silicon dioxide or hafnium dioxide materials.

[0036] This etching solution can be used to etch away the silicon nitride sidewall sacrificial structures within semiconductor devices, thereby forming air sidewalls. Air has a lower dielectric constant than silicon nitride, which further reduces the parasitic capacitance between the structures on both sides of the air sidewall, thus further improving the yield of the semiconductor device. Simultaneously, the removal of the sidewall sacrificial structures can be combined with the thickening of films made of silicon dioxide or hafnium dioxide, reducing the impact on other films within the semiconductor device and improving its yield and performance.

[0037] Specifically, the etching solution may include a phosphoric acid solution, which has a high etching rate for silicon nitride. Therefore, hot phosphoric acid solution is used as the main etching solvent for removing silicon nitride. Secondly, organic solvents can be added to the etching solution to reduce the etching rate of silicon dioxide, hafnium dioxide film, silicon, and germanium silicon when etching away the sidewall sacrificial structure. This reduces damage to silicon dioxide, hafnium dioxide film, silicon, and germanium silicon during the removal of the silicon nitride film.

[0038] As shown in Table 1, when the organic solvent includes either allyltrimethoxysilane or vinyltrimethoxysilane, the etching rate of the etchant on silicon dioxide and hafnium dioxide can be reduced, making the etching rate of the etchant on silicon nitride much greater than that on silicon dioxide and hafnium dioxide. This helps to ensure the thickness and yield of the silicon dioxide and hafnium dioxide films. Specifically, the etching rate selectivity ratio of the etchant for silicon nitride to silicon dioxide can be as high as 2900, and the etching rate selectivity ratio for silicon nitride to hafnium dioxide can be as high as 1800.

[0039]

[0040] Table 1: Etching rate or etching selectivity of etchant for different materials

[0041] In one feasible implementation, the phosphoric acid solution concentration ranges from 80% to 90%, the organic solvent purity ranges from 90% to 99%, and the concentration ranges from 0.1% to 10%.

[0042] Specifically, the concentration of the phosphoric acid solution can be 80%, 82%, 83%, 85%, 89%, 90%, etc., and this application does not impose any particular limitation on it. The purity of the organic solvent can be 90%, 91%, 93%, 94%, 96%, 99%, and the concentration can be 0.1%, 0.5%, 0.8%, 1.0%, 1.5%, 2.6%, 3.9%, 5.8%, 6.7%, 7.5%, 8.8%, 9.0%, 10%, etc., and this application does not impose any particular limitation on it.

[0043] Preferably, the concentration range is 0.1%-1%.

[0044] like Figure 1 As shown, according to an embodiment of this application, a method for fabricating a semiconductor device is also proposed, comprising:

[0045] S200 provides substrate 1.

[0046] S400, such as Figure 2 , Figure 3 and Figure 4 As shown, a transistor structure 2 is formed on one side of a substrate 1. The transistor structure 2 includes a sidewall sacrificial structure 21, a first functional part 22, and a second functional part 23 located on one side of the substrate 1. At least a portion of the sidewall sacrificial structure 21 is located between the first functional part 22 and the second functional part 23.

[0047] Specifically, transistor structure 2 may be the main structure for forming a stacked gate-around nanosheet field-effect transistor (GAA NSFET), or it may be the main structure for forming a general transistor. This application does not make any special limitation in this regard.

[0048] S600, such as Figure 5 and Figure 6 As shown, any of the etching solutions provided in the above embodiments of this application are brought into contact with the sidewall sacrificial structure 21 to remove the sidewall sacrificial structure 21.

[0049] In the semiconductor device fabrication method provided in this application, a sidewall sacrificial structure 21 is formed between the first functional part 22 and the second functional part 23 to achieve mutual isolation between the internal structures of the semiconductor device, thereby reducing the parasitic capacitance within the semiconductor device. Subsequently, the sidewall sacrificial structure 21 is removed by etching with an etchant, thereby forming an isolation gap between the first functional part 22 and the second functional part 23. The isolation gap contains air, and the isolation gap and the air inside it can form an air sidewall 36. Since air has a low dielectric constant, the parasitic capacitance within the semiconductor device can be significantly reduced, effectively improving the operating speed of the semiconductor device. The etching solution has a faster etching rate for silicon nitride and a slower etching rate for materials such as silicon dioxide and hafnium dioxide. Therefore, the sidewall sacrificial structure 21 made of silicon nitride can be used, and the materials of the first functional part 22 and the second functional part 23 can include silicon dioxide or hafnium dioxide. Under the etching action of the etching solution, the etching selectivity of the sidewall sacrificial structure 21 and the first functional part 22 and the second functional part 23 is relatively large. This can greatly reduce the damage to the internal structure of the semiconductor device during the removal of the sidewall sacrificial structure 21, which helps to further improve the fabrication yield and performance of the semiconductor device.

[0050] The semiconductor device fabrication method provided in this application can utilize existing semiconductor device fabrication processes. By adding a step to the existing fabrication process to remove the sidewall sacrificial structure 21 using any of the etching solutions provided in the above embodiments of this application, the air sidewall 36 can be formed. The fabrication process is simple and low in cost.

[0051] In one feasible implementation, the transistor may be a stacked gate-around nanosheet field-effect transistor (GAANSFET).

[0052] Specifically, such as Figures 2 to 3 As shown, transistor structure 2 includes a channel layer stack 24, a source / drain functional portion 25, a gate functional portion 26, a gate dielectric layer 27, and a first dielectric layer 28. The channel layer stack 24 is located on one side of the substrate 1 and includes a plurality of channel layers 241 arranged along a first direction x. Each channel layer 241 includes a first end A1, a middle section A2, and a second end A3 arranged along a second direction y, where the first direction x is perpendicular to the second direction y. The source / drain functional portion 25 includes a source portion 251 and a drain portion 252 located on both sides of the channel layer stack 24 along the second direction y. The gate functional portion 26 surrounds the middle section A2 along the direction surrounding the second direction y and protrudes from the source / drain functional portion 25 in a direction away from the substrate 1. The gate dielectric layer 27 is located between the middle section A2 and the gate functional portion 26, and between the source / drain functional portion 25 and the gate functional portion 26. The first dielectric layer 28 is located on the side of the source / drain functional portion 25 away from the substrate 1.

[0053] Stacked gate-a-ring nanosheet field-effect transistors (GAA NSFETs) can significantly suppress short-channel effects, have better gate control characteristics, and effectively improve the current drive performance of semiconductor devices.

[0054] In the above embodiments, the sidewall sacrificial structure 21 includes a first sidewall sacrificial structure 211 and a second sidewall sacrificial structure 212 that are continuously disposed. The first sidewall sacrificial structure 211 is located between the gate dielectric layer 27 and the source portion 251 and between the gate dielectric layer 27 and the drain portion 252. The second sidewall sacrificial structure 212 is located on both sides of the gate functional portion 26 along the second direction y and is located between the gate dielectric layer 27 and the first dielectric layer 28.

[0055] The first functional unit 22 includes a first dielectric layer 28, and may also include a source portion 251 and a drain portion 252. The second functional unit 23 includes a gate dielectric layer 27.

[0056] In the above embodiments, the source portion 251 and the drain portion 252 may be made of germanium silicon or silicon, the first dielectric layer 28 may be made of silicon dioxide, and the gate dielectric layer 27 may be made of hafnium dioxide.

[0057] Because the etching solution has high selectivity for etching silicon nitride and silicon dioxide, and also high selectivity for etching silicon nitride and hafnium dioxide, that is, under the action of the etching solution, the etching selectivity for the sidewall sacrificial structure 21 and the first functional part 22 is relatively high, the etching selectivity for the sidewall sacrificial structure 21 and the second functional part 23 is relatively high, and the etching selectivity for the sidewall sacrificial structure 21 and the substrate 1 is relatively high, when removing the first sidewall sacrificial structure 211, the etching solution contacts and reacts with the first sidewall sacrificial structure 211, and the reaction rate is greater than the reaction rate of the etching solution with the substrate 1, the source / drain functional part 25, and the gate dielectric layer 27 surrounding the first sidewall sacrificial structure 211. Therefore, during the removal of the first sidewall sacrificial structure 211, the etching solution is less likely to damage the substrate 1, the source / drain functional part 25, and the gate dielectric layer 27, which can improve the yield of semiconductor devices. During the removal of the second sidewall sacrificial structure 212, the etchant comes into contact with and reacts with the second sidewall sacrificial structure 212. The reaction rate is greater than the reaction rate between the etchant and the first dielectric layer 28 and the gate dielectric layer 27 surrounding the second sidewall sacrificial structure 212. Therefore, during the removal of the second sidewall sacrificial structure 212, the etchant is less likely to damage the first dielectric layer 28 and the gate dielectric layer 27, which can improve the yield of semiconductor devices.

[0058] In conventional GAA NSFETs, the area from the gate functional portion 26 to the source / drain functional portion 25 and from the gate functional portion 26 to the first dielectric layer 28 is greatly increased, leading to a sharp increase in parasitic capacitance and a significant reduction in circuit operating speed. Using a material with a low dielectric constant as the sidewall structure can reduce parasitic capacitance within the semiconductor device. Therefore, in this application, by forming a first sidewall sacrificial structure 211 and a second sidewall sacrificial structure 212, and then removing the first sidewall sacrificial structure 211 and the second sidewall sacrificial structure 212 with an etchant, an air sidewall 36 is formed. This uses air to isolate the gate functional portion 26 from the source / drain functional portion 25 and from the first dielectric layer 28. Air is considered an ideal low dielectric constant material, thereby reducing parasitic capacitance within the semiconductor device and effectively improving the operating speed of the semiconductor device and the circuits using it, thus enhancing the performance of the semiconductor device.

[0059] Specifically, such as Figure 2 and Figure 4 As shown, the substrate 1 includes a substrate 10 and a shallow trench isolation structure 14. The shallow trench isolation structure 14 includes a trench structure formed on the substrate 10 and an isolation material filled in the trench structure. The shallow trench isolation structure 14 can achieve mutual isolation between adjacent devices.

[0060] Specifically, such as Figure 2 As shown, the substrate 10 includes a first portion 101 and a second portion 102. The shallow trench isolation structure 14 and the second portion 102 are located on the same side of the first portion 101 and are arranged adjacent to each other.

[0061] During the fabrication process of transistor structure 2, a channel layer stack 24 is formed on one side of substrate 1, including:

[0062] S411, such as Figure 7 As shown, a stacked epitaxial layer is formed on one side of the substrate 10. The stacked epitaxial layer includes a channel layer 241 and a sacrificial layer 32 alternately disposed along a direction away from the substrate 10 (first direction x). The stacked epitaxial layer is then patterned, as shown... Figure 8 As shown, at least one channel layer stack 24 is formed. Simultaneously, the substrate 10 can be patterned to form a first portion 101 and a second portion 102, with the second portion 102 located on one side of the first portion 101, and the channel layer stack 24 located on the side of the second portion 102 opposite to the first portion 101. Figure 9 As shown, a shallow trench isolation structure 14 can also be formed on one side of the substrate 10, and the shallow trench isolation structure 14 is disposed around at least a portion of the edge of the second portion 102. The shallow trench isolation structure 14 can achieve electrical isolation between adjacent structures within the semiconductor device.

[0063] S412, the channel layer stack 24 includes a first end, a middle portion, and a second end arranged along a second direction y, the middle portion including a first surface and a second surface arranged along a third direction z. Figure 10 and Figure 20 As shown, a dummy gate 33 is formed on the side of the channel layer stack 24 away from the substrate 10. The dummy gate 33 covers the middle part of the channel layer stack 24 on the side away from the substrate 10, as well as the first surface B1 and the second surface B2.

[0064] S413, such as Figure 10 and Figure 20 As shown, sidewall sacrificial perimeter structures 34 are formed on both sides of the dummy gate 33 along the second direction y, with the sidewall sacrificial perimeter structures 34 exposing portions of the first end and the second end. Then, as... Figure 11 and Figure 21 As shown, the portion of the channel layer stack 24 not covered by the sidewall sacrificial peripheral structure 34 and the dummy gate 33 is removed, thereby forming a source region forming region 1021 and a drain region forming region 1022 on the surface of the second part 102 away from the first part 101.

[0065] Specifically, the sidewall sacrifice outer structure 34 also covers a portion of the first end and a portion of the second end.

[0066] S414, such as Figure 12 and Figure 22 As shown, the portion of the sacrificial layer 32 located at the first end is removed to form a first gap L1, and the portion of the sacrificial layer 32 located at the second end is removed to form a second gap L2.

[0067] S415, such as Figure 13 and Figure 23 As shown, an inner sidewall sacrificial structure 35 is formed in the first gap L1 and the second gap L2. The inner sidewall sacrificial structure 35 and the outer sidewall sacrificial structure 34 are continuously arranged to form a first sidewall sacrificial structure 211. The first sidewall sacrificial structure 211 includes the portion of the outer sidewall sacrificial structure 34 located on both sides of the channel layer stack 24 along the third direction z.

[0068] In the above steps, an outer sidewall sacrificial structure (not shown in the figure) can also be formed on both sides of the dummy gate 33 along the second direction y and on the side of the sidewall sacrificial peripheral structure 34 facing away from the substrate 10. The outer sidewall sacrificial structure and the sidewall sacrificial peripheral structure 34 are continuously disposed to form a second sidewall sacrificial structure 212. The second sidewall sacrificial structure 212 includes the portion of the sidewall sacrificial peripheral structure 34 located on the side of the channel layer stack portion 24 facing away from the substrate 10. Alternatively, the portion of the sidewall sacrificial peripheral structure 34 located on the side of the channel layer stack portion 24 facing away from the substrate 10 can be directly used as the second sidewall sacrificial structure 212.

[0069] S416, such as Figure 14 and Figure 24 As shown, a source portion 251 is formed in the source portion forming region 1021 and a drain portion 252 is formed in the drain portion forming region 1022.

[0070] S417, such as Figure 15 and Figure 25 As shown, a first dielectric layer 28 is formed on the side of the dummy gate 33, the second sidewall sacrificial structure 212, the source portion 251, and the drain portion 252 facing away from the substrate 10, thereby exposing the dummy gate 33 and the second sidewall sacrificial structure 212 on the surface of the first dielectric layer 28 facing away from the substrate 10. Specifically, the dummy gate 33 and the second sidewall sacrificial structure 212 can be exposed on the surface of the first dielectric layer 28 facing away from the substrate 10 by a chemical mechanical polishing (CMP) process.

[0071] S418, such as Figure 16 and Figure 26 As shown, remove the dummy gate 33.

[0072] S419, such as Figure 17 and Figure 27 As shown, the sacrificial layer 32 located in the middle is removed.

[0073] S420, such as Figure 18 and Figure 28 As shown, a gate dielectric layer 27 is formed, which covers the surface of the channel layer 241 located in the middle portion and the surfaces of the second sidewall sacrificial structure 212 and the first sidewall sacrificial structure 211 facing the middle portion.

[0074] S421, such as Figure 19 and Figure 29 As shown, a gate functional portion 26 is formed, and a second dielectric layer 30 is formed on the side of the gate functional portion 26, the gate dielectric layer 27, the second sidewall sacrificial structure 212, and the first dielectric layer 28 away from the substrate 10.

[0075] Specifically, the portions of the first sidewall sacrificial structure 211 and the second sidewall sacrificial structure 212 located in the aforementioned peripheral sidewall sacrificial structure 34 are continuously arranged. That is, the peripheral sidewall sacrificial structure 34 includes the portion of the first sidewall sacrificial structure 211 located on the first surface B1 and the portion of the second surface B2 of the channel layer stack 24, and also includes the portion of the second sidewall sacrificial structure 212 located on the side of the channel layer stack 24 facing away from the substrate 10. Thus, after either the first sidewall sacrificial structure 211 or the second sidewall sacrificial structure 212 has fully reacted with a sufficient amount of etchant, the other sidewall sacrificial structure can also gradually come into contact with and react with the etchant.

[0076] In one feasible implementation, step S600 includes:

[0077] S611, such as Figure 5 and Figure 6 As shown, a first channel 29 is formed on the base 1, the first channel 29 penetrates the base 1, and the first channel 29 exposes the sidewall sacrificial structure 21.

[0078] S612, Figure 5 and Figure 6 The middle arrow indicates the injection direction of the etching solution, which is injected into the first channel 29 to bring the etching solution into contact with the sidewall sacrificial structure 21, as shown. Figure 30 and Figure 31 As shown.

[0079] In the above embodiments, such as Figure 5 As shown, the orthographic projection of the first channel 29 in the thickness direction of the substrate 1 at least partially overlaps with the orthographic projection of the sidewall sacrificial structure 21 in the thickness direction of the substrate 1. Specifically, the orthographic projection of the first channel 29 in the thickness direction of the substrate 1 can cover the orthographic projection of the sidewall sacrificial structure 21 in the thickness direction of the substrate 1, thereby exposing a portion of the sidewall sacrificial structure 21 in the first channel 29. By injecting etchant into the first channel 29, the etchant can react with the sidewall sacrificial structure 21 to remove the sidewall sacrificial structure 21. Since the first sidewall sacrificial structure 211 and the second sidewall sacrificial structure 212 are continuously arranged, after the etchant is injected into the first channel 29, the etchant can fully react with the first sidewall sacrificial structure 211 and the second sidewall sacrificial structure 212, thereby removing the sidewall sacrificial structure 21 and forming an air sidewall 36.

[0080] In the above embodiments, the portion of the substrate 1 opposite to the channel layer stack 24 can be completely removed, that is, the portion of the substrate 1 covered by the orthogonal projection of the channel layer stack 24 onto the substrate 1 can be removed, thereby reducing the parasitic capacitance between the gate function portion 26 and the underlying substrate 1, and further improving the performance of the semiconductor device.

[0081] Specifically, such as Figure 31 As shown, the first channel 29 penetrates the portion of the substrate 1 where the first part 101 and the second part 102 are stacked.

[0082] Specifically, the first channel 29 can completely remove the substrate 10, or as Figure 31 As shown, a portion of the substrate 10 below the source / drain functional section 25 can be retained.

[0083] In one feasible implementation, the first channel 29 is formed using a dry etching process and / or a wet etching process.

[0084] Specifically, part or all of the first part 101 can be removed by a dry etching process, and the second part 102 can be removed by a wet etching process. The etching solution used in the wet etching process may include a tetramethylammonium hydroxide solution.

[0085] During the process of removing the second part 102 by wet etching, the source part 251, the drain part 252 and the gate dielectric layer 27 are used as etching barrier layers.

[0086] In one feasible implementation, the side surface of the first dielectric layer 28 facing away from the substrate 1 exposes the gate functional portion 26 and the second sidewall sacrificial structure 212; step S600 includes:

[0087] S621, etchant is injected into the side of the second sidewall sacrificial structure 212 away from the substrate 1 so that the etchant comes into contact with the second sidewall sacrificial structure 212.

[0088] In the above embodiments, the first dielectric layer 28 is used to achieve planarization of the semiconductor device.

[0089] In the above embodiments, such as Figure 15 and Figure 25 As shown, in step S417, the dummy gate 33 and the second sidewall sacrificial structure 212 are exposed on the side of the first dielectric layer 28 facing away from the substrate 10. Figure 16 and Figure 26 As shown, in step S418, the dummy gate 33 is removed, and in step S421, a gate functional portion 26 is formed at the original location of the dummy gate 33. The first dielectric layer 28 exposes the gate functional portion 26 and the second sidewall sacrificial structure 212. Figure 19 and Figure 29 As shown, after forming the gate functional portion 26 in step S421 and before forming the second dielectric layer 30, the side of the second sidewall sacrificial structure 212 facing away from the substrate 10 is exposed, allowing the sidewall sacrificial structure 212 to be removed at this time. It is sufficient to directly contact the etchant with the side of the second sidewall sacrificial structure 212 facing away from the substrate 10. Since the first sidewall sacrificial structure 211 and the second sidewall sacrificial structure 212 are continuously arranged, they can be removed together, thus forming an air sidewall 36, with a cross-section as shown. Figure 32 As shown.

[0090] In the above embodiment, the air sidewall 36 is formed first, and then the second dielectric layer 30 is formed. When forming the second dielectric layer 30, a portion of the second dielectric layer 30 may be located at the end of the sidewall of the air sidewall 36 away from the substrate 10, such as... Figure 32 As shown.

[0091] The above-described implementation is simple to operate, thereby reducing manufacturing costs. Here, the substrate 1, source / drain functional units 25, first dielectric layer 28, and gate dielectric layer 27 serve as etch barrier layers. Since the sidewall sacrificial structure 21 is typically made of silicon nitride, the source 251 and drain 252 are made of germanium-silicon or silicon, the first dielectric layer 28 is made of silicon dioxide, and the gate dielectric layer 27 is made of hafnium dioxide. The etching rate of the etchant on silicon nitride is greater than that on silicon dioxide, silicon, and hafnium dioxide, which helps to ensure the thickness and yield of the silicon dioxide, silicon, and hafnium dioxide films. In other words, during the removal of the sidewall sacrificial structure 21, the etchant is less likely to damage the substrate 1, source / drain functional units 25, and gate dielectric layer 27, thus improving the yield of the semiconductor device.

[0092] In one feasible implementation, portions of the sidewall sacrificial structure 21 are located on both sides of the trench layer stack 24 along a third direction z, which is perpendicular to the second direction y and the first direction x. Figure 29 As shown, the fabrication method further includes: forming a second dielectric layer 30 on the side of the first dielectric layer 28 facing away from the substrate 1, the second dielectric layer 30 covering and encapsulating the transistor structure 2. Step S600 includes: S631, as shown... Figure 33 As shown, a second channel 31 is formed in the second dielectric layer 30, penetrating the second dielectric layer 30 along a third direction z. The second channel 31 exposes the sidewall sacrificial structure 21, as shown. Figure 33 and Figure 34 As shown, etchant is injected into the second channel 31 to bring it into contact with the sidewall sacrificial structure 21. After etching away the sidewall sacrificial structure 21, an air sidewall 36 is formed, with a cross-section as shown. Figure 35 As shown.

[0093] The second dielectric layer 30 is made of silicon dioxide. Under the etching action of the etching solution, the etching selectivity between the sidewall sacrificial structure 21 and the second dielectric layer 30 is relatively large, so that the second dielectric layer 30 is not easily damaged when the sidewall sacrificial structure 21 is etched away.

[0094] In the above embodiment, the second dielectric layer 30 is used to cover the gate functional portion 26, the gate dielectric layer 27, the second sidewall sacrificial structure 212, and the side surface of the first dielectric layer 28 facing away from the substrate 10, and is disposed around the transistor structure 2 in a direction surrounding the first direction x.

[0095] In the above embodiment, a second channel 31 is formed in the second dielectric layer 30, penetrating the second dielectric layer 30 in a third direction z, and the second channel 31 exposes the sidewall sacrificial structure 21, so that etching solution can be injected into the second channel 31 to bring the etching solution into contact with the sidewall sacrificial structure 21. Specifically, the second channel 31 can be formed by a dry etching process.

[0096] In the above embodiments, the substrate 1, the source / drain functional unit 25, the gate dielectric layer 27, and the second dielectric layer 30 serve as etch barrier layers. Under the action of the etchant, the etch selectivity of the sidewall sacrificial structure 21 and the substrate 1, the source / drain functional unit 25, the gate dielectric layer 27, and the second dielectric layer 30 is relatively large. Therefore, during the removal of the sidewall sacrificial structure 21, the etchant is less likely to damage the substrate 1, the source / drain functional unit 25, the gate dielectric layer 27, and the second dielectric layer 30, thereby improving the yield of semiconductor devices.

[0097] In the above embodiments, although an additional drilling process is required to form the second channel 31, the etching processes of the second channel 31 and the sidewall sacrificial structure 21 can be performed after the semiconductor structure is fabricated without changing the original process, thereby reducing the fabrication difficulty and cost.

[0098] In another feasible implementation, such as Figure 36 As shown, the substrate 1 includes a source region 11 and a drain region 12 arranged along the fourth direction k, and a channel region 13 located between the source region 11 and the drain region 12.

[0099] S421, the step of forming a transistor structure 2 on one side of the substrate 1 includes: forming a gate functional portion 26 on one side of the channel region 13, forming a sidewall sacrificial structure 21 on both sides of the gate functional portion 26 opposite to each other along the fourth direction k, forming a first dielectric layer 28 on the side of the sidewall sacrificial structure 21 away from the substrate 1, forming a first via opposite to the source region and a second via opposite to the drain region on the first dielectric layer 28, forming a source portion 251 in the first via, and forming a drain portion 252 in the second via.

[0100] The first functional unit 22 includes at least one of a source unit 251 and a drain unit 252, and the second functional unit 23 includes a gate functional unit 26.

[0101] The above embodiment is a method for fabricating a common transistor. In the above embodiment, the sidewall sacrificial structure 21 can be in direct contact with the source portion 251, the drain portion 252, and the gate functional portion 26.

[0102] Specifically, during the fabrication process, a hard mask covering the gate functional portion 26 can be formed on the side of the gate functional portion 26 facing away from the substrate 1. The hard mask can be made of silicon dioxide.

[0103] In the above embodiments, under the etching action of the etchant, the etching selectivity between the sidewall sacrificial structure 21 and the substrate 1 is relatively large, the etching selectivity between the sidewall sacrificial structure 21 and the first functional part 22 is relatively large, and the etching selectivity between the sidewall sacrificial structure 21 and the second functional part 23 is relatively large. Therefore, during the etching process of the sidewall sacrificial structure 21 by the etchant, the damage to the source part 251, the drain part 252, the gate functional part 26 and the substrate 1 can be reduced, thereby improving the fabrication yield and performance of the semiconductor device. Specifically, the sidewall sacrificial structure 21 is made of silicon nitride, the first dielectric layer 28 is made of silicon, the source / drain functional part 25 is made of silicon or germanium-silicon, and the gate functional part 26 is made of metal. The etching solution used in the above embodiments of this application can improve the etching selectivity of silicon nitride to silicon, the etching selectivity of silicon nitride to germanium-silicon, and the etching selectivity of silicon nitride to metal, thereby making the etching rate of the sidewall sacrificial structure 21 higher and the etching rate of the first functional part 22 and the second functional part 23 lower, which helps to improve the yield of semiconductor devices.

[0104] In the above embodiments, when forming the first dielectric layer 28 and the source portion 251 and the drain portion 252, the side surface of the sidewall sacrificial structure 21 facing away from the substrate 1 may be covered. The sidewall sacrificial structure 21 can be exposed by chemical mechanical polishing process so that the sidewall sacrificial structure 21 can come into contact with the etching solution.

[0105] In the above embodiments, the semiconductor device includes a second dielectric layer 30 located on the side of the source / drain functional portion 25 and the gate functional portion 26 facing away from the substrate. Before forming the second dielectric layer 30, such as Figure 36 and Figure 37 As shown, the etching solution can directly contact the sidewall sacrificial structure 21 from the side facing away from the substrate 1, and remove the sidewall sacrificial structure 21 to form an air sidewall 36. The material of the second dielectric layer 30 may also include silicon dioxide.

[0106] In one possible implementation, the following steps are included prior to step S600:

[0107] The process of forming an etching solution includes: adding an organic solvent to a phosphoric acid solution, mixing and stirring until homogeneous, and then allowing it to stand for a preset time, which is greater than or equal to 30 minutes; and then heating the mixed solution to a preset temperature, which is in the range of 120°C to 180°C.

[0108] In the above embodiments, adding an organic solvent to the phosphoric acid solution, mixing and stirring evenly, and then letting it stand for more than or equal to 30 minutes allows the phosphoric acid solution and the organic solvent to react fully, thereby achieving a good etching effect in the subsequent etching process.

[0109] In the above embodiments, the preset temperature can be 120℃, 130℃, 145℃, 160℃, 177℃, 180℃, etc., and this application does not make any special limitation on it.

[0110] Specifically, the preset temperature can be 160℃, which allows the etching solution to achieve a better reaction with silicon nitride and reduces the adverse effects of the etching solution on silicon, silicon dioxide and hafnium dioxide (HfO2).

[0111] In the above embodiments, the preset temperature can meet the reaction temperature of the etching solution and silicon nitride, thereby achieving the etching of silicon nitride.

[0112] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method of manufacturing a semiconductor device, characterized by, include: Provide a base; A transistor structure is formed on one side of the substrate. The transistor structure includes a sidewall sacrificial structure, a first functional portion, and a second functional portion located on one side of the substrate. At least a portion of the sidewall sacrificial structure is located between the first functional portion and the second functional portion. The transistor structure also includes a channel layer stack located on one side of the substrate. The channel layer stack includes a plurality of channel layers arranged along a first direction. Each channel layer includes a first end, a middle section, and a second end arranged along a second direction. The first direction is perpendicular to the second direction. The transistor structure further includes a source / drain functional portion and a gate functional portion located on one side of the substrate. The source / drain functional portion includes a source portion and a drain portion located on both sides of the channel layer stack portion along a second direction. The gate functional portion surrounds the intermediate segment along a direction around the second direction, and the gate functional portion protrudes from the source / drain functional portion along a direction away from the substrate. The transistor structure further includes a gate dielectric layer, which is located between the intermediate segment and the gate functional portion and between the source / drain functional portion and the gate functional portion; The transistor structure further includes a first dielectric layer, which is located on the side of the source / drain functional portion away from the substrate. The sidewall sacrificial structure includes a first sidewall sacrificial structure and a second sidewall sacrificial structure that are continuously disposed thereon. The first sidewall sacrificial structure is located between the gate dielectric layer and the source portion and between the gate dielectric layer and the drain portion. The second sidewall sacrificial structure is located on both sides of the gate functional portion along the second direction and is located between the gate dielectric layer and the first dielectric layer. The first functional unit includes at least one of the source unit, the drain unit, and the first dielectric layer, and the second functional unit includes the gate dielectric layer; The etchant is brought into contact with the sidewall sacrificial structure to remove it. The etchant comprises a phosphoric acid solution and an organic solvent, the organic solvent being one of allyltrimethoxysilane organic solvent and vinyltrimethoxysilane organic solvent.

2. The method of producing a semiconductor device according to claim 1, wherein The step of contacting the etchant with the sidewall sacrificial structure to remove the sidewall sacrificial structure includes: A first channel is formed in the substrate, the first channel penetrating the substrate and exposing the sidewall sacrificial structure; The etching solution is injected into the first channel to bring the etching solution into contact with the sidewall sacrificial structure.

3. The method of producing a semiconductor device according to claim 2, wherein The first channel is formed using either a dry etching process or a wet etching process.

4. The method of producing a semiconductor device according to Claim 1, wherein The side surface of the first dielectric layer facing away from the substrate exposes the gate function and the second sidewall sacrificial structure; The step of contacting the etchant with the sidewall sacrificial structure to remove the sidewall sacrificial structure includes: Etching solution is injected from the side of the second sidewall sacrificial structure away from the substrate so that the etching solution comes into contact with the second sidewall sacrificial structure.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, A portion of the sidewall sacrificial structure is located on both sides of the trench layer stack along a third direction, the third direction being perpendicular to the second direction and the third direction being perpendicular to the first direction; It also includes forming a second dielectric layer on the side of the first dielectric layer opposite to the substrate, the second dielectric layer covering and encapsulating the transistor structure; The step of contacting the etchant with the sidewall sacrificial structure to remove the sidewall sacrificial structure includes: A second channel is formed in the second dielectric layer, extending through the second dielectric layer in a third direction, the second channel exposing the sidewall sacrificial structure, and the etching solution is injected into the second channel to bring the etching solution into contact with the sidewall sacrificial structure; Wherein, under the etching action of the etching solution, the etching selectivity ratio between the sidewall sacrificial structure and the second dielectric layer is greater than 1.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, Prior to the step of contacting the etchant with the sidewall sacrificial structure to remove the sidewall sacrificial structure, the following steps are included: The process of forming an etching solution includes: adding the organic solvent to the phosphoric acid solution, mixing and stirring until homogeneous, and then allowing it to stand for a preset time, the preset time being greater than or equal to 30 minutes, and then heating the mixed solution to a preset temperature, the preset temperature being in the range of 120°C to 180°C.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The concentration range of the phosphoric acid solution is 80%-90%, the purity range of the organic solvent is 90%-99%, and the concentration range of the organic solvent is 0.1%-10%.

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