Voltage regulation circuits, electronic devices and voltage regulation methods

Abstract

This application discloses a voltage regulation circuit, electronic device, and voltage regulation method. When the load following the VRM is working, a logic high level is input to the SYNC pin of the SPS / DrMOS to enable the SPS / DrMOS to operate normally; when the load following the VRM is not working, the SYNC pin of the SPS / DrMOS is set to an intermediate state to enable the SPS / DrMOS to enter standby mode, thereby reducing the quiescent current on the VCC pin and reducing the additional power consumption on the VCC pin of the SPS / DrMOS.

Description

Technical Field

[0001] This application relates to the field of electronic circuits, and more particularly to voltage regulation circuits, electronic devices, and voltage regulation methods. Background Technology

[0002] The load requirements and current draw of some modules in electronic devices, such as the central processing unit (CPU), graphics processing unit (GPU), and application-specific integrated circuit (ASIC), are dynamically changing. For example, the CPU's load voltage and current differ significantly when opening a document versus opening a game. Therefore, the core voltage (Vcore) required by these modules differs and may increase or decrease instantaneously. A power supply with a fixed output voltage cannot meet the voltage requirements of these modules. To address this, electronic devices incorporate a voltage regulator module (VRM) to convert the larger DC voltage (e.g., 12V) output by the power supply into a stable smaller DC voltage (e.g., 0.5V-2V). This VRM can adjust the output voltage in real time according to load demand to meet the operating voltage requirements of the aforementioned modules. Summary of the Invention

[0003] This application provides a voltage regulation circuit, electronic device, and voltage regulation method that can reduce the additional power consumption of the electronic device.

[0004] In a first aspect, a voltage regulation circuit is provided, comprising: a pulse width modulation (PWM) controller, and N first circuits, where N is a positive integer. Each first circuit includes a unidirectional conduction device and a second circuit. The PWM controller outputs a PWM voltage signal to the second circuit, and the second circuit reduces the voltage received at the high-voltage input terminal of the voltage regulation circuit according to the PWM voltage signal before outputting it. The PWM controller includes an EN pin, which is connected to the input terminal of the PWM controller's enable signal. The second circuit includes a DrMOS transistor, which includes a SYNC pin and a VCC pin. The VCC pin is connected to the input terminal of the DrMOS's drive voltage, and the SYNC pin is not connected to the input terminal of the DrMOS's drive voltage. Input terminals: The first terminal of the pull-up resistor module is connected to the VCC pin, and the second terminal is connected to the SYNC pin; the first terminal of the pull-down resistor module is connected to the SYNC pin, and the second terminal is grounded; the pull-up resistor module includes a first resistor and / or a third resistor, and the pull-down resistor module includes a second resistor and / or a fourth resistor; the first terminals of the first and third resistors are both connected to the VCC pin, and the second terminals of both resistors are connected to the SYNC pin; the first terminals of the second and fourth resistors are both connected to the SYNC pin, and the second terminals of both resistors are grounded; the first and second resistors belong to the voltage regulation circuit and are located outside the PWM controller and the second circuit; the third and fourth resistors belong to DrMOS; the first terminal of the unidirectional conduction device is connected to the EN pin of the PWM controller, and the second terminal is connected to the SYNC pin.

[0005] In implementing the voltage regulation circuit of the first aspect, the SYNC pin is not connected to the input terminal of the DrMOS drive voltage. Instead, it is connected to VCC through a pull-up resistor module and grounded through a pull-down resistor module. This allows the voltage on the SYNC pin to be adjusted during the operation and non-operation of the voltage regulation circuit, preventing the SYNC pin from continuously receiving the drive voltage.

[0006] In conjunction with the first aspect, in some implementations, the static current on the VCC pin when the SYNC pin is at an intermediate level is less than the static current on the VCC pin when the SYNC pin is at a logic high level; when the EN pin of the PWM controller receives a logic high level, the unidirectional conduction device is turned on from the first end to the second end, and the SYNC pin receives a high level; when the EN pin of the PWM controller receives a logic low level, the unidirectional conduction device is turned off from the first end to the second end, and the SYNC pin receives an intermediate level.

[0007] In the above implementation method, when the PWM controller is working, a logic high level is input to the SYNC pin so that DrMOS can work normally; when the PWM controller is not working, the SYNC pin is set to an intermediate state, thereby reducing the static current on the VCC pin, that is, reducing the additional power consumption on the VCC pin.

[0008] In conjunction with the first aspect, in some embodiments, the voltage regulation circuit further includes: a first capacitor, a first terminal of which is connected to the SYNC pin, and a second terminal of which is grounded. The first capacitor can be used to adjust the timing of the SYNC pin transitioning from a logic high level to an intermediate state level, so that the SYNC pin powers down slower than the EN pin, thereby preventing undervoltage faults in the PWM controller.

[0009] In conjunction with the first aspect, in some implementations, the first capacitor is located outside the PWM controller and the second circuit.

[0010] In conjunction with the first aspect, in some embodiments, when the pressure difference between the first and second ends of the unidirectional conduction device is greater than the conduction voltage drop of the unidirectional conduction device, the unidirectional conduction device is turned on from the first end to the second end; otherwise, the unidirectional conduction device is turned off.

[0011] In conjunction with the first aspect, in some embodiments, the unidirectional conduction device is a diode, with the anode of the diode connected to the EN pin of the PWM controller and the cathode of the diode connected to the SYNC pin.

[0012] In conjunction with the first aspect, in some embodiments, the DrMOS includes: a driver, a first switch, and a second switch, wherein, for the first switch, the drain is connected to the high-voltage input terminal of the voltage regulation circuit, the gate is connected to the first output terminal of the driver, and the source is connected to the output terminal of the DrMOS; for the second switch, the drain is connected to the output terminal of the DrMOS, the gate is connected to the second output terminal of the driver, and the source is grounded; the input terminal of the driver is connected to the output terminal of the PWM controller.

[0013] In conjunction with the previous embodiment, the first switching transistor can be an N-type field-effect transistor, and the second switching transistor can be an N-type field-effect transistor.

[0014] In conjunction with the previous embodiment, when the PWM voltage signal is in the positive half-cycle, the first output terminal of the driver outputs the first drive signal, the first switch is turned on, and the second switch is turned off; when the PWM voltage signal is in the negative half-cycle, the second output terminal of the driver outputs the second drive signal, the first switch is turned off, and the second switch is turned on.

[0015] In conjunction with the previous embodiment, the second circuit further includes: a first inductor and a second capacitor. The first end of the first inductor is connected to the output terminal of the DrMOS, the second end of the first inductor and the first end of the second capacitor are both connected to the high-voltage output terminal of the voltage regulation circuit, and the second end of the second capacitor is grounded.

[0016] In conjunction with the first aspect, in some implementations, the high-voltage input terminal of the voltage regulation circuit is connected to the high-voltage output terminal of the power supply.

[0017] In conjunction with the first aspect, in some implementations, the high-voltage output terminal of the voltage regulation circuit is connected to the high-voltage input terminal of the load.

[0018] In conjunction with the previous embodiment, the current output from the high-voltage output terminal of the voltage regulation circuit to the load is the sum of the output currents of the first circuits that are activated among the N first circuits.

[0019] In conjunction with the first aspect, in some implementations, the voltage regulation circuit is connected to a load, which includes any of the following: CPU, GPU, ASIC.

[0020] In conjunction with the first aspect, in some implementations, the enable signal input of the PWM controller is a GPIO interface. This GPIO interface can be used to receive control signals from a control unit (such as a CPU, EC, etc.).

[0021] In conjunction with the first aspect, in some implementations, the PWM controller is integrated in a first chip, and the DrMOS is integrated in a second chip; the first chip and the second chip are different.

[0022] In a second aspect, an electronic device is provided, which includes a voltage regulation circuit as provided in the first aspect or any embodiment of the first aspect.

[0023] In conjunction with the second aspect, in some embodiments, the electronic device further includes a power supply for inputting voltage to the voltage regulation circuit.

[0024] In conjunction with the second aspect, in some embodiments, the electronic device further includes a load, and the voltage output by the voltage regulation circuit is used to supply voltage to the load.

[0025] Thirdly, a voltage regulation method is provided, applied to an electronic device provided in the second aspect or any embodiment of the second aspect. The method may include: the electronic device detecting an operation to start a load; inputting a logic high level to the EN pin of a PWM controller; detecting an operation to shut down a load; and inputting a logic low level to the EN pin of the PWM controller.

[0026] The method of the third invention enables electronic devices to reduce the output voltage of a large voltage using a voltage regulation circuit, thereby meeting the actual needs of the downstream load, and also reducing the additional power consumption on the VCC pin of DrMOS when the downstream load is not working.

[0027] In conjunction with the third aspect, in some implementations, the electronic device inputs a logic high level or a logic low level to the EN pin of the PWM controller via a GPIO interface.

[0028] In conjunction with the third aspect, in some implementations, after the electronic device inputs a logic high level to the EN pin of the PWM controller, it can also obtain the voltage demand of the load and adjust the duty cycle of the PWM voltage signal output by the PWM controller to the second circuit according to the voltage demand of the load. For example, if the voltage demand of the load increases, the duty cycle is increased, and vice versa.

[0029] In conjunction with the third aspect, in some embodiments, the electronic device can also acquire the current demand of the load and adjust the number of activated first circuits among the N first circuits of the voltage regulation circuit according to the current demand of the load. For example, if the current demand of the load increases, the number of activated first circuits is increased, and vice versa.

[0030] Fourthly, a PCB board is provided, including the voltage regulation circuit of the first aspect or any embodiment of the first aspect.

[0031] Fifthly, a chip is provided, the chip including the voltage regulation circuit of the first aspect or any embodiment of the first aspect.

[0032] In a sixth aspect, a power supply system is provided, which may include: a power source, a voltage regulation circuit according to the first aspect or any embodiment of the first aspect, and a load. The power source is used to provide an input voltage to the voltage regulation circuit, and the voltage regulation circuit is used to reduce the input voltage provided by the power source and output it to the load.

[0033] In a seventh aspect, a power supply circuit is provided, which may include: a power source, and a voltage regulation circuit as described in the first aspect or any embodiment of the first aspect. The power source provides an input voltage to the voltage regulation circuit, and the voltage regulation circuit reduces the input voltage provided by the power source before outputting it.

[0034] Eighthly, a power supply system is provided, which may include: a voltage regulation circuit as described in the first aspect or any embodiment of the first aspect, and a load. The voltage regulation circuit is used to reduce the received input voltage and output it to the load.

[0035] A ninth aspect provides a readable storage medium including instructions that, when executed on a device, cause the device to perform a method as described in the third aspect or any embodiment of the third aspect.

[0036] In a tenth aspect, a program product is provided that, when the program product is run on a device, causes the device to perform a method as described in the third aspect, or any implementation thereof.

[0037] Eleventhly, a chip system is provided, the chip system including at least one processor for implementing the method as described in the third aspect, or any embodiment of the third aspect. Attached Figure Description

[0038] Figure 1 This is a structural diagram of a single-phase VRM provided in an embodiment of this application;

[0039] Figure 2 This is a structural diagram of a multiphase VRM provided in an embodiment of this application;

[0040] Figure 3 A schematic diagram of some pins of MP2886, some pins of MP86941, and some peripheral structures provided for embodiments of this application;

[0041] Figure 4 A partial structural diagram of an improved VRM provided in an embodiment of this application;

[0042] Figure 5 An internal structure diagram of SPS / DrMOS provided in an embodiment of this application;

[0043] Figure 6 A partial structural diagram of an improved VRM provided in an embodiment of this application;

[0044] Figure 7 A partial structural diagram of an improved VRM provided in an embodiment of this application;

[0045] Figure 8 A partial structural diagram of an improved VRM provided in an embodiment of this application;

[0046] Figure 9 A partial structural diagram of an improved VRM provided in an embodiment of this application;

[0047] Figure 10 This is a structural diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0048] The technical solutions in the embodiments of this application will be clearly and thoroughly described below with reference to the accompanying drawings.

[0049] First, let's introduce some concepts involved in this application.

[0050] VRM

[0051] VRM is used to convert the larger DC voltage (such as 12V) output from the power supply of electronic devices into a stable smaller DC voltage (such as 0.5V-2V), which is then output to modules such as CPU, GPU, and ASIC to meet the operating voltage requirements of these modules.

[0052] Figure 1 This is a schematic diagram of a single-phase voltage regulator module (VRM) 10. This single-phase VRM 10 can also be called a single-phase DC-DC Buck type step-down circuit.

[0053] The single-phase VRM 10 may include: a pulse-width modulation (PWM) controller 101, a driver 102, a high-side power field-effect transistor (HS-FET) M1, a low-side power field-effect transistor (LS-FET) M2, an inductor L, and a capacitor C. The single-phase VRM 10 also includes: a first input terminal and a second input terminal, a first output terminal and a second output terminal.

[0054] The first input terminal, also known as the high-voltage input terminal, connects to the high-voltage output terminal of the device's power supply to receive the input voltage Vin. The second input terminal, also known as the low-voltage input terminal, connects to the low-voltage output terminal of the device's power supply. The first output terminal, also known as the high-voltage output terminal, connects to one input terminal of the downstream load to output the core voltage Vcore required by the downstream load. The second output terminal, also known as the low-voltage output terminal, connects to the other input terminal of the downstream load. Both the second input terminal and the second output terminal can be connected to ground (GND). The input voltage Vin can be the output voltage of the device's power supply, which can be a battery. The downstream load refers to modules such as CPUs, GPUs, and ASICs that have specific operating voltage requirements.

[0055] PWM controller 101 is connected to driver 102 and outputs a PWM voltage signal to driver 102. This PWM voltage signal can be generated by a comparator CP in PWM controller 101, which compares a fixed reference voltage Vref with the core voltage Vcore output by single-phase VRM 10. PWM controller 101 controls the duty cycle of the PWM waveform according to the real-time demand of the load, so that the output voltage is stabilized at the required value of the core voltage Vcore. The PWM voltage signal output by PWM controller 101 is an analog signal with alternating high and low levels. When the PWM voltage signal is high, it is in the positive half-cycle; when the PWM voltage signal is low, it is in the negative half-cycle.

[0056] driver102 may include a control logic circuit 1011 and two driver circuits 1012 and 1013.

[0057] M1 or M2 can be either an N-type field-effect transistor or a P-type field-effect transistor.

[0058] The drain (D) of M1 is connected to the first input terminal, the gate (G) of M1 is connected to the output terminal of driver circuit 1012, and the source (S) of M1 is connected to the first terminal of L. The drain (D) of M2 is connected to the first terminal of L, the gate (G) of M2 receives the output terminal of driver circuit 1013, and the source (S) of M2 is connected to the second input terminal. The second terminal of L is connected to the first output terminal, used to output the required core voltage Vcore to the subsequent load. The first terminal of C is connected to the second terminal of L, and the second terminal of C is connected to the second output terminal.

[0059] When the PWM voltage signal output by the PWM controller 101 is in the positive half-cycle, the control logic circuit 1011 in the driver 102 generates a signal that causes the drive circuit 1012 to output a first drive signal S1 to M1. M1 is turned on, and M2 is turned off / off. Current flows from VCC through M1 and L, charging C, and L generates a self-induced electromotive force. When the PWM voltage signal output by the PWM controller 101 is in the negative half-cycle, the control logic circuit 1011 in the driver 102 generates a signal that causes the drive circuit 1013 to output a second drive signal S2 to M2. M1 is turned off / off, and M2 is turned on. The current in L will attempt to maintain its existing magnetic field, causing the voltage to reverse and accumulate in C. When the electromotive force on L decreases or dwindles, C outputs the supply voltage to the downstream load. Thus, under the action of the PWM voltage signal, the driver 102 controls M1 and M2 to switch frequently to provide a continuous and stable current and voltage to the downstream load.

[0060] Integrating M1, M2, and driver102 into a single chip creates a device known as a smart power stage (SPS), also called DrMOS. This integrated solution reduces overall size and improves power density and efficiency. SPS / DrMOS can also integrate overcurrent protection circuitry to control output current and prevent it from exceeding rated values; it can also integrate fault detection circuitry to detect faults such as overheating, overvoltage, and open circuits.

[0061] The output terminal of DrMOS is connected to the source (S) of M1, and the drain (D) of M2 is connected to the first terminal of L.

[0062] One phase of a VRM refers to a circuit consisting of driver 102, M1, M2, inductor L, and capacitor C. To meet the requirements of different loads and improve output power, a multi-phase voltage regulator module (multi-phase VRM) was introduced.

[0063] Figure 2 This is a schematic diagram of a multiphase VRM 20. This multiphase VRM 20 can also be called a multiphase DC-DC Buck-type step-down circuit.

[0064] The multiphase VRM 20 may include: a PWM controller 201, and multiple interleaved single-phase circuits. Each single-phase circuit is connected to... Figure 1 The single-phase circuits shown have the same structure. The first output terminal of each single-phase circuit is connected to one input terminal of the subsequent load to output the core voltage Vcore required by the subsequent load. The PWM controller 201 is used to provide a PWM voltage signal to some or all of the single-phase circuits in the multi-channel circuit. The current output by the multi-phase VRM 20 to the subsequent load is the sum of the output currents of the single-phase circuits that are started in the multi-channel circuit.

[0065] The multiphase VRM 20 requires the use of multiple SPS / DrMOS.

[0066] Additional power consumption generated by VRM

[0067] Some possible implementations of the VRM may have additional power consumption, such as the following:

[0068] Certain PWM controllers and SPS / DrMOS chips with specific architectures can lead to additional power consumption. Typically, the PWM controller is integrated into a power management IC chip, referred to as a PWM control chip; the SPS / DrMOS chip is integrated into another power management IC chip, referred to as an SPS / DrMOS chip. The following describes the structures of PWM control chips and SPS / DrMOS chips that cause additional power consumption.

[0069] PWM control chips include the above Figure 2 The structure of the PWM controller 201 also includes an enable pin, EN. The EN pin can be connected to a signal interface (such as a general purpose input / output (GPIO) interface) to receive enable signals, also known as control signals, sent from the control unit in the electronic device (such as a CPU, embedded controller (EC)). The PWM control chip operates when the EN pin receives a logic high level, implementing the functions of the PWM controller mentioned earlier; when the EN pin receives a logic low level, the PWM control chip does not operate.

[0070] When the downstream load of the VRM (such as the GPU) is working, the EN pin in the PWM control chip is at a logic high level, so that the PWM control chip can perform the function of the PWM controller mentioned above; when the downstream load of the VRM (such as the GPU) is not working, the EN pin in the PWM control chip is at a logic low level, and the PWM control chip does not run.

[0071] Refer to Table 1, which shows the logic level of the EN pin of the PWM control chip.

[0072]

[0073]

[0074] Table 1

[0075] As shown in Table 1, the logic high level of the EN pin of the PWM control chip is required to be greater than 0.8V, for example, it can be 3.3V or other values.

[0076] SPS / DrMOS chips include the above-mentioned Figure 1 One of the SPS / DrMOS or Figure 2 Multiple SPS / DrMOS in it.

[0077] refer to Figure 3 , Figure 3 Examples are shown of some pins of a PWM control chip, some pins of an SPS / DrMOS chip, and some peripheral structures. For example... Figure 3 As shown, the PWM control chip may include a PWM pin, an EN pin, etc., while the SPS / DrMOS chip includes an EN pin, a VCC pin, a SYNC pin, a PWM pin, a VIN pin, and other pins (such as the SW pin for outputting switching signals, the GND pin, etc.). The EN pin of the PWM control chip can be connected to GPIO to receive an enable signal. The PWM pin of the PWM control chip and the PWM pin of the SPS / DrMOS chip are directly connected, and the PWM pin of the PWM control chip is used to output a PWM voltage signal to the PWM pin of the SPS / DrMOS chip. The SW pin of the SPS / DrMOS chip is connected to the first terminal of the inductor L in VRM, where L can be... Figure 1 or Figure 2 The inductance L in the middle.

[0078] In an SPS / DrMOS chip, the VCC pin is used to receive the power supply voltage that drives the SPS / DrMOS chip. The VCC pin is typically directly connected to the common VCC network in the electronic device to receive the drive voltage output from that common VCC network, which can be, for example, 3.3V. Typically, as... Figure 3As shown, the SYNC pin is also directly connected to the common VCC network around the SPS / DrMOS chip to receive the power supply voltage (e.g., 3.3V) driving the SPS / DrMOS chip. The PWM pin is used to receive the PWM voltage signal output from the preceding PWM controller. The VIN pin is connected to the high-voltage output terminal of the device power supply to receive the DC voltage output by the device power supply.

[0079] The SYNC pin is a mode switching control pin for the chip. When this pin is high, the SPS / DrMOS chip enters active mode; when this pin is in an intermediate state or floating, the SPS / DrMOS chip enters standby mode; when this pin is low, the SPS / DrMOS chip enters diode emulation mode. In diode emulation mode, when the current in inductor L flows from the second terminal to the first terminal, M2 conducts; when the current in inductor L flows from the first terminal to the second terminal, M2 is cut off to prevent current backflow.

[0080] When the SYNC pin is left floating or at an intermediate level, the SPS / DrMOS chip enters standby mode and stops working. Even if the SPS / DrMOS chip receives a PWM voltage signal, it will not output voltage, i.e., it enters standby mode. When the SPS / DrMOS chip enters normal operating mode, it will start working as long as it receives a PWM signal from the PWM controller.

[0081] The SYNC pin can receive high, low, and intermediate voltage levels. Refer to Table 2, which shows the tri-state voltage range of the SYNC pin in the SPS / DrMOS chip.

[0082]

[0083] Table 2

[0084] As shown in Table 2, the intermediate state level of the SYNC pin lies between logic high and logic low. When the SYNC pin is in the intermediate state, the SPS / DrMOS chip is disconnected from other connected devices, i.e., it enters standby mode.

[0085] Referring to Table 3, which shows the correspondence between SPS / DrMOS mode, SYNC pin state, and quiescent current on the VCC pin, the quiescent current on the VCC pin refers to the current consumed by the SPS / DrMOS device when there is no signal input, i.e., the current consumed by the device without external influence.

[0086]

[0087] Table 3

[0088] As shown in Table 3, when the SYNC pin is at a logic high level, the VCC pin has a quiescent current of approximately 4mA, and a power consumption of 3.3V * 4mA = 13.2mW. When the SYNC pin is in an intermediate state, the VCC pin has a quiescent current of approximately 30μA, and a power consumption of only 3.3V * 30μA = 99μW, which is much lower than the power consumption when the SYNC pin is at a logic high level.

[0089] When the downstream load of the VRM (such as the GPU) is working, the SYNC pin in the SPS / DrMOS chip is at a logic high level. A direct connection between the SYNC pin and the VCC pin can meet this requirement. When the SYNC pin is at a logic high level, the SPS / DrMOS chip implements the functions of SPS / DrMOS mentioned earlier.

[0090] However, when the downstream load of the VRM (such as the GPU) is not operating, the direct connection between the SYNC and VCC pins introduces an additional power consumption of 3.3V * 4mA = 13.2mW on the VCC pin. If the VRM in the electronic device is a single-phase VRM, there is approximately 13.2mW of additional power consumption; if the VRM in the electronic device is a multi-phase VRM, there is approximately 13.2mW * number of phases of additional power consumption. If multiple VRMs are used in the electronic device, the above additional power consumption will increase further.

[0091] The aforementioned additional power consumption not only exists in VRMs that use SPS / DrMOS chips as SPS / DrMOS, but is also common in VRMs with the following characteristics: SPS / DrMOS includes a SYNC pin and a VCC pin, there is a large static current on the VCC pin when the SYNC pin is at a logic high level, and the SYNC pin continuously receives a logic high level.

[0092] To address the aforementioned issues, this application provides a power consumption optimization scheme. This scheme improves the external connection relationship of the SYNC pin of the SPS / DrMOS in the VRM to achieve the following objectives: when the downstream load of the VRM is working, a logic high level is input to the SYNC pin to enable the SPS / DrMOS to operate normally; when the downstream load of the VRM is not working, the SYNC pin is set to an intermediate state to enable the SPS / DrMOS to enter standby mode, thereby reducing the static current on the VCC pin and reducing the additional power consumption on the VCC pin.

[0093] The optimization scheme provided in this application can be used to improve the external connection relationship of the SYNC pin in a single-phase VRM, and can also be used to improve the external connection relationship of multiple SYNC pins in a multi-phase VRM.

[0094] The solution provided in this application can be applied to VRMs that have the aforementioned problems and where the VCC pin has a smaller quiescent current when the SPS / DrMOS's SYNC pin is in an intermediate state compared to when it is at a logic high level. For example, it can be applied to VRMs that use a PWM control chip as the PWM controller and an SPS / DrMOS chip as the VRM for an SPS / DrMOS. Taking this example, when the downstream load of the VRM is not operating, the power consumption on the VCC pin of an SPS / DrMOS is only 3.3V * 30μA = 99μW, which is significantly lower than the 3.3V * 4mA = 13.2mW power consumption on the VCC pin of an SPS / DrMOS in the aforementioned problems, greatly reducing the additional power consumption of a single SPS / DrMOS. When multi-phase VRMs or multiple VRMs are used in the electronic device, the overall additional power consumption will be further reduced.

[0095] Improved VRM

[0096] The improvements to the VRM provided in this application mainly involve the following three pins: the EN pin of the PWM controller, the SYNC pin of the SPS / DrMOS, and the VCC pin. For simplicity, the EN pin mentioned below refers to the EN pin of the PWM controller, the SYNC pin mentioned below refers to the SYNC pin of the SPS / DrMOS, and the VCC pin mentioned below refers to the VCC pin of the SPS / DrMOS.

[0097] (1) The first improved VRM

[0098] refer to Figure 4 , Figure 4 This illustration shows an improved external connection method for the SYNC pin in a VRM provided by an embodiment of this application.

[0099] like Figure 4 As shown, two resistors R1 and R2, and a unidirectional conducting device D1 are added around the PWM controller and SPS / DrMOS. That is, resistors R1, R2, and D1 are peripheral circuitry of the PWM controller and SPS / DrMOS, and this peripheral circuitry is not integrated into the same chip as the PWM controller and SPS / DrMOS. The first terminal of R1 is connected to the VCC pin, and the second terminal of R1 is connected to the SYNC pin. The first terminal of R2 is connected to the SYNC pin, and the second terminal of R2 is grounded. The first terminal of D1 is connected to the EN pin of the PWM controller, and the second terminal of D2 is connected to the SYNC pin. When the voltage at the first terminal of D1 is greater than the voltage at the second terminal, and the difference reaches the forward voltage drop of D1, D1 conducts unidirectionally from the first terminal to the second terminal. D1 can be a unidirectional conducting device or circuit that forms a small forward voltage drop (less than 1V), such as a diode.

[0100] Therefore, the SYNC pin is no longer directly connected to the VCC pin in the periphery of SPS / DrMOS.

[0101] When the downstream load of the VRM is working, the voltage on the SYNC pin is at a logic high level. Specifically, this is achieved through the following logic: When the downstream load of the VRM is working, the EN pin of the PWM controller is at a logic high level; R1 and R2 divide the voltage between the VCC pin and ground, and the voltage on the SYNC pin is the voltage divided by R2; the voltage difference between the first and second terminals of D1 (i.e., the voltage difference between the EN pin and the SYNC pin) is greater than the forward voltage drop of D1, therefore the first and second terminals of D1 are turned on; subsequently, the voltage on the SYNC pin is equal to the voltage on the EN pin minus the voltage divided by R2, and the voltage on the SYNC pin is at a logic high level.

[0102] For example, assuming the power supply voltage received by the VCC pin is 3.3V, and the resistance values ​​of R1 and R2 are the same, then the voltage drop across the SYNC pin is 1.65V due to the division of R2. Assuming that when the load after the VRM is working, the logic high level of the EN pin is 3.3V, and the on-state voltage drop of D1 is 0.3V, then D1 will conduct, and the voltage on the SYNC pin will be 3V after D1 conducts. If the three-state voltage of the SYNC pin is as shown in Table 2, then the voltage on the SYNC pin will be at a logic high level at this time.

[0103] When the downstream load of the VRM is not working, the voltage on the SYNC pin is at an intermediate level. This is achieved through the following logic: R1 and R2 divide the voltage between the VCC pin and the ground terminal, and the voltage on the SYNC pin is the voltage divided by R2; the EN pin of the PWM controller is at a logic low level, and the voltage difference between the first and second terminals of D1 (i.e., the voltage difference between the EN pin and the SYNC pin) is less than the forward voltage drop of D1, so the first and second terminals of D1 are not conducting; the voltage on the SYNC pin is still the voltage divided by R2, and the voltage on the SYNC pin is at an intermediate level.

[0104] For example, assuming the power supply voltage received by the VCC pin is 3.3V, and the resistance values ​​of R1 and R2 are the same, then the voltage division of R2 on the SYNC pin is 1.65V; assuming that when the load after VRM is not working, the logic low level of the EN pin is 0.3V, and the on-state voltage drop of D1 is 0.3V, then D1 is not conducting, and the voltage on the SYNC pin is still the voltage division of R2, 1.65V; if the three-state voltage of the SYNC pin is as shown in Table 2, then the voltage on the SYNC pin at this time is the intermediate state level.

[0105] The voltages on the R1, R2, and VCC pins, the logic level of the EN pin, and the on-state voltage drop of D1 provided in this application are used to satisfy the implementation logic in the above two cases.

[0106] (2) The second improved VRM

[0107] refer to Figure 5 , Figure 5 An example of an internal structure of SPS / DrMOS is shown. Figure 5 As shown, inside the SPS / DrMOS, resistor R3 is connected between the SYNC pin and the VCC pin, and resistor R4 is connected between the SYNC pin and GND.

[0108] based on Figure 5 The SPS / DrMOS shown is referenced. Figure 6 , Figure 6 This illustration shows an improved external connection method for the SYNC pin in a VRM provided by an embodiment of this application.

[0109] like Figure 6 As shown, in the PWM controller and Figure 5 A unidirectional conduction device D1 is added to the SPS / DrMOS shown. That is, D1 belongs to the peripheral circuitry of the PWM controller and the SPS / DrMOS; D1, the PWM controller, and the SPS / DrMOS are not integrated into the same chip. The first terminal of D1 is connected to the EN pin of the PWM controller, and the second terminal of D1 is connected to the SYNC pin. When the voltage at the first terminal of D1 is greater than the voltage at the second terminal, and the difference reaches the on-state voltage drop of D1, D1 conducts unidirectionally from the first terminal to the second terminal. In this way, R3 can achieve... Figure 4 The functions of R1 can be implemented by R4. Figure 4 The functionality of R2 is based on Figure 6 The structured VRM can then achieve the aforementioned based on Figure 4 For details on the logic of the VRM structure, please refer to the previous text.

[0110] In some implementations... Figure 4 R1 and Figure 6 R3 and R4 can coexist, so that the parallel resistance of R1 and R3 and R4 divide the voltage between the VCC pin and the ground terminal.

[0111] In some implementations... Figure 4 R2 and Figure 6 R3 and R4 can be present simultaneously. In this way, the parallel resistance of R3, R2 and R4 divides the voltage between the VCC pin and the ground terminal.

[0112] In some implementations... Figure 4 R1, R2 and Figure 6 R3 and R4 can coexist, so that the parallel resistance of R1 and R3, and the parallel resistance of R2 and R4, divide the voltage between the VCC pin and the ground terminal.

[0113] In the three embodiments described above, the voltage division on the SYNC pin can be altered by connecting R1 and R3 in parallel, and / or by connecting R2 and R4 in parallel. By setting R1 and / or R2 according to actual needs, the voltage on the SYNC pin can be positioned at a suitable intermediate level when the downstream load of the VRM is not operating. A suitable intermediate level can be the middle range of the SYNC pin's intermediate level range. For example, if the SYNC pin's intermediate level range is 1.3V-1.7V as shown in Table 2, a suitable intermediate level could be around 1.5V. A suitable intermediate level can improve the stability of the VRM and ensure that the objectives of this application are achieved.

[0114] In some implementations, the SPS / DrMOS may only include R3 and not R4, in which case it needs to be matched with... Figure 4 R2 is used in this configuration. Alternatively, the SPS / DrMOS may only include R4 and not R3, in which case it needs to be matched with... Figure 4 R1 is used in the context.

[0115] (3) The third improved VRM

[0116] refer to Figure 7 , Figure 7 This application illustrates an improved VRM's peripheral connection method for the SYNC pin, as provided in an embodiment of the present application. The VRM includes... Figure 5 The SPS / DrMOS shown.

[0117] like Figure 7 As shown, in the PWM controller and Figure 5 The SPS / DrMOS shown has a reserved position L for a unidirectional conduction device D1 between the EN and SYNC pins. D1 Set a reserved position L for resistor R1 between the VCC and SYNC pins. R1 L D1 When no integrated device is present, the EN and SYNC pins are disconnected; L R1 When no device is integrated, the VCC and SYNC pins are externally disconnected. That is, the reserved position L... D1 Reserved position L R1 The peripheral circuitry located between the PWM controller and the SPS / DrMOS is not integrated into the same chip as the PWM controller and the SPS / DrMOS.

[0118] If in L D1 Set D1, L R1If R1 is not set, the EN pin and SYNC pin are connected through D1, and the VCC pin and SYNC pin are disconnected externally. D1, R3, and R4 can be used to achieve the purpose of this application, that is, when the downstream load of VRM is working, input a logic high level to the SYNC pin so that SPS / DrMOS can work normally, and when the downstream load of VRM is not working, set the SYNC pin to an intermediate state to reduce the additional power consumption on the VCC pin.

[0119] If L D1 Without setting D1, and with R1 set to 0Ω in L2, the EN pin and SYNC pin are disconnected, while the VCC pin and SYNC pin are directly connected externally. This connection method is called... Figure 3 The VRM shown has significant additional power consumption.

[0120] visible, Figure 7 The VRM shown can be flexibly adapted to actual needs in L D1 L R1 Integrated devices are used to achieve different functions.

[0121] (4) The fourth improved VRM

[0122] During normal operation, when the EN pin of the PWM controller is at a logic high level, the VRM outputs voltage; when the EN pin of the PWM controller is at a logic low level, the VRM does not output voltage.

[0123] As described in the improved VRM above, the SYNC pin enters a high-level state when the EN pin is set to logic high, and enters an intermediate state when the EN pin is set to logic low. This indicates that the voltage drop of the SPS / DrMOS's SYNC pin and the PWM controller's EN pin occurs simultaneously. However, the voltage range for the SYNC pin to enter the intermediate state is approximately 1.3V to 1.7V, while the voltage threshold for the EN pin to enter a low state is approximately 0.4V, lower than the SYNC pin's intermediate state level. Therefore, at the instant the VRM stops outputting voltage, the SPS / DrMOS may enter standby mode first, and only after a period of time t will the PWM controller's EN pin enter a low level. During this time period t, the PWM controller's EN pin is enabled, but the SPS / DrMOS is in standby mode. The PWM controller will detect that it is already enabled, but the VRM is not outputting voltage, and will report an undervoltage fault.

[0124] To avoid the aforementioned undervoltage fault, this application also provides an improved VRM that allows the SYNC pin to power down slower than the EN pin. This ensures that the SYNC pin enters a low level before the EN pin enters an intermediate state from a high level, thereby eliminating the reporting of an output undervoltage fault at the moment of power-down.

[0125] refer to Figure 8 , Figure 8 This illustration shows an improved external connection method for the SYNC pin in a VRM provided by an embodiment of this application.

[0126] like Figure 8 As shown, it is in Figure 4 Based on the structure shown, a capacitor C1 is added around the PWM controller and SPS / DrMOS. The first end of C1 is connected to the SYNC pin, and the second end of C1 is grounded. That is, C1 is located in the peripheral circuit of the PWM controller and SPS / DrMOS, and C1, the PWM controller, and the SPS / DrMOS are not integrated into the same chip.

[0127] When the VRM's downstream load is operating, the EN pin of the PWM controller is at a logic high level, D1 is conducting, and the voltage on the SYNC pin is at a logic high level. At this time, capacitor C1 is charged, with the voltage polarity being positive at the top and negative at the bottom. Soon after, it is charged to a voltage approximately equal to the logic high level input to the EN pin. When the VRM's downstream load is not operating, the EN pin of the PWM controller is at a logic low level, D1 is cut off, and capacitor C1 gradually discharges. The voltage released by C1, combined with the voltage divided by R2, is output to the SYNC pin. Therefore, the voltage on the SYNC pin gradually decreases from a logic high level to an intermediate state. Thus, C1 can be used to adjust the timing of the SYNC pin's transition from a logic high level to an intermediate state, making the SYNC pin power down slower than the EN pin.

[0128] The fourth improved VRM can be combined with any of the aforementioned improved VRMs, meaning it can not only be used in... Figure 4 Adding C1 to the base can also be done in Figure 6 Add C1 to the base, or you can also... Figure 6 In the alternative implementation, C1 can be added, and it can also be in Figure 7 Add C1. The first terminal of C1 is connected to the SYNC pin, and the second terminal of C1 is grounded, enabling C1 to... Figure 8 The same function as in [the game / platform].

[0129] For example, refer to Figure 9 , Figure 9 This application illustrates an improved VRM's peripheral connection method for the SYNC pin, as provided in an embodiment of the present application. Figure 6 C1 was added to the SPS / DrMOS shown.

[0130] C1 can also be referred to as the first capacitor.

[0131] Similarly, the power-up process of the PWM controller also carries the same undervoltage risk. After the PWM controller powers on, the SYNC pin of the SPS / DrMOS may not go high until a certain time t has elapsed. During this time period t, the EN pin of the PWM controller is in the enabled state, but the SPS / DrMOS is still in standby mode. The PWM controller will detect that it is already enabled, but the VRM is not outputting voltage, and will report an output voltage undervoltage fault. Therefore, after the EN pin of the PWM controller goes high, the internal components of the PWM controller can delay starting operation for a certain period. This avoids the PWM controller entering the enabled state before the SPS / DrMOS during power-up, thus eliminating the immediate reporting of an output undervoltage fault upon power-up.

[0132] The improved VRM in this application includes DrMOS, L, C, and the aforementioned Figure 4 , Figures 6-8 The circuit containing the PWM controller and the peripheral structure of DrMOS can be referred to as the first circuit. The circuit including DrMOS, L, and C can be referred to as the second circuit. Here, L and C can be... Figure 1 or Figure 2 In the diagram, L can also be called the first inductor, and C can also be called the second capacitor.

[0133] Figure 1 or Figure 2 M1 can also be called the first switching transistor, and M2 can also be called the second switching transistor.

[0134] The pull-up resistor module may include R1 and / or R3 mentioned above, and the pull-down resistor module may include R2 and / or R4 mentioned above. R1 may be referred to as the first resistor, R2 as the second resistor, R3 as the third resistor, and R4 as the fourth resistor.

[0135] In the improved VRM provided in this application, the PWM controller can be integrated into one chip, and the SPS / DrMOS can be integrated into another chip, which are different. Alternatively, the PWM controller, SPS / DrMOS, and the aforementioned peripheral circuits (such as L, C, C1, R1-R4, etc.) can all be integrated into the same chip.

[0136] In summary, the improved VRM provided in this application may include: a PWM controller, one or more SPS / DrMOS transistors, and the external connections between the PWM controller and the one or more SPS / DrMOS transistors. The functions of each module in this VRM are described above, and the external connections between the PWM controller and the one or more SPS / DrMOS transistors can be found above. Figure 4 , Figures 6-8 Any kind of connection relationship.

[0137] The improved VRM provided in this application can be a single-phase VRM or a multi-phase VRM.

[0138] The improved VRM provided in this application is used to convert a larger DC voltage (such as 12V) output from the power supply in electronic devices into a stable smaller DC voltage (such as 0.5V-2V) and output it to the subsequent loads such as CPU, GPU, and ASIC. In addition, the VRM can also reduce the extra power consumption on the VCC pin of SPS / DrMOS when the subsequent load of the VRM is not working.

[0139] This application discloses a printed circuit board (PCB) that may include any of the improved VRMs described above.

[0140] This application discloses a chip system that may include any of the improved VRMs described above.

[0141] This application discloses a power supply system, which may include: a power source, any of the improved VRMs described above, and a load. The power source provides a DC input voltage to the VRM, and the VRM reduces the DC input voltage provided by the power source and outputs it to the load.

[0142] This application discloses a power supply circuit, which may include: a power supply and any of the improved VRMs described above. The power supply provides a DC input voltage to the VRM, and the VRM reduces the DC input voltage provided by the power supply before outputting it.

[0143] This application discloses a power supply circuit, which may include any of the improved VRMs described above, and a load. The VRM is used to reduce the received DC input voltage and output it to the load.

[0144] This application discloses an electronic device that may include any of the improved VRMs described above.

[0145] This application discloses an electronic device that may include the power supply system described above.

[0146] This application discloses an electronic device that may include any of the power supply circuits provided above.

[0147] In the electronic device provided in this application, when the downstream load of the VRM is working, the application processor (AP) (such as CPU) or controller (such as embedded controller (EC)) in the electronic device can input a logic high level to the EN pin of the PWM controller through GPIO; when the downstream load of the VRM is not working, the AP or controller can input a logic low level to the EN pin of the PWM controller through GPIO.

[0148] The electronic devices disclosed in this application can be mobile phones, tablets, desktop computers, desktop computers with touch-sensitive surfaces or touch panels, laptops, smart screens, wearable devices (such as smartwatches, smart bracelets, etc.), augmented reality (AR) devices, virtual reality (VR) devices, artificial intelligence (AI) devices, in-vehicle systems, smart headphones, game consoles, Internet of Things (IoT) devices, or smart home devices, etc.

[0149] refer to Figure 10 , Figure 10 This is a schematic diagram of the hardware structure of an electronic device 100 provided in an embodiment of this application. The electronic device 100 is used in the voltage regulation method provided in this embodiment.

[0150] like Figure 10 As shown, the electronic device 100 may include: a power supply 1001, a power management module 1002, a processor 1003, and a memory 1004.

[0151] The power source 1001 can be a battery, which can be charged via wired or wireless means, and can also supply power to various modules in the electronic device via the power management module 1002.

[0152] The power management module 1002 connects the power supply 1001 and the processor 1003. The power management module 1002 receives the power voltage output from the power supply 1001 and supplies power to the processor 1003 and other modules. The power management module 1002 can also be used to monitor parameters such as battery capacity, battery cycle count, and battery health status (leakage current, impedance). In some other embodiments, the power management module 1002 may also be located within the processor 1003.

[0153] Processor 1003 may include one or more processing units, such as application processor (AP), modem processor, graphics processing unit (GPU), image signal processor (ISP), controller, video codec, digital signal processor (DSP), baseband processor, and / or neural network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors.

[0154] Memory 1004 can be used to store computer executable program code, which may include instructions. Processor 1003 executes various functional applications and data processing of electronic device 100 by running the instructions stored in memory 1004. Memory 1004 may include a program storage area and a data storage area. In specific implementations, memory 1004 may include high-speed random access memory, and may also include non-volatile memory, such as one or more disk storage devices, flash memory devices, or other non-volatile solid-state storage devices.

[0155] The power management module 1002 in this application includes the improved VRM provided above. For example... Figure 10 As shown, the power management module 1002 includes a voltage management unit (VRM) that powers the GPU in the processor 1003. The high-voltage input of the VRM is connected to the high-voltage output of the power supply 1001, and the low-voltage input is connected to the low-voltage output of the power supply 1001 and grounded. The high-voltage output of the VRM is connected to the high-voltage input of the GPU, and the low-voltage output is connected to the low-voltage input of the GPU and grounded. The structure of this VRM can be referenced for example. Figure 4 , Figures 6-8 Any VRM structure.

[0156] Not limited to GPUs, other modules in electronic devices 100, such as APs and ASICs, can be configured with corresponding VRMs in the power management module 1002 to reduce the power supply voltage output by the power supply 1001 to the core voltage required by these load modules before supplying it to the corresponding load modules.

[0157] like Figure 10As shown, the electronic device 100 may further include: a wireless communication module 1005, a mobile communication module 1006, an antenna 1005A, an antenna 1006A, a sensor module 1008, a focusing motor 1009, a camera 1010, a display screen 1011, etc. The sensor module 1008 may include a gyroscope sensor 1008A, an accelerometer sensor 1008B, an ambient light sensor 1008C, an image sensor 1008D, a proximity sensor 1008E, etc. The wireless communication module 1005 may include a WLAN communication module, a Bluetooth communication module, etc. The various parts of the electronic device can transmit data via a bus.

[0158] The wireless communication function of the electronic device 100 can be implemented through antenna 1005A, antenna 1006A, mobile communication module 1006, wireless communication module 1005, modem processor, and baseband processor.

[0159] Antennas 1005A and 1006A can be used to transmit and receive electromagnetic wave signals. Each antenna in electronic device 100 can be used to cover one or more communication frequency bands. Different antennas can also be reused to improve antenna utilization.

[0160] The mobile communication module 1006 can provide solutions for wireless communication, including 2G / 3G / 4G / 5G, applied to the electronic device 100. The mobile communication module 1006 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. The mobile communication module 1006 can receive electromagnetic waves via antenna 1006A, and perform filtering, amplification, and other processing on the received electromagnetic waves before transmitting them to a modem processor for demodulation. The mobile communication module 1006 can also amplify the signal modulated by the modem processor and convert it into electromagnetic waves for radiation via antenna 1006A.

[0161] The modem processor may include a modulator and a demodulator. The modulator modulates the low-frequency baseband signal to be transmitted into a mid-to-high frequency signal. The demodulator demodulates the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After processing by the baseband processor, the low-frequency baseband signal is transmitted to the application processor. The application processor outputs a sound signal through an audio device or displays an image or video through the display screen 1011.

[0162] The wireless communication module 1005 can provide solutions for wireless communication applications on the electronic device 100, including wireless local area networks (WLAN), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), and infrared (IR). The wireless communication module 1005 can be one or more devices integrating at least one communication processing module. The wireless communication module 1005 receives electromagnetic waves via antenna 1005A, performs frequency modulation and filtering of the electromagnetic wave signal, and sends the processed signal to processor 1003. The wireless communication module 1005 can also receive signals to be transmitted from processor 1003, perform frequency modulation and amplification, and convert them into electromagnetic waves for radiation via antenna 1005A.

[0163] The gyroscope sensor 1008A can be used to determine the motion attitude of the electronic device 100. In some embodiments, the gyroscope sensor 1008A can determine the angular velocity of the electronic device 100 about three axes (i.e., the x, y, and z axes). The gyroscope sensor 1008A can be used for image stabilization. For example, when the shutter is pressed, the gyroscope sensor 1008A detects the angle of the shake of the electronic device 100, calculates the distance that the lens module needs to compensate based on the angle, and allows the lens to counteract the shake of the electronic device 100 by moving in the opposite direction, thus achieving image stabilization. The gyroscope sensor 1008A can also be used in navigation and motion-sensing game scenarios.

[0164] The accelerometer 1008B can detect the magnitude of acceleration of the electronic device 100 in various directions (generally three axes). When the electronic device 100 is stationary, it can detect the magnitude and direction of gravity. It can also be used to identify the posture of the electronic device. For example, the accelerometer 1008B can be applied to applications such as screen orientation switching and pedometers.

[0165] The ambient light sensor 1008C is used to sense the ambient light intensity. The electronic device 100 can adaptively adjust the brightness of the display screen 1011 according to the sensed ambient light intensity. The ambient light sensor 1008C can also be used to automatically adjust the white balance when taking pictures.

[0166] The 1008D image sensor, also known as a photosensitive element, utilizes the photoelectric conversion function of photoelectric devices to convert a light image on a photosensitive surface into an electrical signal proportional to the light image. Image sensors can be either charge-coupled device (CCD) sensors or complementary metal-oxide-semiconductor (CMOS) sensors.

[0167] The distance sensor 1008E can be used to measure distance. The electronic device 100 can measure distance via infrared or laser. In some shooting scenarios, the electronic device 100 can use the distance sensor 1008E to measure distance for fast focusing.

[0168] The focusing motor 1009 can be used for rapid focusing. The electronic device 100 can control the movement of the lens via the focusing motor 1009 to achieve autofocus.

[0169] Electronic device 100 can perform shooting functions through ISP, camera 1010, video codec, GPU, display 1011 and application processor.

[0170] The ISP (Image Signal Processor) is used to process data fed back from the camera 1010. For example, when taking a picture, the shutter is opened, and light is transmitted through the lens to the camera's photosensitive element. The light signal is converted into an electrical signal, and the camera's photosensitive element transmits the electrical signal to the ISP for processing, transforming it into an image visible to the naked eye. The ISP can also perform algorithmic optimization on image noise and brightness. The ISP can also optimize parameters such as exposure and color temperature of the shooting scene. In some embodiments, the ISP can be set in the camera 1010.

[0171] The camera 1010 can be used to capture still images or videos. An object is projected onto an image sensor through the lens, generating an optical image. The image sensor converts the light signal into an electrical signal, which is then passed to an ISP (Internet Service Provider) for conversion into a digital image signal. The ISP can output the digital image signal to a DSP (Digital Signal Processor) for processing. The DSP converts the digital image signal into image signals in standard formats such as RGB and YUV. In some embodiments, the electronic device 100 may include one or N processors 1010, where N is a positive integer greater than 1.

[0172] Video codecs are used to compress or decompress digital images. Electronic device 100 may support one or more image codecs. Thus, electronic device 100 can open or save images or videos in various encoding formats.

[0173] Electronic device 100 can implement display functions through a GPU, display screen 1011, and application processor. The GPU is a microprocessor for image processing, connected to the display screen 1011 and the application processor. The GPU is used to perform mathematical and geometric calculations and for graphics rendering. Processor 1003 may include one or more GPUs, which execute program instructions to generate or modify display information.

[0174] The display screen 1011 is used to display images, videos, etc. The display screen 1011 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a miniature LED, a microLED, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the electronic device 100 may include one or N display screens 1011, where N is a positive integer greater than 1.

[0175] It is understood that the structures illustrated in the embodiments of the present invention do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0176] This application also provides a voltage regulation method applied to the improved VRM provided in this application. In this method, when an operation to start the downstream load of the VRM is detected, a logic high level is input to the EN pin of the PWM controller to enable the SPS / DrMOS to operate normally; when an operation to shut down the downstream load of the VRM is detected, a logic low level is input to the EN pin of the PWM controller to enable the SPS / DrMOS to enter standby mode, thereby reducing the quiescent current on the VCC pin and reducing the additional power consumption on the VCC pin.

[0177] In conjunction with this voltage regulation method, in some implementations, after the electronic device inputs a logic high level to the EN pin of the PWM controller, it can also obtain the voltage demand of the load and adjust the duty cycle of the PWM voltage signal output by the PWM controller to the second circuit according to the load's voltage demand. For example, if the load's voltage demand increases, the duty cycle is increased; conversely, the duty cycle is decreased.

[0178] In conjunction with this voltage regulation method, in some embodiments, the electronic device can also acquire the current demand of the load and adjust the number of activated first circuits among the N first circuits of the voltage regulation circuit according to the current demand of the load. For example, if the current demand of the load increases, the number of activated first circuits is increased, and vice versa.

[0179] The various embodiments of this application can be combined arbitrarily to achieve different technical effects.

[0180] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0181] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.

[0182] The terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0183] In summary, the above description is merely an embodiment of the technical solution of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made based on the disclosure of this application should be included within the scope of protection of this application.

Claims

1. A voltage regulation circuit, characterized in that, include: A pulse width modulation (PWM) controller, comprising N first circuits, where N is a positive integer, wherein... The first circuit includes: a unidirectional conduction device and a second circuit, wherein, The PWM controller is used to output a PWM voltage signal to the second circuit, and the second circuit is used to reduce the voltage received at the high voltage input terminal of the voltage regulation circuit and output it according to the PWM voltage signal. The PWM controller includes an EN pin, which is connected to the input terminal of the enable signal of the PWM controller; the second circuit includes a DrMOS, which includes a SYNC pin and a VCC pin, the VCC pin is connected to the input terminal of the drive voltage of the DrMOS, and the SYNC pin is not connected to the input terminal of the drive voltage of the DrMOS. The first end of the pull-up resistor module is connected to the VCC pin, and the second end is connected to the SYNC pin; the first end of the pull-down resistor module is connected to the SYNC pin, and the second end is grounded; the pull-up resistor module includes a first resistor and / or a third resistor, and the pull-down resistor module includes a second resistor and / or a fourth resistor; the first ends of the first resistor and the third resistor are both connected to the VCC pin, and the second ends of both are connected to the SYNC pin; the first ends of the second resistor and the fourth resistor are both connected to the SYNC pin, and the second ends of both are grounded; the first resistor and the second resistor belong to the voltage regulation circuit and are located outside the PWM controller and the second circuit; the third resistor and the fourth resistor belong to the DrMOS; The first end of the unidirectional conduction device is connected to the EN pin of the PWM controller, and the second end is connected to the SYNC pin.

2. The voltage regulation circuit according to claim 1, characterized in that, The static current on the VCC pin when the SYNC pin is at an intermediate level is less than the static current on the VCC pin when the SYNC pin is at a logic high level. When the EN pin of the PWM controller receives a logic high level, the unidirectional conduction device is turned on from the first end to the second end, and the SYNC pin receives a high level. When the EN pin of the PWM controller receives a logic low level, the unidirectional conduction device is cut off from the first end to the second end, and the SYNC pin receives an intermediate state level.

3. The voltage regulation circuit according to claim 1, characterized in that, The voltage regulation circuit further includes: a first capacitor, the first end of which is connected to the SYNC pin, and the second end of which is grounded.

4. The voltage regulation circuit according to claim 3, characterized in that, The first capacitor is located outside the PWM controller and the second circuit.

5. The voltage regulation circuit according to claim 1, characterized in that, The unidirectional conduction device is a diode, with the anode of the diode connected to the EN pin of the PWM controller and the cathode of the diode connected to the SYNC pin.

6. The voltage regulation circuit according to claim 1, characterized in that, The DrMOS includes: a driver, a first switch, and a second switch, wherein... For the first switching transistor, the drain is connected to the high-voltage input terminal of the voltage regulation circuit, the gate is connected to the first output terminal of the driver, and the source is connected to the output terminal of the DrMOS. For the second switching transistor, the drain is connected to the output terminal of the DrMOS, the gate is connected to the second output terminal of the driver, and the source is grounded; The input terminal of the driver is connected to the output terminal of the PWM controller.

7. The voltage regulation circuit according to claim 6, characterized in that, When the PWM voltage signal is in the positive half-cycle, the first output terminal of the driver outputs a first drive signal, the first switch is turned on, and the second switch is turned off. When the PWM voltage signal is in the negative half-cycle, the second output terminal of the driver outputs a second drive signal, the first switch is turned off, and the second switch is turned on.

8. The voltage regulation circuit according to claim 6, characterized in that, The second circuit also includes: a first inductor and a second capacitor. The first end of the first inductor is connected to the output terminal of the DrMOS, the second end of the first inductor and the first end of the second capacitor are both connected to the high voltage output terminal of the voltage regulation circuit, and the second end of the second capacitor is grounded.

9. The voltage regulation circuit according to any one of claims 1-8, characterized in that, The high-voltage input terminal of the voltage regulation circuit is connected to the high-voltage output terminal of the power supply.

10. The voltage regulation circuit according to any one of claims 1-8, characterized in that, The high-voltage output terminal of the voltage regulation circuit is connected to the high-voltage input terminal of the load.

11. The voltage regulation circuit according to claim 10, characterized in that, The current output from the high-voltage output terminal of the voltage regulation circuit to the load is the sum of the output currents of the first circuits that are activated among the N first circuits.

12. The voltage regulation circuit according to any one of claims 1-8, characterized in that, The voltage regulation circuit is connected to a load, which includes any one of the following: CPU, GPU, or ASIC.

13. The voltage regulation circuit according to any one of claims 1-8, characterized in that, The enable signal input of the PWM controller is a GPIO interface.

14. The voltage regulation circuit according to any one of claims 1-8, characterized in that, The PWM controller is integrated in a first chip, and the DrMOS is integrated in a second chip. The first chip and the second chip are different.

15. An electronic device, characterized in that, The electronic device includes a voltage regulation circuit as described in any one of claims 1-14.

16. A chip, characterized in that, The chip includes a voltage regulation circuit as described in any one of claims 1-13.

17. A voltage regulation method, characterized in that, The method is applied to an electronic device, the electronic device including the voltage regulation circuit of claim 12, the electronic device including a load connected to the voltage regulation circuit, the method comprising: The electronic device detects the operation of activating the load; The electronic device inputs a logic high level to the EN pin of the PWM controller; The electronic device detects the operation of shutting down the load; The electronic device inputs a logic low level to the EN pin of the PWM controller.

18. The method according to claim 17, characterized in that, The electronic device inputs a logic high level or a logic low level to the EN pin of the PWM controller through the GPIO interface.

19. The method according to claim 17, characterized in that, After the electronic device inputs a logic high level to the EN pin of the PWM controller, the method further includes: The electronic device obtains the voltage requirement of the load; The electronic device adjusts the duty cycle of the PWM voltage signal output by the PWM controller to the second circuit according to the voltage requirements of the load.

20. The method according to any one of claims 17-19, characterized in that, The method further includes: The electronic device obtains the current requirement of the load; The electronic device adjusts the number of activated first circuits among the N first circuits of the voltage regulation circuit according to the current demand of the load.

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