Methods, apparatus, equipment, storage media, and program products for processing queue commands.

Abstract

This application relates to a method, apparatus, device, storage medium, and program product for processing queue commands. The method includes: acquiring type information and / or configuration information of a submission queue (SQ) command to be transmitted; generating a queue entry corresponding to the SQ command in a circular array structure of the submission queue corresponding to the SQ command based on the SQ command type information and / or SQ command configuration information, and refreshing the pointer of the queue entry; generating doorbell information for the SQ command based on the pointer of the queue entry; sending the doorbell information of the SQ command to a controller in a data processor, so that the controller retrieves the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command based on the doorbell information and executes the SQ command based on the queue entry; and, upon receiving an interrupt information, retrieving the queue entry corresponding to a completion queue (CQ) command. This method can improve the simulation verification speed of NVMe drivers.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a method, apparatus, device, storage medium, and program product for processing queue commands. Background Technology

[0002] With the rapid development of the cloud computing industry, the demands on hard drive performance are increasing. The Non-volatile Memory Express (NVMe) protocol defines the hardware interface and transmission protocol. Because the advent of the NVMe protocol has greatly improved hard drive performance, data processing units (DPUs) widely support the NVMe protocol.

[0003] In related technologies, when simulating the NVMe driver, the simulation verification platform mainly simulates the NVMe driver and the behavior of the host device side, generating various input / output (I / O) requests. NVMe usually uses a queue to implement the transmission of I / O requests.

[0004] However, since the DPU supports thousands of queue pairs (QPs), the number of QPs corresponding to various scenarios is huge when simulating and verifying NVMe drivers. Currently, it is not possible to effectively manage multiple QPs, which reduces the simulation and verification speed of NVMe drivers. Summary of the Invention

[0005] Therefore, it is necessary to provide a method, apparatus, device, storage medium, and program product for processing queue commands that can improve the simulation verification speed of NVMe drivers, in order to address the above-mentioned technical problems.

[0006] Firstly, this application provides a method for processing queue commands. The method includes:

[0007] Obtain the type information of the SQ command to be transmitted and / or the configuration information of the SQ command;

[0008] Based on the type information and / or configuration information of the SQ command, generate a queue entry corresponding to the SQ command in the circular array structure of the submission queue corresponding to the SQ command, and refresh the pointer of the queue entry;

[0009] Based on the pointers to the queue entries, generate the doorbell information for the SQ command;

[0010] The doorbell information of the SQ command is sent to the controller so that the controller can obtain the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command based on the doorbell information of the SQ command and execute the SQ command according to the queue entry corresponding to the SQ command.

[0011] Upon receiving the interruption information, the queue entry corresponding to the CQ command in the completion queue is obtained. The queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command.

[0012] In one embodiment, after obtaining the queue entry corresponding to the completed queue CQ command, the method further includes...

[0013] Based on the queue entry corresponding to the CQ command, release the resources of the submission queue corresponding to the SQ command.

[0014] In one embodiment, releasing the resources of the submission queue corresponding to the SQ command based on the queue entry corresponding to the CQ command includes:

[0015] The submission queue corresponding to the SQ command is determined based on the submission queue identifier in the queue entry corresponding to the CQ command.

[0016] The queue entry corresponding to the SQ command is determined based on the head pointer information in the submission queue corresponding to the SQ command and the queue entry corresponding to the CQ command.

[0017] Based on the information added to the queue entry corresponding to the SQ command, release the resources of the submission queue corresponding to the SQ command.

[0018] In one embodiment, the resources of the submission queue include at least one of the following: cache space, a message list of memory descriptors, and a queue entry corresponding to the SQ command.

[0019] In one embodiment, generating a queue entry corresponding to the SQ command in a circular array structure of the submission queue corresponding to the SQ command based on the type information and / or configuration information of the SQ command includes:

[0020] If the type information of the SQ command indicates that the SQ command is a management command, then the control information corresponding to the SQ command is added to the first initial queue entry to generate the queue entry corresponding to the SQ command. The first initial queue entry is located in the space of the circular array structure of the first submission queue corresponding to the management command.

[0021] In one embodiment, generating a queue entry corresponding to the SQ command in a circular array structure of the submission queue corresponding to the SQ command based on the type information and / or configuration information of the SQ command includes:

[0022] If the type information of the SQ command indicates that the SQ command is an input / output command, then at least one memory descriptor structure corresponding to the SQ command is generated according to the configuration information of the SQ command.

[0023] The at least one memory descriptor structure is filled into the cache space of the second submission queue corresponding to the SQ command, where the second submission queue is the submission queue corresponding to the input / output command.

[0024] Based on the number of memory descriptor structures generated, order information is added to the message list space of the memory descriptors. The order information is used to characterize the order of memory addresses of each memory descriptor structure in the cache space of the second submission queue.

[0025] The memory addresses of each memory descriptor structure in the cache space of the second submission queue and / or the memory addresses of the message list space of the memory descriptor are added to the second initial queue entry to generate the queue entry corresponding to the SQ command. The second initial queue entry is located in the space of the circular array structure of the second submission queue.

[0026] In one embodiment, the step of obtaining the queue entry corresponding to the completion queue CQ command after receiving the interrupt information includes:

[0027] Upon receiving the interruption information, the identifier information of the queue entry corresponding to the CQ command is determined by querying the local index;

[0028] Based on the identifier information of the queue entry corresponding to the CQ command, obtain the queue entry corresponding to the CQ command.

[0029] In one embodiment, after obtaining the type information and configuration information of the submission queue SQ command to be transmitted, the method further includes:

[0030] Obtain the configuration information of the non-volatile memory NVMe queue, which includes the configuration information of the data processor (DPU) and the queue configuration information of each queue;

[0031] Based on the configuration information of the DPU, a memory address range is allocated to each queue in the NVMe queue;

[0032] The memory address range of the internal resources in each queue is determined based on the memory address range allocated to each queue, the queue configuration information of each queue, and the type information of each queue.

[0033] In one embodiment, the internal resources include at least one of the following: doorbell information, queue entries, a message list of a memory descriptor, cache space, and interrupt information.

[0034] In one embodiment, after obtaining the queue entry corresponding to the completed queue CQ command, the method further includes:

[0035] Perform a validity check on the queue entry corresponding to the CQ command and determine the validity check result.

[0036] Secondly, this application also provides a processing apparatus for queue commands. The apparatus includes:

[0037] The acquisition module is used to acquire the type information of the submission queue SQ command to be transmitted and / or the configuration information of the SQ command;

[0038] The processing module is configured to generate a queue entry corresponding to the SQ command in a circular array structure of the submission queue corresponding to the SQ command based on the type information and / or configuration information of the SQ command, and refresh the pointer of the queue entry; and generate the doorbell information of the SQ command based on the pointer of the queue entry.

[0039] The sending module is used to send the doorbell information of the SQ command to the controller in the data processor, so that the controller can obtain the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command according to the doorbell information of the SQ command and execute the SQ command according to the queue entry corresponding to the SQ command.

[0040] The receiving module is used to obtain the queue entry corresponding to the completion queue CQ command after receiving the interrupt information. The queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command.

[0041] In one embodiment, the processing module is further configured to release the resources of the submission queue corresponding to the SQ command based on the queue entry corresponding to the CQ command.

[0042] In one embodiment, the processing module is specifically configured to: determine the submission queue corresponding to the SQ command based on the submission queue identifier in the queue entry corresponding to the CQ command; determine the queue entry corresponding to the SQ command based on the submission queue corresponding to the SQ command and the head pointer information in the queue entry corresponding to the CQ command; and release the resources of the submission queue corresponding to the SQ command based on the information added to the queue entry corresponding to the SQ command.

[0043] In one embodiment, the resources of the submission queue include at least one of the following: cache space, a message list of memory descriptors, and a queue entry corresponding to the SQ command.

[0044] In one embodiment, the processing module is specifically configured to add the control information corresponding to the SQ command to a first initial queue entry if the type information of the SQ command indicates that the SQ command is a management command, thereby generating a queue entry corresponding to the SQ command. The first initial queue entry is located in the space of a circular array structure of the first submission queue corresponding to the management command.

[0045] In one embodiment, the processing module is specifically configured to: if the type information of the SQ command indicates that the SQ command is an input / output command, generate at least one memory descriptor structure corresponding to the SQ command according to the configuration information of the SQ command; fill the at least one memory descriptor structure into the cache space of the second submission queue corresponding to the SQ command, the second submission queue being the submission queue corresponding to the input / output command; add order information to the message list space of the memory descriptors according to the number of memory descriptor structures generated, the order information being used to characterize the order of the memory addresses of each memory descriptor structure in the cache space of the second submission queue; add the memory addresses of each memory descriptor structure in the cache space of the second submission queue and / or the memory addresses of the message list space of the memory descriptors to a second initial queue entry, generating a queue entry corresponding to the SQ command, the second initial queue entry being located in the space of the circular array structure of the second submission queue.

[0046] In one embodiment, the receiving module is specifically configured to, after receiving the interrupt information, determine the identification information of the queue entry corresponding to the CQ command by querying the local index; and obtain the queue entry corresponding to the CQ command based on the identification information of the queue entry corresponding to the CQ command.

[0047] In one embodiment, the queue command processing device further includes:

[0048] The configuration module is used to obtain the configuration information of the non-volatile memory NVMe queue, which includes the configuration information of the data processor (DPU) and the intra-queue configuration information of each queue; according to the configuration information of the DPU, a memory address range is allocated to each queue in the NVMe queue; according to the memory address range allocated to each queue, the intra-queue configuration information of each queue, and the type information of each queue, the memory address range of the internal resources in each queue is determined.

[0049] In one embodiment, the internal resources include at least one of the following: doorbell information, queue entries, a message list of a memory descriptor, cache space, and interrupt information.

[0050] In one embodiment, the processing module is further configured to perform a validity check on the queue entry corresponding to the CQ command and determine the validity check result.

[0051] Thirdly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the queue command processing method described in the first aspect.

[0052] Fourthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, the computer program being executed by a processor using the queue command processing method described in the first aspect.

[0053] Fifthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the queue command processing method described in the first aspect.

[0054] The aforementioned queue command processing method, apparatus, device, storage medium, and program product first obtain the type information and / or configuration information of the submission queue SQ command to be transmitted. Second, based on the SQ command type information and / or SQ command configuration information, a queue entry corresponding to the SQ command is generated in the circular array structure of the submission queue corresponding to the SQ command, and the pointer of the queue entry is refreshed. Third, based on the queue entry pointer, doorbell information for the SQ command is generated and sent to the controller in the data processor, so that the controller, based on the doorbell information, retrieves the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command and executes the SQ command according to the queue entry. Finally, upon receiving an interrupt information, the queue entry corresponding to the completion queue CQ command is obtained, and the queue entry corresponding to the CQ command contains the completion status information of the SQ command. This method generates queue entries corresponding to SQ commands based on their type and / or configuration information, and generates doorbell information for SQ commands based on pointers to these queue entries. This allows the controller to obtain the queue entries corresponding to SQ commands based on the doorbell information and generate queue entries corresponding to CQ commands. This enables the stimulation of QPs composed of SQ and CQ commands in different scenarios, effectively managing queue resources for I / O data corresponding to QPs and improving the simulation verification speed of NVMe drivers. Attached Figure Description

[0055] Figure 1 This is a schematic diagram of a DPU implementing an NVMe controller in related technologies;

[0056] Figure 2 This is a schematic diagram of an SQ and CQ in related technologies;

[0057] Figure 3 This is a schematic diagram of another type of SQ and CQ in related technologies;

[0058] Figure 4 This application provides an application environment for a queue command processing method according to an embodiment of this application.

[0059] Figure 5 A flowchart illustrating a queue command processing method provided in an embodiment of this application;

[0060] Figure 6 A schematic diagram illustrating the generation of a control request by an Admin SQ, provided as an embodiment of this application;

[0061] Figure 7 A schematic diagram illustrating the generation of I / O requests using an I / O SQ, provided as an embodiment of this application;

[0062] Figure 8A flowchart illustrating another queue command processing method provided in an embodiment of this application;

[0063] Figure 9 A schematic diagram illustrating the division of memory address ranges provided in an embodiment of this application;

[0064] Figure 10 A flowchart illustrating another method for processing queue commands provided in an embodiment of this application;

[0065] Figure 11 A flowchart illustrating another queue command processing method provided in this application embodiment;

[0066] Figure 12 A structural block diagram of a queue command processing device provided in an embodiment of this application;

[0067] Figure 13 This is an internal structural diagram of a computer device provided in an embodiment of this application. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0069] The NVMe protocol will be explained first below.

[0070] Currently, almost all common operating systems support the NVMe protocol. Figure 1 This is a schematic diagram illustrating the implementation of an NVMe controller using a DPU in related technologies. Figure 1 As shown, the DPU connects to both the host device and the storage device. The host device integrates the NVMe driver, the DPU has an NVMe controller, and the storage device has a Flash Translation Layer (FTL) and NAND flash memory. The DPU and host device are connected via Peripheral Component Interconnect Express (PCIe). The PCIe bus has three layers: the physical layer, the data link layer, and the processing layer, forwarding data through packets. The NVMe protocol defines the application layer above PCIe; therefore, the DPU is an end device in the application layer.

[0071] NVMe uses queues to transmit I / O requests. The Queues (QPs) that carry NVMe commands consist of a Submission Queue (SQ) and a Completion Queue (CQ). There are two types of QPs: Admin QPs and I / O QPs. Admin QPs carry admin commands, while I / O QPs carry I / O commands; I / O QPs are also called Data Queues. The host device submits NVMe commands to the NVMe controller on the DPU via the SQ, and the NVMe controller submits the completion status to the CQ.

[0072] It should be noted that SQ and CQ are usually stored in the host's Double Data Rate (DDR) synchronous dynamic random access memory. When the host issues an SQ command, it essentially fills the SQ queue with the command and then notifies the NVMe controller to retrieve the command from DDR.

[0073] The Admin QP is primarily used to store Admin commands, which are used for host device management and control I / O QPs. The I / O QPs are mainly used to transmit data commands, facilitating data transfer between the host device and the DPU. For example, Admin commands perform some solid-state drive (SSD) management operations, such as namespace management and firmware upgrades.

[0074] It should be noted that there is only one pair of Admin SQ and Admin CQ in the system, but there can be multiple pairs of I / O SQ and I / OCQ. Figure 2 and Figure 3 An example demonstrates the deployment of the host-side Admin QP and I / O QP, such as... Figure 2 As shown, the SQ and CQ of I / O are deployed in a one-to-one manner, such as... Figure 3 As shown, the SQ and CQ of I / O are deployed in a many-to-one manner.

[0075] The following describes the data interaction process between the host device and the DPU via a queue in the relevant technology. This data interaction process includes S101-S108:

[0076] S101, The host device submits a new command.

[0077] In some embodiments, when a host device issues a new command, it places it into the SQ in the host device's memory.

[0078] S102, The host device notifies the DPU controller to retrieve new commands.

[0079] In some embodiments, after the host device writes a new command to the SQ, the driver is unaware of the new command. Therefore, the host device needs to send a notification message to the controller. This process is accomplished by updating the SQ Tail Doorbell register inside the controller. The notification message could be, for example, "I have submitted a new command request; please process it as soon as possible!"

[0080] S103. The controller retrieves new commands from the SQ. After retrieving the new commands, the position of the queue head needs to be updated in the SQ Head Pointer register inside the controller. If NVMe does not specify the execution order of new commands stored in the queue, the controller can retrieve multiple new commands at once for batch processing.

[0081] S104. The controller executes the new command extracted from SQ.

[0082] It should be understood that the execution order of new commands in a queue is not fixed, which may result in earlier submitted requests being processed later. When executing a new read or write command, this process also involves data transfer with the host device's memory.

[0083] S105. The controller writes the completion status of the new command to the CQ. At this time, the controller needs to update the CQ Tail Pointer register.

[0084] S106. The controller notifies the host device to check the completion status of the new command. The controller informs the host device by sending an interrupt message. For example, the interrupt message could be something like, "I have completed executing the new command you submitted. Please check the result!"

[0085] S107. The host device checks the completion status of new commands in the CQ.

[0086] S108. The host device informs the controller that the processing is complete. At this time, the host device updates the CQ Head Doorbell register inside the controller and sends a notification message to the controller. For example, this notification message could be something like, "I have completed processing the new command execution result you sent back. Thank you very much!"

[0087] In related technologies, simulation verification platforms primarily simulate the NVMe driver and the host device's behavior when simulating NVMe drivers, generating various input / output (I / O) requests. NVMe typically uses queues to transmit I / O requests. However, because DPUs support thousands of queue pairs (QPs), the number of QPs corresponding to various scenarios during NVMe driver simulation verification is enormous. Currently, it is impossible to effectively manage multiple QPs, thus reducing the simulation verification speed of NVMe drivers.

[0088] To address the aforementioned technical problems, embodiments of this application provide a method, apparatus, device, storage medium, and program product for processing queue commands. The method generates queue entries corresponding to SQ commands based on the type information and / or configuration information of the SQ command, and generates doorbell information for the SQ command based on the pointer of the queue entry. This enables the controller to obtain the queue entry corresponding to the SQ command based on the doorbell information and generate the queue entry corresponding to the CQ command. This achieves stimulation of QPs in different scenarios, effectively manages the queue resources of I / O data corresponding to QPs, and improves the simulation verification speed of NVMe drivers.

[0089] The queue command processing method provided in this application embodiment can be applied to, for example, Figure 4 In the application environment shown, host device 202 and DPU 204 are connected via PCIe. Host device 202 obtains the type information and / or configuration information of the SQ command to be transmitted in the submission queue. Next, based on the SQ command type information and / or SQ command configuration information, host device 202 generates a queue entry corresponding to the SQ command in the circular array structure of the submission queue corresponding to the SQ command and refreshes the queue entry pointer. Then, host device 202 generates doorbell information for the SQ command based on the queue entry pointer. Finally, host device 202 sends the doorbell information of the SQ command to the controller in DPU 204. DPU 204, based on the doorbell information of the SQ command, obtains the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command and executes the SQ command according to the queue entry. Subsequently, DPU 204 generates a queue entry corresponding to the CQ command. After receiving the interrupt information, the host device 202 obtains the queue entry corresponding to the CQ command in the completion queue. The queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command.

[0090] The host device 202 can be, but is not limited to, various personal computers, network devices, laptops, smartphones, tablets, IoT devices, and portable wearable devices. Network devices can be smart network cards, etc., and IoT devices can be smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, etc. Portable wearable devices can be smartwatches, smart bracelets, head-mounted devices, etc.

[0091] In one embodiment, such as Figure 5 As shown, a method for processing queue commands is provided, which can be applied to... Figure 4 The following explanation uses the host devices as an example, including S301-S305:

[0092] S301. Obtain the type information and / or configuration information of the SQ command in the submission queue to be transmitted.

[0093] In this application, when the host device generates an SQ command, it can obtain the type information and / or configuration information of the SQ command to be transmitted.

[0094] The type information of the SQ command can be used to indicate the type of the SQ command. The types of SQ commands include management commands and input / output commands. Input / output commands can also be data commands.

[0095] In some embodiments, if the type information of the SQ command indicates that the type of the SQ command is a management command, the host device does not need to obtain the configuration information of the SQ command, and can directly generate the queue entry corresponding to the SQ command based on the type information of the SQ command.

[0096] In other embodiments, if the type information of the SQ command indicates that the type of the SQ command is an input / output command, the host device needs to further obtain the configuration information of the SQ command and generate the queue entry corresponding to the SQ command based on the type information and configuration information of the SQ command.

[0097] It should be understood that the embodiments of this application do not limit the configuration information of the SQ command. In some embodiments, the configuration information of the SQ command may include the number of I / O operations, the total packet length of each I / O operation, the chain length of the message list of the memory descriptor, the address offset, I / O data, etc.

[0098] S302. Based on the type information and / or configuration information of the SQ command, generate the queue entry corresponding to the SQ command in the circular array structure of the submission queue corresponding to the SQ command, and refresh the pointer of the queue entry.

[0099] In this application, different methods can be used to generate queue entries corresponding to different SQ commands for different types of SQ commands.

[0100] In some embodiments, if the type information of the SQ command indicates that the SQ command is a management command, then the control information corresponding to the SQ command is added to the first initial queue entry to generate the queue entry corresponding to the SQ command. The first initial queue entry is located in the space of the circular array structure of the first submission queue corresponding to the management command.

[0101] For example, Figure 6 This is a schematic diagram illustrating how an Admin SQ generates a control request, as provided in an embodiment of this application. Figure 6 As shown, the first submission queue is Admin SQ, and the circular array structure can be a ring space containing multiple initial queue entries. The first initial queue entry can be any initial queue entry in the ring space.

[0102] For example, the initial queue entries in the space of the circular array structure of the first submission queue can be submission queue entries (SQE), with each SQE corresponding to a control request.

[0103] It should be understood that the aforementioned control information is encoded to correspond to different control requests. By adding the control information to the first initial queue entry, a queue entry corresponding to the SQ command is generated, and the relevant control request can be transmitted to the DPU. After filling is complete, the SQE pointer is refreshed to generate the doorbell information for the SQ command.

[0104] In other embodiments, if the type information of the SQ command indicates that the SQ command is an input / output command, the host device can first generate at least one memory descriptor structure corresponding to the SQ command based on the configuration information of the SQ command. Next, the host device fills the cache space of the second submission queue corresponding to the SQ command with at least one memory descriptor structure. Then, the host device adds order information to the message list space of the memory descriptors based on the number of memory descriptor structures generated. Finally, the host device adds the memory addresses of each memory descriptor structure in the cache space of the second submission queue and / or the memory addresses of the memory descriptors in the message list space to the second initial queue entry, generating the queue entry corresponding to the SQ command.

[0105] For example, Figure 7 This is a schematic diagram illustrating the generation of I / O requests using an I / O SQ, as provided in an embodiment of this application. Figure 7 As shown, the second submission queue is the I / O SQ corresponding to the I / O command. Sequence information is used to characterize the order of memory addresses of each memory descriptor structure in the cache space of the second submission queue. The second initial queue entries are located in the space of the circular array structure of the second submission queue.

[0106] It should be understood that the embodiments of this application do not limit how to generate at least one memory descriptor structure corresponding to the SQ command based on the configuration information of the SQ command. In some embodiments, the host device can slice the I / O data based on the configuration information of the SQ command to generate at least one memory descriptor structure.

[0107] For example, the memory descriptor structure described above can be a Physical Region Page (PRP) structure, which can be sliced ​​to generate a single PRP, two PRPs, multiple PRPs, etc.

[0108] It should be understood that this application embodiment does not impose restrictions on how to add order information to the message list space of the memory descriptor based on the number of memory descriptor structures generated. In some embodiments, if the number of memory descriptor structures generated is less than a threshold, then it is not necessary to add order information to the message list space of the memory descriptor. If the number of memory descriptor structures generated is greater than or equal to the threshold, then order information is added to the message list space of the memory descriptor.

[0109] The thresholds mentioned above can be set according to the specific circumstances, for example, to three. That is, when there are three or more memory descriptor structures, the order information is added to the message list space of the memory descriptor. When there are fewer than three memory descriptor structures, it is not necessary to add the order information to the message list space of the memory descriptor.

[0110] Accordingly, if order information is added to the message list space of the memory descriptor, the memory addresses of each memory descriptor structure in the cache space of the second submission queue and the memory addresses of the memory descriptor's message list space can be added to the second initial queue entry to generate the queue entry corresponding to the SQ command. If no order information is added to the message list space of the memory descriptor, the memory addresses of each memory descriptor structure in the cache space of the second submission queue can be directly added to the second initial queue entry to generate the queue entry corresponding to the SQ command.

[0111] It should be noted that the processing of multiple queues is the same as that of a single queue, and this embodiment of the application will not be described in detail here.

[0112] S303. Generate doorbell information for the SQ command based on the pointer to the queue entry.

[0113] In this step, after refreshing the pointer to the queue entry, the host device can generate doorbell information for the SQ command based on the pointer to the queue entry.

[0114] It should be understood that the embodiments of this application do not limit how the doorbell information of the SQ command is generated. In some embodiments, the host device can write the index of the updated queue entry pointer into the address of the doorbell information of the SQ command to generate the doorbell information of the SQ command.

[0115] Different doorbell addresses can be used for different types of SQ commands. For example, if the SQ command is an Adimn command, the index of the updated queue entry's pointer is written to the doorbell address of the Adimn SQ. If the SQ command is an I / O command, the index of the updated queue entry's pointer is written to the doorbell address of the I / O SQ.

[0116] S304. Send the doorbell information of the SQ command to the controller in the data processor, so that the controller can obtain the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command according to the doorbell information of the SQ command, and execute the SQ command according to the queue entry corresponding to the SQ command.

[0117] In this step, the host device can send the doorbell information of the SQ command to the controller in the DPU, so that the controller can obtain the queue entry corresponding to the SQ command and execute the SQ command according to the queue entry corresponding to the SQ command.

[0118] It should be understood that the process by which the aforementioned host device can send doorbell information to the controller can be accomplished through the SQ Tail Doorbell inside the controller.

[0119] In some embodiments, after the controller retrieves the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command, it can take the information written in the queue entry corresponding to the SQ command to obtain the SQ command. Subsequently, the position of the Head in the SQ Head Pointer register inside the controller is updated.

[0120] In some embodiments, after receiving an SQ command, the controller can execute the SQ command. The execution order of the SQ commands can be determined based on the order of the queue entries corresponding to the SQ commands in the submission queue. Furthermore, when the controller executes read / write SQ commands, this process also involves data transfer with the host device's memory.

[0121] In some embodiments, after executing the SQ command, the controller can generate a queue entry corresponding to the CQ command, write the completion status of the SQ command into the CQ, and send an interrupt message to the host device to inform the host device that the controller has completed the execution of the SQ command.

[0122] S305. After receiving the interrupt information, obtain the queue entry corresponding to the CQ command in the completion queue. The queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command.

[0123] It should be understood that the embodiments of this application do not limit how the queue entry corresponding to the completion queue CQ command is obtained. In some embodiments, the host device can determine the identification information of the queue entry corresponding to the CQ command by querying the local index after receiving the interrupt information. Subsequently, the host device obtains the queue entry corresponding to the CQ command based on the identification information of the queue entry corresponding to the CQ command.

[0124] In some embodiments, after retrieving the identification information of a queue entry, the host device can update the identification information of the queue entry. For example, if the identification information of the queue entry is CQE index, the host device can update the identification information to index+1.

[0125] In some embodiments, after obtaining the queue entry corresponding to the completed queue CQ command, the host device can also perform a validity check on the queue entry corresponding to the CQ command and determine the validity check result. It should be understood that the embodiments of this application do not limit the method of validity check. In some embodiments, the completion status information written in the queue entry corresponding to the CQ command can be checked to determine whether the completion status information conforms to the preset data content and data format requirements. If the check result indicates no error, the host device can also inform the controller that the queue entry corresponding to the CQ command has been processed.

[0126] In some embodiments, after the host device obtains the queue entry corresponding to the completion queue CQ command, it can also release the resources of the submission queue corresponding to the SQ command based on the queue entry corresponding to the CQ command.

[0127] It should be understood that the embodiments of this application do not limit how the resources of the commit queue corresponding to the SQ command are released. In some embodiments, the host device can first determine the commit queue corresponding to the SQ command based on the commit queue identifier in the queue entry corresponding to the CQ command. Subsequently, the host device can determine the queue entry corresponding to the SQ command based on the commit queue corresponding to the SQ command and the head pointer information in the queue entry corresponding to the CQ command. Finally, the host device can release the resources of the commit queue corresponding to the SQ command based on the information added to the queue entry corresponding to the SQ command.

[0128] The resources of the submission queue include at least one of the following: cache space, message list of memory descriptors, and queue entries corresponding to SQ commands.

[0129] In this application, upon receiving an interruption message, it can be determined that the transmission of the SQ command has been completed, and the resources in the submission queue can be released accordingly. When a new SQ command is generated, the resources in the submission queue may be exhausted or insufficient. In this case, the transmission of the queue command can be delayed until the resources in the submission queue are released. This method enables priority management and timely reuse of the resources in the submission queue, greatly improving verification efficiency and quality.

[0130] This application provides a method for processing queue commands. It generates queue entries corresponding to SQ commands based on SQ command type information and / or configuration information, and generates doorbell information for SQ commands based on pointers to these queue entries. This allows the controller to obtain the queue entries corresponding to SQ commands based on the doorbell information and generate queue entries corresponding to CQ commands. This enables the stimulation of QPs in different scenarios, effectively manages the queue resources of I / O data corresponding to QPs, and improves the simulation verification speed of NVMe drivers.

[0131] The following explains how to allocate memory before processing queue commands. Figure 8 This is a flowchart illustrating another method for processing queue commands provided in an embodiment of this application. Figure 8 As shown, the processing method for this queue command includes S401-S408:

[0132] S401. Obtain the configuration information of the non-volatile memory NVMe queue. The configuration information includes the configuration information of the data processor (DPU) and the queue configuration information of each queue.

[0133] The configuration information of the aforementioned DPU includes: the number of NVMe devices supported, the number of queues supported in each NVMe device, and the correspondence between SQ and CQ for input and output types.

[0134] The configuration information within each queue includes: the NVMe stride field (nvme_stride), the packet size field (page_size), and the queue size.

[0135] S402. Based on the DPU configuration information, allocate a memory address range for each queue in the NVMe queue.

[0136] In some embodiments, the host device can determine the memory space required for each queue based on DPU configuration information such as the number of NVMe devices, the number of queues supported by each NVMe device, and the correspondence between SQ and CQ for input / output types. Subsequently, based on the memory space required for each queue, the memory is partitioned, and a memory address range is allocated for each queue in the NVMe queue.

[0137] S403. Determine the memory address range of the internal resources in each queue based on the memory address range allocated to each queue, the queue configuration information of each queue, and the type information of each queue.

[0138] Internal resources include at least one of the following: doorbell information, queue entries, message list of memory descriptors, cache space, and interrupt information.

[0139] Example, Figure 9 This is a schematic diagram illustrating the division of memory address ranges provided in an embodiment of this application, as shown below. Figure 9 As shown, the total address space is the memory address space represented by m + n + 64 bits. The high n bits are used to distinguish different NVMe devices, and the next high m bits are used to distinguish the queues supported by the same NVMe device. Correspondingly, m is determined by the maximum number of NVMe devices supported by the DPU, and n is determined by the number of queues supported by each NVMe device. Therefore, the memory address range of each queue is uniquely allocated during initialization. The lowest 64 bits are used to distinguish the memory addresses needed by each queue. Different queue types can be allocated different memory address ranges for internal resources within their own memory address space.

[0140] For example, the Admin SQ includes the memory address range of the doorbell and the memory address range of the SQE. The AdminCQ includes the memory address range of the doorbell and the memory address range of the CQE. The I / O SQ includes the memory address range of the doorbell, the memory address range of the SQE, the memory address range of the address space of the message list of the memory descriptor, and the memory address range of the cache space. The I / O CQ includes the memory address range of the doorbell, the memory address range of the CQE, and the memory address range of the interrupt information.

[0141] For example, the memory address range of the doorbell is determined by adding the offset of the queue identifier to a power of the configured value of the NVMe stride field. The memory address ranges of the SQE and CQE are determined by the queue size. The memory address range of the cache space is determined by the protocol and the maximum supported packet length.

[0142] It should be understood that the aforementioned cache space may include a first-level cache space and a second-level cache space. The first-level cache space is a buffer located in the memory space of the host device; the second-level cache space is a buffer in the memory space of the DPU.

[0143] In some embodiments, after allocating the memory address range of each queue in the NVMe queue and the memory address range of the internal resources in each queue, the allocated memory address range can be recorded and sent to the DPU.

[0144] It should be noted that the allocated memory address range will not change unless there is a deletion or reconstruction of the NVMe device or queue.

[0145] S404. Obtain the type information and / or configuration information of the SQ command in the submission queue to be transmitted.

[0146] S405. Based on the type information and / or configuration information of the SQ command, generate the queue entry corresponding to the SQ command in the circular array structure of the submission queue corresponding to the SQ command, and refresh the pointer of the queue entry.

[0147] S406. Generate doorbell information for the SQ command based on the pointer to the queue entry.

[0148] S407. Send the doorbell information of the SQ command to the controller in the data processor, so that the controller can obtain the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command according to the doorbell information of the SQ command, and execute the SQ command according to the queue entry corresponding to the SQ command.

[0149] S408. After receiving the interrupt information, obtain the queue entry corresponding to the CQ command in the completion queue. The queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command.

[0150] In this application, by allocating the memory address range in advance, overlapping memory spaces are avoided, which facilitates use and maintenance and greatly improves verification efficiency and quality.

[0151] The following explains how resources in the submission queue are reclaimed. Figure 10 This is a flowchart illustrating another method for processing queue commands provided in an embodiment of this application. Figure 10 As shown, the processing method for this queue command includes S501-S508:

[0152] S501. Obtain the type information and / or configuration information of the SQ command in the submission queue to be transmitted.

[0153] S502. Based on the type information and / or configuration information of the SQ command, generate the queue entry corresponding to the SQ command in the circular array structure of the submission queue corresponding to the SQ command, and refresh the pointer of the queue entry.

[0154] S503. Generate doorbell information for the SQ command based on the pointer to the queue entry.

[0155] S504. Send the doorbell information of the SQ command to the controller in the data processor, so that the controller can obtain the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command according to the doorbell information of the SQ command, and execute the SQ command according to the queue entry corresponding to the SQ command.

[0156] S505. After receiving the interrupt information, obtain the queue entry corresponding to the CQ command in the completion queue. The queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command.

[0157] S506. Determine the submission queue corresponding to the SQ command based on the submission queue identifier in the queue entry corresponding to the CQ command.

[0158] In some embodiments, the commit queue identifier can be the commit queue identifier (SQ identifier) ​​field in the CQE. The host device extracts the commit queue identifier field (SQ identifier) ​​from the CQE, and then matches the SQ identifier field to determine the SQ corresponding to the SQ command.

[0159] S507. Determine the queue entry corresponding to the SQ command based on the head pointer information in the submission queue corresponding to the SQ command and the queue entry corresponding to the CQ command.

[0160] In some embodiments, the head pointer information can be the head pointer field in the CQE. Through the head pointer field, the host device can further determine the identifier of the relevant SQE in the determined SQ.

[0161] S508. Based on the information added to the queue entry corresponding to the SQ command, release the resources of the submission queue corresponding to the SQ command.

[0162] It should be understood that this application embodiment does not provide details on how to release the resources of the commit queue corresponding to the SQ command. In some embodiments, the information added to the queue entry corresponding to the SQ command can be used to determine the address of the relevant commit queue resources. Accordingly, the relevant commit queue resources can be released through the information added to the queue entry.

[0163] For example, based on the information added to the SQE, the cache space resources and message list resources of the memory descriptor used by it can be released, or the SQE can be released to the SQE resource pool. In addition, the host device can also release circular array structure resources.

[0164] In some embodiments, when transmitting the next SQ command, it can be checked whether there are sufficient SQEs available in the SQE resource pool. If there are not enough, the process waits; if there are enough, relevant information is populated into the SQEs, including the memory address, data length, and other information.

[0165] In this application, upon receiving an interruption message, it can be determined that the transmission of the SQ command has been completed, and the resources in the submission queue can be released accordingly. When a new SQ command is generated, the resources in the submission queue may be exhausted or insufficient. In this case, the transmission of the queue command can be delayed until the resources in the submission queue are released. This method enables priority management and timely reuse of the resources in the submission queue, greatly improving verification efficiency and quality.

[0166] Figure 11 This is a flowchart illustrating another method for processing queue commands provided in an embodiment of this application. Figure 11 As shown, the processing method for this queue command includes S501-S508:

[0167] S601. Obtain the configuration information of the non-volatile memory NVMe queue. The configuration information includes the configuration information of the data processor (DPU) and the queue configuration information of each queue.

[0168] S602. Based on the DPU's configuration information, allocate a memory address range for each queue in the NVMe queue;

[0169] S603. Determine the memory address range of the internal resources in each queue based on the memory address range allocated to each queue, the queue configuration information of each queue, and the type information of each queue.

[0170] S604. Obtain the type information and / or configuration information of the SQ command in the submission queue to be transmitted.

[0171] S605. Based on the type information and / or configuration information of the SQ command, generate the queue entry corresponding to the SQ command in the circular array structure of the submission queue corresponding to the SQ command, and refresh the pointer of the queue entry.

[0172] S606. Generate doorbell information for the SQ command based on the pointer to the queue entry.

[0173] S607. Send the doorbell information of the SQ command to the controller in the data processor, so that the controller can obtain the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command according to the doorbell information of the SQ command, and execute the SQ command according to the queue entry corresponding to the SQ command.

[0174] S608. After receiving the interrupt information, obtain the queue entry corresponding to the CQ command in the completion queue. The queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command.

[0175] S609. Based on the queue entry corresponding to the CQ command, release the resources of the submission queue corresponding to the SQ command.

[0176] S610. Determine if any SQ commands have not been completed.

[0177] If yes, then execute S604; otherwise, execute S612.

[0178] S611. Determine the completion of queue command processing.

[0179] The queue command processing method provided in this application first obtains the type information and / or configuration information of the submission queue SQ command to be transmitted. Second, based on the SQ command type information and / or SQ command configuration information, a queue entry corresponding to the SQ command is generated in the circular array structure of the submission queue corresponding to the SQ command, and the pointer of the queue entry is refreshed. Third, based on the pointer of the queue entry, doorbell information of the SQ command is generated and sent to the controller in the data processor, so that the controller, based on the doorbell information of the SQ command, obtains the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command and executes the SQ command according to the queue entry corresponding to the SQ command. Finally, after receiving interrupt information, the queue entry corresponding to the completion queue CQ command is obtained, and the queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command. In this way, queue entries corresponding to SQ commands are generated based on the type information and / or configuration information of SQ commands. Doorbell information for SQ commands is generated based on the pointers of the queue entries. This enables the controller to obtain the queue entries corresponding to SQ commands based on the doorbell information and generate queue entries corresponding to CQ commands. This achieves the stimulation of QP in different scenarios, effectively manages the queue resources of I / O data corresponding to QP, and improves the simulation verification speed of NVMe drivers.

[0180] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0181] Based on the same inventive concept, this application also provides a queue command processing apparatus for implementing the queue command processing method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations of one or more queue command processing apparatus embodiments provided below can be found in the limitations of the queue command processing method described above, and will not be repeated here.

[0182] In one embodiment, such as Figure 12 As shown, a queue command processing device 700 is provided, including: an acquisition module 701, a processing module 702, a sending module 703, a receiving module 704, and a configuration module 705, wherein:

[0183] The acquisition module 701 is used to acquire the type information and / or configuration information of the SQ command to be transmitted in the submission queue.

[0184] The processing module 702 is used to generate a queue entry corresponding to the SQ command in the circular array structure of the submission queue corresponding to the SQ command according to the type information and / or configuration information of the SQ command, and refresh the pointer of the queue entry; and generate the doorbell information of the SQ command according to the pointer of the queue entry.

[0185] The sending module 703 is used to send the doorbell information of the SQ command to the controller in the data processor, so that the controller can obtain the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command according to the doorbell information of the SQ command and execute the SQ command according to the queue entry corresponding to the SQ command.

[0186] The receiving module 704 is used to obtain the queue entry corresponding to the CQ command in the completion queue after receiving the interrupt information. The queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command.

[0187] In one embodiment, the processing module 702 is further configured to release the resources of the submission queue corresponding to the SQ command based on the queue entry corresponding to the CQ command.

[0188] In one embodiment, the processing module 702 is specifically configured to determine the submission queue corresponding to the SQ command based on the submission queue identifier in the queue entry corresponding to the CQ command; determine the queue entry corresponding to the SQ command based on the submission queue corresponding to the SQ command and the head pointer information in the queue entry corresponding to the CQ command; and release the resources of the submission queue corresponding to the SQ command based on the information added to the queue entry corresponding to the SQ command.

[0189] In one embodiment, the resources of the submission queue include at least one of the following: cache space, a message list of memory descriptors, and a queue entry corresponding to the SQ command.

[0190] In one embodiment, the processing module 702 is specifically used to add the control information corresponding to the SQ command to the first initial queue entry if the type information of the SQ command indicates that the SQ command is a management command, thereby generating the queue entry corresponding to the SQ command. The first initial queue entry is located in the space of the circular array structure of the first submission queue corresponding to the management command.

[0191] In one embodiment, the processing module 702 is specifically configured to: if the type information of the SQ command indicates that the SQ command is an input / output command, generate at least one memory descriptor structure corresponding to the SQ command according to the configuration information of the SQ command; fill the cache space of the second submission queue corresponding to the SQ command with at least one memory descriptor structure, the second submission queue being the submission queue corresponding to the input / output command; add order information to the message list space of the memory descriptors according to the number of memory descriptor structures generated, the order information being used to characterize the order of the memory addresses of each memory descriptor structure in the cache space of the second submission queue; add the memory addresses of each memory descriptor structure in the cache space of the second submission queue and / or the memory addresses of the message list space of the memory descriptors to the second initial queue entry, generating the queue entry corresponding to the SQ command, the second initial queue entry being located in the space of the circular array structure of the second submission queue.

[0192] In one embodiment, the receiving module 704 is specifically configured to, after receiving the interrupt information, determine the identification information of the queue entry corresponding to the CQ command by querying the local index; and obtain the queue entry corresponding to the CQ command based on the identification information of the queue entry corresponding to the CQ command.

[0193] In one embodiment, the queue command processing device further includes:

[0194] Configuration module 705 is used to obtain configuration information of non-volatile memory NVMe queues. The configuration information includes configuration information of data processors (DPUs) and intra-queue configuration information of each queue. Based on the configuration information of the DPUs, a memory address range is allocated to each queue in the NVMe queue. Based on the memory address range allocated to each queue, the intra-queue configuration information of each queue, and the type information of each queue, the memory address range of the internal resources in each queue is determined.

[0195] In one embodiment, the internal resources include at least one of the following: doorbell information, queue entries, a message list of a memory descriptor, cache space, and interrupt information.

[0196] In one embodiment, the processing module 702 is further configured to perform a validity check on the queue entry corresponding to the CQ command and determine the validity check result.

[0197] The modules in the aforementioned queue command processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0198] In one embodiment, a computer device is provided, which may be a host device, and its internal structure diagram may be as follows: Figure 13 As shown, the computer device includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interface is used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When executed by the processor, the computer program implements a queue command processing method.

[0199] Those skilled in the art will understand that Figure 13The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0200] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the above-described method for processing queue commands.

[0201] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the above-described method for processing queue commands.

[0202] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described method for processing queue commands.

[0203] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0204] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0205] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for processing queue commands, characterized in that, The method includes: Obtain the type information of the submission queue SQ command to be transmitted and / or the configuration information of the SQ command, wherein the SQ command is the SQ command generated by simulating the behavior of the driver and host device during simulation verification; Based on the type information and / or configuration information of the SQ command, generate a queue entry corresponding to the SQ command in the circular array structure of the submission queue corresponding to the SQ command, and refresh the pointer of the queue entry; Based on the pointer to the queue entry, generate the doorbell information for the SQ command, which includes the index of the updated queue entry pointer. The doorbell information of the SQ command is sent to the controller in the data processor so that the controller can obtain the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command based on the doorbell information of the SQ command and execute the SQ command according to the queue entry corresponding to the SQ command. After receiving the interruption information, the queue entry corresponding to the completion queue CQ command is obtained. The queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command. The step of generating a queue entry corresponding to the SQ command in a circular array structure of the submission queue corresponding to the SQ command based on the type information and / or configuration information of the SQ command includes: If the type information of the SQ command indicates that the SQ command is a management command, then the control information corresponding to the SQ command is added to the first initial queue entry to generate the queue entry corresponding to the SQ command. The first initial queue entry is located in the space of the circular array structure of the first submission queue corresponding to the management command. If the type information of the SQ command indicates that the SQ command is an input / output command, then according to the configuration information of the SQ command, at least one memory descriptor structure corresponding to the SQ command is generated; the at least one memory descriptor structure is filled into the cache space of the second submission queue corresponding to the SQ command, the second submission queue being the submission queue corresponding to the input / output command; according to the number of memory descriptor structures generated, order information is added to the message list space of the memory descriptors, the order information being used to characterize the order of the memory addresses of each memory descriptor structure in the cache space of the second submission queue; the memory addresses of each memory descriptor structure in the cache space of the second submission queue and / or the memory addresses of the message list space of the memory descriptors are added to the second initial queue entry to generate the queue entry corresponding to the SQ command, the second initial queue entry being located in the space of the circular array structure of the second submission queue.

2. The method according to claim 1, characterized in that, After obtaining the queue entry corresponding to the completed queue CQ command, the method further includes: Based on the queue entry corresponding to the CQ command, release the resources of the submission queue corresponding to the SQ command.

3. The method according to claim 2, characterized in that, The step of releasing the resources of the submission queue corresponding to the SQ command according to the queue entry corresponding to the CQ command includes: The submission queue corresponding to the SQ command is determined based on the submission queue identifier in the queue entry corresponding to the CQ command. The queue entry corresponding to the SQ command is determined based on the head pointer information in the submission queue corresponding to the SQ command and the queue entry corresponding to the CQ command. Based on the information added to the queue entry corresponding to the SQ command, release the resources of the submission queue corresponding to the SQ command.

4. The method according to claim 3, characterized in that, The resources of the submission queue include at least one of the following: cache space, a message list of memory descriptors, and the queue entry corresponding to the SQ command.

5. The method according to claim 1, characterized in that, Upon receiving the interrupt information, the step of obtaining the queue entry corresponding to the completed queue CQ command includes: Upon receiving the interruption information, the identifier information of the queue entry corresponding to the CQ command is determined by querying the local index; Based on the identifier information of the queue entry corresponding to the CQ command, obtain the queue entry corresponding to the CQ command.

6. The method according to claim 1, characterized in that, Before obtaining the type information and configuration information of the submission queue SQ command to be transmitted, the method further includes: Obtain the configuration information of the non-volatile memory NVMe queue, which includes the configuration information of the data processor (DPU) and the queue configuration information of each queue; Based on the configuration information of the DPU, a memory address range is allocated to each queue in the NVMe queue; The memory address range of the internal resources in each queue is determined based on the memory address range allocated to each queue, the queue configuration information of each queue, and the type information of each queue.

7. The method according to claim 6, characterized in that, The internal resources include at least one of the following: doorbell information, queue entries, message list of memory descriptors, cache space, and interrupt information.

8. The method according to claim 1, characterized in that, After obtaining the queue entry corresponding to the completed queue CQ command, the method further includes: Perform a validity check on the queue entry corresponding to the CQ command and determine the validity check result.

9. A processing device for queue commands, characterized in that, The device includes: The acquisition module is used to acquire the type information of the submission queue SQ command to be transmitted and / or the configuration information of the SQ command, wherein the SQ command is the SQ command generated by simulating the behavior of the driver and host device during simulation verification; The processing module is configured to generate a queue entry corresponding to the SQ command in a circular array structure of the submission queue corresponding to the SQ command based on the type information and / or configuration information of the SQ command, and refresh the pointer of the queue entry; and generate doorbell information of the SQ command based on the pointer of the queue entry, wherein the doorbell information includes the index of the updated pointer of the queue entry. The sending module is used to send the doorbell information of the SQ command to the controller in the data processor, so that the controller can obtain the queue entry corresponding to the SQ command from the circular array structure of the submission queue corresponding to the SQ command according to the doorbell information of the SQ command and execute the SQ command according to the queue entry corresponding to the SQ command. The receiving module is used to obtain the queue entry corresponding to the completion queue CQ command after receiving the interrupt information. The queue entry corresponding to the CQ command contains the completion status information corresponding to the SQ command. The processing module is specifically used to add the control information corresponding to the SQ command to the first initial queue entry if the type information of the SQ command indicates that the SQ command is a management command, thereby generating the queue entry corresponding to the SQ command. The first initial queue entry is located in the space of the circular array structure of the first submission queue corresponding to the management command. The processing module is specifically configured to: if the type information of the SQ command indicates that the SQ command is an input / output command, generate at least one memory descriptor structure corresponding to the SQ command according to the configuration information of the SQ command; fill the cache space of the second submission queue corresponding to the SQ command with at least one memory descriptor structure, the second submission queue being the submission queue corresponding to the input / output command; add order information to the message list space of the memory descriptors according to the number of memory descriptor structures generated, the order information being used to characterize the order of the memory addresses of each memory descriptor structure in the cache space of the second submission queue; add the memory addresses of each memory descriptor structure in the cache space of the second submission queue and / or the memory addresses of the message list space of the memory descriptors to the second initial queue entry, generating the queue entry corresponding to the SQ command, the second initial queue entry being located in the space of the circular array structure of the second submission queue.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

12. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

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