Trench gate transistor test structure and test method
By optimizing the test structure and electrode connection method of trench gate transistors, the problem of detecting weak points at the bottom of the gate dielectric layer was solved, enabling precise monitoring of the gate dielectric layer formation process and improving the reliability and performance of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNITED NOVA TECH - XIANFENG (SHAOXING) CORP
- Filing Date
- 2024-12-25
- Publication Date
- 2026-08-04
AI Technical Summary
Existing technologies cannot effectively monitor the formation of weak points at the bottom of the gate dielectric layer in trench gate transistors, leading to decreased device performance and increased reliability risks.
A test structure for trench gate transistors was designed. By optimizing the electrode connection method and gate trench layout, the detection area at the bottom of the gate trench was increased, and a field plate structure was introduced to adjust the electric field distribution, so as to achieve accurate testing of weak points at the bottom of the gate dielectric layer.
It can effectively detect weak points at the bottom of the gate dielectric layer, reduce device reliability risks, improve the monitoring capability of the process, and avoid the impact of weak points on device performance.
Smart Images
Figure CN119725326B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a test structure and test method for a trench gate transistor. Background Technology
[0002] Compared to planar gate transistors, trench gate transistors can significantly reduce cell size, thereby greatly increasing current density. For example, trench gate metal-oxide-semiconductor field-effect transistors (MOSFETs) offer significantly improved performance compared to planar gate MOSFETs, achieving not only higher channel mobility but also lower on-resistance, resulting in improved on-current density and conduction performance.
[0003] However, the gate trenches in trench gate transistors often have a high aspect ratio, which makes it difficult for the reactive gas source to reach the bottom of the gate trench during the gate dielectric layer formation process. This results in a weak point in the final gate dielectric layer at the bottom of the trench; the weak point is more likely to occur when the flow rate of the reactive gas source is abnormal. The presence of a weak point in the gate dielectric layer leads to a lower breakdown voltage (BV), affecting device performance.
[0004] Monitoring the manufacturing process and identifying any weak points in the gate dielectric layer is crucial for the fabrication of trench gate transistors. Summary of the Invention
[0005] In view of this, the present application provides a test structure and test method for trench gate transistors to solve at least one problem existing in the background art.
[0006] In a first aspect, embodiments of this application provide a test structure for a trench gate transistor, comprising:
[0007] Semiconductor material layer;
[0008] A gate trench extends from the upper surface of the semiconductor material layer into the interior of the semiconductor material layer;
[0009] A gate dielectric layer and a gate are located within the gate trench, wherein the gate dielectric layer covers the sidewalls and bottom wall of the gate trench, and the gate is located within the gate dielectric layer;
[0010] A body region is located outside and adjacent to the gate trench, the gate trench extending deeper than the lower interface of the body region, and the body region has a first conductivity type.
[0011] The drift region is in contact with the lower interface of the body region and the portion of the gate trench other than the portion adjacent to the body region, and the drift region has a second conductivity type;
[0012] The first electrode is electrically connected to the gate and the body region and is used to apply a low potential.
[0013] The second electrode is electrically connected to the drift region and is used to apply a high potential.
[0014] In conjunction with the first aspect of this application, in an optional embodiment, it further includes:
[0015] A first conductive plug is connected between the first electrode and the gate.
[0016] A second conductive plug is connected between the second electrode and the drift region;
[0017] A field plate structure is located on the semiconductor material layer between the first conductive plug and the second conductive plug.
[0018] In conjunction with the first aspect of this application, in an optional embodiment, the body region is formed by doping the semiconductor material layer with a first conductivity type, and the upper surface side of the semiconductor material layer further includes a first portion that is not doped into the body region, the drift region extending to the first portion; the second conductive plug is formed by forming an opening on the semiconductor material layer that exposes the first portion and filling the opening with conductive material, the second conductive plug being conductively connected to the drift region by directly contacting the first portion.
[0019] In conjunction with a first aspect of this application, in an alternative embodiment, the gate trench includes a first side and a second side opposite to each other, the body region is adjacent to the first side, and the field plate structure is located on the second side;
[0020] The field plate structure includes a field oxide layer and a field plate layer. The field oxide layer is located on the semiconductor material layer on the second side. A portion of the gate material used to form the gate fills the gate trench, and a portion extends onto the field oxide layer to form the field plate layer.
[0021] In conjunction with the first aspect of this application, in an alternative embodiment, the field oxygen layer is formed by a LOCOS process.
[0022] In conjunction with the first aspect of this application, in an optional embodiment, the gate trench includes a plurality of first gate trenches extending along a first direction and a plurality of second gate trenches extending along a second direction, the first direction intersecting the second direction, and the plurality of first gate trenches and the plurality of second gate trenches being connected by the intersection.
[0023] In conjunction with the first aspect of this application, in an alternative embodiment, the first direction intersects the second direction perpendicularly.
[0024] In conjunction with the first aspect of this application, in an alternative embodiment, the test structure of the trench gate transistor is located in the dicing region of the wafer.
[0025] Secondly, embodiments of this application provide a testing method for trench gate transistors, the method comprising:
[0026] Provide a test structure for a trench gate transistor as described in any one of the first aspects;
[0027] A low potential is applied to the first electrode and a high potential is applied to the second electrode of the test structure of the trench gate transistor to perform electrical performance testing on the test structure of the trench gate transistor.
[0028] Based on the results of the electrical performance test, feedback is provided on the deposition status of the gate dielectric layer at the bottom wall of the gate trench.
[0029] In conjunction with a second aspect of this application, in an alternative embodiment, the test method is performed during the Wafer Acceptability Test (WAT) stage.
[0030] The trench gate transistor test structure and test method provided in this application, through optimization of the test structure, not only enables the testing of the withstand voltage of the gate dielectric layer, but also eliminates the withstand voltage influence of the portion of the gate dielectric layer located between the gate and the body region. It can test the withstand voltage of the portion of the gate dielectric layer below the lower interface of the body region, which is more conducive to the feedback of weak points at the bottom of the gate trench. Furthermore, it can monitor whether the flow rate of the reaction gas source in the gate dielectric layer formation process is abnormal, greatly reducing the reliability risk of the device and avoiding the impact of weak points on device performance.
[0031] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0032] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0033] Figure 1 This is an electron microscope image of the gate trench portion in a trench gate transistor.
[0034] Figure 2 for Figure 1 A magnified view of the location of the weak point;
[0035] Figure 3 A cross-sectional view of the test structure of the trench gate transistor provided in an embodiment of this application;
[0036] Figure 4 This is a layout of the test structure for a trench gate transistor provided in an embodiment of this application;
[0037] Figure 5 This is a cross-sectional view of the test structure of a trench gate transistor in related technologies;
[0038] Figure 6 A flowchart illustrating the steps of a test method for a trench gate transistor provided in an embodiment of this application. Detailed Implementation
[0039] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.
[0040] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.
[0041] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.
[0042] When an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. Although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.
[0043] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. In addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “below,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0045] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.
[0046] Figure 1 This is an electron microscope image of the gate trench portion in a trench gate transistor. Figure 2 for Figure 1 The image shows a magnified view of the location of the weak point. For gate trenches with a high aspect ratio, weak points are prone to appear in the bottom gate dielectric layer, resulting in a lower breakdown voltage of the gate dielectric layer and ultimately affecting device performance.
[0047] During and after semiconductor manufacturing, various tests are required to verify product performance. WAT (Wafer Acceptance Test) measures the electrical parameters of specific test structures after wafer fabrication and before quality inspection. The purpose of WAT is to assess the process status of each wafer, evaluate the quality and stability of the semiconductor manufacturing process, and determine whether the wafer meets the electrical specifications of the process technology platform by testing the electrical parameters of these specific test structures. CP (Chip Probing) involves using probe cards to contact the chips on the wafer after semiconductor manufacturing is completed and before they are diced and packaged, performing electrical tests to ensure they meet specifications.
[0048] However, current tests (both WAT and CP) fail to detect weak points in the gate dielectric layer at the bottom of the gate trench due to insufficient reactive gas supply. This is mainly because: the withstand voltage of the gate dielectric layer is generally higher than the bias voltage used in the GE leakage current test during CP, making it impossible to detect weak points in the gate dielectric layer; furthermore, the bias voltage cannot be increased to its limit during testing, otherwise it would damage the chip. In contrast, the gate trench opening area of the conventional WAT test structure is relatively small, and the requirement for reactive gas supply content is relatively low. Even if the flow rate of the reactive gas supply is abnormal, the WAT test structure may not be able to reflect the problem in the chip area, thus failing to detect weak points at the bottom of the gate dielectric layer. However, this weak point poses a risk of HTGB (High Temperature Gate Bias – Accelerated Aging Physical Model for Environmental Reliability Testing of Power Devices) failure.
[0049] Based on this, this application provides a test structure for a trench gate transistor. Please refer to... Figure 3 and Figure 4The test structure includes: a semiconductor material layer 100; a gate trench 110 extending from the upper surface 1001 of the semiconductor material layer 100 into the interior of the semiconductor material layer 100; a gate dielectric layer 111 and a gate 112 located within the gate trench 110, wherein the gate dielectric layer 111 covers the sidewalls 1101 and bottom wall 1102 of the gate trench 110, and the gate 112 is located within the gate dielectric layer 111; and a body region 101 adjacent to the gate trench 110 outside the gate trench 110. The extension depth of 110 is deeper than the location of the lower interface 1012 of the body region 101, and the body region 101 has a first conductivity type; the drift region 102 is in contact with the lower interface 1012 of the body region 101 and the portion of the gate trench 110 other than the adjacent body region 101, and the drift region 102 has a second conductivity type; the first electrode 121 is electrically connected to the gate 112 and the body region 101 for applying a low potential; the second electrode 122 is electrically connected to the drift region 102 for applying a high potential.
[0050] Understandably, this embodiment of the application optimizes the test structure so that the gate 112 and the body region 101 are both connected to the first electrode 121, that is, the gate 112 and the body region 101 are at the same potential and specifically connected to a low potential. In addition, the drift region 102 is also led out through the second electrode 122, so that another electrical signal can be applied to the drift region 102, specifically applying a high potential. In this way, not only can the withstand voltage of the gate dielectric layer 111 be tested, but the withstand voltage influence of the portion of the gate dielectric layer 111 located between the gate 112 and the body region 101 is also eliminated. The withstand voltage of the portion of the gate dielectric layer 111 located below the lower interface 1012 of the body region 101 can be tested, which is more conducive to the feedback of the weak point problem at the bottom of the gate trench 110. In addition, it is possible to monitor whether the flow rate of the reaction gas source in the gate dielectric layer 111 formation process is abnormal, which greatly reduces the reliability risk of the device and avoids the impact of weak points on the device performance.
[0051] In practical applications, this test structure can also be called a WAT test structure. This test structure and the trench gate transistor chip are located on the same wafer and formed synchronously under the same fabrication conditions. The wafer has a chip area and a dicing area, and the test structure of the trench gate transistor is located in the dicing area of the wafer.
[0052] The semiconductor material layer 100 includes an upper surface 1001 and a lower surface 1002 that are opposite to each other; the upper surface 1001 of the semiconductor material layer 100 is the operating surface in the process of forming the gate trench 110. Ignoring the flatness of the upper and lower surfaces of the semiconductor material layer 100, the direction perpendicular to the upper surface 1001 is defined as the thickness direction of the semiconductor material layer 100, or the thickness / height direction of the device.
[0053] The semiconductor material layer 100 can be made of silicon, germanium, silicon carbide, etc., and this application does not specifically limit it. The semiconductor material layer 100 can be a growth substrate or an epitaxial layer formed on the growth substrate by an epitaxial growth process.
[0054] The semiconductor material layer 100 can be a doped layer, and specifically can have a second conductivity type. The second conductivity type is different from the first conductivity type; when the first conductivity type is P-type, the second conductivity type is N-type; correspondingly, when the first conductivity type is N-type, the second conductivity type is P-type.
[0055] In some embodiments, the second conductivity type is N-type. The semiconductor material layer 100 is an N-type semiconductor material layer, specifically an N-semiconductor material layer.
[0056] A gate trench 110 extends from the upper surface 1001 of the semiconductor material layer 100 into the interior of the semiconductor material layer 100; the gate trench 110 includes sidewalls 1101 and a bottom wall 1102. Exemplarily, the gate trench 110 can be formed by a photolithography process. Specifically, a mask material is first deposited on the semiconductor material layer 100, and then a predetermined formation location for the gate trench 110 is defined in the mask material using a photolithography process, thereby forming a patterned mask layer. Next, using the patterned mask layer as a mask, the semiconductor material layer 100 is etched until the gate trench 110 is formed. This process is well known to those skilled in the art and will not be described in detail here.
[0057] A gate dielectric layer 111 is located within a gate trench 110 and covers the sidewalls 1101 and bottom wall 1102 of the gate trench 110. In actual devices, the gate dielectric layer 111 can be an oxide layer, and therefore can also be called a gate oxide layer (GOX); specifically, for example, a silicon dioxide layer. In actual fabrication, the gate oxide layer can be formed by an oxidation process, a deposition process, or a process of oxidation followed by deposition. In the process of forming the gate oxide layer, oxygen (i.e., the aforementioned reactive gas source) needs to be introduced. On the one hand, for trenches with a high aspect ratio, it is inherently difficult for oxygen to reach the bottom of the trench; on the other hand, in specific process procedures, abnormal oxygen flow may occur, resulting in insufficient oxygen; ultimately forming weak points in the gate oxide layer at the bottom of the deep trench. Therefore, the test structure provided in this application embodiment can monitor whether oxygen is sufficient during the gate oxide layer process.
[0058] Gate 112 is located within gate dielectric layer 111, thereby being insulated from semiconductor material layer 100 through gate dielectric layer 111. Exemplarily, the material of gate 112 includes, for example, polysilicon.
[0059] Please refer to Figure 4 , Figure 4 This is a layout of a test structure for a trench gate transistor provided in an embodiment of this application, wherein... Figure 3 It can be understood as along Figure 4 A partial cross-sectional view of the structure of section XX. As an optional specific embodiment, the gate trench 110 includes a plurality of first gate trenches 1110 extending along a first direction and a plurality of second gate trenches 1120 extending along a second direction. The first direction intersects the second direction, so that the plurality of first gate trenches 1110 and the plurality of second gate trenches 1120 are connected by the intersection.
[0060] Thus, by changing the layout of the gate trench 110 in the test structure, multiple second gate trenches 1120 are added in the second direction, thereby forming a superimposed structure of multiple first gate trenches 1110 extending in the first direction and multiple second gate trenches 1120 extending in the second direction. This increases the exposure area of the photolithography process and, consequently, the area at the bottom of the gate trench 110 in the test structure. If the flow rate of the reaction gas source is insufficient, the weak point problem in the test structure will be amplified and thus more easily detected.
[0061] It should be understood that both the first and second directions are parallel to the plane containing the semiconductor material layer 100.
[0062] Specifically, the first direction may intersect the second direction perpendicularly; thereby reducing the complexity of the layout and making it easier to arrange the conductive plugs 130.
[0063] In practical applications, the spacing between multiple first gate trenches 1110 can be equal; the spacing between multiple second gate trenches 1120 can be equal; and the spacing between multiple first gate trenches 1110 can be equal to the spacing between multiple second gate trenches 1120. The linewidths of multiple first gate trenches 1110 can be equal; the linewidths of multiple second gate trenches 1120 can be equal; and the linewidths of multiple first gate trenches 1110 can be equal to the linewidths of multiple second gate trenches 1120.
[0064] In the specific process, multiple first gate trenches 1110 and multiple second gate trenches 1120 can be formed simultaneously in the same step. Thus, the fabrication of multiple interlaced gate trenches 110 can be achieved simply by changing the pattern corresponding to the test structure area on the mask, without adding any additional process steps. It should be understood that after forming the gate trenches 110, including multiple first gate trenches 1110 and multiple second gate trenches 1120, the process for depositing the gate dielectric layer 111 and the gate 112 can continue using the original process without affecting the fabrication of the chip region.
[0065] Body region 101 is adjacent to gate trench 110 outside gate trench 110. The depth of gate trench 110 is deeper than the location of the lower interface 1012 of body region 101. Body region 101 has a first conductivity type.
[0066] Understandably, in the corresponding chip, the portion of the body region 101 near the gate trench 110 is used to form a channel.
[0067] The body region 101 can be formed by doping the semiconductor material layer 100 with a first conductivity type, specifically, for example, by an ion implantation process. In some embodiments, the first conductivity type is P-type; the body region 101 can be a P-type body region, and the body region 101 can also be referred to as a Pbody region.
[0068] The depth of the gate trench 110 is greater than the location of the lower interface 1012 of the body region 101. That is, the distance between the bottom wall 1102 of the gate trench 110 and the upper surface 1001 of the semiconductor material layer 100 is greater than the distance between the lower interface 1012 of the body region 101 and the upper surface 1001 of the semiconductor material layer 100. The bottom wall 1102 of the gate trench 110 is closer to the lower surface 1002 of the semiconductor material layer 100 than the lower interface 1012 of the body region 101.
[0069] Drift region 102 has a second conductivity type. In the actual device, semiconductor material layer 110 has a second conductivity type, and the remaining portion of semiconductor material layer 110 that has not been further doped or removed / oxidized forms the drift region 102 of the device.
[0070] Please refer to Figure 3 The upper surface 1001 side of the semiconductor material layer 100 also includes a first portion of an undoped solid region 101 (as shown by the elliptical dashed box in the figure), and the drift region 102 extends to the first portion; thus, it provides conditions for the subsequent formation of the second conductive plug 132 and the conductive lead-out of the drift region 102.
[0071] The first electrode 121, electrically connected to the gate 112 and the body region 101, is used to apply a low potential; the second electrode 122, electrically connected to the drift region 102, is used to apply a high potential. In specific applications, the first electrode 121 and the second electrode 122 can also be referred to as a low-potential electrode pad and a high-potential electrode pad, respectively. Figure 3 As shown, the first electrode 121 and the second electrode 122 are insulated from the semiconductor material layer 100 by an interlayer dielectric layer 150 (ILD layer).
[0072] Please refer to Figure 5 , Figure 5This is a cross-sectional view of a test structure for a trench gate transistor in related technologies. In related technologies, the gate 112 of the test structure is connected to the second electrode 122 (Highpad), and the body region 101 is connected to the first electrode 121 (Lowpad). Therefore, when a voltage is applied to the first electrode 121 and the second electrode 122, the breakdown range is the entire gate trench 110. Consequently, the tested withstand voltage is the withstand voltage of the entire gate dielectric layer 111, making it difficult to monitor the bottom. However, the test structure provided in this application, by changing the conductive connection of the electrodes, makes the gate 112 and the body region 101 at the same potential and jointly connected to the Lowpad, while the body… The drift region 102 below region 101 is electrically led out and connected to the highpad, thereby forming a PN junction between body region 101 and drift region 102, and reverse-suppressing body region 101. Body region 101 can withstand the high voltage (e.g., 100V) used in the test, thus eliminating the voltage withstand effect of the portion of the gate dielectric layer 111 located between the gate 112 and body region 101. This allows for testing the voltage withstand of the portion of the gate dielectric layer 111 below the lower interface 1012 of body region 101, which is more beneficial for identifying weak points at the bottom of the gate trench 110. In summary, the test structure provided in this embodiment can test only the voltage withstand of the gate dielectric layer 111 in the bottom region of the gate trench 110, eliminating interference from the voltage withstand of the gate dielectric layer 111 at other locations in the gate trench 110.
[0073] The test structure for the trench gate transistor further includes: a first conductive plug 131 connected between the first electrode 121 and the gate 112; and a second conductive plug 132 connected between the second electrode 122 and the drift region 102.
[0074] In actual fabrication, an opening is first formed on the interlayer dielectric layer 150 using a photolithography-etching process to expose a predetermined area for the conductive plug 130 (including a first conductive plug 131, a second conductive plug 132, a third conductive plug 133, etc.). Then, conductive material is filled into the opening to form the conductive plug 130. The conductive plug can also be referred to as (Contact, CT).
[0075] Regarding the location of the second conductive plug 132, in the case where the upper surface 1001 side of the semiconductor material layer 100 also includes a first portion of an undoped bulk region 101, the second conductive plug 132 is located directly above the first portion. Specifically, the second conductive plug 132 is formed by forming an opening on the semiconductor material layer 100 that exposes the first portion and filling the opening with conductive material. The second conductive plug 132 is electrically connected to the drift region 102 by directly contacting the first portion.
[0076] As an optional specific implementation, the test structure for the trench gate transistor further includes a field plate structure 140 located on the semiconductor material layer 100 between the first conductive plug 131 and the second conductive plug 132. Thus, the field plate structure 140 compresses the electric field, adjusts the electric field distribution, and improves the withstand voltage, ensuring the detection of weak points at the bottom of the gate trench 110. Specifically, the portion of the semiconductor material layer 100 located between the first conductive plug 131 and the second conductive plug 132 needs to withstand both lateral and longitudinal withstand voltages. Generally, the longitudinal withstand voltage is sufficient, but the lateral withstand voltage may be problematic, leading to PN junction breakdown and ultimately preventing the measurement of weak points at the bottom of the gate trench 110. Adding the field plate structure 140 to the test structure effectively solves this problem, ultimately ensuring the detection of weak points at the bottom of the gate trench 110.
[0077] Please continue to refer to this. Figure 3 The gate trench 110 includes a first side (shown as 1103 in the figure) and a second side (shown as 1104 in the figure) opposite to each other, the body region 101 is adjacent to the first side, and the field plate structure 140 is located on the second side.
[0078] The field plate structure 140 includes a field oxide layer 141 and a field plate layer 142. The field oxide layer 141 is located on the semiconductor material layer 100 on the second side. A portion of the gate material used to form the gate 112 is filled in the gate trench 110, and a portion extends to the field oxide layer 141 to form the field plate layer 142.
[0079] Understandably, the field plate layer 142 is connected to the gate 112 and together they are connected to the first electrode 121.
[0080] Optionally, the field oxide layer 142 is formed using the LOCOS (Local Oxidation of Silicon) process.
[0081] Based on this, the embodiments of this application also provide a testing method for trench gate transistors, please refer to... Figure 6 The method includes:
[0082] Step S601: Provide a test structure for the trench gate transistor in any of the foregoing embodiments of this application;
[0083] Step S602: A low potential is applied to the first electrode and a high potential is applied to the second electrode of the test structure of the trench gate transistor to perform electrical performance testing on the test structure of the trench gate transistor.
[0084] Step S603: Based on the results of the electrical performance test, feedback is provided on the deposition status of the gate dielectric layer at the bottom wall of the gate trench.
[0085] Understandably, the test method for trench gate transistors provided in this application not only enables the testing of the withstand voltage of the gate dielectric layer 111, but also eliminates interference from the withstand voltage of the portion of the gate dielectric layer 111 located between the gate 112 and the body region 101. It can test the withstand voltage of the portion of the gate dielectric layer 111 located below the lower interface 1012 of the body region 101, thus providing better feedback on weak points at the bottom of the gate trench 110. Furthermore, it allows for monitoring of whether the flow rate of the reaction gas source during the formation process of the gate dielectric layer 111 is abnormal. By compressing the electric field through the field plate structure 140 and adjusting the electric field distribution, the lateral withstand voltage problem is solved, further ensuring the detection of weak points at the bottom of the gate trench 110. By changing the layout of the gate trench 110 in the test structure, multiple second gate trenches 1120 are added in the second direction, thereby forming a superimposed structure of multiple first gate trenches 1110 extending along the first direction and multiple second gate trenches 1120 extending along the second direction. This increases the exposure area of the photolithography process and thus increases the area at the bottom of the gate trench 110 in the test structure. If the flow rate of the reaction gas source is insufficient, the weak point problem in the test structure will be amplified and thus more easily detected.
[0086] After conducting a feasibility assessment, the inventors adopted the test structure of the trench gate transistor provided in the embodiments of this application and changed the oxygen flow rate in the formation process of the gate oxide layer. Ultimately, the reduced oxygen flow rate was reflected in both the WAT test data and the CPVramp test data.
[0087] Vramp test, short for Voltage Ramp Test, is a test method used to evaluate the performance and reliability of semiconductor devices under voltage variation conditions.
[0088] As an optional implementation, this testing method is performed during the WAT (Waste Air Testing) stage. Understandably, because the embodiments of this application have improved the test structure for trench gate transistors, it is possible to detect weak points during the WAT stage, thereby shortening the problem discovery cycle time and facilitating rapid handling during the manufacturing process.
[0089] It should be noted that the test method embodiments and test structure embodiments provided in this application belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.
[0090] It should be understood that the above embodiments are exemplary and not intended to encompass all possible implementations. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.
Claims
1. A test structure for a trench gate transistor, characterized in that, include: Semiconductor material layer; A gate trench extends from the upper surface of the semiconductor material layer into the interior of the semiconductor material layer; A gate dielectric layer and a gate are located within the gate trench, wherein the gate dielectric layer covers the sidewalls and bottom wall of the gate trench, and the gate is located within the gate dielectric layer; A body region is located outside and adjacent to the gate trench, the gate trench extending deeper than the lower interface of the body region, and the body region has a first conductivity type. The drift region is in contact with the lower interface of the body region and the portion of the gate trench other than the portion adjacent to the body region, and the drift region has a second conductivity type; The first electrode is electrically connected to the gate and the body region and is used to apply a low potential. The second electrode is electrically connected to the drift region and is used to apply a high potential.
2. The test structure for the trench gate transistor according to claim 1, characterized in that, Also includes: A first conductive plug is connected between the first electrode and the gate. A second conductive plug is connected between the second electrode and the drift region; A field plate structure is located on the semiconductor material layer between the first conductive plug and the second conductive plug.
3. The test structure for the trench gate transistor according to claim 2, characterized in that, The body region is formed by doping the semiconductor material layer with a first conductivity type, and the upper surface of the semiconductor material layer also includes a first portion that is not doped into the body region, and the drift region extends to the first portion; The second conductive plug is formed by forming an opening on the semiconductor material layer that exposes the first portion and filling the opening with a conductive material. The second conductive plug is electrically connected to the drift region by directly contacting the first portion.
4. The test structure for the trench gate transistor according to claim 2, characterized in that, The gate trench includes a first side and a second side opposite to each other, the body region is adjacent to the first side, and the field plate structure is located on the second side; The field plate structure includes a field oxide layer and a field plate layer, wherein the field oxide layer is located on the semiconductor material layer on the second side; A portion of the gate material used to form the gate fills the gate trench, and a portion extends onto the field oxide layer to form the field plate layer.
5. The test structure for the trench gate transistor according to claim 4, characterized in that, The field oxygen layer is formed using the LOCOS process.
6. The test structure for a trench gate transistor according to claim 1, characterized in that, The gate trench includes multiple first gate trenches extending along a first direction and multiple second gate trenches extending along a second direction. The first direction intersects with the second direction, and the multiple first gate trenches and multiple second gate trenches are connected by their intersection.
7. The test structure for a trench gate transistor according to claim 6, characterized in that, The first direction intersects the second direction perpendicularly.
8. The test structure for a trench gate transistor according to claim 1, characterized in that, The test structure of the trench gate transistor is located in the dicing area of the wafer.
9. A test method for a trench gate transistor, characterized in that, The method includes: Provide a test structure for a trench gate transistor as described in any one of claims 1 to 8; A low potential is applied to the first electrode and a high potential is applied to the second electrode of the test structure of the trench gate transistor to perform electrical performance testing on the test structure of the trench gate transistor. Based on the results of the electrical performance test, feedback is provided on the deposition status of the gate dielectric layer at the bottom wall of the gate trench.
10. The test method for trench gate transistors according to claim 9, characterized in that, The test method is performed during the Wafer Acceptability Test (WAT) phase.