LIN bus transceiver and method thereof

Abstract

The invention relates to an LIN bus transceiver and a method thereof. A method for listening to a network node is described herein. According to one embodiment, the method includes receiving data from a serial bus interface, where the data (at least) includes a first header of a first data frame. The method further includes detecting completion of reception of the first header, detecting whether data received after the first header includes a recessive bit, and storing information indicating whether the recessive bit has been detected. Further, the method includes detecting a stop bit in data received after the first header, and when the detection of the stop bit fails, detecting an interrupt delimiter indicating an end of an interrupt field of the second header, signaling a frame error if the stored information indicates that the recessive bit has been received, and otherwise, signaling the frame error if the stored information indicates that the recessive bit has been received. If the stored information indicates that the recessive bit has not been received, a loss response is signaled.

Description

Technical Field

[0001] The present disclosure relates generally to serial bus communications and, more particularly, to enhancements to a Local Interconnect Network (LIN) bus. Background Art

[0002] The Local Interconnect Network (also known as LIN bus) represents a bus system for serial communication between multiple network nodes (e.g., sensors and actuators). It can be considered a fieldbus. As an industry standard, the LIN specification was developed by the LIN Alliance until 2010. It includes the physical layer, the bus protocol (layers 2-4 according to the OSI model), the interface to the application, and a unified format for describing the entire LIN. The latest version of the specification, 2.2A, has been transferred to ISO and published as ISO standard 17987-1 (Road vehicles - Local Interconnect Network (LIN) - Parts 1-8).

[0003] Semiconductor chips with integrated LIN transceivers are already available on the market. Such LIN transceivers can be used in LIN commander (master) and LIN responder (slave) network nodes. The inventors have set themselves the goal of improving existing LIN network nodes. Summary of the invention

[0004] The above object is achieved by a method according to claim 1 and a circuit according to claim 9. The dependent claims cover various embodiments and further developments.

[0005] A method for listening to a network node is described herein. According to one embodiment, the method includes receiving data from a serial bus interface, wherein the data (at least) includes a first header of a first data frame. The method also includes detecting completion of reception of the first header, detecting whether the data received after the first header includes a recessive bit, and storing information indicating whether the recessive bit is detected. In addition, the method includes detecting a stop bit in the data received after the first header, and when detection of the stop bit fails, detecting an interrupt delimiter indicating the end of an interrupt field of a second header, signaling a frame error if the stored information indicates that the recessive bit has been received, and signaling a lost response if the stored information indicates that the recessive bit has not been received.

[0006] In addition, a network node is described herein. According to one embodiment, the network node includes a serial bus interface configured to receive data from a serial bus, wherein the received data (at least) includes a first header of a first data frame. The network node also includes a frame processor configured to detect completion of reception of the first header, detect whether the data received after the first header includes a recessive bit, and store information indicating whether the recessive bit is detected, and detect a stop bit in the data received after the first header. In addition, the frame processor is configured to: when detection of the stop bit fails, detect an interrupt delimiter indicating the end of an interrupt field of a second header, if the stored information indicates that the recessive bit has been received, then issue a frame error signal, and if the stored information indicates that the recessive bit has not been received, then signal a lost response. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention may be better understood with reference to the following drawings and description. The components in the drawings are not necessarily drawn to scale; instead, emphasis is placed on illustrating the principles of the present invention. Additionally, in the drawings, like reference numerals designate corresponding parts. In the drawings:

[0008] Figure 1 The diagram shows a local interconnect network (LIN bus system) having one commander node and (at least) two responder nodes;

[0009] Figure 2 The diagram shows the frame structure according to LIN specification version 2.2A. The frame consists of a header and a response.

[0010] Figure 3 illustrates the structure of the common byte fields of a LIN frame;

[0011] Figure 4 The structure of the break field (Figure (a)) and the synchronization byte field (Figure (b)) of the LIN frame are illustrated;

[0012] Figure 5 Illustrated is a scenario where the bus commander sends the break field of a new frame after an incomplete frame (missing or incomplete response), so the listening bus node will detect a frame error;

[0013] Figure 6 illustrates how a snooping bus node can be enabled to differentiate between a framing error due to a lost response and a framing error due to an incomplete response; and

[0014] Figure 7 The diagram shows the ability to detect Figure 6 Block diagram of a LIN bus responder node showing the causes of framing errors. DETAILED DESCRIPTION

[0015] Figure 1 A local interconnect network is illustrated, which may also be referred to as a LIN bus system. The network comprises a commander node 11 and one or more responder nodes, in the example shown, a responder node 12 and a responder node 13. All network nodes are connected via a bus 15. The commander node 11 is configured to perform commander tasks, and in addition, may also be configured to perform responder tasks (same as responder nodes), and therefore may also operate as a responder. The basic structure of the LIN bus system and the required functions of the commander and responder network nodes are known according to the LIN specification, and therefore will not be discussed further herein.

[0016] The LIN commander node 11 may include a communication interface that allows communication with other entities or subsystems. In the example shown, the commander node 11 includes an interface for communicating with a control area network (CAN) via a CAN bus 19. Additionally or alternatively, the commander node may include (or be coupled to) any other data source.

[0017] Figure 2 The structure of a LIN frame according to LIN specification version 2.2A is shown. Accordingly, a frame consists of two parts, a header part and a response part. For each frame, the header is generated by the commander node, while the response can be generated by the commander node 11 or the responder node. The header consists of an interrupt field (see Figure 4 Figure (a)), synchronization field (see Figure 4 Figure (b)) and a protected identifier (PID) field.

[0018] The header starts with the falling edge of the break field and ends after the end of the stop bit of the protected identifier (PID) field. The response consists of one or more data fields and a special data field including a checksum (checksum field). The response starts with the end of the stop bit of the PID field and ends after the stop bit of the checksum field.

[0019] The inter-byte space is the time between the end of the stop bit of the previous field and the start bit of the next byte. The response space is the inter-byte space between the PID field and the first data field of the response.

[0020] Figure 3 The structure of the general byte field of the LIN frame is illustrated. The synchronization field, PID field, data field and checksum field have the structure of the byte field. That is, each field starts with a (dominant) start bit, followed by eight bits (bits 0-7), and ends with a (recessive) stop bit. The dominant bit has a low level (bit with a value of 0), and the recessive bit has a high level (bit with a value of 1). Therefore, the length of the byte field corresponds to the length of ten bits.

[0021] Figure 4 Two special fields are shown, the break field in Figure (a) and the sync field (also called the sync byte field) in Figure (b). The break field is used to signal the start of a new frame. It is always generated by the commander node and is not compliant with Figure 3 The only field in the field structure shown. Figure 4 As shown, the interrupt field is longer than the normal byte field. According to the specification, it is at least 13 nominal bit times long (value 0), followed by an interrupt delimiter, which is at least one nominal bit long (value 1). In other words, the interrupt field includes at least 13 dominant bits, and the interrupt delimiter includes at least one recessive bit.

[0022] Typically, responder nodes may use an interrupt detection threshold of 11 (dominant) bit times. Responder nodes are not required to check that the interrupt delimiter is at least one nominal bit time long. The Sync field is a normal byte field with the value 85 (decimal) or 0b01010101 (binary). The most significant bit is bit 7.

[0023] A responder node should always be able to detect a Break / Sync field sequence even if it expects a Byte field (assuming the Byte fields are separated from each other).When a Break / Sync field sequence occurs, the ongoing transmission should be aborted and processing of a new frame should begin.

[0024] The PID field consists of two subfields, the frame identifier and the parity bits. Bits 0 to 5 are the frame identifier (possible values ​​0 to 63), and bits 6 and 7 are the parity bits.

[0025] As described above, the header is generated by the commander node (and output to the bus), while the response is generated by one of the responder nodes or by the commander node as a responder. It is possible that the frame is incomplete. This may happen when no bus node outputs a response after the header, which can be an ideal scenario in certain situations. Incomplete frames may also occur if the response is incomplete for whatever reason. For example, a responder node sending a response may be interrupted by a commander node that sends a new interrupt field (consisting of 13 dominant bits).

[0026] Figure 5A scenario is illustrated in which the commander node sends the interrupt field of a new frame after an incomplete frame (with a lost or incomplete response). Therefore, a frame error (stop bit error) will be detected by the listening bus node because it expects a data field. Assuming that the second header is sent by the bus commander instead of waiting for a response, the listening responder node (not yet knowing that the second header is sent) will interpret the first (dominant) bit of the interrupt field of the second header as the start bit of the data field, and will expect a (hidden) stop bit after receiving / detecting eight bits (bits 0-7). However, since the interrupt field includes at least 13 dominant bits, a recessive stop bit will not occur. Therefore, the listening responder node will signal a frame error (stop bit error) when the stop bit is expected. Only later, when the interrupt delimiter bit is detected, the interrupt field (and therefore the new header) is identified.

[0027] References Figure 5 There can be two reasons for the interpreted frame error, namely, the second header follows the first header without a response in between, and the second header interrupts the response after the first header. In some applications, it is necessary to distinguish between these two reasons. A straightforward method for distinguishing between these two scenarios (lost response and incomplete response) may be to store the received bits in a buffer memory and analyze the history of the received bits when a stop bit error occurs. However, this approach complicates the circuit arrangement of the responder node, and the embodiments described herein are intended to provide a simpler solution, which will be referred to below. Figure 6 Have a discussion.

[0028] Figure 6 The first (top) figure schematically illustrates a normal frame having a header followed by a response comprising several data fields and a trailing checksum field ( Figure 6 not shown). Figure 6 The second figure illustrates a first header followed by a second header, which indicates the start of a new frame, although no response is sent after the first header. Figure 6 The third (bottom) diagram of illustrates a similar scenario to that shown in the second diagram, but an incomplete response is sent after the first header. That is, the response sent after the first header is interrupted by the interrupt field of the second header (for whatever reason).

[0029] In both scenarios (such as Figure 6 Incomplete frames due to lost or incomplete responses) as shown in the second and third figures of Figure 5As described above, a stop bit error is detected. The framing error occurs because the responder expects a stop bit at the end of the data field (which is always a recessive bit), but in fact, it detects a dominant bit of the break field of the new header. The embodiments described herein implement a mechanism that enables the responder to distinguish between these two scenarios (lost response and incomplete response).

[0030] like Figure 6 As shown in the second figure, the start bit of the break field of the second header is initially interpreted as the start bit of the first data field of the response. After receiving / detecting 8 bits (bits 0-7), the responder node expects a (hidden) stop bit, but this does not occur because the break field of the second header always includes a sequence of at least 13 dominant bits. Therefore, a frame error / stop bit error is signaled when the expected stop bit should occur. Only later, after at least 13 dominant bits, can the responder detect the break delimiter and identify the sequence received up to the break field of the new header. From Figure 6 (Combined Figure 5 ) It can be seen that after receiving the first header, the listening responder node does not receive the recessive bit until the stop bit error occurs. This is different in the second scenario, where the response is not lost, but incomplete because it is interrupted by the new header.

[0031] If one or more data fields are received before a stop bit error occurs, at least one recessive bit will be received before the stop bit error occurs. Therefore, when the listening bus node receives a response (or receives a bit sequence interpreted as a response), it can set a flag after the reception of the first recessive bit. The flag is a 1-bit storage element and can be a dedicated bit stored in a register. Alternatively, the flag can be implemented using a simple SR latch (set-reset flip-flop). If the flag is set when an interrupt delimiter is detected after a stop bit error occurs (indicating that a recessive bit has been detected before), the listening bus can conclude that an incomplete response is received before the reception of the interrupt field, i.e., the previous response is interrupted by a new header.

[0032] When the response is completely lost and the second header is sent directly after the first header (without an incomplete response in between), this flag will not be set. Thus, by evaluating this flag, a listening bus node can distinguish between the two scenarios (lost response, incomplete response) very easily.

[0033] Figure 7 The diagram shows the ability to receive frames and detect Figure 6 The block diagram of the LIN bus responder node shows the cause of the frame error. It should be understood that Figure 7is a simplified block diagram in which elements that are known and not necessary for discussion of the embodiments are omitted to keep the drawings simple and easy to understand.

[0034] according to Figure 7 , the bus / network node comprises a serial bus interface 121 configured to receive data from the serial bus 15. In the example shown, the bus interface 121 is formed by a comparator. Known more complex interface circuits may be used. The signal representing the received data is marked as RXD. The received data comprises a plurality of data frames, each data frame comprising at least a header.

[0035] The network node also includes a frame processor, which in this example includes a break field detector 122, a sync byte and PID evaluator 123, a RXD level monitor 124, and an AND gate 125. It should be understood that a person skilled in the art will consider various other implementations of the frame processor, all of which perform substantially the same functions. According to one embodiment, the frame processor is configured to detect the completion of reception of the first header. Figure 7 In the example of , the detection is performed by the interrupt field detector 122 and the synchronization byte and PID evaluator 123, where the logic signal EOPID provided by the synchronization byte and PID evaluator 123 signals the completion of header reception (e.g., EOPID=1 signals the end of header reception).

[0036] The frame processor is also configured to detect whether the data received after the first header includes a recessive bit, and store information indicating whether the recessive bit has been detected. The detection is performed by the RXD level monitor 124, wherein the signal RBD provided by the RXD monitor 124 indicates that the recessive bit has been detected (e.g., RBD=1 indicates that the recessive bit has been detected). The signal RBD can be an output signal of a latch included in the RXD level monitor 124. When a new PID field is detected (e.g., signaled by the EOPID), the latch can be reset (to output RBD=0).

[0037] In addition, the frame processor is configured to detect a stop bit in the data received after the first header. In addition, the frame processor is configured to detect a break delimiter indicating (e.g., by EOB=1) the end of the break field of the second header in the event that the detection of the stop bit fails, signal a frame error (e.g., FER=1 and NFR=0) if the stored information indicates that a recessive bit has been received (e.g., RBD=1), and signal a "no response frame" (e.g., NFR=1) if the stored information indicates that a recessive bit has not been received (e.g., RBD=0).

[0038] In the example shown, the signal FER indicates (eg, by FER=1) as described above with reference to Figure 5 and Figure 6 The AND gate 125 generates a conjunction and EOB as output signal NFR. Therefore, when a new header (see Figure 6 The signal NFR is "1" when the interrupt field of the second header in the AND gate 125 is received (EOB=1) and the recessive bit is not detected (RBD=0). When a new frame is detected (EOPID=1), the signal / flag RBD is reset. That is, the monitor circuit 125 generates RBD=0 at the beginning of the (expected) response. If the "response" turns out to be the second header, this fact is indicated by NFR=1 at the output of the AND gate 125. Alternatively, if the response is interrupted by the second header, this fact is indicated by NFR=0 at the output of the AND gate 125.

[0039] Although the present invention has been illustrated and described with respect to one or more implementations, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the above-described components or structures (units, assemblies, devices, circuits, systems, etc.), unless otherwise indicated, the terms used to describe such components (including references to "parts") are intended to correspond to any component or structure that performs the specified function of the above-described components (e.g., functionally equivalent), even if not structurally equivalent to the disclosed structures that perform the functions in the illustrated exemplary implementations of the present invention.

Claims

1. A method comprising: receiving data from a serial bus interface, the data comprising a first header of a first data frame; detecting completion of reception of the first header; detecting whether data received after the first header includes a recessive bit, and storing information indicating whether the recessive bit has been detected; detecting a stop bit in the data received after the first header; and When the detection of the stop bit fails: detecting a break delimiter, the break delimiter indicating an end of a break field of the second header; if the stored information indicates that a recessive bit has been received, signaling a frame error; as well as If the stored information indicates that a recessive bit has not been received, a lost response is signaled.

2. The method according to claim 1, The serial bus interface is a local interconnect network LIN interface.

3. The method according to claim 1 or 2, wherein in case the detection of the stop bit fails, the received data up to the break delimiter is interpreted as a break field of a second header, and The method further comprises receiving further data of the second header.

4. The method according to any one of claims 1 to 3, The information indicating whether a recessive bit has been detected is stored in the latch.

5. The method according to any one of claims 1 to 4, The receiving of data from the serial bus interface begins with receiving a start bit.

6. The method according to any one of claims 1 to 5, The first header includes the interrupt field, the synchronization field and the frame identifier field.

7. The method according to any one of claims 1 to 5, Receiving data includes repeatedly sampling bit values ​​synchronously with a clock signal.

8. The method according to claim 7, Wherein the clock signal is synchronized using a synchronization field included in the first header.

9. A network node, comprising: A serial bus interface (121) configured to receive data from a serial bus, the received data comprising a first header of a first data frame; The frame processor is configured as follows: detecting completion of reception of the first header; detecting whether data received after the first header includes a recessive bit, and storing information indicating whether the recessive bit has been detected; detecting a stop bit in the data received after the first header; and When the detection of the stop bit fails: detecting a break delimiter, the break delimiter indicating an end of a break field of the second header; If the stored information indicates that a recessive bit has been received, a frame error is signaled; as well as If the stored information indicates that a recessive bit has not been received, a lost response is signaled.

10. The network node according to claim 9, The serial bus interface (121) comprises a comparator.

11. The network node according to claim 9 or 10, The serial bus interface (121) is a local interconnect network (LIN) interface.

12. The network node according to any one of claims 9 to 11, wherein the frame processor is further configured to: In case the detection of the stop bit fails, interpreting the received data up to the break delimiter as a break field of the second header, and then, Further data of the second header is received.

13. The network node according to any one of claims 9 to 12, Wherein said frame processor comprises a latch for storing said information indicating whether a recessive bit has been detected.

14. The network node according to any one of claims 9 to 13, The first header includes the interrupt field, the synchronization field and the frame identifier field.

15. The network node according to any one of claims 9 to 14, Before receiving data, the frame processor is configured to repeatedly sample the bit value in synchronization with a clock signal.

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