半导体结构及其制造方法、存储系统
By forming independent semiconductor pillars and gate structures in the semiconductor structure, the coupling problem caused by the increase in semiconductor storage density is solved, and the independence of the storage cell and the reliability of the process are improved.
CN119730254BActive Publication Date: 2026-07-17YANGTZE MEMORY TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2023-09-26
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
As the storage density of semiconductor structures increases, the coupling between adjacent components becomes more severe, affecting the performance and reliability of storage cells.
Method used
By forming multiple semiconductor pillars in a semiconductor layer and a gate structure extending along a third direction on its sidewalls, combined with bit line design, coupling between adjacent semiconductor pillars is reduced, forming an independent semiconductor structure.
Benefits of technology
This effectively reduces coupling between adjacent semiconductor pillars, improving the independence of memory cells and the reliability of the manufacturing process.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN119730254B_ABST
Abstract
本申请提供了一种半导体结构及其制造方法、存储系统。制造半导体结构的方法包括：获取初始半导体结构，其中初始半导体结构包括：半导体层，包括多个半导体柱，半导体柱沿第二方向延伸且沿第一方向和第三方向阵列分布，其中第一方向和第三方向相交，第二方向垂直于第一方向和第三方向；以及栅极结构，位于半导体柱的侧壁上且沿第三方向延伸；从远离半导体柱的一侧去除部分半导体层至暴露出半导体柱的第一端；以及形成与半导体柱的第一端连接且沿第一方向延伸的位线。
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