IGBT devices

Abstract

This invention discloses an IGBT device, comprising: multiple parallel gate trench structures and emitter trench structures passing through a well region. A gate conductive material layer is connected to the gate. An emitter conductive material layer is connected to the emitter. A drift region is formed at the bottom of the well region, and a collector region is formed at the bottom of the drift region. An emitter region is formed in a selected surface region of the well region. The emitter region is located on both sides of each gate trench structure and is self-aligned with the side surface of the gate trench structure; the emitter region does not contact the side surface of the emitter trench structure. The emitter trench structure serves as a shielding structure for the gate trench structure to reduce Cgc (conversion coefficient). The depth of the emitter trench is greater than the depth of the gate trench, thereby increasing the shielding effect on the gate trench structure. This invention can reduce Cgc.

Description

Technical Field

[0001] This invention relates to a semiconductor power device, and more particularly to an IGBT device. Background Technology

[0002] Compared to planar gate structures, trench gate technology eliminates the junction gate field-effect transistor (JEFT) region, resulting in compact cells and low on-state voltage drop, allowing for higher current densities. Therefore, it is widely used in electric vehicle chips.

[0003] In traditional IGBT chips, the carrier concentration decreases from the back collector to the front emitter, and the low carrier concentration at the front emitter limits the reduction of the on-state voltage drop. Therefore, achieving an increase in IGBT chip current density and a decrease in power loss requires combining carrier storage technology to make the carrier distribution in the IGBT chip closer to the optimal state.

[0004] like Figure 1 The diagram shown is a structural schematic of an existing IGBT device; taking an N-type device as an example, the existing IGBT device 201 includes:

[0005] Multiple parallel trench gates, each trench gate including a gate trench, a gate dielectric layer 110 formed on the inner surface of the gate trench, and a gate conductive material layer 111 filled in the gate trench.

[0006] The gate conductive material layer 111 is connected to the gate, which is composed of the front metal layer 109.

[0007] Each trench gate passes through the P-type doped well region 105.

[0008] An N-type doped drift region 103 is formed at the bottom of the well region 105.

[0009] A P-type heavily doped collector region 101 is formed at the bottom of the drift region 103. A back metal layer is formed on the back side of the collector region 101, and the back metal layer forms the collector electrode.

[0010] In the present invention, an N-type heavily doped buffer layer 102 is also included between the drift region 103 and the collector region 1011.

[0011] N-type heavily doped emitter regions 106 are formed in the surface region of the well region 105 in the platform region on both sides of the trench gate, and the emitter regions 106 and the corresponding trench gate side surfaces are self-aligned.

[0012] In the top region of the drift region 103, an N-type heavily doped carrier stored (CS) layer 104 is also formed.

[0013] Each gate trench passes through the carrier storage layer 104.

[0014] Figure 1 The IGBT device 201 shown improves the current density of the IGBT chip by using fine trench technology, and adds a carrier storage layer to prevent holes from entering the P-base region, i.e., the well region 105, thereby increasing the hole concentration near the emitter and reducing the on-state voltage by at least 20%.

[0015] Due to its design structure, the IGBT device 201 contains many parasitic capacitances. These equivalent capacitances can be simplified to the capacitances between the electrodes of the IGBT device 201, such as... Figure 2 The diagram shown is the equivalent circuit diagram of an existing IGBT device. The collector of the IGBT device 201 is represented by COLLECTOR, the emitter by EMITTER, and the gate by GATE. It includes three parasitic capacitances:

[0016] Parasitic capacitance C between gate and collector GC ;

[0017] Parasitic capacitance C between the gate and emitter GE ;

[0018] Parasitic capacitance C between collector and emitter CE .

[0019] In a half-bridge topology, when the upper IGBT (S1) is turned on, a changing voltage dv / dt is applied between the collector and emitter of the lower IGBT (S2). Current flows through the parasitic Miller capacitance Cgc, the gate drive resistor Rg, and the internal integrated gate drive resistor Rdrive of S2. The magnitude of the gate current can be roughly estimated using the following formula:

[0020] Icg=Ccg*(dvce / dt)(1);

[0021] This current generates a voltage difference across the gate resistor. If this voltage exceeds the IGBT's gate drive threshold, it will cause parasitic conduction, resulting in bridge arm shoot-through and module short-circuit failure. Therefore, reducing Cgc is an effective way to mitigate drive crosstalk. Summary of the Invention

[0022] The technical problem to be solved by the present invention is to provide an IGBT device that can reduce Cgc.

[0023] To solve the above-mentioned technical problems, the IGBT device provided by the present invention includes: a plurality of parallel gate trench structures and emitter trench structures.

[0024] The gate trench structure includes a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filled in the gate trench.

[0025] The emitter trench structure includes an emitter trench, an emitter dielectric layer formed on the inner surface of the emitter trench, and an emitter conductive material layer filled in the emitter trench.

[0026] The gate conductive material layer is connected to the gate, which is composed of a front metal layer.

[0027] The emitter conductive material layer is connected to the emitter, which is composed of a front metal layer.

[0028] Each of the gate trench structures and each of the emitter trench structures passes through a well region doped with a second conductivity type.

[0029] A drift region doped with a first conductivity type is formed at the bottom of the well region.

[0030] A heavily doped collector region of a second conductivity type is formed at the bottom of the drift region.

[0031] A heavily doped emitter region of a first conductivity type is formed in a selected area of ​​the surface region of the well region.

[0032] The emitter region is located on both sides of each of the gate trench structures and is self-aligned with the side of the corresponding gate trench structure; the emitter region does not contact the side of the emitter trench structure.

[0033] The emitter trench structure serves as a shielding structure for the gate trench structure to reduce Cgc, where Cgc is the gate-collector capacitance. The depth of the emitter trench is greater than the depth of the gate trench, thereby increasing the shielding effect on the gate trench structure.

[0034] A further improvement is that a carrier storage layer heavily doped with a first conductivity type is also formed in the top region of the drift region.

[0035] A further improvement is that both the gate trench and the emitter trench extend through the carrier storage layer.

[0036] A further improvement is that the width of the emitter trench is greater than the width of the gate trench, and the emitter trench and the gate trench are formed simultaneously using the same etching process; the greater the width of the emitter trench, the deeper the emitter trench.

[0037] A further improvement is that the spacing between the center positions of two adjacent gate trenches, the spacing between the center positions of two adjacent emitter trenches, or the spacing between the center positions of adjacent gate trenches and emitter trenches are equal.

[0038] The increased width of the emitter trench makes the width of the plateau region (mesa) on both sides of each emitter trench smaller than the width of the plateau region between each gate trench, thereby increasing the carrier injection effect.

[0039] A further improvement is that the top of the emitter region on both sides of each of the gate trench structures is connected to the emitter via a contact hole, and the contact hole at the top of the emitter region also passes through the emitter region and contacts the well region at the bottom of the emitter region.

[0040] The top of the well region on both sides of each emitter trench structure is connected to the emitter through a contact hole; or, no contact hole is provided on the top of the well region on both sides of each emitter trench structure to form a floating structure.

[0041] A further improvement is that the gate trench structure and the emitter trench structure are arranged periodically in a ratio of m:n, where m is the number of gate trench structures in the arrangement period and n is the number of emitter trench structures in the arrangement period, and m is greater than or equal to 1 and n is greater than or equal to 1.

[0042] A further improvement is that the values ​​of m:n include:

[0043] 1:1, 1:2, 1:3, 2:2, 3:3.

[0044] A further improvement is that a trench bottom injection region doped with a second conductivity type is formed in the drift region at the bottom of the emitter trench, and the trench bottom injection region extends laterally into the drift regions on both sides of the emitter trench. The trench bottom injection region is used to increase the shielding effect on the gate trench structure.

[0045] A further improvement is that, in the platform region between adjacent emitter trenches, the trench bottom injection regions at the bottom of two adjacent emitter trenches are laterally connected together.

[0046] At the bottom of each of the gate trenches, there is a spacing between adjacent trench bottom injection regions.

[0047] A further improvement is that a buffer layer heavily doped with a first conductivity type is also included between the drift region and the collector region 1.

[0048] A further improvement is that the width of the emitter trench is 0.05 μm to 0.2 μm larger than the width of the gate trench.

[0049] A further improvement is that the gate dielectric layer and the emitter dielectric layer are made of the same material and are formed simultaneously.

[0050] The gate conductive material layer and the emitter conductive material layer are made of the same material and are formed simultaneously.

[0051] A further improvement is that the material of the gate dielectric layer includes an oxide layer, and the material of the gate conductive material layer includes polysilicon.

[0052] A further improvement is that the IGBT device is an N-type device, with the first conductivity type being N-type and the second conductivity type being P-type;

[0053] Alternatively, the IGBT device is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0054] This invention provides an emitter trench structure arranged parallel to the gate trench structure, and sets the depth of the emitter trench to be greater than the depth of the gate trench. In this way, by increasing the depth of the emitter trench, the coupling effect between the gate conductive material layer and the bottom drift region can be reduced, that is, the gate trench structure can be shielded, thereby reducing Cgc, i.e., gate-collector capacitance. The deeper the emitter trench, the stronger the shielding effect and the better the Cgc reduction effect.

[0055] The gate trench and emitter trench of the present invention can be formed simultaneously using the same etching process. By utilizing the etching effect, the depth of the emitter trench can be increased by simply increasing the width of the emitter trench, i.e., the critical dimension (CD), and the depth of the emitter trench can be made deeper than the depth of the gate trench. Therefore, the present invention also has the advantages of simple process and low cost.

[0056] Furthermore, while keeping the pitch of each trench, including the gate trench and the emitter trench, constant or finely adjusted, as the width of the emitter trench increases, the width of the plateau regions on both sides of the emitter trench will inevitably decrease based on the width of the plateau regions between the gate trenches. After the width of the plateau regions decreases, the path for minority carriers to leak from the drift region to the emitter region becomes narrower, which can enhance the carrier injection effect, thereby simultaneously reducing the on-state voltage drop of the device and thus reducing the on-state loss.

[0057] In addition, when a carrier storage layer is formed, the width of the plateau region is reduced, and under the same conditions, the injection dose of the carrier storage layer can be increased, which can also enhance the carrier injection effect and thus reduce the on-state loss. Attached Figure Description

[0058] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0059] Figure 1 This is a schematic diagram of the structure of an existing IGBT device;

[0060] Figure 2 This is the equivalent circuit diagram of an existing IGBT device;

[0061] Figure 3 This is a schematic diagram of the structure of the IGBT device according to the first embodiment of the present invention;

[0062] Figure 4 This is a schematic diagram of the structure of the IGBT device according to the second embodiment of the present invention;

[0063] Figure 5 This is a schematic diagram of the structure of the IGBT device according to the third embodiment of the present invention;

[0064] Figure 6 This is a schematic diagram of the structure of the IGBT device according to the fourth embodiment of the present invention;

[0065] Figure 7 This is a schematic diagram of the structure of the IGBT device according to the fifth embodiment of the present invention. Detailed Implementation

[0066] like Figure 3 The diagram shown is a structural schematic of an IGBT device according to a first embodiment of the present invention. The IGBT device according to the first embodiment of the present invention includes: a plurality of parallel gate trench structures 301 and emitter trench structures 302.

[0067] The gate trench structure 301 includes a gate trench 303, a gate dielectric layer 10a formed on the inner surface of the gate trench 303 (Gate TCH), and a gate conductive material layer 11a filled in the gate trench 303.

[0068] The emitter trench structure 302 includes an emitter trench 304, an emitter dielectric layer 10b formed on the inner surface of the emitter trench 304 (Emitter TCH), and an emitter conductive material layer 11b filled in the emitter trench 304.

[0069] The gate conductive material layer 11a is connected to the gate, which is composed of the front metal layer 9. Figure 3 In this context, the gate conductive material layer 11a is also represented by G.

[0070] The emitter conductive material layer 11b is connected to the emitter, which is composed of the front metal layer 9. Figure 3 The gate is not shown in the corresponding cross-section; the corresponding front metal layer 9 is the emitter. The emitter conductive material layer 11b is also denoted by E.

[0071] Each gate trench structure 301 and each emitter trench structure 302 passes through the well region 5 doped with the second conductivity type.

[0072] A drift region 3 with a first conductivity type doped is formed at the bottom of the well region 5.

[0073] A heavily doped collector region 1 of the second conductivity type is formed at the bottom of the drift region 3. A back metal layer is formed on the back side of the collector region 1, and the back metal layer forms the collector electrode. Figure 3 In this context, the collector is also represented by the term Collector.

[0074] In the first embodiment of the present invention, a buffer layer 2 heavily doped with a first conductivity type is further included between the drift region 3 and the collector region 11.

[0075] A heavily doped emitter region 6 of the first conductivity type is formed in a selected area of ​​the surface region of the well region 5.

[0076] The emitter region 6 is located on both sides of each gate trench structure 301 and is self-aligned with the side of the corresponding gate trench structure 301; the emitter region 6 does not contact the side of the emitter trench structure 302.

[0077] The emitter trench structure 302 serves as a shielding structure for the gate trench structure 301 to reduce Cgc, where Cgc is the gate-collector capacitance. The depth of the emitter trench 304 is greater than the depth of the gate trench 303. Increasing the depth of the emitter trench 304 enhances the shielding effect on the gate trench structure 301.

[0078] In the first embodiment of the present invention, a carrier storage layer 4 heavily doped with a first conductivity type is also formed in the top region of the drift region 3.

[0079] Both the gate trench 303 and the emitter trench 304 pass through the carrier storage layer 4.

[0080] The width of the emitter trench 304 is greater than the width of the gate trench 303. The emitter trench 304 and the gate trench 303 are formed simultaneously using the same etching process. Based on the etching effect that the greater the trench width, the greater the etching depth, it can be seen that the greater the width of the emitter trench 304, the deeper the emitter trench 304.

[0081] In the first embodiment of the present invention, the gate dielectric layer 10a and the emitter dielectric layer 10b are made of the same material and are formed simultaneously.

[0082] The gate conductive material layer 11a and the emitter conductive material layer 11b are made of the same material and are formed simultaneously.

[0083] In some embodiments, the width of the emitter trench 304 is 0.05 μm to 0.2 μm larger than the width of the gate trench 303.

[0084] The gate dielectric layer 10a is made of an oxide layer, and the gate conductive material layer 11a is made of polysilicon.

[0085] In the first embodiment of the present invention, the spacing between the centers of two adjacent gate trenches 303, the spacing between the centers of two adjacent emitter trenches 304, or the spacing between the centers of adjacent gate trenches 303 and emitter trenches 304 are equal. The spacing between the centers of two adjacent gate trenches 303 is the sum of the width of one gate trench 303 and the width of the plateau region between the gate trenches 303, corresponding to a pitch, which is the sum of the spacing between the trenches. The introduction of the emitter trench 304 does not change the pitch size; that is, the sum of the widths of the emitter trench 304 and the adjacent plateau region is equal to the sum of the widths of the gate trench 303 and the plateau region between the gate trenches 303. In other embodiments, it is also possible to fine-tune the pitch of the region corresponding to the emitter trench 304 after its introduction.

[0086] The increased width of the emitter trench 304 makes the width of the plateau region on both sides of each emitter trench 304 smaller than the width of the plateau region between each gate trench 303. This reduction in plateau region width leads to a decrease in the number of minority carriers leaking from the drift region 3 into the well region 5 formed in the plateau region. Consequently, the number of minority carriers in the drift region 3 increases, thereby enhancing the carrier injection effect. Furthermore, in the first embodiment of the present invention, the reduced width of the plateau region, under the same conditions, also allows for an increase in the injection dose of the carrier storage layer 4, which further enhances the carrier injection effect and reduces on-state losses.

[0087] In the first embodiment of the present invention, the top of the emitter region 6 on both sides of each gate trench structure 301 is connected to the emitter through a contact hole 7 passing through the interlayer film 8. The contact hole 7 at the top of the emitter region 6 also passes through the emitter region 6 and contacts the well region 5 at the bottom of the emitter region 6.

[0088] The top of the well region 5 on both sides of each emitter trench structure 302 is connected to the emitter through contact holes 7.

[0089] In the first embodiment of the present invention, the gate trench structure 301 and the emitter trench structure 302 are arranged periodically in a ratio of m:n, where m is the number of gate trench structures 301 in the arrangement period and n is the number of emitter trench structures 302 in the arrangement period, m is greater than or equal to 1 and n is greater than or equal to 1. Further, in the first embodiment of the present invention, the value of m:n is 2:3.

[0090] In the first embodiment of the present invention, the IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the IGBT device can also be a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

[0091] In the first embodiment of the present invention, an emitter trench structure 302 is arranged parallel to the gate trench structure 301, and the depth of the emitter trench 304 is set to be greater than the depth of the gate trench 303. In this way, by increasing the depth of the emitter trench 304, the coupling effect between the gate conductive material layer 11a and the bottom drift region 3 can be reduced, that is, the gate trench structure 301 can be shielded, thereby reducing Cgc, i.e., the gate-collector capacitance. The deeper the emitter trench 304, the stronger the shielding effect and the better the Cgc reduction effect.

[0092] In the first embodiment of the present invention, the gate trench 303 and the emitter trench 304 can be formed simultaneously using the same etching process. By utilizing the etching effect, the depth of the emitter trench 304 can be increased by simply increasing the width of the emitter trench 304, i.e., the critical dimension (CD), and the depth of the emitter trench 304 can be made deeper than the depth of the gate trench 303. Therefore, the first embodiment of the present invention also has the advantages of simple process and low cost.

[0093] Furthermore, while keeping the pitch of each trench, including the gate trench 303 and the emitter trench 304, and the plateau regions between each trench unchanged or finely adjusted, after the width of the emitter trench 304 is increased, the width of the plateau regions on both sides of the emitter trench 304 will inevitably be reduced based on the width of the plateau regions between the gate trenches 303. After the width of the plateau regions is reduced, the path for minority carriers in the drift region 3 to leak to the emitter region 6 becomes narrower, which can enhance the carrier injection effect, thereby simultaneously reducing the on-state voltage drop of the device and thus reducing the on-state loss.

[0094] In addition, when the carrier storage layer 4 is formed, the width of the plateau region is reduced, and under the same conditions, the injection dose of the carrier storage layer 4 can be increased, which can also enhance the carrier injection effect and thus reduce the on-state loss.

[0095] In the first embodiment of the present invention, by increasing the CD of the Emitter TCH (emitter trench 304), the depth of the Emitter TCH will be deeper than that of the Gate TCH (gate trench 303) under the same etching conditions. This strengthens the shielding effect of the Emitter TCH on the Gate TCH, thereby reducing Cgc. Simultaneously, increasing the Emitter TCH CD reduces the width of the mesa (plateau region), resulting in a stronger carrier injection effect under the same conditions and reducing the on-state voltage drop of the IGBT.

[0096] like Figure 4 The diagram shown is a structural schematic of the IGBT device according to the second embodiment of the present invention. The difference between the second and first embodiments is that, in the second embodiment, no contact holes 7 are provided at the top of the well regions 5 on both sides of each emitter trench structure 302, resulting in a floating structure. Figure 4 The area corresponding to the dashed box 305 does not have a contact hole 7.

[0097] like Figure 5 The diagram shown is a structural schematic of the IGBT device according to the third embodiment of the present invention. The difference between the IGBT device and the first embodiment of the present invention is that the value of m:n in the IGBT device of the third embodiment of the present invention is 1:1.

[0098] like Figure 6 The diagram shown is a structural schematic of the IGBT device according to the fourth embodiment of the present invention. The difference between the IGBT device and the first embodiment of the present invention is that the value of m:n in the IGBT device of the fourth embodiment of the present invention is 1:3.

[0099] Other embodiments can be obtained by changing m:n. In some embodiments, the value of m:n can be 1:2, 2:2, or 3:3.

[0100] like Figure 7 The diagram shown is a structural schematic of the IGBT device according to the fifth embodiment of the present invention; the difference between the fifth embodiment and the first embodiment of the present invention is that, in the fifth embodiment of the present invention, the IGBT device:

[0101] A trench bottom injection region 306 with a second conductivity type doped is formed in the drift region 3 at the bottom of the emitter trench 304. The trench bottom injection region 306 also extends laterally into the drift regions 3 on both sides of the emitter trench 304. The trench bottom injection region 306 is used to increase the shielding effect on the gate trench structure 301.

[0102] In the platform region between adjacent emitter trenches 304, the trench bottom injection regions 306 at the bottom of the two adjacent emitter trenches 304 are laterally connected together.

[0103] At the bottom of each gate trench 303, there is a spacing between adjacent trench bottom injection regions 306.

[0104] Since the IGBT device in the fifth embodiment of the present invention is an N-type device and the second conductivity type is P-type, Figure 7 In the middle, the injection zone 306 at the bottom of the trench is also represented by P-type injection.

[0105] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. An IGBT device, characterized in that, include: Multiple parallel gate trench structures and emitter trench structures; The gate trench structure includes a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filled in the gate trench. The emitter trench structure includes an emitter trench, an emitter dielectric layer formed on the inner surface of the emitter trench, and an emitter conductive material layer filled in the emitter trench. The gate conductive material layer is connected to the gate, which is composed of a front metal layer; The emitter conductive material layer is connected to the emitter, which is composed of a front metal layer; Each of the gate trench structures and each of the emitter trench structures passes through a well region doped with a second conductivity type; A drift region doped with a first conductivity type is formed at the bottom of the well region; A heavily doped collector region of a second conductivity type is formed at the bottom of the drift region; A heavily doped emitter region of a first conductivity type is formed in a selected area of ​​the surface region of the well region; The emitter region is located on both sides of each of the gate trench structures and is self-aligned with the side of the corresponding gate trench structure; the emitter region does not contact the side of the emitter trench structure; The emitter trench structure serves as a shielding structure for the gate trench structure to reduce Cgc, where Cgc is the gate-collector capacitance. The depth of the emitter trench is greater than the depth of the gate trench, thereby increasing the shielding effect on the gate trench structure by increasing the depth of the emitter trench. The width of the emitter trench is greater than the width of the gate trench, and the emitter trench and the gate trench are formed simultaneously using the same etching process; the greater the width of the emitter trench, the deeper the emitter trench. The spacing between the center positions of two adjacent gate trenches, the spacing between the center positions of two adjacent emitter trenches, or the spacing between the center positions of adjacent gate trenches and emitter trenches are equal. The increased width of the emitter trench makes the width of the plateau region on both sides of each emitter trench smaller than the width of the plateau region between each gate trench, thereby increasing the carrier injection effect. A carrier storage layer heavily doped with a first conductivity type is also formed in the top region of the drift region; both the gate trench and the emitter trench pass through the carrier storage layer; under the same conditions, the injection dose of the carrier storage layer in the plateau region on both sides of each emitter trench with a smaller width can be increased to enhance the carrier injection effect.

2. The IGBT device as described in claim 1, characterized in that: The top of the emitter region on both sides of each of the gate trench structures is connected to the emitter through a contact hole, and the contact hole at the top of the emitter region also passes through the emitter region and contacts the well region at the bottom of the emitter region; The top of the well region on both sides of each emitter trench structure is connected to the emitter through a contact hole; or, no contact hole is provided on the top of the well region on both sides of each emitter trench structure to form a floating structure.

3. The IGBT device as described in claim 1, characterized in that: The gate trench structure and the emitter trench structure are arranged periodically in a ratio of m:n, where m is the number of gate trench structures in the arrangement period and n is the number of emitter trench structures in the arrangement period, and m is greater than or equal to 1 and n is greater than or equal to 1.

4. The IGBT device as described in claim 3, characterized in that: The values ​​of m:n include: 1：1，1：2，1：3，2：2，3：3。 5. The IGBT device as described in claim 1, characterized in that: A trench bottom injection region doped with a second conductivity type is formed in the drift region at the bottom of the emitter trench. The trench bottom injection region also extends laterally into the drift regions on both sides of the emitter trench. The trench bottom injection region is used to increase the shielding effect on the gate trench structure.

6. The IGBT device as described in claim 5, characterized in that: In the platform region between adjacent emitter trenches, the trench bottom injection regions at the bottom of two adjacent emitter trenches are laterally connected together; At the bottom of each of the gate trenches, there is a spacing between adjacent trench bottom injection regions.

7. The IGBT device as described in claim 1, characterized in that: A buffer layer heavily doped with a first conductivity type is also included between the drift region and the collector region.

8. The IGBT device as described in claim 1, characterized in that: The width of the emitter trench is 0.05 μm to 0.2 μm larger than the width of the gate trench.

9. The IGBT device as described in claim 1, characterized in that: The gate dielectric layer and the emitter dielectric layer are made of the same material and are formed simultaneously. The gate conductive material layer and the emitter conductive material layer are made of the same material and are formed simultaneously.

10. The IGBT device as described in claim 9, characterized in that: The gate dielectric layer is made of an oxide layer, and the gate conductive material layer is made of polysilicon.

11. The IGBT device according to any one of claims 1 to 10, characterized in that: IGBT devices are N-type devices, with N-type as the first conductivity type and P-type as the second conductivity type; Alternatively, the IGBT device is a P-type device, with the first conductivity type being P-type and the second conductivity type being N-type.

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