An ultra-steep sub-threshold slope transistor and a method of fabricating the same
By using a transistor structure with a superlattice stacked high-κ gate dielectric, the problems of large leakage current and large subthreshold swing of traditional transistors are solved, achieving low power consumption and fast signal transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- PEKING UNIV
- Filing Date
- 2023-12-21
- Publication Date
- 2026-06-19
AI Technical Summary
Traditional transistors have large leakage current and large subthreshold swing, making it difficult to achieve low power consumption and fast signal transmission.
A high-κ gate dielectric is formed by superlattice stacking, including HfO2/ZrO2/HfO2 stacked units. It is grown by atomic layer deposition (ALD) and the pulse time of the intercalation layer material and oxygen source is adjusted to form a gate dielectric with a ferroelectric and antiferroelectric mixed phase, thereby enhancing the capacitance effect.
It realizes a low-power transistor with low subthreshold swing and high on-state current, and is suitable for ultra-steep subthreshold slope transistors with various structures, featuring lower operating voltage and larger on-state current.
Smart Images
Figure CN119730335B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, and relates to low-power dynamic random access memory devices and logic devices, and particularly to an ultra-steep subthreshold slope transistor based on superlattice stacked high-κ gate dielectric and its fabrication method. Background Technology
[0002] With technological advancements, the demand for integrated circuits continues to increase. In the fields of information technology and electronic equipment, the need for higher performance and lower power consumption is growing, especially in memory and logic applications where lower power consumption is sought. Traditional transistors' leakage current is primarily limited by mechanisms such as the Hall effect and thermionic emission, making it difficult to achieve a small subthreshold swing. Ultra-steep subthreshold transistors, by introducing new materials, structures, and processes, achieve more ideal characteristics, reducing the operating voltage required by integrated circuits and thus achieving lower power consumption. Traditional ultra-steep subthreshold transistors mainly include tunneling transistors and ferroelectric negative capacitance transistors. Tunneling transistors have excessively low on-state current, resulting in slow transmission speeds from zero to one. Ferroelectric negative capacitance transistors require adjustment of the ferroelectric and dielectric components, making it difficult to achieve a uniform threshold voltage and lacking sufficient κ (potential capacitance), hindering faster signal transmission. Summary of the Invention
[0003] The purpose of this invention is to provide an ultra-steep subthreshold slope transistor and its fabrication method. It uses superlattice stacked high-κ gate dielectric to achieve a steady-state capacitance enhancement effect, thereby realizing a low-power transistor with low subthreshold swing and high on-state current.
[0004] The technical solution of the present invention is as follows:
[0005] An ultra-steep subthreshold slope transistor is characterized in that the gate dielectric layer of the transistor is a superlattice stacked high-κ gate dielectric, comprising multiple stacked HfO2 / ZrO2 / HfO2 stacked units, with an insertion layer between two adjacent stacked units; in the HfO2 / ZrO2 / HfO2 stacked units, the upper and lower layers are HfO2, and the middle layer is ZrO2; the insertion layer is selected from one or more of the following materials: alumina, lanthanum oxide, silicon oxide, beryllium oxide, titanium oxide, tantalum oxide, yttrium oxide, and tungsten oxide.
[0006] Preferably, the HfO2 / ZrO2 / HfO2 stacked units are grown by atomic layer deposition (ALD), wherein the HfO2 layer is grown for 4 to 6 cycles with a thickness of 0.4 to 0.6 nm, and the ZrO2 layer is grown for 12 to 17 cycles with a thickness of 1.2 to 1.7 nm. The molar ratio of HfO2 to ZrO2 in each stacked unit is preferably 2:3.
[0007] Preferably, the insertion layer is also grown by ALD and has a thickness of 0.1 to 0.2 nm.
[0008] This invention employs a super-steep subthreshold slope transistor using superlattice stacked high-κ gate dielectrics, which is not limited to a specific structure and can be a back-gate, top-gate, dual-gate, gate-around, or fin-gate field-effect transistor. In one embodiment of this invention, a dual-gate field-effect transistor with a back-gate and top-gate structure is fabricated, comprising a substrate and a back-gate electrode, a back-gate dielectric layer, a channel layer, a top-gate dielectric layer, and a top-gate electrode sequentially stacked on the substrate, with source and drain electrodes connected at both ends of the channel; wherein the back-gate dielectric layer and the top-gate dielectric layer are both superlattice stacked high-κ gate dielectrics.
[0009] In the ultra-steep subthreshold slope transistor, the channel layer can be made of new materials such as silicon, germanium, gallium arsenide, gallium nitride, two-dimensional materials, and oxide semiconductors. The channel layer is prepared by techniques such as mechanical lift-off, chemical vapor deposition, magnetron sputtering, atomic layer deposition, and laser pulse deposition. The gate metal and source / drain metals can be high-temperature resistant metals such as titanium nitride, platinum, tungsten, and palladium, while the source / drain metals can also be a series of high-temperature resistant metals and semiconductors such as nickel, molybdenum, and oxides.
[0010] The high-κ gate dielectric of the superlattice stack is prepared by atomic layer deposition followed by rapid thermal annealing. HfO2 and ZrO2 materials are grown in the superlattice stack, and the leakage current and the ratio of ferroelectric orthorhombic to antiferroelectric tetragonal phases in the gate dielectric are adjusted by intercalation layers. After annealing, the intercalation layers are doped. Different dopants and their concentrations control the stability of different phases after annealing of HfO2 / ZrO2 / HfO2, thereby adjusting the ratio of orthorhombic to tetragonal phases in the mixture. For example, doping with La promotes the formation of the ferroelectric orthorhombic phase, while doping with Al promotes the formation of the antiferroelectric tetragonal phase. The ratio of ferroelectric orthorhombic to antiferroelectric tetragonal phases in the HfO2 / ZrO2 / HfO2 stack is adjusted by doping. The formation of the monoclinic phase is controlled by adjusting the oxygen source and its pulse time to regulate the interface, leakage current, and the ratio of orthorhombic to tetragonal phases. The oxygen source and oxygen source pulse time for HfO2 and ZrO2 in the contact area with the channel are used to adjust the interface. For example, for oxide channels, when growing the gate dielectric in the contact area with the channel, O3 or O plasma oxygen source is used, with an oxygen source pulse time of 0.1s to 30s; while when growing the gate dielectric in other parts, H2O is used as the oxygen source, with an oxygen source pulse time of 0.1s to 30s. Adjusting the oxygen source and oxygen source pulse time of HfO2, ZrO2, and the insertion layer adjusts the carbon content and oxygen vacancies in the gate dielectric, thereby adjusting the leakage characteristics and the ratio of orthorhombic to tetragonal phases. Different stacking methods are combined to adapt to the channel material and achieve the fabrication of ultra-steep subthreshold slope transistors. Annealing after depositing the high-κ gate dielectric film or annealing after electrode fabrication allows the gate dielectric to crystallize.
[0011] This invention proposes using superlattice-stacked HfO2 and ZrO2 high-κ materials as the gate dielectric. During ALD growth, the threshold voltage, dielectric constant, and leakage characteristics are adjusted by regulating the oxygen source and oxygen source pulse time, thereby achieving a high on / off ratio ultra-steep subthreshold slope transistor. Compared to conventional transistors, the transistor of this invention exhibits higher on-state current, lower subthreshold swing, and smaller leakage current. The ultra-steep subthreshold slope transistor based on superlattice-stacked high-κ gate dielectric and its fabrication method have the following main advantages:
[0012] (1) The gate dielectric is grown by superlattice method to enhance surface stress, thereby achieving a stable capacitance enhancement effect under the hybrid ferroelectric and antiferroelectric conditions;
[0013] (2) Based on the hybridization of ferroelectric and antiferroelectric phases, stable capacitance enhancement is achieved within a voltage range, which increases the gate capacitance while reducing the subthreshold swing, and simultaneously achieves a lower operating voltage and a larger on-state current.
[0014] (3) It provides multiple adjustment methods, such as adjusting the oxygen source pulse and pulse time, the type of insertion layer, the interface between the channel and the gate dielectric, the capacitance and leakage current of the gate dielectric, and has a wide range of applications.
[0015] (4) The superlattice high-κ material is resistant to high temperature and can withstand the high-temperature process at the back end. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the ALD growth of high-κ gate dielectric in Example 1, where: 10 is the HfO2 layer, 9 is the ZrO2 layer, and 8 is the intermediate insertion layer (which can be La2O3, SiO2, Al2O3, BeO, etc.).
[0017] Figure 2 This is a schematic diagram of the structure of the ultra-steep subdomain slope transistor in Example 2, wherein: 1 is a high-resistivity silicon substrate, 2 is SiO2, 3 is a back-gate superlattice high-κ dielectric, 4 is a channel material, 5 is titanium nitride, 6 is a top-gate superlattice high-κ gate dielectric, and 7 is tungsten.
[0018] Figure 3 This is a schematic diagram of the fabrication process of the superlattice stacked dual-gate self-aligned transistor in Example 2, which consists of 14 steps. Steps 5 and 11 are for the fabrication of high-κ gate dielectric, which can be adjusted according to the characteristics of the channel and source / drain metals. Detailed Implementation
[0019] The fabrication methods of high-κ gate dielectrics and ultra-steep subthreshold slope transistors in superlattice stacks are described below with reference to the accompanying drawings and through embodiments. In the following description, many details are set forth to provide a thorough understanding of the invention; however, the invention can be implemented in many other ways than those described. Therefore, the invention is not limited to the embodiments disclosed below.
[0020] Example 1: Fabrication of high-κ gate dielectrics in superlattice stacking
[0021] The gate dielectric was grown in situ using atomic layer deposition (ALD). The hafnium source was tetra(ethylmethylamino)hafnium, the zirconium source was tetra(ethylmethylamino)zirconium, the lanthanum source was tris(N,N'-diisopropylmethylammonium)lanthanum, the aluminum source was trimethylaluminum, the silicon source was (dimethylamino)silicon, and the beryllium source was diethylberyllium. Available oxygen sources included H2O, O3, and O plasma. The ALD growth temperature was 300℃.
[0022] Figure 1 The specific growth method is shown. First, four cycles of HfO2 are grown in the contact region with the channel. The threshold voltage and leakage current characteristics of the device are adjusted by regulating the oxygen source and / or the oxygen source pulse time in the first four or more cycles. For oxide channels (such as IGZO, ITO, InO, ITWO, IZO, etc.), oxygen vacancies can be introduced or filled by adjusting the pulse time of the O3 or O plasma oxygen source, thereby achieving the effect of adjusting the threshold voltage. For silicon channels, using H2O as the oxygen source results in a thinner interface SiO2, achieving a higher EOT. Using O3 or oxygen plasma as the oxygen source results in a better interface and better dielectric properties.
[0023] ZrO2 is regenerated for 12 cycles, with the first few cycles allowing for adjustment of the oxygen source and pulse timing to affect the channel threshold and interface.
[0024] Four more cycles of HfO2 were then grown. The HfO2:ZrO2:HfO2 ratio of 4:12:4 was a single superlattice cycle, in which the molar ratio of Hf to Zr was 4:6.
[0025] Then, a cycle of insertion layers is grown as needed. For those seeking lower leakage current, Al₂O₃, SiO₂, or BeO are chosen as the insertion layer. Insertion layers have a higher bandgap, reducing leakage current and increasing the tetragonal phase ratio. This allows for better ferroelectric and antiferroelectric mixing and interweaving in the gate dielectric, achieving a steady-state negative capacitance. La₂O₃ insertion layers can increase the orthorhombic phase ratio and decrease the low-dielectric-constant monoclinic phase ratio, while simultaneously increasing the gate dielectric bandgap, reducing leakage current, and increasing reliability. High κ and leakage current characteristics of the overall gate dielectric stack can be achieved through combinations of different insertion layers.
[0026] Alternating layer (ALD) growth of HfO2 / ZrO2 / HfO2, intercalation layer, HfO2 / ZrO2 / HfO2, intercalation layer, ..., until the desired thickness is reached, achieves the desired high κ and leakage characteristics. The intercalation layers can be combined, and the oxygen source and pulse time can be selected according to the requirements of the gate dielectric. By adjusting the type of intercalation layer and the oxygen source and pulse time, the ratio of ferroelectric orthorhombic to antiferroelectric tetragonal phases is adjusted to achieve a stable capacitance boost effect near the transistor's operating voltage. This results in a steady-state negative capacitance, thus realizing an ultra-steep subthreshold slope transistor.
[0027] After the ALD (Alternating Layer) growth of the gate dielectric or gate metal is completed, rapid thermal annealing is performed. The gate dielectric is annealed at 500°C for 60 seconds in a forming gas or nitrogen atmosphere to form a stable ferroelectric-antiferroelectric hybrid high-κ gate dielectric.
[0028] Example 2: Transistor Fabrication
[0029] Figure 2 This demonstrates a transistor structure with a dual-gate superlattice stacked high-κ gate dielectric. From top to bottom, the layers are: high-resistivity silicon substrate 1, SiO2 layer, back gate electrode, back gate superlattice high-κ dielectric 3, channel material 4, top gate superlattice high-κ dielectric 6, and top gate electrode. The source and drain electrodes are located at both ends of the channel. The fabrication process of this dual-gate superlattice stacked high-κ gate dielectric transistor is as follows: Figure 3 As shown, it includes:
[0030] Step 1: Substrate Cleaning
[0031] The high-resistivity single-crystal silicon substrate with a SiO2 layer on its surface was ultrasonically cleaned using RCA1 solution, acetone, isopropanol, and deionized water to remove organic matter and particles from the substrate surface, and then dried with high-purity nitrogen.
[0032] Step 2: Back grid etching
[0033] Using a photoresist mask, this step can be done by photolithography, electron beam exposure, or other methods to define the pattern. ICP SF6 / O2 is used to etch trenches, and the trench depth is no greater than the SiO2 layer thickness.
[0034] Step 3: Back gate metal deposition
[0035] In this example, a magnetron-controlled TiN / W with a thickness of 10nm / 20nm is used as the back gate metal.
[0036] Step 4: CMP polishing, annealing, and removal of metal outside the grooves to make the surface smooth.
[0037] Step 5: Deposition of back-gate superlattice high-κ gate dielectric
[0038] In this example, ALD was used to grow the back-gate dielectric, growing HfO2 / ZrO2 / HfO2 / Al2O3 / HfO2 / ZrO2 / HfO2 / HfO2 / ZrO2 / HfO2. The first few cycles used H2O low-oxygen source pulse time growth, while the last four cycles used O3 medium-length oxygen source pulse time growth.
[0039] Step 6: Deposition Channel Materials
[0040] In this example, 3nm indium tin oxide (ITO) is used as the channel by magnetron sputtering. In practice, the channel layer can also be made of silicon, germanium, gallium arsenide, gallium nitride, two-dimensional materials, oxide semiconductors, and other novel materials. The channel layer is prepared using techniques such as mechanical lift-off, chemical vapor deposition, magnetron sputtering, and atomic layer deposition. If the channel is heat-resistant, annealing is performed after the complete transistor fabrication process. If the transistor is not heat-resistant, rapid N2 thermal annealing for 60 seconds is performed after step five to crystallize the material, followed by deposition or transfer of the channel material.
[0041] Step 7: Deposition source leaks metal.
[0042] In this example, magnetron sputtered TiN is used as the source and drain contact metal.
[0043] Step 8: Spin-coating HSQ for masking.
[0044] Step 9: Expose and develop HSQ to form the top grid area.
[0045] Step 10: Top gate metal etching. Use Cl2 / AlCl3 to etch the TiN in the top gate region to expose the channel.
[0046] Step 11: Deposition of high-κ gate dielectric in top-gate superlattice
[0047] In this example, ALD is used to grow the back gate dielectric, growing HfO2 / ZrO2 / HfO2 / Al2O3 / HfO2 / ZrO2 / HfO2 / Al2O3 / HfO2 / ZrO2 / HfO2. The first group of HfO2 is prepared by long pulse time with O3, and the subsequent cycles are prepared by short pulse growth with H2O.
[0048] Step 12: Source / drain via etching
[0049] The high-κ gate dielectric is etched onto the top superlattice stack using ICP SF6 / O2, and then etched into the source / drain TiN region to form a self-aligned structure.
[0050] Step 13: Top gate deposition of TiN / W forms the top gate metal and source / drain metal contact, and W deposition prevents TiN oxidation.
[0051] Step 14: CMP top gate planarization removes excess metal at the top, isolates the source and drain from the gate, forming a complete dual-gate transistor. After fabrication, it is rapidly annealed at 500°C in an N2 atmosphere for 60 seconds to crystallize the gate and fill the damage to the channel and metal caused during the fabrication process.
[0052] If the channel material or gate metal is not heat-resistant, annealing can be performed after depositing the gate dielectric film in step five, without performing the annealing in step fourteen. In this case, step eleven can be achieved by adjusting the gate dielectric thickness, oxygen source, and pulse time to achieve non-annealing crystallization, or by directly utilizing the high κ characteristics of the HfO2 / ZrO2 mixed gate dielectric.
Claims
1. An ultra-steep subthreshold slope transistor, characterized in that, The gate dielectric layer of the transistor is a superlattice stacked high-κ gate dielectric, comprising multiple stacked HfO2 / ZrO2 / HfO2 stacked units, with an insertion layer between adjacent stacked units; in each HfO2 / ZrO2 / HfO2 stacked unit, the upper and lower layers are HfO2, and the middle layer is ZrO2; the insertion layer is selected from one or more of the following materials: alumina, lanthanum oxide, silicon oxide, beryllium oxide, titanium oxide, tantalum oxide, yttrium oxide, and tungsten oxide; in each HfO2 / ZrO2 / HfO2 stacked unit, the thickness of each HfO2 layer is 0.4~0.6 nm, the thickness of each ZrO2 layer is 1.2~1.7 nm, and the thickness of the insertion layer is 0.1~0.2 nm.
2. The ultra-steep subthreshold slope transistor as described in claim 1, characterized in that, The molar ratio of HfO2 to ZrO2 in each HfO2 / ZrO2 / HfO2 stacked unit is 2:
3.
3. The ultra-steep subthreshold slope transistor as described in claim 1, characterized in that, The transistor is a back-gate, top-gate, dual-gate, gate-around, or fin-gate field-effect transistor.
4. The ultra-steep subthreshold slope transistor as described in claim 1, characterized in that, The transistor is a dual-gate field-effect transistor with a back gate and a top gate structure, including a substrate and a back gate electrode, a back gate dielectric layer, a channel layer, a top gate dielectric layer, and a top gate electrode stacked sequentially on the substrate, with the source and drain electrodes connected at both ends of the channel. The back gate dielectric layer and the top gate dielectric layer are both superlattice stacked high-κ gate dielectrics.
5. The ultra-steep subthreshold slope transistor as described in claim 1, characterized in that, The HfO2 / ZrO2 / HfO2 stacked units are grown by atomic layer deposition, wherein the HfO2 layer is grown for 4 to 6 cycles and the ZrO2 layer is grown for 12 to 17 cycles.
6. The method for fabricating an ultra-steep subthreshold slope transistor according to any one of claims 1 to 5, characterized in that, The superlattice stacked high-κ gate dielectric is grown using atomic layer deposition and then annealed. By adjusting the type of intercalation layer and / or by adjusting the oxygen source and pulse time during growth, the ratio of ferroelectric orthorhombic phase to antiferroelectric tetragonal phase and the leakage characteristics in the gate dielectric are adjusted to achieve the function of steady-state negative capacitance.
7. The preparation method according to claim 6, characterized in that, When using atomic layer deposition to grow the gate dielectric in situ, the hafnium source is tetra(ethylmethylamino)hafnium, the zirconium source is tetra(ethylmethylamino)zirconium, the lanthanum source is tris(N,N'-diisopropylmethylammonium)lanthanum, the aluminum source is trimethylaluminum, the silicon source is (dimethylamino)silicon, the beryllium source is diethylberyllium, and the oxygen source is selected from H2O, O3, and O plasma.
8. The preparation method according to claim 6, characterized in that, When growing the gate dielectric in the contact area with the channel, the interface is adjusted by regulating the oxygen source and its pulse time.
9. The preparation method according to claim 8, characterized in that, For oxide channels, when growing the gate dielectric in the part in contact with the channel, an O3 or O plasma oxygen source is used, with an oxygen source pulse time of 0.1 s to 30 s; while when growing the gate dielectric in other parts, H2O is used as the oxygen source, with an oxygen source pulse time of 0.1 s to 30 s.