Chip structure, preparation method thereof and display device

Abstract

A chip structure, a preparation method thereof, and a display device. The chip structure includes a chip wafer unit and a color conversion unit arranged on a light-outgoing side of the chip wafer unit. The color conversion unit includes a substrate, which includes a main body and an edge portion surrounding the main body. The edge portion includes original layers and modified layers arranged alternately along a first direction. In the edge portion, the layers located on the two most outer sides in the first direction are both original layers. The first direction is perpendicular to a surface of the substrate away from the chip wafer unit. The original layers and the modified layers have different light reflectivities.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a chip structure and its fabrication method, and a display device. Background Technology

[0002] Micro-LED (micro-light-emitting diode) display devices are a new generation of display technology, with advantages such as high brightness, high luminous efficiency, low power consumption, and fast response speed. Summary of the Invention

[0003] On one hand, a chip structure is provided. The chip structure includes: a chip wafer unit and a color conversion unit disposed on the light-emitting side of the chip wafer unit. The color conversion unit includes a substrate, the substrate including a main body portion and an edge portion surrounding the main body portion. The edge portion includes a primary layer and a modified layer alternately disposed along a first direction, and in the edge portion, the outermost layers located on both sides in the first direction are primary layers. The primary layer and the modified layer have different light reflectivities. The first direction is perpendicular to the surface of the substrate away from the chip wafer unit.

[0004] In some embodiments, the main body has the same light reflectivity as the original layer.

[0005] In some embodiments, the substrate includes a first surface and a second surface opposite to each other along a first direction, and a plurality of side surfaces connecting the first surface and the second surface, wherein the second surface is closer to the chip wafer cell than the first surface. The edge portion includes a plurality of sub-portions respectively disposed corresponding to the plurality of side surfaces, wherein the plurality of sub-portions include the same number of modified layers; or, the plurality of sub-portions include different numbers of modified layers.

[0006] In some embodiments, at least one of the plurality of sub-regions of the edge portion includes N modified layers, where N is a positive integer and N≥2. The modified layer furthest from the chip wafer cell is the first modified layer, and the modified layer closest to the chip wafer cell is the Nth modified layer. The distance between the first modified layer and the first surface is greater than or equal to the distance between any two adjacent modified layers; and / or, the distance between the Nth modified layer and the second surface is greater than or equal to the distance between any two adjacent modified layers.

[0007] In some embodiments, the distance between the first modified layer and the first surface ranges from 15 μm to 35 μm; and / or, the distance between the Nth modified layer and the second surface ranges from 15 μm to 35 μm.

[0008] In some embodiments, the distance between the first modified layer and the first surface is greater than or equal to 20 μm; and / or, the distance between the Nth modified layer and the second surface is greater than or equal to 20 μm.

[0009] In some embodiments, the color conversion unit further includes a color filter layer, a defining dam layer, and a color conversion layer. The color filter layer is disposed on the side of the substrate facing the chip wafer unit, and includes a black matrix and a plurality of filter portions defined by the black matrix. In a projected image onto the substrate, the black matrix is ​​located within the area enclosed by the edge portions. The defining dam layer is disposed on the side of the color filter layer away from the substrate, and includes a plurality of opening regions corresponding one-to-one with the plurality of filter portions. The color conversion layer is disposed in the same layer as the defining dam layer.

[0010] In some embodiments, the dam layer includes multiple opening regions comprising: a first type of opening region and a second type of opening region. The color conversion layer includes: a color conversion portion and a filling portion. The color conversion portion includes a quantum dot conversion portion or a fluorescent color conversion portion. The filling portion includes a scattering particle portion or a transparent adhesive. The color conversion portion is disposed within the first type of opening region, and the filling portion is disposed within the second type of opening region.

[0011] In some embodiments, the substrate includes a functional region and a peripheral region surrounding the functional region. The orthographic projection of the chip wafer unit onto the substrate is located within the functional region, with the main body portion located at least within the functional region and the edge portion located within the peripheral region. The color conversion unit also includes an encapsulation layer covering the color filter layer. In the orthographic projection onto the substrate, the portion of the encapsulation layer located in the peripheral region overlaps with the edge portion.

[0012] In some embodiments, the distance between the boundary of the black matrix and the side surface of the substrate is e1, and the dimension of the modified layer in the direction parallel to the first surface of the substrate and perpendicular to the side surface of the substrate is e2, where e2≤e1.

[0013] In some embodiments, the size e2 of the modified layer in a direction parallel to the first surface of the substrate and perpendicular to the side surface of the substrate ranges from 5 μm to 10 μm.

[0014] In some embodiments, the distance e1 between the boundary of the black matrix and the side surface of the substrate ranges from 10 μm to 30 μm.

[0015] On the other hand, a display device is provided. The display device includes a driving substrate and a plurality of chip structures according to any of the above embodiments, wherein the driving substrate is coupled to the plurality of chip structures respectively.

[0016] On the other hand, a method for fabricating a chip structure is provided, including the following steps.

[0017] Forming an initial wafer; the initial wafer comprises multiple chip wafer units.

[0018] A color conversion substrate is formed; the color conversion substrate includes a substrate mother plate and multiple color conversion structures disposed on the substrate mother plate, each color conversion structure and its corresponding substrate mother plate being a color conversion unit.

[0019] The color conversion substrate is coupled to the initial wafer to obtain a coupling structure; wherein each chip wafer unit is opposite to a color conversion unit.

[0020] A laser is sequentially applied to multiple focal points within the substrate motherboard to create cutting lines within the substrate motherboard. These focal points are arranged sequentially along a first direction, perpendicular to the surface of the substrate motherboard away from the multiple color conversion structures. After cutting, the substrate motherboard forms multiple substrates. Each substrate includes a main body and an edge portion surrounding the main body. The edge portion includes original layers and modified layers alternately arranged along the first direction, with the outermost layers in the first direction being original layers.

[0021] In some embodiments, in the step of cutting by sequentially applying a laser to multiple focal points inside the substrate mother plate, the color conversion substrate side of the self-coupled structure cuts the substrate mother plate.

[0022] In some embodiments, the substrate motherboard includes multiple cutting tracks, and the laser cuts along the cutting tracks. When cutting each cutting track, the number of focal points acted by the laser may be the same or not exactly the same.

[0023] In some embodiments, in the step of cutting by sequentially applying a laser to multiple focal points inside the substrate mother plate, the number of focal points is N, where N is a positive integer and N≥2, the focal point furthest from the initial wafer is the first focal point, and the focal point closest to the initial wafer is the Nth focal point; the surface of the substrate mother plate furthest from the initial wafer is the first surface, and the surface of the substrate mother plate closest to the initial wafer is the second surface.

[0024] The distance between the first focal point and the first surface of the substrate mother plate is greater than or equal to the distance between any two adjacent focal points; and / or, the distance between the Nth focal point and the second surface of the substrate mother plate is greater than or equal to the distance between any two adjacent focal points.

[0025] In some embodiments, the distance between the first focal point and the first surface of the substrate mother plate ranges from 15 μm to 35 μm; and / or, the distance between the Nth focal point and the second surface of the substrate mother plate ranges from 15 μm to 35 μm.

[0026] In some embodiments, the distance between any two adjacent chip structures ranges from 30 μm to 50 μm. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0028] Figure 1 This is a plan view of a display device according to some embodiments;

[0029] Figure 2 According to Figure 1 The cross-sectional structure diagram of section line GG in the diagram;

[0030] Figure 3 This is a flowchart of a method for fabricating a chip structure according to some embodiments;

[0031] Figure 4 According to Figure 3 The top view of the structure corresponding to step S1 in the preparation method;

[0032] Figure 5 According to Figure 3 The top view of the structure corresponding to step S2 in the preparation method;

[0033] Figure 6 According to Figure 3 The top view of the structure corresponding to step S3 in the preparation method;

[0034] Figure 7 According to Figure 3 The side view structure diagram corresponding to step S4 in the preparation method;

[0035] Figure 8 According to Figure 7 Enlarged structural diagram of the cross-section line FF in the diagram;

[0036] Figure 9 According to Figure 7 Enlarged structural diagram at point E in the middle;

[0037] Figure 10 The following are side view structural diagrams corresponding to steps S11 to S14 in the preparation method according to some embodiments;

[0038] Figure 11 This is a side view of the structure corresponding to step S15 in the preparation method according to some embodiments;

[0039] Figure 12 This is a side view of the structure corresponding to step S16 in the preparation method according to some embodiments;

[0040] Figure 13 This is a side view of the structure corresponding to step S21 in the preparation method according to some embodiments;

[0041] Figure 14 This is a side view structural diagram corresponding to steps S22 and S23 in the preparation method according to some embodiments;

[0042] Figure 15 This is a side view structural diagram corresponding to steps S24 and S31 in the preparation method according to some embodiments;

[0043] Figure 16 This is a side view of the structure corresponding to step S32 in the preparation method according to some embodiments;

[0044] Figure 17 This is a side view of the structure corresponding to step S33 in the preparation method according to some embodiments;

[0045] Figure 18 This is a side view of the structure corresponding to step S34 in the preparation method according to some embodiments;

[0046] Figure 19 This is a side view of the structure corresponding to step S35 in the preparation method according to some embodiments;

[0047] Figure 20 This is a top view structural diagram corresponding to step S6 in the preparation method according to some embodiments. Detailed Implementation

[0048] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0049] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0050] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0051] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0052] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0053] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0054] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0055] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0056] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0057] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0058] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0059] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0060] In some embodiments, such as Figure 2As shown, the chip structure 10 includes a chip wafer unit 1 and a color conversion unit 2 disposed on the light-emitting side of the chip wafer unit 1. The chip wafer unit 1 is configured to emit at least one of a variety of colors of light, and the color conversion unit 2 is configured to perform color conversion on the color light emitted by the chip wafer unit 1.

[0061] For example, the chip wafer unit 1 includes a plurality of light-emitting layers 13, each of which is configured to emit one of a plurality of colors of light. The color conversion unit 2 includes a color conversion portion 241 and a filling portion 242 disposed corresponding to the light-emitting layers 13. Each color conversion portion 241 is disposed opposite to at least one light-emitting layer 13, and each filling portion 242 is disposed opposite to at least one light-emitting layer 13. Each light-emitting layer 13 is disposed corresponding to one color conversion portion 241 or one filling portion 242.

[0062] In some examples, the colors of the light emitted by each of the multiple light-emitting layers 13 are not exactly the same.

[0063] For example, some of the multiple light-emitting layers 13 emit blue light, some emit green light, and some emit red light.

[0064] In other examples, each of the multiple light-emitting layers 13 emits light of the same color.

[0065] The following explanation will be based on the example that each light-emitting layer 13 emits light of the same color.

[0066] The single-color light emitted by the light-emitting layer 13 is emitted after passing through the filling part 242, for example, maintaining the same color. The single-color light emitted by the light-emitting layer 13 is converted into another color of light by the color conversion part 241 and emitted, thereby enabling the chip structure 10 to emit light of multiple colors.

[0067] For example, the chip structure 10 includes a functional area AA and a peripheral area AN surrounding the functional area AA. The functional structures in the chip structure 10, such as the light-emitting layer 13, the color conversion part 241, and the filling part 242, are all located within the functional area AA.

[0068] For example, the functional structure of the chip structure 10 also includes an anode and a cathode located on opposite sides of the light-emitting layer 13.

[0069] In the fabrication of chip structures, for example, multiple chip structures are first formed on a motherboard, and then the motherboard is cut to obtain multiple chip structures.

[0070] In some examples, a diamond cutter is used to cut the motherboard; or, an abrasive wheel cutter is used to saw the motherboard.

[0071] Using this method, the edges of the resulting chip structure are prone to defects such as cutting debris and microcracks, leading to a low yield rate. Furthermore, this method results in lower cutting precision and efficiency for the motherboard.

[0072] In other examples, a laser surface cutting process is used to cut the motherboard, where a laser beam is irradiated on one side of the motherboard surface and cuts along the thickness direction of the motherboard.

[0073] To ensure complete separation of the multiple chip structures within the motherboard using this method, the laser beam needs to irradiate from one surface of the motherboard to the opposite surface. The laser beam's energy must be able to penetrate the motherboard; therefore, the energy must be maintained at a high level to achieve proper cutting. Laser cutting generates heat. The higher the laser beam's energy, the larger the heat-affected zone (HAZ). This could lead to the HAZ covering the functional areas of the chip structure, affecting the light-emitting layers and causing the chip structure to malfunction and fail to emit light.

[0074] Based on this, some embodiments of the present disclosure provide a chip structure and its fabrication method, as well as a display device, to overcome the above-mentioned problems. The chip structure 10 and its fabrication method, and the display device 100 provided in some embodiments of the present disclosure are described below.

[0075] In this disclosure, Figure 1 This is a plan view of the display device 100. Figure 2 According to Figure 1 A cross-sectional structural diagram of the display device 100. Figure 9 An enlarged structural view of the alternating original layer 2121 and modified layer 2122 included in the edge portion 212. Figure 6 This is a top view of the coupling structure C. Figure 7 This is a cross-sectional view of the coupled structure C after it has been cut along a cutting path Q. Figure 8 This is an enlarged structural diagram of the cutting channel Q. Figure 10 , Figure 11 and Figure 12 This is a side view of the chip wafer unit 1 during its fabrication process. Figure 13 , Figure 14 and Figure 15 This is a side view of the color conversion unit 2 during its fabrication process. Figure 16 , Figure 17 , Figure 18 and Figure 19 This is a cross-sectional structural diagram showing the steps involved in thinning the substrate mother plate 21' after coupling the initial wafer A and the color conversion substrate B, before laser cutting the substrate mother plate 21'.

[0076] Figure 8 and Figure 20 The diagram shown is a top view of the fabrication process of removing structures such as the light-emitting layer 13 in the chip wafer unit 1 to obtain a chip structure 10 that only includes the substrate 21 and the pad layers (e.g., the first pad 15 and the second pad 16).

[0077] In some embodiments of this disclosure, a display device 100 is provided. For example... Figure 1 and Figure 2 As shown, the display device 100 includes a driving substrate 20 and a plurality of chip structures 10 provided according to any of the above embodiments.

[0078] For example, the driving substrate 20 includes, but is not limited to, FPC (Flexible Printed Circuit) and PCB (Printed Circuit Board).

[0079] For example, a circuit structure is provided on the surface of the driving substrate 20 facing the chip structure 10. The chip structure 10 is provided, for example, through a pad layer (e.g., Figure 2 The first pad 15 and the second pad 16 shown are electrically connected to the circuit structure on the driving substrate 20. The driving substrate 20 is configured to drive the chip structure 10 to emit light.

[0080] In some embodiments, such as Figure 2 As shown, solder paste reflow soldering is used to bond the pad layer (e.g.) Figure 2 The first pad 15 and the second pad 16 shown are soldered onto the circuit structure to connect the chip structure 10 to the driving substrate 20. The driving substrate 20 emits a light-emitting control signal, which is transmitted to the light-emitting layer 13 through the pad layer, thereby driving the light-emitting layer 13 to emit light.

[0081] For example, such as Figure 1 As shown, the display device 100 includes a plurality of chip structures 10 arranged in an array, for example.

[0082] For example, such as Figure 1 As shown, the display device 100 includes a plurality of pixels, and the plurality of pixels includes sub-pixels P (pixels) of at least three colors. The sub-pixels P of at least three colors include at least a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. Wherein, the first color, the second color, and the third color are three primary colors, such as R (Red), G (Green), and B (Blue).

[0083] For example, each chip structure 10 is configured to emit at least one of multiple colors of light.

[0084] In some examples, a single chip structure 10 can emit multiple colors of light. For instance, a single chip structure 10 may include multiple light-emitting regions, each of which can emit a single color of light, and the colors of the light emitted by the multiple light-emitting regions are not exactly the same.

[0085] When the chip structure 10 is applied to the display device 100, a single chip structure 10 can achieve multi-color light output. For example, a single chip structure 10 can achieve R, G, and B three-color light output, thereby enabling the display device 100 to achieve multi-color display.

[0086] It is understood that, given the same chip structure 10 size, in some embodiments of this disclosure, a single chip structure 10 can achieve multi-color light emission. Thus, the light-emitting area corresponding to each color is smaller than that of a single chip structure capable of emitting only monochromatic light, resulting in higher pixel accuracy and better display performance for the display device 100. The specific structure of the chip structure 10 is described below.

[0087] Some embodiments of this disclosure also provide a method for fabricating a chip structure 10.

[0088] like Figure 3 As shown, the fabrication method of the chip structure 10 includes steps S1 to S4.

[0089] S1, such as Figure 4 As shown, an initial wafer A is formed. The initial wafer A includes multiple chip wafer units 1.

[0090] For example, such as Figure 4 As shown, each chip wafer unit 1 includes multiple light-emitting layers 13. Each light-emitting layer 13 is configured to emit one of multiple colors of light. For example, multiple light-emitting layers 13 emit light of the same color; or, at least two of the multiple light-emitting layers 13 emit light of different colors.

[0091] Light of various colors includes, but is not limited to, blue, red, and green light.

[0092] For example, the light-emitting layer 13 is, for example, an MQW (Multiple Quantum Well).

[0093] For example, the shape of the initial wafer A includes, but is not limited to, a circle.

[0094] For example, the shape of the chip wafer unit 1 includes, but is not limited to, a rectangle.

[0095] S2, such as Figure 5As shown, a color conversion substrate B is formed. The color conversion substrate B includes a substrate mother plate 21' and a plurality of color conversion structures J disposed on the substrate mother plate 21'. Each color conversion structure J and its corresponding substrate mother plate 21' constitute a color conversion unit 2.

[0096] For example, the substrate mother plate 21' is made of a transparent material. The material of the substrate mother plate 21' includes, but is not limited to, any one of glass, sapphire, silicon carbide, silicon, gallium arsenide, or aluminum nitride.

[0097] For example, the shape of the color conversion substrate B is the same as the shape of the initial wafer A.

[0098] For example, the shape of the substrate mother plate 21' includes, but is not limited to, a circle.

[0099] For example, the shape of the color conversion unit 2 is the same as the shape of the chip wafer unit 1.

[0100] It should be noted that the order of preparation in steps S1 and S2 is not limited; this is merely an illustration of one possible implementation.

[0101] S3, such as Figure 6 As shown, the color conversion substrate B is coupled to the initial wafer A to obtain the coupling structure C. Each chip wafer unit 1 is opposite to a color conversion unit 2.

[0102] For example, such as Figure 4 and Figure 5 As shown, the initial chip A has a size of 4 inches or 6 inches, and the color conversion substrate B has the same size as the initial chip A.

[0103] For example, such as Figure 2 As shown, the chip wafer unit 1 and the color conversion unit 2 are coupled through the connection layer 3.

[0104] For example, the connecting layer 3 includes, but is not limited to, an adhesive layer or a bonding layer.

[0105] In some examples, a bonding process is used to couple the color conversion substrate B to the initial wafer A.

[0106] In other examples, an adhesive bonding process is used to couple the color conversion substrate B to the initial wafer A.

[0107] This is merely an example of one possible implementation and is not intended to limit the specific implementation disclosed herein.

[0108] S4, such as Figure 7 , Figure 8 and Figure 9As shown, the laser is applied sequentially to multiple focal points D inside the substrate mother plate 21' to cut, so as to form a cutting line inside the substrate mother plate 21'.

[0109] Among them, multiple focal points D are arranged sequentially along the first direction X, which is perpendicular to the surface of the substrate mother plate 21' that is far away from the multiple color conversion structures J.

[0110] After being cut, the substrate mother plate 21' is formed into a plurality of substrates 21. Each substrate 21 includes a main body portion 211 and an edge portion 212 surrounding the main body portion 211. The edge portion 212 includes a primary layer 2121 and a modified layer 2122 alternately arranged along a first direction X, and the layers located on the outermost sides in the first direction X are both primary layers 2121.

[0111] By applying laser light to multiple focal points D inside the substrate mother plate 21' for cutting, the energy of the laser is lower each time the chip structure 10 is formed compared to surface cutting, thereby reducing the range of the heat-affected zone of the laser beam and avoiding the impact of laser cutting on the functional structures in the chip structure 10, such as the light-emitting layer 13, thus avoiding the problem of poor light emission in the chip structure 10.

[0112] It should be noted that during the laser cutting process within the substrate mother plate 21', the area near the laser cut (the heat-affected zone) is heated, and the structure within this area undergoes certain changes under the heat effect of the laser. For example, if the substrate mother plate 21' is glass, when the laser cuts within the substrate mother plate 21', and the laser cuts at any focal point D, the chemical bonds of the atoms within the heat-affected zone centered on focal point D, such as Si-O bonds (silicon-oxygen covalent bonds), break under the laser's action, resulting in a stress layer within the substrate mother plate 21'. The portion between any two stress layers is not affected by the laser's heat, therefore, the atoms within it maintain their original structure without change. Thus, in the chip structure 10, a special structure is formed in the edge portion 212 of the substrate 21, comprising alternating original layers 2121 and modified layers 2122, where the modified layer 2122 is the stress layer generated during the laser cutting process.

[0113] The substrate 21 is cut from the substrate mother plate 21'. The side surface of the substrate 21 is the cutting surface of the substrate mother plate 21' (the surface obtained by laser cutting); or, the side surface of the substrate 21 is a part of the side surface of the substrate mother plate 21'.

[0114] For example, such as Figure 8As shown, in the coupling structure C, the interval between the functional areas AA of any two chip structures 10 is a dicing track Q. The substrate mother plate 21' includes multiple dicing tracks Q, and the laser cuts along each dicing track Q. When the laser cuts along a dicing track Q, the laser sequentially acts on N focal points D within the substrate mother plate 21', and these N focal points are all located within a dicing track Q, where N is a positive integer and N≥2. When cutting each dicing track Q, the number of focal points D acted on by the laser may be the same or not exactly the same.

[0115] The following description uses laser cutting within a single cutting path Q as an example. The laser acts on N focal points D within the substrate mother plate 21' to perform the cutting, including the following steps.

[0116] like Figure 9 As shown, firstly, the energy focusing point of the laser beam is aligned with the first focal point D(1), and then the laser beam moves along... Figure 8 The laser beam moves within the cutting path Q in the Y or Z direction shown, and the path of the laser beam is the laser cutting path. The laser cutting path is located in the plane parallel to the first surface 21'a or the second surface 21'b of the substrate mother plate 21', where the focal point D is located, and the laser cutting path is parallel to... Figure 8 The Y direction or Z direction is shown in the diagram.

[0117] Repeat the above steps until the energy focus of the laser beam is aligned with the Nth focus D(n), and complete the cutting of the substrate mother plate 21'.

[0118] See Figure 9 When the laser acts on any focal point D to cut, a modified layer 2122 is formed in the substrate mother plate 21'. When the laser acts on N focal points D in sequence to cut, N modified layers 2122 are formed accordingly.

[0119] Each laser cut follows a path within a single cutting track Q. The laser may employ a 3-focus or 4-focus cutting method. It should be noted that the use of a 3-focus or 4-focus cutting method here refers to the laser sequentially striking three or four focal points within the substrate mother plate 21' for cutting. The number of focal points used in laser cutting is merely an example of a possible implementation and is not intended to limit the specific embodiments of this disclosure.

[0120] During the fabrication of chip structure 10, the laser cuts a total of M cutting tracks Q, where M is a positive integer. The laser sequentially cuts the first cutting track Q(1) to the m-th cutting track Q(m).

[0121] In some examples, when laser cutting the first to the mth cutting tracks Q, the number of focal points D N used for each cut is the same.

[0122] For example, when laser cutting the first cutting track Q(1) to the m-th cutting track Q(m), 3-focal cutting is used.

[0123] In other examples, when laser cutting the first to the mth cutting tracks Q, the number N of focal points D used for each cut is not exactly the same.

[0124] For example, when laser cutting the first cutting track Q(1), 3-focal cutting is used; when laser cutting the second cutting track Q(2), 4-focal cutting is used; when laser cutting the third cutting track Q(3), 3-focal cutting is used; when laser cutting the m-th cutting track Q(m), 5-focal cutting is used.

[0125] For example, when laser cutting the first to the mth cutting tracks Q, the number N of focal points D used for each cut is different.

[0126] For example, the chip structure 10 includes a plurality of side surfaces of the substrate 21, which are cut surfaces of the substrate mother plate 21'. The plurality of side surfaces are obtained after laser cutting of a plurality of dicing tracks Q. It can be understood that when the laser cuts the plurality of dicing tracks Q, the number of focal points D acting on the substrate mother plate 21' each time is the same. At this time, the plurality of side surfaces of the substrate 21 include the same number of modified layers 2122. When the laser cuts the plurality of dicing tracks Q, the number of focal points D acting on the substrate mother plate 21' each time is not exactly the same. At this time, the plurality of side surfaces of the substrate 21 include the same number of modified layers 2122.

[0127] This is reflected in chip structure 10, such as Figure 8 As shown, the substrate 21 has a special structure including a main body 211 and an edge portion 212 surrounding the main body 211. The edge portion 212 includes multiple sub-parts 212(k) corresponding one-to-one with multiple side surfaces of the substrate 21 (k is the number of side surfaces of the substrate 21, and each of the k side surfaces corresponds to one of the k sub-parts of the edge portion 212). The multiple sub-parts 212(k) of the edge portion 212 include the same number of modified layers 2122; or, the multiple sub-parts of the edge portion 212 include different numbers of modified layers 2122. The number of modified layers 2122 included in each sub-part 212(k) of the edge portion 212 is the same as the number of focal points D when laser cutting that portion.

[0128] like Figure 8As shown, the substrate 21 is, for example, rectangular and includes four side surfaces. Correspondingly, the edge portion 212 of the substrate 21 includes four sub-portions, namely a first sub-portion 212(1), a second sub-portion 212(2), a third sub-portion 212(3), and a fourth sub-portion 212(4). The first sub-portion 212(1), the second sub-portion 212(2), the third sub-portion 212(3), and the fourth sub-portion 212(4) each include, for example, four modified layers 2122. Alternatively, the first sub-part 212(1) and the second sub-part 212(2) include 3 layers of modified layers 2122, and the third sub-part 212(3) and the fourth sub-part 212(4) include 4 layers of modified layers 2122; or, the first sub-part 212(1) includes 3 layers of modified layers 2122, the second sub-part 212(2) includes 4 layers of modified layers 2122, and the third sub-part 212(3) and the fourth sub-part 212(4) include 5 layers of modified layers 2122.

[0129] The laser beam originates from one side of the conversion substrate B and cuts through multiple focal points D within the coupling structure C. For example... Figure 7 As shown, when laser cutting the coupling structure C, if the laser cuts the substrate mother plate 21' from the initial wafer A side, the distance between the laser emission position and the focal point D is farther than when the laser cuts the substrate mother plate 21' from the conversion substrate B side. It can be understood that the farther the distance between the laser emission position and the focal point D, the more difficult it is to accurately locate the focal point D. When the focal point D shifts and exceeds the range corresponding to the cutting path Q, for example, if the focal point D is located within the functional area AA of the chip structure 10, the functional structures within the functional area AA may be damaged by laser irradiation during laser cutting, resulting in abnormal light emission from the chip structure 10.

[0130] The following explanation will be based on the example where each sub-part of the edge portion 212 includes the same number of modified layers 2122.

[0131] In some embodiments, in step S4, such as Figure 7 As shown, the color conversion substrate B side of the self-coupling structure C is cut to the substrate mother plate 21'.

[0132] In some examples, the distance between any two adjacent chip structures in the multiple chip wafer units included in the initial wafer ranges from 20 μm to 100 μm.

[0133] In some embodiments of this disclosure, a multi-focal cutting method is used to cut the substrate mother plate 21', which can effectively narrow the width of the cutting path Q, such as... Figure 8 As shown, in the initial wafer A, which includes multiple chip wafer units 1, the distance d4 between any two adjacent chip structures 10 ranges from 20μm to 50μm.

[0134] like Figure 7 As shown, when the distance d4 between the functional areas AA of any two adjacent chip structures arranged in the coupling structure C is small, for example, when the distance d4 is in the range of 20μm to 50μm, this method makes the distance between the laser emission position and the focal point D closer, which is more conducive to the accurate positioning of the focal point D. This avoids the problem that the laser focal point D is not easy to align due to the small size of the cutting path Q, and deviates from the cutting path Q.

[0135] Understandably, to ensure that the resulting multiple chip structures 10 have the same or approximately the same size, the laser cutting path is collinear or approximately collinear with the axis of symmetry of the cutting track Q. For example... Figure 8 As shown, the cutting path Q is, for example, rectangular. A rectangle has two axes of symmetry. The axis of symmetry for the cutting path Q is the axis of symmetry that extends along the length of the cutting path Q. For example, Figure 8 The laser cutting path shown in the figure is collinear or approximately collinear with the axis of symmetry of the cutting path Q extending in the direction Z shown in the figure.

[0136] In some embodiments, in step S4, such as Figure 9 As shown, the laser sequentially acts on N focal points D inside the substrate mother plate 21' for cutting, where N is a positive integer and N≥2. The focal point D furthest from the initial wafer A is the first focal point D(1), and the focal point D closest to the initial wafer A is the Nth focal point D(n). The surface of the substrate mother plate 21' furthest from the initial wafer A is the first surface 21'a, and the surface of the substrate mother plate 21' closest to the initial wafer A is the second surface b.

[0137] In some examples, such as Figure 9 As shown, the distance d1 between the first focus D(1) and the first surface 21'a is greater than or equal to the distance d2 between any two adjacent focuses D.

[0138] When the material of the substrate mother plate 21' is glass, when the laser acts on the focal point D position inside the substrate mother plate 21', cracks will be generated inside the substrate mother plate 21' near the focal point D, and the cracks will extend from the focal point D position to a certain area. By controlling the distance d1 between the first focal point D (1) and the first surface 21'a, the cracks generated inside the substrate mother plate 21' when the laser acts on the substrate mother plate 21' are prevented from extending to the first surface 21'a of the substrate mother plate 21', thereby avoiding the problem of the first surface 21'a of the substrate mother plate 21' cracking and fragmentation.

[0139] In other examples, such as Figure 9As shown, the distance d3 between the Nth focus D(n) and the second surface 21'b is greater than or equal to the distance d2 between any two adjacent focuses D.

[0140] By controlling the distance d1 between the Nth focal point D(n) and the second surface 21'b, the cracks generated inside the substrate mother plate 21' when the laser acts on the interior of the substrate mother plate 21' are prevented from extending to the second surface 21'b of the substrate mother plate 21', thereby avoiding the problem of cracking and fragmentation of the second surface 21'b of the substrate mother plate 21'.

[0141] In some other examples, such as Figure 9 As shown, the distance d1 between the first focus D(1) and the first surface 21'a is greater than or equal to the distance d2 between any two adjacent focuses D, and the distance d3 between the Nth focus D(n) and the second surface 21'b is greater than or equal to the distance d2 between any two adjacent focuses D.

[0142] Referring to the previous description, by controlling the distance d1 between the first focal point D(1) and the first surface 21'a, and the distance d3 between the Nth focal point D(n) and the second surface 21'b, when the laser acts on the substrate mother plate 21' for cutting, the crack generated in the substrate mother plate 21' will not extend to the surface of the substrate mother plate 21', thereby avoiding the problem of chipping and fragmentation on the surface of the substrate mother plate 21'.

[0143] For example, the distance d2 between any two adjacent foci D can range from 15 μm to 35 μm. d2 can be, for example, 15 μm, 20 μm, or 35 μm.

[0144] For example, the distance d1 between the first focal point D(1) and the first surface 21'a of the substrate mother plate 21' ranges from 15μm to 35μm. d1 is, for example, 15μm, 20μm or 35μm. Further, the distance d1 between the first focal point D(1) and the first surface 21'a of the substrate mother plate 21' is greater than or equal to 20μm.

[0145] For example, the distance d3 between the Nth focal point D(n) and the second surface 21'b of the substrate mother plate 21' ranges from 15 μm to 35 μm. d3 is, for example, 15 μm, 20 μm, or 35 μm. Further, the distance d3 between the Nth focal point D(n) and the second surface 21'b of the substrate mother plate 21' is greater than or equal to 20 μm.

[0146] By appropriately increasing the distance d1 between the first focal point D(1) and the first surface 21'a of the substrate mother plate 21', and the distance d3 between the Nth focal point D(n) and the second surface 21'b of the substrate mother plate 21', it is possible to effectively prevent the cracks generated inside the substrate mother plate 21' when the laser acts on the focal point for cutting, so that they do not extend to the surface of the substrate mother plate 21', thereby avoiding the problem of chipping and fragmentation on the surface of the substrate mother plate 21'.

[0147] It should be noted that, provided that d1≥d2 and d3≥d2, the value of d1+k×d2+d3 should also be equal to the thickness of the substrate mother plate 21' (e.g., along the...). Figure 9 (The dimension in the direction Z shown). k is the number of spacings d2 between the N foci arranged along the first direction X, k = N-1.

[0148] For example, the thickness of the substrate mother plate 21' is 100 μm. The following description uses a substrate mother plate 21' with a thickness of 100 μm as an example.

[0149] In some examples, three focal points are used for cutting, N=3. The laser acts sequentially on three focal points D inside the substrate mother plate 21' for cutting, d1+2×d2+d3=100μm.

[0150] For example, if the distance d2 between any two adjacent foci D is 18 μm, then d1 + d3 = 100 - 18 × 2 = 64 μm. In this case, d1 = d3 = 32 μm; or d1 = 29 μm, d3 = 35 μm; or d1 = 35 μm, d3 = 29 μm; or d1 = 31 μm, d3 = 33 μm.

[0151] For example, if the distance d2 between any two adjacent foci D is 15μm, then d1+d3=100-15×2=70μm, and in this case, d1=d3=35μm.

[0152] In other examples, four focal points are used for cutting, N=4. The laser sequentially acts on four focal points D inside the substrate mother plate 21' for cutting, d1+3×d2+d3=100μm.

[0153] For example, if the distance d2 between any two adjacent foci D is 18 μm, then d1 + d3 = 100 - 18 × 3 = 46 μm. In this case, d1 = d3 = 23 μm; or d1 = 18 μm, d3 = 28 μm; or d1 = 28 μm, d3 = 18 μm; or d1 = 20 μm, d3 = 23 μm.

[0154] For example, if the distance d2 between any two adjacent foci D is 15μm, then d1+d3=100-15×3=55μm. In this case, d1=20μm, d3=35μm; or d1=35μm, d3=20μm; or d1=25μm, d3=30μm.

[0155] It should be noted that the dimensions of the substrate mother plate 21', the distance d2 between any two adjacent focal points D, and the distance (d1 and d3) between the focal point D and the surface of the substrate mother plate 21' are only examples of possible implementations and are not intended to limit the specific implementation of this disclosure.

[0156] For example, such as Figure 9 As shown, the laser sequentially acts on N focal points D inside the substrate mother plate 21' to cut, forming N modified layers 2122 arranged sequentially along the first direction X, and the spacing between any two adjacent modified layers 2122 along the first direction X is greater than 0.

[0157] In some embodiments of this disclosure, a laser is applied to the substrate mother plate 21' to cut, thereby obtaining multiple chip structures 10. It is understood that the opposing side surfaces of the substrate mother plate 21 included in any two adjacent chip structures 10 are cut surfaces, obtained by cutting within the substrate mother plate 21' using a laser. During the laser cutting process, the area near the laser cut (the heat-affected zone of the laser) is heated, and the structure in this area undergoes certain changes under the heat effect of the laser.

[0158] It should be noted that the stress in the portion of the substrate mother plate 21' near the focal point D, which is within the laser heat-affected zone, is different from that in other locations outside the laser heat-affected zone. In the chip structure 10, this is reflected in the fact that the stress of the original layer 2121 and the modified layer 2122 included in the edge portion 212 is different. At the same time, the main body portion 211 and the original layer 2121 are both portions that are not affected by laser heat, therefore, the stress of the main body portion 211 and the original layer 2121 is the same.

[0159] Under the influence of laser light, cracks will form within the substrate mother plate 21', extending from the focal point D in a direction away from the focal point D. The direction of crack extension is divergent and irregular. Therefore, the light reflectivity (e.g., reflectivity for light in the wavelength range of 380μm to 780μm) of the portion of the substrate mother plate 21' near the focal point D within the laser heat-affected zone differs from that of the rest of the substrate mother plate 21'. In the chip structure 10, this manifests as different light reflectivities between the original layer 2121 and the modified layer 2122, while the original layer 2121 and the main body 211 have the same light reflectivity.

[0160] By controlling the energy of the laser beam within a certain range, the laser beam acts on the focal point D with lower energy. This results in a smaller heat-affected zone and, consequently, a smaller crack extension range when the laser acts on the focal point D. After sequentially cutting multiple focal points D, the resulting multi-layered modified layers 2122 will have a certain spacing along the first direction X and will not connect. Simultaneously, because the crack extension range when the laser acts on the focal point D is smaller, in the final chip structure 10, the modified layer 2122 only exists within the peripheral region AN of the chip structure 10 and does not extend into the functional region AA. This ensures that when the light emitted from the chip wafer unit 1 passes through the color conversion unit 2 and exits, the portion of the substrate 21 located within the functional region AA has better light reflectivity, thus guaranteeing the light-emitting effect of the chip structure 10.

[0161] The outermost layers of the edge portion 212 in the first direction X are both original layers 2121, and the original layers 2121 and the modified layers 2122 are alternately arranged. It can be understood that the original layers 2121 have one more layer than the modified layers 2122, and the number of original layers 2121 is P, where P = N + 1.

[0162] By employing a multi-focal cutting method, the laser sequentially acts on N focal points D within the substrate mother plate 21'. When laser cutting a substrate mother plate 21' of the same thickness, the larger the value of the number of focal points D N, the smaller the energy value of the laser beam acting on a single focal point D can be, and the smaller the heat-affected zone during laser cutting. Thus, when forming the coupling structure C, the size of the distance d4 between any two adjacent chip structures 10 can also be smaller, thereby allowing more chip structures 10 to be set within the coupling structure C of the same size, thereby reducing the manufacturing cost of the chip structure 10.

[0163] Referring to the previous description of step S4 (applying the laser sequentially to multiple focal points D inside the substrate mother plate 21' to cut, thereby forming a cutting line inside the substrate mother plate 21'), when laser cutting the coupling structure C, a multi-focal cutting method is adopted. The laser sequentially applies the laser to multiple focal points D inside the substrate mother plate 21' to cut. In this way, the energy of the laser beam each time the laser acts is smaller than that of the surface cutting method. Correspondingly, the range of the heat-affected zone will be smaller, thereby making the spacing between the chip structures 10 arranged in the coupling structure C smaller, that is, the width of the cutting track Q is narrower. More chip structures 10 can be cut from the coupling structure C of the same size. It can be understood that in this way, more chip structures 10 can be prepared with the same amount of time and materials, reducing the preparation cost of chip structures 10 and improving the preparation efficiency of chip structures 10.

[0164] like Figure 8As shown, the area between any two adjacent functional areas AA of the chip structure 10 is the dicing track Q. When the laser acts on the substrate mother plate 21' to cut, multiple focal points D are located within the same dicing track Q. The laser cuts along the cutting surface, which is the plane perpendicular to the first surface 21'a or the second surface 21'b of the substrate mother plate 21' where the multiple focal points D are located. The cutting surface roughly divides the dicing track Q into two parts (these two parts are the same or approximately the same size).

[0165] For example, such as Figure 7 As shown, during the fabrication of the chip structure 10, the wavelength of the laser is less than 2000nm each time the substrate mother plate 21' is cut by laser.

[0166] For example, each time the substrate motherboard 21' is cut with a laser, the wavelength of the laser used is 1024nm.

[0167] To clearly describe the fabrication method of the chip structure 10, the following description uses the formation of a single chip structure 10 as an example. It can be understood that the fabrication method of this chip structure 10 involves first forming a coupling structure C comprising multiple chip structures 10 arranged in an array, and then obtaining multiple chip structures 10 by cutting the coupling structure C.

[0168] The following describes the specific implementation methods of each step in the fabrication method of chip structure 10. The chip structure 10 formed according to this embodiment is... Figure 1 and Figure 2 The chip structure shown is 10.

[0169] For example, step S1 (forming an initial wafer A, which includes a plurality of chip wafer units 1) includes steps S11 to S16.

[0170] S11, such as Figure 10 As shown, a buffer layer 11 and an N-type gallium nitride layer 12 are formed on the first substrate W1.

[0171] For example, such as Figure 10 As shown, the first substrate W1 is a silicon-based substrate or a sapphire substrate.

[0172] For example, such as Figure 10 As shown, the buffer layer 11 and the N-type gallium nitride layer 12 are formed, for example, by metal sputtering or chemical deposition.

[0173] S12, such as Figure 10 As shown, a plurality of light-emitting layers 13 are formed on the side of the N-type gallium nitride layer 12 away from the first substrate W1.

[0174] In some embodiments, each of the plurality of light-emitting layers 13 is configured, for example, to emit one of a plurality of colors of light.

[0175] In some examples, multiple light-emitting layers 13 emit light of the same color, for example.

[0176] For example, multiple colors of light include, but are not limited to, blue light.

[0177] For example, such as Figure 10 As shown, the light-emitting layer 13 includes, for example, a quantum well layer.

[0178] For example, the quantum well layer is a blue quantum well, and the light-emitting layer 13, which includes the blue quantum well, emits blue light.

[0179] For example, the quantum well layer is a red quantum well, and the light-emitting layer 13 of the red quantum well emits red light.

[0180] For example, the quantum well layer is a green quantum well, and the light-emitting layer 13 of the green quantum well emits green light.

[0181] S13, such as Figure 10 As shown, a cathode transfer electrode 14 is formed on the side of the N-type gallium nitride layer 12 away from the first substrate W1.

[0182] For example, the cathode transfer electrode 14 and the plurality of light-emitting layers 13 are disposed in the same layer.

[0183] For example, such as Figure 8 As shown, the chip structure 10 includes a functional area AA, which includes a connection area A1 and multiple light-emitting areas A2. The connection area A1 and the multiple light-emitting areas A2 are arranged in an array, for example. Each connection area A1 is provided with a cathode transfer electrode 14.

[0184] Each light-emitting region A2 is provided with at least one light-emitting layer 13. When each light-emitting region A2 includes multiple light-emitting layers 13, the multiple light-emitting layers 13 are connected to each other. The multiple light-emitting layers 13 in each light-emitting region A2 can be connected in series or in parallel, for example.

[0185] For example, the cathode transfer electrode 14 is made of a conductive material. The material of the cathode transfer electrode 14 includes, but is not limited to, at least one of gold, silver, lead, tin, copper, titanium, aluminum, molybdenum, nickel-gold, and conductive silver paste.

[0186] S14, such as Figure 10 As shown, a pad layer is formed on the side of the plurality of light-emitting layers 13 away from the first substrate W1. The pad layer includes a second pad 16 and a plurality of first pads 15 corresponding one-to-one with the plurality of light-emitting layers 13.

[0187] For example, the material of the pad layer is a conductive material.

[0188] The materials of the pad layer include, but are not limited to, at least one of gold, silver, copper, titanium, aluminum, molybdenum, niobium, nickel gold, and conductive silver paste.

[0189] In some examples, the pad layer is a single-layer structure.

[0190] For example, the pad layer is a copper layer.

[0191] In other examples, the pad layer has a multi-layer structure.

[0192] For example, the pad layer is a stacked structure formed by sequentially stacking MoNb / Cu / CuNi (molybdenum-niobium alloy / copper / copper-nickel alloy).

[0193] For example, the pad layer is configured to enable the connection between the chip structure 10 and other structures; the pad layer is also configured to transmit electrical signals.

[0194] In some examples, such as Figure 1 and Figure 2 As shown, when the chip structure 10 is applied in the display device 100, multiple chip structures 10 are disposed on the driving substrate 20 (e.g., FPC or PCB). Each chip structure 10 is connected to the driving substrate 20 via a first pad 15 and a second pad 16 in the pad layer. For example, the first pad 15 and the second pad 16 are soldered to the circuit structure of the driving substrate 20 using solder paste reflow soldering, thereby realizing the connection between the chip structure 10 and the driving substrate 20. The electrical signals emitted by the driving substrate 20 are transmitted to the chip structure 10 through the pad layer.

[0195] S15, such as Figure 11 As shown, a second substrate W2 is formed on the side of the pad layer away from the first substrate W1.

[0196] For example, the second substrate W2 includes, but is not limited to, any one of glass, sapphire, and PI film (polyimide film).

[0197] S16, as Figure 12 As shown, the first substrate W1 is removed.

[0198] For example, referring to the previous description of step S3 (coupling the color conversion substrate B with the initial wafer A to obtain the coupling structure C), the side of the color conversion structure J away from the second substrate W2 is configured to be connected to the chip wafer unit 1. The second substrate W2 serves as a temporary carrier, supporting the color conversion structure J after the first substrate W1 is removed and before the color conversion structure J is connected to the chip wafer unit 1.

[0199] In some embodiments, step S2 (forming color conversion substrate B) includes steps S21 to S24.

[0200] S21, such as Figure 13 As shown, a color filter layer 22 is formed on a substrate mother plate 21'. The color filter layer 22 includes a black matrix 221 and a plurality of filter sections 222 defined by the black matrix 221.

[0201] For example, the thickness of the substrate mother plate 21' is h1.

[0202] For example, the color filter layer 22 is formed by coating, exposure, development, post-baking, etc.

[0203] For example, a black matrix 221 and multiple filter sections 222 defined by the black matrix 221 are formed by means of coating, exposure, development, and post-baking.

[0204] For example, each filter element 222 is disposed corresponding to at least one light-emitting layer 13. The plurality of filter elements 222 may include, for example, a first filter element, a second filter element, and a third filter element. The first filter element, the second filter element, and the third filter element are respectively disposed opposite to at least one light-emitting layer 13.

[0205] When each light-emitting area A2 includes multiple light-emitting layers 13, the multiple light-emitting layers 13 in each light-emitting area A2 are all disposed corresponding to the same filter unit 222; or, the multiple light-emitting layers 13 in each light-emitting area A2 are disposed corresponding to multiple filter units 222 respectively.

[0206] For example, the substrate mother plate 21' includes, but is not limited to, a glass substrate, a quartz substrate, a plastic substrate, a sapphire substrate, or a silicon substrate.

[0207] In the chip structure 10, the light emitted from the light-emitting layer 13 is emitted after passing through the light-filtering section 222. By providing the light-filtering section 222, the color gamut of the light emitted from the light-emitting layer 13 can be improved, thereby improving the color gamut of the light emitted from the chip structure 10.

[0208] S22, such as Figure 14 As shown, a limiting dam layer 23 is formed. The limiting dam layer 23 is disposed on the side of the color filter layer 22 away from the substrate mother plate 21', and the limiting dam layer 23 includes a plurality of opening regions 231 corresponding to a plurality of filter sections 222.

[0209] For example, the defined dam layer 23 is formed by coating, exposure, development, post-baking, etc.

[0210] For example, the plurality of opening regions 231 include a first type of opening region 2311 corresponding to the first filter and the second filter and a second type of opening region 2312 corresponding to the third filter.

[0211] Each first-class opening region 2311 corresponds to a first filter section or a second filter section.

[0212] S23, such as Figure 14 As shown, a color conversion layer 24 is formed. The color conversion layer 24 includes a plurality of color conversion portions 241 and filling portions 242 disposed within the opening area 231.

[0213] For example, a color conversion layer 24 is formed in the opening area by means of coating, exposure, development, post-baking, or inkjet printing.

[0214] For example, a quantum dot conversion section is formed within the first type of opening region 2311. The light-emitting layer 13 in the light-emitting region A2 corresponding to the first type of opening region 2311 emits colored light, which is converted into another color of light after passing through the quantum dot conversion section.

[0215] For example, the quantum dot conversion unit uses red quantum dot luminescent materials or red fluorescent materials.

[0216] For example, the quantum dot conversion unit uses green quantum dot luminescent materials or green fluorescent materials.

[0217] It should be noted that the material of the quantum dot conversion unit can be any material capable of color conversion. This is only an example of one possible implementation and is not intended to limit the specific implementation of this disclosure.

[0218] For example, a scattering particle section is formed within the second type of opening region 2312. The scattering particle section may employ scattering particles.

[0219] It should be noted that the scattering particle section has good light transmittance. After the light emitted by the chip wafer unit 1 passes through the scattering particle section, the intensity of the light does not change significantly and remains basically unchanged, thereby ensuring the light output effect of the chip structure 10.

[0220] The light emitted by the light-emitting layer 13 in the light-emitting region A2 corresponding to the second type of opening region 2312 retains the same color after passing through the scattering particles. The scattering particles fill the second type of opening region 2312, resulting in better uniformity of the thickness of the limiting dam layer 23, and thus better uniformity of the thickness of the chip structure 10.

[0221] S24, such as Figure 15 As shown, an encapsulation layer 25 is formed. The encapsulation layer 25 covers the color filter layer 22, the limiting dam layer 23, and the color conversion layer 24.

[0222] For example, the material of the encapsulation layer 25 has good sealing and heat resistance. The material of the encapsulation layer 25 includes, but is not limited to, silicon nitride, silicon oxide, or silicon oxynitride.

[0223] For example, the encapsulation layer 25 is formed by deposition using a CVD (chemical vapor deposition) process.

[0224] By setting the encapsulation layer 25, the color conversion layer 24 can be effectively prevented from being corroded by water and oxygen or subjected to mechanical damage due to long-term exposure to air, thus affecting its color conversion effect. This improves the operational stability of the color conversion layer 24 and consequently the operational stability of the chip structure 10. Simultaneously, it provides the color conversion layer 24 with better luminous efficiency and heat dissipation, thereby extending its lifespan and, consequently, the lifespan of the chip structure 10.

[0225] In some embodiments, step S3 (coupling the color conversion substrate B with the initial wafer A to obtain the coupling structure C) includes steps S31 to S36, or includes steps S31 to S37.

[0226] S31, such as Figure 15 As shown, a connecting layer 3 is formed on the side of the encapsulation layer 25 away from the substrate mother plate 21'.

[0227] For example, the chip wafer unit 1 and the color conversion unit 2 are bonded together, for example, by a bonding layer 3. The bonding effect of the bonding layer 3 can be adhesive bonding or metal bonding.

[0228] This is merely an example of one possible implementation and is not intended to limit the specific implementation disclosed herein.

[0229] S32, such as Figure 16 As shown, the chip wafer unit 1 and the color conversion unit 2 are coupled together through the connection layer 3.

[0230] S33, such as Figure 17 As shown, the second substrate W2 is removed.

[0231] S34, such as Figure 18 As shown, a protective film 4 is applied to one side of the chip wafer unit 1. The protective film 4 covers the remaining parts of the chip wafer unit 1 and the color conversion unit 2 except for the substrate mother plate 21'. The protective film 4 also covers the second surface 21'b of the substrate mother plate 21' and the portions of multiple side surfaces of the substrate mother plate 21' near the second surface 21'b.

[0232] For example, the protective film 4 includes, but is not limited to, an acid-resistant film.

[0233] S35, such as Figure 17 As shown, the substrate mother plate 21' is thinned.

[0234] For example, such as Figure 17 and Figure 18As shown, the substrate mother plate 21' is, for example, a glass substrate. When thinning the substrate mother plate 21', the chip wafer unit 1 covered with the protective film 4 is placed in an etching solution (e.g., potassium nitrate solution). The portion covered by the protective film 4 is not damaged by the etching solution, while the exposed portion of the substrate mother plate 21' is etched and thinned under the action of the etching solution. The thickness of the substrate mother plate 21' is reduced from h1 to h2.

[0235] S36, such as Figure 19 As shown, remove the protective film 4.

[0236] In some embodiments, step S37 is included after step S36.

[0237] S37, such as Figure 7 As shown, a third substrate W3 is attached to one side of the chip wafer unit 1.

[0238] For example, the third substrate W3 has high temperature resistance and good ductility.

[0239] The third substrate W3 includes, but is not limited to, the blue film.

[0240] This is merely an example of one possible implementation and is not intended to limit the specific implementation of this disclosure.

[0241] Furthermore, after step S4 (cutting by sequentially applying the laser to multiple focal points D inside the substrate mother plate 21'), steps S5 and S6 are also included.

[0242] S5. Apply pressure to the substrate mother plate 21' from the side away from the chip wafer unit 1, so that the substrate mother plate 21' is broken along the cutting surface.

[0243] Since the cracks generated by the laser in the substrate mother plate 21' during the laser cutting process do not extend to the surface of the substrate mother plate 21', it is understandable that the multiple chip structures 10 have not been completely separated at this time. Therefore, it is necessary to press and split the coupling structure C after laser cutting so that the substrate mother plate 21' can be broken along the cutting surface, so that the multiple chip structures 10 can be completely separated from each other.

[0244] S6, such as Figure 20 As shown, the third substrate W3 extends along the second direction Y and the third direction Z, and the spacing between any two adjacent chip structures 10 is greater than zero.

[0245] For example, such as Figure 20As shown, in step S6, the distance k between any two adjacent chip structures 10 changes from 0 in step S4 to k. For example, the range of k is 20μm to 30μm.

[0246] By step S6, after extending the third substrate W3, it is possible to further separate the multiple chip structures 10 from each other. For example, in step S5, the adjacent side surfaces of the substrates 21 of some adjacent chip structures 10 are not completely separated. By step S6, the incompletely separated portions of the adjacent substrates 21 can be further separated.

[0247] It should be noted that the size of k is related to the ductility of the third substrate W3, and is set according to the actual situation during the fabrication of the chip structure 10. This is only an example of a possible implementation and is not intended to limit the specific implementation of this disclosure.

[0248] S7. Remove the third substrate W3.

[0249] For example, after step S6, the substrate mother plate 21' is divided into multiple substrates 21 along the cutting surface, and each substrate 21 corresponds to a chip structure 10. At this time, multiple chip structures 10 located on the third substrate W3 are obtained. After removing the third substrate W3, multiple chip structures 10 are obtained.

[0250] In step S5, the separation of multiple substrates 21 is achieved, so that multiple chip structures 10 are separated from each other; in step S6, during the process of extending and unfolding the third substrate W3, the distance between multiple chip structures 10 also increases. For example, multiple chip structures 10 are picked up and removed from the third substrate W3 by a gripping device, thus increasing the gripping space for the chip structures 10 and making it easier to separate multiple chip structures 10 from the third substrate W3.

[0251] It is understandable that the purpose of setting the third substrate W3 in the aforementioned steps is to ensure that the multiple chip structures 10 can be held on one side of the third substrate W3 during the processes of step S5 (cracking) and step S6 (film expansion), so as to prevent the chip structures 10 from accidentally falling and causing damage.

[0252] It is understandable that in step S4, if the substrate mother plate 21' has been completely separated after laser cutting and the multiple chip structures 10 have become independent structures, then steps S5 and S6 are not required.

[0253] Some embodiments of this disclosure provide a chip structure 10. The chip structure 10 is fabricated, for example, using the fabrication method described above.

[0254] like Figure 1 and Figure 2 As shown, the chip structure 10 includes a chip wafer unit 1 and a color conversion unit 2 disposed on the light-emitting side of the chip wafer unit 1. The color conversion unit 2 includes a substrate 21, which includes a main body portion 211 and an edge portion 212 surrounding the main body portion 211. The edge portion 212 includes a primary layer 2121 and a modified layer 2122 alternately disposed along a first direction X. The primary layer 2121 and the modified layer 2122 have different light reflectivities.

[0255] In the edge portion 212, the layers located on both outermost sides in the first direction X are the original layers 2121. The first direction X is perpendicular to the surface of the substrate 21 that is away from the chip wafer unit 1.

[0256] For example, the light reflectivity mentioned herein refers to the reflectivity of the original layer 2121 and the modified layer 2122 for light with a wavelength range of 380μm to 780μm.

[0257] For example, during the fabrication of the chip structure 10, referring to the description of the chip structure fabrication method above, the laser sequentially acts on N focal points inside the substrate mother plate 21' to cut it. The modified layer 2122 is the part of the substrate mother plate 21' that is close to the laser cutting surface and undergoes structural changes due to the laser. The original layer 2121 is the part of the substrate mother plate 21' that is close to the laser cutting surface and is not affected by the laser, maintaining the original structure.

[0258] It should be noted that the substrate 21 is cut from the substrate mother plate 21', and the side surface of the substrate 21 is the cutting surface of the substrate mother plate 21'; or, the side surface of the substrate 21 is a part of the side surface of the substrate mother plate 21'. The original layer 2121 and the modified layer 2122 are both generated by laser cutting within the substrate mother plate 21'.

[0259] The structural changes described herein include, but are not limited to, changes in the atomic structure of the material based on the substrate 21 (e.g., chemical bonds of atoms within the glass in the laser heat-affected zone, such as Si-O bonds breaking under laser irradiation, resulting in changes in atomic structure) and / or visible surface cracks.

[0260] For example, such as Figure 2 As shown, the substrate 21 includes a functional region AA and a peripheral region AN surrounding the functional region AA. The orthographic projection of the chip wafer unit 1 on the substrate 21 is located in the functional region AA. The main body portion 211 is located at least in the functional region AA, and the edge portion 212 is located within the peripheral region AN.

[0261] For example, the substrate 21 is made of a transparent material. The material of the substrate 21 includes, but is not limited to, glass.

[0262] For example, referring to the preceding description of the fabrication method of the chip structure 10, the multiple side surfaces of the substrate 21 are cut surfaces obtained by laser cutting the substrate mother plate 21' during the formation of the chip structure 10. For example, when the material of the substrate mother plate 21' is glass, cracks will be generated on the cut surfaces during laser cutting, causing structural changes in that part, resulting in changes in the light reflectivity and stress of that part. However, inside the substrate 21, it is not affected by the laser and maintains the original structure of the material (the light reflectivity and stress do not change). This forms a special structure in which the substrate 21 includes a main body portion 211 and an edge portion 212, and the edge portion 212 includes alternating original layers 2121 and modified layers 2122.

[0263] Referring to the preceding description of the fabrication method of chip structure 10, it can be understood that the substrate 21 is a single integral structure. The main body 211 and the edge 212 are merely divisions indicating whether the substrate 21 is affected by laser cutting during the fabrication of chip structure 10, rather than indicating that the substrate 21 is composed of two combined structures. The main body 211 is the part of the substrate 21 that is not affected by laser during the fabrication of chip structure 10, the edge 212 is the part of the substrate 21 near the laser cutting path during the fabrication of chip structure 10, and the modified layer 2122 is the part of the chip structure 10 that is affected by laser during laser cutting.

[0264] For example, the modified layer 2122 of the substrate 21 has a lower light reflectivity than the main body 211 and the original layer 2121, and correspondingly, a lower light transmittance. The illuminance of light with illuminance P after passing through the main body 211 and / or the original layer 2121 is, for example, 0.95P to P; while the illuminance of light with illuminance P after passing through the modified layer 2122 is, for example, 0.8P. It is understood that if the modified layer 2122 extends into the functional region AA, it will affect the light emission effect of the chip structure 10.

[0265] For example, the stresses of the original layer 2121 and the modified layer 2122 are different.

[0266] It is understandable that the main body 211 of the substrate 21 is the part of the substrate 21 that is not affected by the laser, the modified layer 2122 of the edge 212 is the part of the substrate 21 that is close to the cutting surface and undergoes structural changes due to the laser, and the original layer 2121 is also the part that is not affected by the laser during laser cutting.

[0267] For example, the main body 211 has the same light reflectivity as the original layer 2121.

[0268] The light reflectivity mentioned here refers to the reflectivity of the main body 211 and the original layer 2121 for light with a wavelength range of 380μm to 780μm.

[0269] For example, the stress of the main body 211 is the same as that of the original layer 2121.

[0270] In some embodiments, such as Figure 2 As shown, the substrate 21 includes a first surface 21a and a second surface 21b opposite to each other, and a plurality of side surfaces connecting the first surface 21a and the second surface 21b. The second surface 21b is closer to the chip wafer cell 1 than the first surface 21a. Figure 8 As shown, the edge portion 212 includes a plurality of sub-portions 212(k) respectively disposed on a plurality of side surfaces of the substrate 21.

[0271] In some examples, multiple sub-sections 212(k) include the same number of modified layers 2122.

[0272] In other examples, the number of modified layers 2122 included in multiple sub-sections 212(k) is not exactly the same.

[0273] It should be noted that, referring to the previous description of the fabrication method of chip structure 10, the number of modified layers 2122 included in each of the multiple sub-parts 212(k) of the edge portion 212 is the same as the number of focal points D during laser cutting.

[0274] In some embodiments, refer to the preceding description of the fabrication method of the corresponding chip structure 10, such as... Figure 8 As shown, the chip structure 10 includes a functional area AA, which includes multiple light-emitting areas A2. Each light-emitting area A2 has at least one light-emitting layer 13. When each light-emitting area A2 includes multiple light-emitting layers 13, the multiple light-emitting layers 13 are connected to each other. The multiple light-emitting layers 13 in each light-emitting area A2 can be connected in series or in parallel, for example.

[0275] For example, the multiple light-emitting areas A2 include a first color light-emitting area, a second color light-emitting area, and a third color light-emitting area.

[0276] For example, the first color is red, the second color is green, and the third color is blue.

[0277] For example, the light-emitting layer 13 within the same light-emitting area A2 is configured to emit one of a variety of colors of light. The variety of colors of light includes, but is not limited to, blue light.

[0278] In some examples, multiple light-emitting layers 13 are configured to emit blue light, such as Figure 2As shown, the blue light emitted from the light-emitting layer 13 in each light-emitting region A2 is emitted as blue light after passing through the color conversion layer 24, or is converted into red or green light.

[0279] In some examples, the light-emitting layers 13 in different light-emitting areas A2 are configured to emit light of the same color.

[0280] At this time, the chip wafer unit 1 realizes multi-color light emission. For example, the light-emitting layers 13 corresponding to multiple light-emitting areas A2 emit light of different colors. After passing through the color conversion unit 2, the light emitted by the light-emitting layer 13 corresponding to each light-emitting area A2 is still emitted as light of the same color, thereby realizing multi-color light emission of the chip structure 10.

[0281] In other examples, the light-emitting layers 13 in at least two light-emitting regions A2 are configured to emit light of different colors.

[0282] At this time, the chip wafer unit 1 achieves monochromatic light output. For example, the light-emitting layers 13 corresponding to multiple light-emitting areas A2 all emit light of the same color. After passing through the color conversion unit 2, the colored light emitted by the light-emitting layer 13 corresponding to each light-emitting area A2 is emitted in the same color, or is converted into light of other colors and emitted, thereby realizing multi-color light output of the chip structure 10.

[0283] The chip structure 10 provided in some embodiments of this disclosure, such as Figure 2 As shown, a color conversion unit 2 is used to convert the color of the light emitted by the chip wafer unit 1. In this way, the multiple light-emitting layers 13 of the chip wafer unit 1 can emit light of the same color. For example, if multiple light-emitting layers 13 are all configured to emit blue light, the chip structure 10 can still achieve the emission of light of multiple colors.

[0284] For example, in the multiple light-emitting layers 13 included in the chip wafer unit 1, the blue light emitted from the light-emitting layer 13 in one light-emitting region A2 is kept blue after passing through the color conversion layer 24, for example, and the blue light emitted from the light-emitting layer 13 in another light-emitting region A2 is converted into red light after passing through the color conversion layer 24, for example, and the blue light emitted from the light-emitting layer 13 in yet another light-emitting region A2 is converted into green light after passing through the color conversion layer 24, for example.

[0285] When the chip structure 10 is applied to the display device 100, for example, only a blue light chip wafer unit 1 needs to be fabricated, and the blue light emitted by the blue light chip wafer unit 1 is kept as blue light or converted into other colors of light, such as red light or green light, through the color conversion unit 2. In this way, when fabricating the chip structure 10, the chip wafer unit 1 can achieve monochromatic light emission, and the color of the light emitted by the chip wafer unit 1 can be converted through the color conversion unit 2, thereby realizing multi-color light emission of the chip structure 10, and thus realizing multi-color display of the display device 100.

[0286] In some embodiments, the chip wafer unit can achieve multi-color light emission. In this case, the light-emitting layer in each light-emitting region of the chip structure needs to emit light of different colors. The light-emitting layer is, for example, an MQW. It is understood that in this way, multiple MQWs that can emit light of different colors need to be used to prepare the light-emitting layer in each light-emitting region on a single chip wafer unit, which is a complicated process.

[0287] In some embodiments of this disclosure, the chip wafer unit 1 achieves monochromatic light emission, and the color conversion unit 2 performs color conversion on the light emitted by the chip structure 10, thereby achieving multicolor light emission from the chip structure 10. It is understood that, compared to achieving multicolor light emission through the chip wafer unit, this method, during the fabrication of the chip structure 10, uses the same MQW, such as an InGaN MQW (in-poor gallium nitride multiple quantum well), to form multiple light-emitting layers 13. In this case, the light-emitting layer 13 can emit blue light. The blue light emitted by the light-emitting layer 13 in each light-emitting region A2 is then converted by the color conversion layer 24, for example, maintaining blue light emission or being converted into red or green light emission. This simplifies the fabrication steps of the chip structure 10, thereby improving the fabrication efficiency of the chip structure.

[0288] For example, the chip wafer unit 1 and the color conversion unit 2 are bonded together, for example, by a bonding layer 3. The bonding effect of the bonding layer 3 can be adhesive bonding or metal bonding.

[0289] For example, the connecting layer 3 is an adhesive bonding layer. Using an adhesive bonding layer offers higher shear strength and better bonding stability compared to metal bonding, effectively preventing cracking at the bonding location between the chip wafer unit 1 and the color conversion unit 2. This is merely an example of one possible implementation and is not intended to limit the specific embodiments disclosed herein.

[0290] The following explanation uses the example where the number of modified layers 2122 included in the multiple sub-parts of the edge portion 212 is the same.

[0291] In some embodiments, such as Figure 9 As shown, the edge portion 212 includes N modified layers 2122, where N is a positive integer and N≥2. The modified layer 2122 furthest from the chip wafer unit 1 is the first modified layer 2122(1), and the modified layer 2122 closest to the chip wafer unit 1 is the Nth modified layer 2122(n).

[0292] In some examples, the distance h1 between the first modified layer 2122(1) and the first surface 21a of the substrate 21 is greater than or equal to the distance h2 between any two adjacent modified layers 2122.

[0293] The distance h1 between the first modified layer 2122(1) and the first surface 21a of the substrate 21 is, for example, 15 μm to 35 μm.

[0294] Furthermore, the distance h1 between the first modified layer 2122(1) and the first surface 21a of the substrate 21 is, for example, greater than or equal to 20 μm.

[0295] In other examples, the distance h3 between the Nth modified layer 2122(n) and the second surface 21b of the substrate 21 is greater than or equal to the distance h2 between any two adjacent modified layers 2122.

[0296] The distance h3 between the Nth modified layer 2122(n) and the second surface 21b of the substrate 21 is, for example, 15 μm to 35 μm.

[0297] Furthermore, the distance h3 between the Nth modified layer 2122(n) and the second surface 21b of the substrate 21 is greater than or equal to 20 μm.

[0298] In some other examples, the distance h1 between the first modified layer 2122(1) and the first surface 21a of the substrate 21 is greater than or equal to the distance h2 between any two adjacent modified layers 2122, and the distance h3 between the Nth modified layer 2122(n) and the second surface 21b of the substrate 21 is greater than or equal to the distance h2 between any two adjacent modified layers 2122. Meanwhile, the distance h1 between the first modified layer 2122(1) and the first surface 21a of the substrate 21, and the distance h3 between the Nth modified layer 2122(n) and the second surface 21b of the substrate 21, may be the same or different.

[0299] Referring to the preceding description of the fabrication method of chip structure 10, during the fabrication process of chip structure 10, when the laser sequentially acts on N focal points D within the substrate mother plate 21' for cutting, in order to prevent cracks generated within the substrate mother plate 21' during laser cutting from extending to the surface of the substrate mother plate 21', the first focal point (1) and the Nth focal point D (n) need to maintain a certain distance from the surface of the substrate mother plate 21', for example... Figure 9 The distances d1 and d3 shown are required, and d1 and d3 need to be greater than d2, so as to ensure that the crack generated in the substrate mother plate 21' extends to the surface of the substrate mother plate 21'.

[0300] Thus, the chip structure 10 formed by the preparation method described above, based on the distance relationship between the N focal points D, and the distance relationship between the first focal point (1) and the Nth focal point D (n) and the surface of the substrate mother plate 21', is reflected in the chip structure 10, forming the edge portion 212 including the multiple original layers 2121 and modified layers 2122. The distance h1 between the first modified layer 2122 and the first surface 21a of the substrate 21 is greater than or equal to the distance h2 between any two adjacent modified layers 2122, and the distance h3 between the Nth modified layer 2122 and the second surface 21b of the substrate 21 is greater than or equal to the distance h2 between any two adjacent modified layers 2122.

[0301] In this way, the cracks generated during laser cutting during the fabrication of the chip structure 10 can be prevented from extending to the surface of the substrate 21, which would cause defects such as chipping on the surface of the substrate 21. This ensures the yield of the chip structure 10 and reduces the fabrication cost of the chip structure 10.

[0302] In some embodiments, such as Figure 2 As shown, the color conversion unit 2 further includes: a color filter layer 22, a limiting dam layer 23, a color conversion layer 24, and an encapsulation layer 25. The color filter layer 22 is disposed on the side of the substrate 21 facing the chip wafer unit 1, and includes a black matrix 221 and a plurality of filter portions 222 defined by the black matrix 221. The limiting dam layer 23 is disposed on the side of the color filter layer 22 away from the substrate 21, and includes a plurality of opening regions 231, each opening region 231 being disposed opposite to a filter portion 222. The color conversion layer 24 is disposed in the same layer as the limiting dam layer 23.

[0303] See Figure 7 and Figure 8 As shown, in the orthographic projection onto the substrate 21, the black matrix 221 is located within the area enclosed by the edge portion 212, and the portion of the encapsulation layer 25 located in the peripheral region AN overlaps with the edge portion 212.

[0304] Referring to the description of the manufacturing method of the chip structure 10 in the foregoing text, it can be understood that during the manufacturing process of the chip structure 10, the edge portion 212 is formed due to the structural change generated on the cutting surface under the action of laser when laser-cutting the substrate mother board 21'. Since the part of the substrate 21 affected by the laser and having a structural change (such as the modified layer 2122 in the edge portion 212) has a lower light reflectivity compared to the part not affected by the laser (such as the main body portion 211 and the original layer 2121 in the edge portion 212). For example, when the range of the modified layer 2122 extends into the functional area AA, in this way, when the light emitted by the chip wafer unit 1 passes through the substrate 21, the reflectivity of the part of the light entering the modified layer 2122 is lower than that of the part entering the main body portion 211 and the part entering the original layer 2121, and the light transmittance will decrease, thereby reducing the light extraction efficiency of the chip structure.

[0305] Therefore, to ensure the light-emitting effect of the chip structure 10, the part of the substrate 21 with a structural change should not extend into the functional area AA, that is, the modified layer 2122 in the edge portion 212 needs to be located outside the functional area AA (such as in the peripheral area AN), so as to ensure that when the light emitted by the chip wafer unit 1 passes through the color conversion unit 2 and exits, the light can be better reflected during the process of passing through the substrate 21 and exiting, thereby ensuring the light extraction efficiency of the chip structure 10.

[0306] It can be understood that according to the description of the edge portion 212 in the foregoing text, the edge portion 212 is the part of the substrate 21 near the cutting surface during the laser manufacturing process and affected by the laser to have a modified layer 2122 (a modified layer 2122 is formed by laser cutting along a focus D). Therefore, the width of the modified layer 2122 (such as Figure 2 the dimension e2 shown) is variable, the width of the modified layer 2122 is less than or equal to the width of the peripheral area AN, and the functional structure main body portion 211 in the substrate 21 is at least located in the functional area AA and can extend into the peripheral area AN.

[0307] It should be noted that the substrate 21 is, for example, rectangular. At this time, the substrate 21 includes four side surfaces and a "hui"-shaped peripheral area AN. The peripheral area AN includes four parts corresponding to each side surface one by one. Here, for the width of the modified layer 2122 and the width of the peripheral area AN, what is compared is the width of the peripheral area AN corresponding to any one side surface of the substrate 21 and the width of the modified layer 2122 in the sub-part 212(k) of the edge portion 212 located in this part of the peripheral area AN.

[0308] In some embodiments, such as Figure 2As shown, the plurality of opening areas 231 include: a first type of opening area 2311 and a second type of opening area 2312. The color conversion layer 24 includes a color conversion portion 241 disposed in the first type of opening area 2311 and a filling portion 242 disposed in the second type of opening area 2312.

[0309] For example, each filter element 222 is disposed corresponding to at least one light-emitting layer 13. The plurality of filter elements 222 may include, for example, a first filter element, a second filter element, and a third filter element. The first filter element, the second filter element, and the third filter element are respectively disposed opposite to at least one light-emitting layer 13.

[0310] When each light-emitting area A2 includes multiple light-emitting layers 13, the multiple light-emitting layers 13 in each light-emitting area A2 are all disposed corresponding to the same filter unit 222; or, the multiple light-emitting layers 13 in each light-emitting area A2 are disposed corresponding to multiple filter units 222 respectively.

[0311] For example, the filter section 222 is a color filter or a color filter film.

[0312] In some examples, the first filter is a red filter, the second filter is a green filter, and the third filter is a blue filter.

[0313] For example, the color conversion unit 241 is a quantum dot conversion unit or a fluorescent color conversion unit.

[0314] In some examples, the quantum dot conversion unit includes, for example, a first quantum dot conversion unit and a second quantum dot conversion unit.

[0315] In other examples, the fluorescence conversion section may include, for example, a first fluorescence conversion section or a second fluorescence conversion section.

[0316] For example, the light-emitting layer emits blue light, which is then converted into red light and emitted after passing through a first quantum dot conversion unit or a first fluorescent color conversion unit.

[0317] For example, the light-emitting layer emits blue light, which is then converted into green light, for example, after passing through the second quantum dot conversion unit or the second fluorescent color conversion unit.

[0318] It is understood that the color conversion unit 241 may also be made of other materials, as long as the color conversion function can be achieved. This is only an example of one possible implementation and is not intended to limit the specific implementation of this disclosure.

[0319] For example, the material of the filling portion 242 includes, but is not limited to, scattering particles or transparent adhesive.

[0320] For example, the light-emitting layer 13 in the light-emitting area A2 corresponding to the filling part 242 emits blue light, and the chip structure 10 also emits blue light corresponding to the same light-emitting area A2. Therefore, the light emitted by this part of the light-emitting layer 13 does not need to be color-converted. It can be understood that the filling part 242 is configured to fill the corresponding opening area 231, so that the opening area 231 is filled flat, and the material of the filling part 242 should have good light transmittance, thereby ensuring the light-emitting effect of the chip structure 10.

[0321] It is understood that the filling portion 242 can also be made of other materials, as long as it can achieve the filling effect of the corresponding opening area 231, has good light transmittance, and does not change the color of the light when it passes through the filling portion 242. This is only an example of one possible implementation and is not intended to limit the specific implementation of this disclosure.

[0322] In some embodiments, such as Figure 2 As shown, the distance between the boundary of the black matrix 221 and the side surface of the substrate 21 is e1, and the dimension of the modified layer 2122 in the direction parallel to the first surface 21a of the substrate 21 and perpendicular to the side surface of the substrate 21 is e2, e2≤e1.

[0323] Understandably, the comparison here refers to the distance between any side surface of the substrate 21 and the boundary of the black matrix 221 that it is close to.

[0324] For example, such as Figure 2 As shown, the distance e1 between the boundary of the black matrix 221 and the side surface of the substrate 21 ranges from 10 μm to 30 μm.

[0325] For example, such as Figure 2 As shown, the size e2 of the modified layer 2122 in the direction parallel to the first surface 21a of the substrate 21 and perpendicular to the side surface of the substrate 21 ranges from 5 μm to 10 μm.

[0326] For example, the black matrix 221 is located within the functional area AA.

[0327] See Figure 2 As described above regarding the fabrication method of chip structure 10, the distance e1 between the boundary of the black matrix 221 and the boundary of the substrate 21 is formed after the laser cuts the substrate mother plate 21' along the cutting path Q. During the cutting of the substrate mother plate 21', the laser cutting path coincides with or approximately coincides with the surface of the first surface 21'a of the substrate mother plate 21', which is perpendicular to the axis of symmetry of the cutting path Q. Therefore, in the multiple chip structures 10 ultimately formed, the distance e1 between the boundary of the black matrix 221 and the boundary of the substrate 21 ranges from approximately... Figure 8The distance d4 shown is half of the distance shown.

[0328] Specifically, using the fabrication method described above, including the coupling structure C of multiple chip structures 10, the width of the cleavage track Q (e.g.) Figure 8 The dimension d4 shown in the figure ranges from 20μm to 50μm. During laser cutting, the cutting path may not be able to completely divide the cutting track Q into two opposite parts.

[0329] Therefore, corresponding to the chip structure 10, the distance e1 between the boundary of the black matrix 221 and the boundary of the substrate 21 is relatively smaller than that between the two sides. The scope will be larger.

[0330] By controlling the distance between the focal point D and the surfaces (first surface 21'a and / or second surface 21'b) of the substrate mother plate 21' during the fabrication process, the width of the peripheral region AN of the formed chip structure 10 is reflected in the chip structure 10. When the substrate mother plate 21' is laser-cut, the heat-affected zone of the laser cannot cover the surface structure of the chip structure 10 (e.g., the structure within the functional area AA). For example, if the encapsulation layer 25 is located 20 μm from the cutting line, and the heat-affected zone during laser cutting exceeds 20 μm, it will damage the encapsulation layer 25, causing the color conversion layer 24 (e.g., color conversion part 241) covered by the encapsulation layer 25 to fail, resulting in the chip structure 10 being unable to emit light normally.

[0331] Referring to the previous description of the fabrication method of chip structure 10, the cutting line mentioned here is the cutting path when the laser cuts along the path where the focal point D is located, parallel to the first surface 21'a of the substrate mother plate 21', and located within the cutting channel Q.

[0332] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A chip structure, characterized in that, include: A chip wafer unit and a color conversion unit disposed on the light-emitting side of the chip wafer unit; wherein, The color conversion unit includes a substrate, the substrate includes a main body and an edge portion surrounding the main body, the edge portion includes a primary layer and a modified layer alternately arranged along a first direction, and the outermost layers in the edge portion along the first direction are both primary layers; the primary layer and the modified layer have different light reflectivities; The first direction is perpendicular to the surface of the substrate that is away from the chip wafer unit; The substrate includes a first surface and a second surface opposite to each other along the first direction, and a plurality of side surfaces connecting the first surface and the second surface. The second surface is close to the chip wafer cell relative to the first surface. The edge portion includes a plurality of sub-portions respectively corresponding to the plurality of side surfaces. At least one of the plurality of sub-parts includes N modified layers, where N is a positive integer and N≥2; The modified layer furthest from the chip wafer cell is the first modified layer, and the distance between the first modified layer and the first surface is greater than the distance between any two adjacent modified layers; and / or, The modification layer closest to the chip wafer unit is the Nth modification layer, and the distance between the Nth modification layer and the second surface is greater than the distance between any two adjacent modification layers.

2. The chip structure according to claim 1, characterized in that, The main body has the same light reflectivity as the original layer.

3. The chip structure according to claim 1, characterized in that, The plurality of sub-parts all include the same number of modified layers; or, The number of modified layers included in the plurality of sub-parts is not exactly the same.

4. The chip structure according to claim 1, characterized in that, The distance between the first modified layer and the first surface ranges from 15 μm to 35 μm; And / or, The distance between the Nth modified layer and the second surface ranges from 15 μm to 35 μm.

5. The chip structure according to claim 4, characterized in that, The distance between the first modified layer and the first surface is greater than or equal to 20 μm; and / or, The distance between the Nth modified layer and the second surface is greater than or equal to 20 μm.

6. The chip structure according to any one of claims 1 to 5, characterized in that, The color conversion unit further includes: A color filter layer is disposed on the side of the substrate facing the chip wafer unit, and includes a black matrix and a plurality of filter portions defined by the black matrix; in a positive projection onto the substrate, the black matrix is ​​located within the area enclosed by the edge portions; A dam layer is defined and disposed on the side of the color filter layer away from the substrate, and includes multiple opening areas, each of which corresponds to one of the multiple filter portions; A color conversion layer is provided on the same layer as the defined dam layer.

7. The chip structure according to claim 6, characterized in that, The plurality of opening regions include: a first type of opening region and a second type of opening region; The color conversion layer includes a color conversion part and a filling part; the color conversion part is disposed in the first type of opening area, and the filling part is disposed in the second type of opening area; The color conversion unit includes a quantum dot conversion unit or a fluorescent color conversion unit; The filling portion includes a scattering particle portion or a transparent adhesive.

8. The chip structure according to claim 6, characterized in that, The substrate includes a functional region and a peripheral region surrounding the functional region, and the orthographic projection of the chip wafer unit on the substrate is located in the functional region; the main body is located at least within the functional region, and the edge portion is located within the peripheral region; The color conversion unit further includes: An encapsulation layer covers the color filter layer, and in a normal projection onto the substrate, the portion of the encapsulation layer located in the peripheral region overlaps with the edge portion.

9. The chip structure according to claim 6, characterized in that, The distance between the boundary of the black matrix and the side surface of the substrate is e1, and the dimension of the modified layer in the direction parallel to the first surface and perpendicular to the side surface is e2, where e2≤e1.

10. The chip structure according to claim 9, characterized in that, The modified layer has a dimension e2 ranging from 5 μm to 10 μm in a direction parallel to the first surface and perpendicular to the side surface.

11. The chip structure according to claim 6, characterized in that, The distance e1 between the boundary of the black matrix and the side surface ranges from 10μm to 30μm.

12. A display device, characterized in that, include: A driving substrate and a plurality of chip structures as described in any one of claims 1 to 11; The driving substrate is coupled to multiple chip structures.

13. A method for fabricating a chip structure, characterized in that, include: Forming the initial wafer; The initial wafer comprises multiple chip wafer units; Forming a color conversion substrate; The color conversion substrate includes a substrate mother plate and a plurality of color conversion structures disposed on the substrate mother plate, wherein each color conversion structure and its corresponding substrate mother plate constitute a color conversion unit. The color conversion substrate is coupled to the initial wafer to obtain a coupling structure; each chip wafer unit is opposite to one of the color conversion units; The laser is applied sequentially to multiple focal points inside the substrate mother plate to cut the substrate; wherein the multiple focal points are arranged sequentially along a first direction, the first direction being perpendicular to the surface of the substrate mother plate away from the multiple color conversion structures; after the substrate mother plate is cut, multiple substrates are formed, each substrate including a main body and an edge portion surrounding the main body, the edge portion including original layers and modified layers alternately arranged along the first direction, and the layers located on the outermost sides in the first direction are both original layers; The substrate includes a first surface and a second surface opposite to each other along the first direction, and a plurality of side surfaces connecting the first surface and the second surface. The second surface is close to the chip wafer cell relative to the first surface. The edge portion includes a plurality of sub-portions respectively corresponding to the plurality of side surfaces. At least one of the plurality of sub-parts includes N modified layers, where N is a positive integer and N≥2; The modified layer furthest from the chip wafer cell is the first modified layer, and the distance between the first modified layer and the first surface is greater than the distance between any two adjacent modified layers; and / or, The modification layer closest to the chip wafer unit is the Nth modification layer, and the distance between the Nth modification layer and the second surface is greater than the distance between any two adjacent modification layers.

14. The preparation method according to claim 13, characterized in that, In the step of sequentially applying laser light to multiple focal points inside the substrate mother plate for cutting, the substrate mother plate is cut from the side of the color conversion substrate of the coupling structure.

15. The preparation method according to claim 13 or 14, characterized in that, The substrate motherboard includes multiple cutting tracks, and the laser cuts along the cutting tracks; When cutting each of the aforementioned cutting paths, the number of focal points on which the laser acts may be the same or not exactly the same.

16. The preparation method according to claim 13 or 14, characterized in that, The number of the plurality of focal points is N, where N is a positive integer and N≥2. The focal point furthest from the initial wafer is the first focal point, and the focal point closest to the initial wafer is the Nth focal point. The surface of the substrate mother plate that is away from the initial wafer is a first surface, and the surface of the substrate mother plate that is close to the initial wafer is a second surface; The distance between the first focal point and the first surface is greater than or equal to the distance between any two adjacent focal points; And / or, The distance between the Nth focus and the second surface is greater than or equal to the distance between any two adjacent focuses.

17. The preparation method according to claim 16, characterized in that, The distance between the first focal point and the first surface ranges from 15 μm to 35 μm; And / or, The distance between the Nth focus and the second surface ranges from 15μm to 35μm.

18. The preparation method according to claim 13 or 14, characterized in that, The distance between any two adjacent chip structures ranges from 20μm to 50μm.

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