Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes a plurality of pixel driving circuits. Each pixel driving circuit of the plurality of pixel driving circuits includes a driving transistor (Td), a data writing transistor, a compensation transistor, one or more reset transistors, and a storage capacitor (Cst). The array substrate further includes a light shielding layer (LSL). A footprint of the light shielding layer (LSL) on a substrate (BS) at least partially overlaps a footprint of an active layer (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, ACTd) of each of the driving transistor (Td), the data writing transistor, the compensation transistor, and the one or more reset transistors on the substrate (BS).

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) displays are currently a hot topic in flat panel display research. Unlike thin-film transistor liquid crystal displays (TFT-LCDs), which use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control illuminance. An OLED display panel includes multiple pixel units configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the row in which the pixel unit is selected is turned on, a switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line through the switching transistor to the driving transistor, causing the driving transistor to output a current corresponding to the data voltage to the OLED device. This drives the OLED device to emit light of a corresponding brightness. Summary of the Invention

[0003] On one hand, this disclosure provides an array substrate including a plurality of pixel driving circuits; wherein each pixel driving circuit in the plurality of pixel driving circuits includes a driving transistor, a data writing transistor, a compensation transistor, one or more reset transistors and a storage capacitor; wherein the array substrate further includes a light-shielding layer; wherein the orthographic projection of the light-shielding layer on the substrate at least partially overlaps with the orthographic projection of the active layer of each of the driving transistor, the data writing transistor, the compensation transistor and the one or more reset transistors on the substrate.

[0004] Optionally, the orthogonal projection of the light-shielding layer on the substrate covers the orthogonal projection of the active layer of each of the driving transistor, the data writing transistor, the compensation transistor, and the one or more reset transistors on the substrate.

[0005] Optionally, the light-shielding layer includes a plurality of first light-shielding rays; wherein the orthographic projection of each of the plurality of first light-shielding rays on the substrate covers the orthographic projection of the active layer of the one or more reset transistors on the substrate.

[0006] Optionally, the orthographic projection of the corresponding first shading light of the current row among the plurality of first shading lights on the substrate covers the orthographic projection of the active layer of the first reset transistor in the current row pixel driving circuit and the active layer of the second reset transistor in the previous adjacent row pixel driving circuit on the substrate; and the orthographic projection of the corresponding first shading light of the next adjacent row among the plurality of first shading lights on the substrate covers the orthographic projection of the active layer of the second reset transistor in the current row pixel driving circuit and the active layer of the first reset transistor in the next adjacent row pixel driving circuit on the substrate.

[0007] Optionally, the array substrate further includes a plurality of reset control signal lines; wherein the orthographic projection of each of the first shielding rays on the substrate at least partially overlaps with the orthographic projection of the corresponding reset control signal line among the plurality of reset control signal lines on the substrate.

[0008] Optionally, the light-shielding layer further includes a plurality of second light-shielding rays; wherein the orthographic projection of each of the plurality of second light-shielding rays on the substrate covers the orthographic projection of the active layer of the data writing transistor and the active layer of the compensation transistor on the substrate.

[0009] Optionally, the array substrate further includes a plurality of gate lines; wherein the orthographic projection of each of the second shielding rays on the substrate at least partially overlaps with the orthographic projection of the corresponding gate line among the plurality of gate lines on the substrate.

[0010] Optionally, the light-shielding layer includes a plurality of first light-shielding lines and a plurality of second light-shielding lines; wherein the corresponding second light-shielding line in the current row of the plurality of second light-shielding lines and the corresponding first light-shielding line in the next adjacent row of the plurality of first light-shielding lines are connected to each other in the peripheral region to form a ring structure.

[0011] Optionally, the light-shielding layer includes a plurality of first light-shielding lines and a plurality of second light-shielding lines; wherein the plurality of first light-shielding lines and the plurality of second light-shielding lines are connected to a grid scanning circuit, the grid scanning circuit being located in the peripheral region and configured to provide a grid scanning signal.

[0012] Optionally, the light-shielding layer includes a plurality of islands; wherein the orthographic projection of each of the plurality of islands on the substrate at least partially overlaps with the orthographic projection of the first capacitor electrode of the storage capacitor on the substrate.

[0013] Optionally, the array substrate further includes a plurality of voltage supply lines; wherein the light-shielding layer further includes a plurality of extensions; wherein the plurality of islands are separated from each other; each of the plurality of extensions extends away from a corresponding island among the plurality of islands; and each of the extensions is connected to a corresponding voltage supply line among the plurality of voltage supply lines.

[0014] Optionally, the light-shielding layer further includes a plurality of bridges; wherein adjacent islands among the plurality of islands are connected by corresponding bridges among the plurality of bridges.

[0015] Optionally, the array substrate further includes a plurality of voltage supply lines; wherein the light-shielding layer further includes an extension extending away from one of the plurality of islands; wherein the extension is connected to one of the plurality of voltage supply lines.

[0016] Optionally, the array substrate includes a display area and a peripheral area; wherein, the light-shielding layer includes a plurality of third light-shielding lines located in the display area, a peripheral light-shielding signal line located in the peripheral area, and a plurality of peripheral connection lines located in the peripheral area; each of the plurality of third light-shielding lines includes a portion of an island among the plurality of islands and a portion of a bridge among the plurality of bridges; and each of the plurality of peripheral connection lines connects the corresponding third light-shielding line to the peripheral light-shielding signal line.

[0017] Optionally, the light-shielding layer is an integral structure of an interconnected light-shielding network extending across multiple sub-pixels; wherein the integral structure includes multiple first islands, multiple second islands, multiple first bridges, multiple second bridges, multiple third bridges, and multiple branches.

[0018] Optionally, the interconnected shading network includes multiple rows of islands; wherein each row of islands includes multiple first islands arranged in a direction substantially parallel to a first direction and multiple second islands arranged in a direction substantially parallel to the first direction; each of the multiple first bridges connects a first island in two adjacent rows and a second island in two adjacent rows; each of the multiple second bridges connects a first island in the same row and a second island in the same row; each of the multiple third bridges connects two adjacent first islands in the same row; and each of the multiple branches extends away from the corresponding first island in the multiple first islands.

[0019] Optionally, the orthographic projection of the respective first island on the substrate covers the orthographic projection of the active layer of the driving transistor on the substrate; the orthographic projection of each of the plurality of second islands on the substrate covers the orthographic projection of the active layer of the compensation transistor on the substrate; the orthographic projection of each branch on the substrate covers the orthographic projection of the active layer of the data write transistor on the substrate; and the orthographic projection of each first bridge on the substrate covers the orthographic projection of the active layers of the first reset transistor and the second reset transistor on the substrate.

[0020] Optionally, the array substrate includes a display area and a peripheral area; wherein, in the peripheral area, the light-shielding layer further includes peripheral light-shielding signal lines and a plurality of peripheral connection lines connecting the overall structure located in the display area and the peripheral light-shielding signal lines located in the peripheral area; wherein, the interconnecting light-shielding network includes multiple rows of islands; each row of islands includes a plurality of first islands arranged in a direction substantially parallel to a first direction and a plurality of second islands arranged in a direction substantially parallel to the first direction; and each peripheral connection line of the plurality of peripheral connection lines connects a corresponding row of the multiple rows of islands to the peripheral light-shielding signal lines.

[0021] Optionally, the array substrate includes K reset signal lines, each of which is configured to provide a reset signal to a reset transistor in a K-column pixel driving circuit of the array substrate; wherein the K reset signal lines include: a plurality of third reset signal lines located in the (2k-1)th column of the K columns, where K and k are positive integers, 1≤k≤(K / 2); and a plurality of fourth reset signal lines located in the (2k)th column of the K columns; wherein each third reset signal line and each fourth reset signal line has a different line pattern.

[0022] On the other hand, this disclosure provides an array substrate including a plurality of pixel driving circuits; wherein each pixel driving circuit includes a driving transistor, a data writing transistor, a compensation transistor, one or more reset transistors, and a storage capacitor; wherein the array substrate further includes a light-shielding layer; wherein the orthographic projection of a first portion of the light-shielding layer on a substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor on the substrate; the orthographic projection of a second portion of the light-shielding layer on the substrate at least partially overlaps with the orthographic projection of the active layer of at least one of the data writing transistor, the compensation transistor, and the one or more reset transistors on the substrate; and the first portion and the second portion are configured to be provided with different signals.

[0023] Optionally, the first portion is configured to be provided with a constant voltage signal, and the second portion is configured to be provided with a pulse signal.

[0024] Optionally, the first portion is configured to be provided with a voltage supply signal, and the second portion is configured to be provided with a gate scan signal.

[0025] Optionally, the first portion includes a plurality of third shielding lines; the second portion includes a plurality of first shielding lines and a plurality of second shielding lines; the plurality of first shielding lines and the plurality of second shielding lines are connected to a gate scan circuit configured to provide a gate scan signal; and the plurality of third shielding lines are connected to a signal line configured to provide a voltage supply signal.

[0026] Optionally, the array substrate further includes a plurality of voltage supply lines located in the display area of ​​the array substrate; wherein one of the plurality of voltage supply lines is connected to an extension of a corresponding third shielding light among the plurality of third shielding light lines via a via; and the plurality of third shielding light lines are connected to the same voltage supply line among the plurality of voltage supply lines.

[0027] Optionally, the light-shielding layer further includes peripheral light-shielding signal lines located in the peripheral region of the array substrate, and a plurality of peripheral connection lines connecting the plurality of third light-shielding lines located in the display region of the array substrate with the peripheral light-shielding signal lines located in the peripheral region.

[0028] Optionally, the array substrate further includes a plurality of voltage supply lines located in the display area of ​​the array substrate; wherein, one of the plurality of voltage supply lines is connected to an extension of a corresponding third shading light among the plurality of third shading light lines through a via; the plurality of third shading light lines are connected to the same voltage supply line among the plurality of voltage supply lines; and the light-shielding layer further includes peripheral light-shielding signal lines located in the peripheral area of ​​the array substrate, and a plurality of peripheral connection lines connecting the plurality of third shading light lines located in the display area of ​​the array substrate with the peripheral light-shielding signal lines located in the peripheral area.

[0029] Optionally, the first portion includes a plurality of islands separated from each other and a plurality of extensions; the second portion includes a plurality of first light-shielding lines and a plurality of second light-shielding lines; each of the plurality of extensions extends away from a corresponding island among the plurality of islands; wherein the array substrate further includes a plurality of voltage supply lines located in the display area of ​​the array substrate; and each of the plurality of voltage supply lines is connected to a corresponding extension through a via.

[0030] On the other hand, this disclosure provides a display device including the array substrate described herein, and one or more integrated circuits connected to the array substrate. Attached Figure Description

[0031] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0032] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure.

[0033] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0034] Figure 2B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0035] Figure 2C This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0036] Figure 3A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0037] Figure 3B It is shown Figure 3A A schematic diagram of the arrangement of multiple pixel driving circuits in a portion of an array substrate depicted in the figure.

[0038] Figure 3C It is shown Figure 3A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure.

[0039] Figure 3D It is shown Figure 3A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0040] Figure 3E It is shown Figure 3A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure.

[0041] Figure 3F It is shown Figure 3A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the figure.

[0042] Figure 3G It is shown Figure 3A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure.

[0043] Figure 3H It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0044] Figure 4A It is along Figure 3A A cross-sectional view of line A-A' in the diagram.

[0045] Figure 4B It is along Figure 3A A cross-sectional view of line B-B' in the diagram.

[0046] Figure 4C It is along Figure 3A A cross-sectional view of the C-C' line in the diagram.

[0047] Figure 4D It is along Figure 3A A cross-sectional view of the D-D' line in the diagram.

[0048] Figure 4E It is along Figure 3A A cross-sectional view of the E-E' line in the diagram.

[0049] Figure 5 It is shown Figure 3A A schematic diagram of the structure of the light-shielding layer and semiconductor material layer in a portion of the array substrate depicted in the figure.

[0050] Figure 6 It is shown Figure 3A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure.

[0051] Figure 7 It is shown Figure 3A A schematic diagram of the structure of the light-shielding layer and the first conductive layer in a portion of the array substrate depicted in the figure.

[0052] Figure 8 The layout of a light-shielding layer, a semiconductor material layer, and a first conductive layer in a portion of an array substrate according to some embodiments of the present disclosure is shown.

[0053] Figure 9 It shows Figure 8 The layout of the light-shielding layer in a portion of the array substrate is depicted.

[0054] Figure 10 An annular structure according to some embodiments of the present disclosure is shown, which is formed by a corresponding second shading light of the current row of a plurality of second shading lights and a corresponding first shading light of the next adjacent row of a plurality of first shading lights.

[0055] Figure 11 The Id-Vg curves of some array substrates are shown.

[0056] Figure 12 The Wy-Lv correspondence of some array substrates is shown.

[0057] Figure 13A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0058] Figure 13B It is shown Figure 13A A schematic diagram of the arrangement of multiple pixel driving circuits in a portion of an array substrate depicted in the figure.

[0059] Figure 13C It is shown Figure 13A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure.

[0060] Figure 13D It is shown Figure 13A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0061] Figure 13E It is shown Figure 13A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure.

[0062] Figure 13F It is shown Figure 13A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0063] Figure 14 It is shown Figure 13A A schematic diagram of the structure of the light-shielding layer and semiconductor material layer in a portion of the array substrate depicted in the figure.

[0064] Figure 15 The layout of a light-shielding layer in a portion of an array substrate according to some embodiments of the present disclosure is shown.

[0065] Figure 16A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0066] Figure 16B It is shown Figure 16A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure.

[0067] Figure 16C It is shown Figure 16A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0068] Figure 16D It is shown Figure 16A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure.

[0069] Figure 16E It is shown Figure 16A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0070] Figure 17A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0071] Figure 17B It is shown Figure 17A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure.

[0072] Figure 17C It is shown Figure 17A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0073] Figure 17D It is shown Figure 17A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure.

[0074] Figure 17E It is shown Figure 17A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the figure.

[0075] Figure 17F It is shown Figure 17A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0076] Figure 18A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0077] Figure 18B It is shown Figure 18A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure.

[0078] Figure 18C It is shown Figure 18A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0079] Figure 18D It is shown Figure 18A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the diagram.

[0080] Figure 18E It is shown Figure 18A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the diagram.

[0081] Figure 18F It is shown Figure 18AA schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0082] Figure 19A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0083] Figure 19B It is shown Figure 19A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure.

[0084] Figure 19C It is shown Figure 19A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0085] Figure 19D It is shown Figure 19A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure.

[0086] Figure 19E It is shown Figure 19A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the figure.

[0087] Figure 19F It is shown Figure 19A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure. Detailed Implementation

[0088] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0089] This disclosure provides, in particular, an array substrate and a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of pixel driving circuits. Optionally, each pixel driving circuit in the plurality of pixel driving circuits includes a driving transistor, a data writing transistor, a compensation transistor, one or more reset transistors, and a storage capacitor. Optionally, the array substrate also includes a light-shielding layer. Optionally, the orthographic projection of the light-shielding layer onto the substrate at least partially overlaps with the orthographic projection of the active layer of each of the driving transistor, the data writing transistor, the compensation transistor, and the one or more reset transistors onto the substrate.

[0090] Various suitable pixel driving circuits can be used in the array substrate described in this disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each pixel driving circuit in a plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in this disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes (OLEDs), quantum dot OLEDs, and micro-LEDs. Optionally, the light-emitting element is a micro-LED. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0091] Figure 1 This is a plan view of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 1 The array substrate comprises an array of subpixels Sp. Each subpixel includes electronic components, such as a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes multiple gate lines GL, multiple data lines DL, and multiple voltage supply lines Vdd. Each subpixel is driven to emit light by a corresponding pixel driving circuit PDC. In one example, a high-voltage signal is input to the corresponding pixel driving circuit PDC connected to the anode of the light-emitting element via each of the multiple voltage supply lines Vdd; a low-voltage signal is input to the cathode of the light-emitting element. The voltage difference between the high-voltage signal (e.g., VDD signal) and the low-voltage signal (e.g., VSS signal) is the driving voltage ΔV, which drives the light-emitting element to emit light.

[0092] Figure 2A This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2AIn some embodiments, each pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding reset control signal line rstN of the current stage (or current row) among a plurality of reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1N of the current stage (or current row) among a plurality of first reset signal lines, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding gate line of a plurality of gate lines GL, a first electrode connected to a corresponding data line of a plurality of data lines DL, and a second electrode connected to the first electrode of the driving transistor Td; and a third transistor T3 having a gate connected to a corresponding gate line, a first electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td. The second electrode is connected to the second electrode of the driving transistor Td; the fourth transistor T4 has a gate connected to a corresponding light-emitting control signal line among a plurality of light-emitting control signal lines em, a first electrode connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, and a second electrode connected to the first electrode of the driving transistor Td and the second electrode of the second transistor T2; the fifth transistor T5 has a gate connected to a corresponding light-emitting control signal line, a first electrode connected to the second electrode of the driving transistor Td and the third transistor T3, and a second electrode connected to the anode of the light-emitting element LE; and the sixth transistor T6 has a gate connected to the corresponding reset control signal line rst(N+1) of the next adjacent stage (or the next adjacent row) among a plurality of reset control signal lines, a first electrode connected to the corresponding second reset signal line Vint2N of the current stage (or the current row) among a plurality of second reset signal lines, and a second electrode connected to the second electrode of the fifth transistor and the anode of the light-emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the fourth transistor T4.

[0093] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a second transistor T2), a compensation transistor (e.g., a third transistor T3), two light-emitting control transistors (e.g., a fourth transistor T4 and a fifth transistor T5), and two reset transistors (e.g., a first transistor T1 and a sixth transistor T6).

[0094] Figure 2B This is a circuit diagram illustrating the structure of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2BIn some embodiments, the third transistor T3 is a "dual-gate" transistor, and the first transistor T1 is a "dual-gate" transistor. Optionally, in the "dual-gate" first transistor, the active layer of the first transistor crosses the corresponding reset control signal line twice (alternatively, the corresponding reset control signal line crosses the active layer of the first transistor T1 twice). Similarly, in the "dual-gate" third transistor, the active layer of the third transistor T3 crosses the corresponding first gate line of the plurality of first gate lines GL1 twice (alternatively, the corresponding gate line crosses the active layer of the third transistor T3 twice). The gate of the first transistor T1 is... Figure 13E and Figure 16D The designation is "G1", where the first transistor T1 is a "dual-gate" transistor. The gate of the third transistor T3 is... Figure 13E and Figure 16D The designation is "G3", where the third transistor, T3, is a "dual-gate" transistor.

[0095] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the third transistor T3. The second node N2 is connected to the second electrode of the fourth transistor T4, the second electrode of the second transistor T2, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the third transistor T3, and the first electrode of the fifth transistor T5. The fourth node N4 is connected to the second electrode of the fifth transistor T5, the second electrode of the sixth transistor T6, and the anode of the light-emitting element LE.

[0096] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, both of which are connected to the active layer of the transistor. The direction of current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of current flowing through the transistor, in one example, the first electrode is configured to receive an input signal and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal and the first electrode is configured to output an output signal.

[0097] Figure 2C This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2A , Figure 2B and Figure 2CDuring one frame of an image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2, and a light emission sub-stage t3. In the initial sub-stage t0, a cutoff reset control signal is provided to the gate of the first transistor T1 via the current stage reset control signal line rstN, causing the first transistor T1 to turn off. In the initial sub-stage t0, the gate line GL is provided with a cutoff signal, therefore the second transistor T2 and the third transistor T3 are turned off.

[0098] In reset stage t1, a turn-on reset control signal is provided to the gate of the first transistor T1 via the current stage reset control signal line rstN to turn on the first transistor T1. This allows the initialization voltage signal from the corresponding first reset signal line Vint1N of the current stage to be transmitted from the first electrode of the first transistor T1 to the second electrode of the first transistor T1, and further to the first capacitor electrode Ce1 and the gate of the driving transistor Td. The gate of the driving transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding voltage supply line among the plurality of voltage supply lines Vdd. Due to the increased voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2, the first capacitor electrode Ce1 is charged in reset stage t1. In reset stage t1, the corresponding gate lines among the plurality of gate lines GL are provided with a cutoff signal, thus turning off the second transistor T2 and the third transistor T3. The corresponding light-emitting control signal lines among the plurality of light-emitting control signal lines em are provided with a high voltage signal to turn off the fourth transistor T4 and the fifth transistor T5.

[0099] In data write sub-stage t2, a cutoff reset control signal is again provided to the gate of the first transistor T1 via the current stage reset control signal line rstN to turn off the first transistor T1. The corresponding gate lines in the plurality of gate lines GL are provided with conduction signals, thus turning on the second transistor T2 and the third transistor T3. The second electrode of the driving transistor Td is connected to the second electrode of the third transistor T3. The gate of the driving transistor Td is electrically connected to the first electrode of the third transistor T3. Since the third transistor T3 is turned on in data write sub-stage t2, the gate and second electrode of the driving transistor Td are connected and short-circuited, so only the PN junction between the gate and the first electrode of the driving transistor Td is effective, thus making the driving transistor Td a diode-connected mode. The second transistor T2 is turned on in data write sub-stage t2. The data voltage signal transmitted through the corresponding data lines in the plurality of data lines DL is received by the first electrode of the second transistor T2 and then transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the second transistor T2. The node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate of the driving transistor Td and the first electrode is active, during the data write sub-stage t2, the voltage level at node N1 gradually rises to (Vdata + Vth), where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst discharges. The corresponding light-emitting control signal lines in the plurality of light-emitting control signal lines em are provided with high-voltage signals to cut off the fourth transistor T4 and the fifth transistor T5.

[0100] During the data write sub-stage t2, a turn-on reset control signal is provided to the gate of the sixth transistor T6 via the corresponding reset control signal line rst(N+1) of the next adjacent stage to turn on the sixth transistor T6; this allows the initialization voltage signal from the corresponding second reset signal line Vint2N of the current stage to be transmitted from the first electrode of the sixth transistor T6 to the second electrode of the sixth transistor T6; and further to node N4. The anode of the light-emitting element LE is initialized.

[0101] In the light-emitting stage t3, a cutoff reset control signal is again provided to the gate of the first transistor T1 via the current stage reset control signal line rstN to turn off the first transistor T1. Corresponding gate lines among the plurality of gate lines GL are provided with cutoff signals, turning off the second transistor T2 and the third transistor T3. Corresponding light-emitting control signal lines among the plurality of light-emitting control signal lines em are provided with low voltage signals to turn on the fourth transistor T4 and the fifth transistor T5. In the light-emitting stage t3, the voltage level at node N1 is maintained at (Vdata + Vth), and the driving transistor Td is turned on by this voltage level, operating in the saturation region. A path is formed through the fourth transistor T4, the driving transistor Td, and the fifth transistor T5 to the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at node N3, connected to the second electrode of the driving transistor Td, is equal to the emission voltage of the light-emitting element LE.

[0102] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a repeating array in the format S1-S2-S3, wherein S1 represents a corresponding first sub-pixel, S2 represents a corresponding second sub-pixel, and S3 represents a corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents a corresponding first sub-pixel of a first color, C2 represents a corresponding second sub-pixel of a second color, and C3 represents a corresponding third sub-pixel of a third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0103] In another example, the array of multiple subpixels includes a repeating array in the format S1-S2-S3-S4, where S1 represents the corresponding first subpixel, S2 represents the corresponding second subpixel, S3 represents the corresponding third subpixel, and S4 represents the corresponding fourth subpixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, where C1 represents the corresponding first subpixel of the first color, C2 represents the corresponding second subpixel of the second color, C3 represents the corresponding third subpixel of the third color, and C4 represents the corresponding fourth subpixel of the fourth color. In yet another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, where C1 represents the corresponding first subpixel of the first color, C2 represents the corresponding second subpixel of the second color, C3 represents the corresponding third subpixel of the third color, and C2' represents the corresponding fourth subpixel of the second color. In another example, the C1-C2-C3-C2' format is RGBG format, where the corresponding first subpixel is a red subpixel, the corresponding second subpixel is a green subpixel, the corresponding third subpixel is a blue subpixel, and the corresponding fourth subpixel is a green subpixel.

[0104] In some embodiments, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, and the corresponding third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0105] In an alternative embodiment, the smallest repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0106] Figure 3A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 3B It is shown Figure 3A A schematic diagram of the arrangement of multiple pixel driving circuits in a portion of an array substrate depicted in the figure. Figure 3C It is shown Figure 3A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure. Figure 3D It is shown Figure 3A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 3E It is shown Figure 3A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure. Figure 3F It is shown Figure 3A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the figure. Figure 3G It is shown Figure 3A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the array substrate depicted in the figure. Figure 3H It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure. Figure 4A It is along Figure 3A A cross-sectional view of line A-A' in the diagram. Figures 3A to 3H and Figure 4A A portion of an array substrate with two pixel driving circuits (including PDC1 and PDC2) is depicted.

[0107] Reference Figures 3A to 3H and Figure 4A In some embodiments, the array substrate includes: a substrate BS; a light-shielding layer LSL located on the substrate BS; a buffer layer BUF located on the side of the light-shielding layer LSL away from the substrate BS; a semiconductor material layer SML located on the side of the buffer layer BUF away from the substrate BS; a gate insulating layer GI located on the side of the semiconductor material layer SML away from the substrate BS; a first conductive layer CT1 located on the side of the gate insulating layer GI away from the semiconductor material layer SML; an insulating layer IN located on the side of the first conductive layer away from the gate insulating layer GI; a second conductive layer CT2 located on the side of the insulating layer IN away from the first conductive layer CT1; an interlayer dielectric layer ILD located on the side of the second conductive layer CT2 away from the insulating layer IN; a first signal line layer SL1 located on the side of the interlayer dielectric layer ILD away from the second conductive layer CT2; and a planarization layer PLN located on the side of the first signal line layer SL1 away from the interlayer dielectric layer ILD.

[0108] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3C In some embodiments, the light-shielding layer LSL includes a light-shielding element LS. Various suitable materials and various suitable manufacturing methods can be used to manufacture the light-shielding layer LSL. For example, metallic materials can be deposited on a substrate using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable metallic materials for manufacturing the light-shielding layer LSL include, but are not limited to, aluminum, chromium, tungsten, titanium, tantalum, molybdenum, copper, and alloys or stacks comprising them.

[0109] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3D Each pixel driving circuit is labeled with a number, which indicates the region corresponding to the multiple transistors (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and driving transistor Td) in each pixel driving circuit. Each pixel driving circuit is also labeled with a number representing a component of each of the multiple transistors in the pixel driving circuit. For example, first transistor T1 includes active layer ACT1, first electrode S1, and second electrode D1. Second transistor T2 includes active layer ACT2, first electrode S2, and second electrode D2. Third transistor T3 includes active layer ACT3, first electrode S3, and second electrode D3. Fourth transistor T4 includes active layer ACT4, first electrode S4, and second electrode D4. Fifth transistor T5 includes active layer ACT5, first electrode S5, and second electrode D5. Sixth transistor T6 includes active layer ACT6, first electrode S6, and second electrode D6. Driving transistor Td includes active layer ACTd, first electrode Sd, and second electrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), the first electrode (S1, S2, S3, S4, S5, S6, and Sd), and the second electrode (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In yet another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer.

[0110] As used herein, an active layer refers to a portion of a transistor comprising a semiconductor material layer, the orthographic projection of which onto the substrate overlaps with the orthographic projection of the gate onto the substrate. A first electrode refers to a portion of the transistor connected to one side of the active layer, and a second electrode refers to a portion of the transistor connected to the other side of the active layer. In the context of a dual-gate transistor (e.g., a third transistor T3), an active layer refers to a portion of the transistor comprising a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first and second portions, wherein the orthographic projection of the first portion of the semiconductor material layer onto the substrate overlaps with the orthographic projection of the first gate onto the substrate, and the orthographic projection of the second portion of the semiconductor material layer onto the substrate overlaps with the orthographic projection of the second gate onto the substrate. In the context of a dual-gate transistor, a first electrode refers to a portion of the transistor connected to the side of the first portion away from the third portion, and a second electrode refers to a portion of the transistor connected to the side of the second portion away from the third portion.

[0111] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3E In some embodiments, the first conductive layer includes a plurality of gate lines GL, a plurality of reset control signal lines (including a current-level corresponding reset control signal line rstN and a next-level reset control signal line rst(N+1)), a plurality of light-emitting control signal lines em, and a first capacitor electrode Ce1 of a storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to fabricate the first conductive layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, the plurality of gate lines GL, the plurality of reset control signal lines, the plurality of light-emitting control signal lines em, and the first capacitor electrode Ce1 are located in the same layer.

[0112] As used herein, the term "same layer" refers to a relationship between layers formed simultaneously in the same step. In one example, multiple gate lines GL and a first capacitor electrode Ce1 are located in the same layer when they are formed due to one or more steps of the same patterning process performed in the same material layer. In another example, multiple gate lines GL and a first capacitor electrode Ce1 can be formed in the same layer by simultaneously performing the steps of forming multiple gate lines GL and forming the first capacitor electrode Ce1. The term "same layer" does not always mean that the layer thickness or layer height is the same in a cross-sectional view.

[0113] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3F In some embodiments, the second conductive layer includes a plurality of first reset signal lines (including a corresponding first reset signal line Vint1N for the current stage and a corresponding first reset signal line Vint1(N+1) for the next adjacent stage), a plurality of second reset signal lines (including a corresponding second reset signal line Vint2N for the current stage and a corresponding second reset signal line Vint2(N-1) for the previous adjacent stage), an anti-interference block IPB, and a second capacitor electrode Ce2 of the storage capacitor Cst. The anti-interference block IPB effectively reduces crosstalk, especially vertical crosstalk between the N1 node and adjacent data lines. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on a substrate and patterned by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, multiple first reset signal lines, multiple second reset signal lines, the second capacitor electrode Ce2, and the anti-interference block IPB are located on the same layer.

[0114] Figure 3F The image depicts vias extending through the interlayer dielectric layer (ILD).

[0115] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3H In some embodiments, the first signal line layer includes multiple voltage supply lines Vdd, node connection lines Cln, first initialization connection lines Cli1, second initialization connection lines Cli2, relay electrodes RE, data connection pads DCP, multiple third reset signal lines (including a corresponding third reset signal line VintA located in column (2k-1) of column K), and multiple fourth reset signal lines (including a corresponding fourth reset signal line VintB located in column (2k)). The node connection lines Cln connect the first capacitor electrode Ce1 and the first electrode of the third transistor T3 in the corresponding pixel driving circuit together.

[0116] As used herein, the terms "column (2k-1)" and "column (2k)" are used in the context of column K. The array substrate may or may not include additional columns preceding the first column of column K and / or additional columns following the last column of column K. In the context of the array substrate, the term "column (2k-1)" does not necessarily refer to an odd-numbered column, and the term "column (2k)" does not necessarily refer to an even-numbered column. In one example, column (2k-1) is an odd-numbered column in the context of column K, but may be an even-numbered column in the context of the array substrate. In another example, column (2k-1) is an odd-numbered column in the context of column K and is also an odd-numbered column in the context of the array substrate. In one example, column (2k) is an even-numbered column in the context of column K, but may be an odd-numbered column in the context of the array substrate. In another example, column (2k) is an even-numbered column in the context of column K and is also an even-numbered column in the context of the array substrate.

[0117] Optionally, the first initialization connection line Cli1 exists in column (2k) but not in column (2k-1). Optionally, each third reset signal line VintA exists in column (2k-1) but not in column (2k). In column (2k-1), the transmission of the reset signal is not accomplished through discrete initialization connection lines, but rather through the corresponding third reset signal line VintA, which is a monolithic signal line extending throughout column (2k-1). Therefore, the first initialization connection line Cli1 does not exist in column (2k-1).

[0118] Optionally, the second initialization connection line Cli2 exists in column (2k-1) but not in column (2k). Optionally, each fourth reset signal line VintB exists in column (2k) but not in column (2k-1). In column (2k), the transmission of the reset signal is not accomplished through discrete initialization connection lines, but rather through the corresponding fourth reset signal line VintB, which is a monolithic signal line extending throughout column (2k). Therefore, the second initialization connection line Cli2 does not exist in column (2k).

[0119] The corresponding third reset signal line VintA in column (2k-1) connects the corresponding first reset signal line (e.g., the corresponding first reset signal line Vint1N in the current stage) among the plurality of first reset signal lines to the first electrode S1 of the first transistor T1 in the corresponding pixel driving circuit in column (2k-1).

[0120] The first initialization connection line Cli1 in column (2k) connects the corresponding first reset signal line (e.g., the corresponding first reset signal line Vint1N in the current stage) among the plurality of first reset signal lines to the first electrode S1 of the first transistor T1 in the corresponding pixel driving circuit in column (2k).

[0121] The corresponding fourth reset signal line VintB in column (2k) connects the corresponding second reset signal line (e.g., the corresponding second reset signal line Vint2N in the current stage) among a plurality of second reset signal lines to the first electrode S6 of the sixth transistor T6 in the corresponding pixel driving circuit in column (2k).

[0122] The second initialization connection line Cli2 in column (2k-1) connects the corresponding second reset signal line (e.g., the corresponding second reset signal line Vint2N in the current stage) among the multiple second reset signal lines to the first electrode S6 of the sixth transistor T6 in the corresponding pixel driving circuit in column (2k-1).

[0123] The relay electrode RE connects the first electrode S5 of the fifth transistor T5 in the corresponding pixel driving circuit to the anode contact pad in the corresponding pixel driving circuit, which in turn connects to the anode in the corresponding light-emitting element of the corresponding sub-pixel.

[0124] The data signal connection pad (DCP) connects each data line to the first electrode of the second transistor T2 in the corresponding pixel drive circuit.

[0125] Various suitable conductive materials and various suitable manufacturing methods can be used to fabricate the first signal line layer. For example, the conductive material can be deposited on a substrate and patterned using a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, copper-molybdenum-aluminum alloys, etc. Optionally, multiple voltage supply lines Vdd, multiple third reset signal lines, multiple fourth reset signal lines, node connection lines Cln, first initialization connection lines Cli1, second initialization connection lines Cli2, data connection pads DCP, and relay electrodes RE are located in the same layer.

[0126] Reference Figure 2A , Figure 2B , Figures 3A to 3H ,and Figure 4AIn some embodiments, except for the via region H in which a portion of the second capacitor electrode Ce2 is absent, the orthographic projection of the second capacitor electrode Ce2 onto the substrate BS completely covers and extends beyond the orthographic projection of the first capacitor electrode Ce1 onto the substrate BS. In some embodiments, the first signal line layer includes a node connection line Cln located on the side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. Optionally, the node connection line Cln is located in the same layer as a plurality of voltage supply lines Vdd. Optionally, the array substrate also includes a first via v1 located in the via region H and extending through the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via v1. In some embodiments, the first capacitor electrode Ce1 is located on the side of the gate insulating layer GI away from the substrate BS. Optionally, the array substrate also includes a first via v1 and a second via v2. The first via v1 is located in the via region H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via v2 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through a first via v1 and to the semiconductor material layer SML through a second via v2. Optionally, as... Figure 4A As depicted, the node connection line Cln is connected to the second electrode D3 of the third transistor.

[0127] Reference Figure 2A , Figure 2B , Figures 3A to 3H and Figure 4A In some embodiments, the anti-interference block IPB and the second capacitor electrode Ce2 are located on the same layer. Each of the plurality of voltage supply lines Vdd is connected to the anti-interference block IPB via a third via v3. Optionally, the third via v3 extends through the interlayer dielectric layer ILD. Optionally, the orthographic projection of the anti-interference block IPB on the substrate BS partially overlaps with the orthographic projection of the corresponding voltage supply line among the plurality of voltage supply lines Vdd on the substrate BS. Optionally, the orthographic projection of the anti-interference block IPB on the substrate BS at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate BS. In one example, the orthographic projection of the anti-interference block IPB on the substrate BS at least partially overlaps with the orthographic projections of the two channel portions of the active layer ACT3 of the third transistor T3 on the substrate BS. In another example, the orthographic projection of the anti-interference block IPB on the substrate BS covers the orthographic projections of the two channel portions of the active layer ACT3 of the third transistor T3 on the substrate BS.

[0128] Figure 4B It is along Figure 3A Cross-sectional view of line B-B' in the diagram. (Refer to...) Figure 4B as well as Figures 3A to 3H The corresponding third reset signal line VintA in column (2k-1) connects the corresponding first reset signal line (e.g., the corresponding first reset signal line Vint1N of the current stage) among a plurality of first reset signal lines to the source S1 of the first transistor T1 of the corresponding pixel driving circuit in column (2k-1). The corresponding first reset signal line (e.g., the corresponding first reset signal line Vint1N of the current stage) among a plurality of first reset signal lines is configured to provide a reset signal to the source S1 of the first transistor T1 in the corresponding pixel driving circuit in column (2k-1) through the corresponding third reset signal line VintA in column (2k-1). Optionally, the corresponding third reset signal line VintA in column (2k-1) is connected to the corresponding first reset signal line Vint1N of the current stage through a fourth via v4 extending through the interlayer dielectric layer ILD. Optionally, the corresponding third reset signal line VintA in the (2k-1)th column is connected to the source S1 of the first transistor T1 in the corresponding pixel driving circuit in the (2k-1)th column via a fifth via v5 extending through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI.

[0129] Figure 4C It is along Figure 3A A cross-sectional view of line C-C' in the diagram. (Refer to...) Figure 4C as well as Figures 3A to 3H The second initialization connection line Cli2 in column (2k-1) connects a corresponding second reset signal line (e.g., the current stage corresponding second reset signal line Vint2N) among a plurality of second reset signal lines to the source S6 of the sixth transistor T6 in the corresponding pixel driving circuit in column (2k-1). The corresponding second reset signal line (e.g., the current stage corresponding second reset signal line Vint2N) is configured to provide a reset signal to the source S6 of the sixth transistor T6 in the corresponding pixel driving circuit in column (2k-1) via the second initialization connection line Cli2 in column (2k-1). Optionally, the second initialization connection line Cli2 is connected to the current stage corresponding second reset signal line Vint2N via a sixth via v6 extending through the interlayer dielectric layer ILD. Optionally, the second initialization connection line Cli2 is connected to the source S6 of the sixth transistor T6 in the corresponding pixel driving circuit in the (2k-1)th column via a seventh via v7 extending through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI.

[0130] Figure 4D It is along Figure 3A A cross-sectional view of line D-D' in the diagram. (Refer to...) Figure 4D as well as Figures 3A to 3HThe first initialization connection line Cli1 in column (2k) connects a corresponding first reset signal line (e.g., the corresponding first reset signal line Vint1N in the current stage) among a plurality of first reset signal lines to the source S1 of the first transistor T1 in the corresponding pixel driving circuit in column (2k). The corresponding first reset signal line (e.g., the corresponding first reset signal line Vint1N in the current stage) among the plurality of first reset signal lines is configured to provide a reset signal to the source S1 of the first transistor T1 in the corresponding pixel driving circuit in column (2k) via the first initialization connection line Cli1 in column (2k). Optionally, the first initialization connection line Cli1 in column (2k) is connected to the corresponding first reset signal line Vint1N in the current stage via an eighth via v8 extending through the interlayer dielectric layer ILD. Optionally, the first initialization connection line Cli1 in column (2k) is connected to the source S1 of the first transistor T1 in the corresponding pixel driving circuit in column (2k) through a ninth via v9 extending through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI.

[0131] Figure 4E It is along Figure 3A A cross-sectional view of line E-E' in the diagram. (Refer to...) Figure 4E as well as Figures 3A to 3H The fourth reset signal line VintB in column (2k) connects a corresponding second reset signal line (e.g., the corresponding second reset signal line Vint2N of the current stage) among a plurality of second reset signal lines to the source S6 of the sixth transistor T6 in the corresponding pixel driving circuit in column (2k). The corresponding second reset signal line (e.g., the corresponding second reset signal line Vint2N of the current stage) is configured to provide a reset signal to the source S6 of the sixth transistor T6 in the corresponding pixel driving circuit in column (2k) via the corresponding fourth reset signal line VintB in column (2k). Optionally, the corresponding fourth reset signal line VintB in column (2k) is connected to the corresponding second reset signal line Vint2N of the current stage via a tenth via v10 extending through the interlayer dielectric layer ILD. Optionally, the corresponding fourth reset signal line VintB in column (2k) is connected to the source S6 of the sixth transistor T6 in the corresponding pixel driving circuit in column (2k) via an eleventh via v11 extending through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI.

[0132] Reference Figures 3A to 3H as well as Figures 4A to 4EIn various pixel driving circuits, in some embodiments, a respective gate line among a plurality of gate lines GL includes a main portion MP extending along the extension direction of the respective gate line, and a gate protrusion GP protruding away from the main portion MP (e.g., along the direction from the current level corresponding gate line among the plurality of gate lines GL toward the current level corresponding reset control signal line rstN).

[0133] In some embodiments, as described above, the third transistor T3 is a dual-gate transistor. In some embodiments, the gate protrusion GP is one of the two gates in the third transistor T3. In some embodiments, refer to Figure 4A The orthographic projection of the gate protrusion GP on the substrate BS at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 on the substrate BS.

[0134] In some embodiments, the total number of pixel driving circuits (or the total number of sub-pixels) in each column of pixel driving circuits is P. In at least one corresponding column of pixel driving circuits, the ratio of the total number of reset signal lines extending along the second direction DR2 and passing through the P pixel driving circuits to the total number of initialization connection lines is 1:P. (Refer to...) Figure 3A , Figure 3B and Figure 3H In column (2k-1) C(2k-1), the total number of pixel driving circuits (or the total number of sub-pixels) is P. In column (2k-1) C(2k-1), the ratio of the total number of third reset signal lines to the total number of second initialization connection lines Cli2 is 1:P; the ratio of the total number of third reset signal lines to the total number of first initialization connection lines Cli1 is 1:0. In column (2k) C(2k), the total number of pixel driving circuits (or the total number of sub-pixels) is P. In column (2k) C(2k), the ratio of the total number of fourth reset signal lines to the total number of first initialization connection lines Cli1 is 1:P; the ratio of the total number of fourth reset signal lines to the total number of second initialization connection lines Cli2 is 1:0. As used herein, in the context of "the ratio of the total number of reset signal lines extending along the second direction DR2 and passing through P pixel driving circuits to the total number of initialization connection lines is 1:P", the term "P pixel driving circuits" refers to a pixel driving circuit configured to drive the light-emitting element to emit light. For example, the array substrate may include dummy sub-pixels, which may include "dummy" pixel driving circuits that cannot drive the dummy sub-pixels to emit light. Initialization connection lines may be absent in these dummy sub-pixels. Therefore, when the array substrate includes p dummy sub-pixels and (Pp) emitting sub-pixels, the ratio of the total number of reset signal lines extending along the second direction DR2 and passing through the (Pp) pixel driving circuits and the p "dummy" pixel driving circuits to the total number of initialization connection lines is 1:(Pp).

[0135] The inventors of this disclosure observed that in a correlated array substrate, subpixels of different colors experience varying degrees of degradation after reliability testing. Specifically, in the correlated array substrate, the luminous efficiency of red and blue subpixels decreases faster than that of green subpixels. This results in a green bias in the correlated array substrate after reliability testing. The inventors of this disclosure have discovered that the structure and layout of the array substrate of this disclosure avoids this problem, achieving excellent display quality.

[0136] In some embodiments, the orthographic projection of the light-shielding layer on the substrate at least partially overlaps with the orthographic projection of the active layer of each of the driving transistor, data writing transistor, compensation transistor, and reset transistor on the substrate. Figure 5 It is shown Figure 3A A schematic diagram depicting the structure of a light-shielding layer and a semiconductor material layer in a portion of an array substrate. (Refer to...) Figure 5 In some embodiments, the orthogonal projection of the light-shielding layer on the substrate at least partially overlaps with the orthogonal projections of the active layers of each of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, and the driving transistor Td on the substrate. Optionally, the orthogonal projection of the light-shielding layer on the substrate covers the orthogonal projections of the active layers of each of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, and the driving transistor Td on the substrate.

[0137] In some embodiments, the orthographic projection of the light-shielding layer onto the substrate at least partially overlaps with the orthographic projection of the gate of each of the driving transistor, data writing transistor, compensation transistor, and reset transistor onto the substrate. (See also...) Figure 3A , Figure 3C and Figure 3E In some embodiments, the orthogonal projection of the light-shielding layer on the substrate at least partially overlaps with the orthogonal projections of the gates of each of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, and the driving transistor Td on the substrate. Optionally, the orthogonal projection of the light-shielding layer on the substrate covers the orthogonal projections of the gates of each of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, and the driving transistor Td on the substrate.

[0138] Figure 6 yes Figure 3A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted. (Refer to...) Figure 6In some embodiments, the light-shielding layer includes a plurality of first light-shielding lines (e.g., a first light-shielding line LSL1N corresponding to the current level (e.g., the current row) of the plurality of first light-shielding lines, a first light-shielding line LSL1(N+1) corresponding to the next adjacent level (e.g., the next adjacent row) of the plurality of first light-shielding lines), a plurality of second light-shielding lines LSL2, and a plurality of third light-shielding lines LSL3.

[0139] Reference Figure 5 and Figure 6 In some embodiments, the orthogonal projections of the plurality of first shielding rays onto the substrate at least partially overlap with the orthogonal projections of the active layers of the first transistor T1 and the sixth transistor T6 onto the substrate. Optionally, the orthogonal projections of the plurality of first shielding rays onto the substrate cover the orthogonal projections of the active layers of the first transistor T1 and the sixth transistor T6 onto the substrate.

[0140] Reference Figure 5 and Figure 6 In some embodiments, the orthographic projection of a corresponding first shielding light among a plurality of first shielding light rays onto the substrate at least partially overlaps with the orthographic projections of the active layer of the first transistor T1 in the current row pixel driving circuit and the active layer of the sixth transistor T6 in the previous adjacent row pixel driving circuit onto the substrate. Optionally, the orthographic projection of each of the plurality of first shielding light rays onto the substrate covers the orthographic projections of the active layer of the first transistor T1 in the current row pixel driving circuit and the active layer of the sixth transistor T6 in the previous adjacent row pixel driving circuit onto the substrate.

[0141] Reference Figure 5 and Figure 6 In some embodiments, the orthographic projection of the corresponding first shading light LSL1(N+1) of the next adjacent row among the plurality of first shading light rays on the substrate at least partially overlaps with the orthographic projections of the active layer of the sixth transistor T6 in the current row pixel driving circuit and the active layer of the first transistor T1 in the next adjacent row pixel driving circuit on the substrate. Optionally, the orthographic projection of the corresponding first shading light LSL1(N+1) of the next adjacent row among the plurality of first shading light rays on the substrate covers the orthographic projections of the active layer of the sixth transistor T6 in the current row pixel driving circuit and the active layer of the first transistor T1 in the next adjacent row pixel driving circuit on the substrate.

[0142] Reference Figure 5 and Figure 6In some embodiments, the orthographic projection of the current row corresponding first shading light LSL1N among the plurality of first shading light rays on the substrate at least partially overlaps with the orthographic projections of the active layer of the first transistor T1 in the current row pixel driving circuit and the active layer of the sixth transistor T6 in the previous adjacent row pixel driving circuit on the substrate. Optionally, the orthographic projection of the current row corresponding first shading light LSL1N among the plurality of first shading light rays on the substrate covers the orthographic projections of the active layer of the first transistor T1 in the current row pixel driving circuit and the active layer of the sixth transistor T6 in the previous adjacent row pixel driving circuit on the substrate.

[0143] Reference Figure 5 and Figure 6 In some embodiments, the orthographic projection of a corresponding second shielding light among the plurality of second shielding light LSL2 onto the substrate at least partially overlaps with the orthographic projections of the active layers of the second transistor T2 and the third transistor T3 onto the substrate. Optionally, the orthographic projection of a corresponding second shielding light among the plurality of second shielding light LSL2 onto the substrate covers the orthographic projections of the active layers of the second transistor T2 and the third transistor T3 onto the substrate.

[0144] In some embodiments, each of the second light-shielding rays includes a body MB extending along a direction substantially parallel to the first direction DR1, and a light-shielding protrusion LSP protruding away from the body MB along a direction substantially parallel to the second direction DR2. The second direction DR2 is different from the first direction DR1. The orthographic projection of the light-shielding protrusion LSP on the substrate at least partially overlaps with the orthographic projection of one of the two channel portions of the active layer of the third transistor T3 on the substrate. Optionally, the orthographic projection of the light-shielding protrusion LSP on the substrate covers the orthographic projection of one of the two channel portions of the active layer of the third transistor T3 on the substrate.

[0145] Reference Figure 5 and Figure 6 In some embodiments, the orthographic projection of a corresponding third shading light among the plurality of third shading light LSL3 onto the substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor Td onto the substrate. Optionally, the orthographic projection of a corresponding third shading light among the plurality of third shading light LSL3 onto the substrate covers the orthographic projection of the active layer of the driving transistor Td onto the substrate.

[0146] In some embodiments, each third shielding light includes a plurality of islands Is and a plurality of bridges Br. Adjacent islands in the plurality of islands Is are connected by corresponding bridges in the plurality of bridges Br. The orthographic projection of each island in the plurality of islands Is onto the substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor Td onto the substrate. Optionally, the orthographic projection of each island in the plurality of islands Is onto the substrate covers the orthographic projection of the active layer of the driving transistor Td onto the substrate.

[0147] In some embodiments, each third shading light also includes an extension E extending away from one of the islands. The islands Is and the bridges Br are arranged alternately along a direction substantially parallel to the first direction DR1. The extension E extends away from one of the islands Is along a direction substantially parallel to the second direction DR2. (See reference...) Figures 3A to 3H as well as Figure 6 In some embodiments, extension E is connected to one of a plurality of voltage supply lines Vdd. In one example, one of the plurality of voltage supply lines Vdd is connected to extension E via a twelfth via v12. For example, the twelfth via v12 extends through the interlayer dielectric layer ILD, the insulating layer IN, the gate insulating layer GI, and the buffer layer BUF. In some embodiments, a corresponding third shielding line is configured to be provided with a voltage supply signal from one of the plurality of voltage supply lines Vdd.

[0148] Figure 7 It is shown Figure 3A A schematic diagram depicting the structure of the light-shielding layer and the first conductive layer in a portion of the array substrate. (Refer to...) Figure 3E , Figure 6 and Figure 7 In some embodiments, the orthographic projections of the plurality of first shielding lines on the substrate at least partially overlap with the orthographic projections of the plurality of reset control signal lines on the substrate. Optionally, the orthographic projections of the plurality of first shielding lines on the substrate cover the orthographic projections of the plurality of reset control signal lines on the substrate.

[0149] In some embodiments, the orthographic projection of the current row corresponding first shielding line LSL1N among the plurality of first shielding lines on the substrate at least partially overlaps with the orthographic projection of the current row corresponding reset control signal line rstN among the plurality of reset control signal lines on the substrate; the orthographic projection of the next adjacent row corresponding first shielding line LSL1(N+1) among the plurality of first shielding lines on the substrate at least partially overlaps with the orthographic projection of the next adjacent row corresponding reset control signal line rst(N+1) among the plurality of reset control signal lines on the substrate. Optionally, the orthographic projection of the current row corresponding first shielding line LSL1N among the plurality of first shielding lines on the substrate covers the orthographic projection of the current row corresponding reset control signal line rstN among the plurality of reset control signal lines on the substrate; the orthographic projection of the next adjacent row corresponding first shielding line LSL1(N+1) among the plurality of first shielding lines on the substrate covers the orthographic projection of the next adjacent row corresponding reset control signal line rst(N+1) among the plurality of reset control signal lines on the substrate.

[0150] In some embodiments, the orthographic projection of each of the plurality of second shielding rays LSL2 onto the substrate at least partially overlaps with the orthographic projection of the corresponding gate line among the plurality of gate lines GL onto the substrate. Optionally, the orthographic projection of each of the plurality of second shielding rays LSL2 onto the substrate covers the orthographic projection of the corresponding gate line GL among the plurality of gate lines GL onto the substrate.

[0151] In some embodiments, the orthographic projection of the main body MB of each second light-shielding light onto the substrate at least partially overlaps with the orthographic projection of the main portion MP of the corresponding gate line onto the substrate. Optionally, the orthographic projection of the main body MB of each second light-shielding light onto the substrate covers the orthographic projection of the main portion MP of the corresponding gate line onto the substrate.

[0152] In some embodiments, the orthographic projection of the light-shielding protrusion LSP of each second light-shielding line on the substrate at least partially overlaps with the orthographic projection of the gate protrusion GP of the corresponding gate line on the substrate. Optionally, the orthographic projection of the light-shielding protrusion LSP of each second light-shielding line on the substrate covers the orthographic projection of the gate protrusion GP of the corresponding gate line on the substrate.

[0153] In some embodiments, the orthographic projection of a corresponding island among the plurality of islands Is of the corresponding third light-shielding light onto the substrate at least partially overlaps with the orthographic projection of the first capacitor electrode Ce1 of the storage capacitor onto the substrate. Optionally, the orthographic projection of a corresponding island among the plurality of islands Is of the corresponding third light-shielding light onto the substrate covers the orthographic projection of the first capacitor electrode Ce1 of the storage capacitor onto the substrate.

[0154] Figure 8The layout of a light-shielding layer, a semiconductor material layer, and a first conductive layer in a portion of an array substrate according to some embodiments of the present disclosure is shown. Figure 9 It shows Figure 8 The layout of the light-shielding layer in a portion of the array substrate is depicted. (See reference...) Figure 8 and Figure 9 The array substrate includes a display area DA and a peripheral area PA. As used herein, the term "display area" refers to the area of ​​the array substrate that actually displays an image. Optionally, the display area may include subpixel areas and inter-subpixel areas. A subpixel area refers to the light-emitting area of ​​a subpixel (e.g., the area corresponding to the pixel electrode in a liquid crystal display or the area corresponding to the light-emitting layer in an organic light-emitting diode display panel). An inter-subpixel area refers to the area between adjacent subpixel areas, such as the area corresponding to the black matrix in a liquid crystal display or the area corresponding to the pixel defining layer in an organic light-emitting diode display. Optionally, the inter-subpixel area is the area between adjacent subpixel areas within the same pixel. Optionally, the inter-subpixel area is the area between two adjacent subpixel areas in two adjacent pixels. The term "peripheral area" refers to the area of ​​the array substrate in which various circuits and wires are provided to transmit signals to the display substrate. To increase the transparency of the display device, opaque or light-blocking components of the display device (e.g., batteries, printed circuit boards, metal frames) may be arranged in the peripheral area instead of the display area.

[0155] In some embodiments, a plurality of first shielding light rays and a plurality of second shielding light rays LSL2 are configured to be provided with a gate scan signal. In some embodiments, the plurality of first shielding light rays and the plurality of second shielding light rays LSL2 are connected to a gate scan circuit (e.g., a gate scan circuit on an array) configured to provide the gate scan signal. Optionally, the gate scan circuit is located in the peripheral region PA.

[0156] In some embodiments, the current row corresponding second shading light in a plurality of second shading light LSL2 and the next adjacent row corresponding first shading light LSL1(N+1) in a plurality of first shading light LSL2 are connected to each other in the peripheral region PA.

[0157] In some embodiments, the current row corresponding second shading light of a plurality of second shading light LSL2 and the next adjacent row corresponding first shading light LSL1 (N+1) of a plurality of first shading light LSL2 are connected to each other in the peripheral areas PA on both sides of the display area DA. Figure 10 An annular structure according to some embodiments of the present disclosure is shown, which is formed by a corresponding second shading light of the current row of a plurality of second shading lights and a corresponding first shading light of the next adjacent row of a plurality of first shading lights.

[0158] In some embodiments, a plurality of third shielding light lines LSL3 are configured to be provided with a voltage supply signal. As described above, each third shielding light line is configured to be provided with a voltage supply signal from one of a plurality of voltage supply lines. For example, one of the plurality of voltage supply lines is connected to an extension of the respective third shielding light line via a via. Optionally, the plurality of third shielding light lines LSL3 are connected to the same voltage supply line among the plurality of voltage supply lines.

[0159] Figure 11 The Id-Vg curves for some array substrates are shown. (Refer to...) Figure 11 Vg represents the gate voltage of the transistor, and Id represents the drain current corresponding to the gate voltage. The Id-Vg curve shows the relationship between the drain current and the gate voltage. S0 is the Id-Vg curve of the array substrate in its initial state. S1 is the Id-Vg curve of the corresponding array substrate without a light-shielding layer. S2 is the Id-Vg curve of the array substrate with a light-shielding layer according to this disclosure. Figure 11 As shown, compared to the Id-Vg curve of the array substrate with a light-shielding layer according to the present disclosure, the Id-Vg curve of the relevant array substrate has a larger drift relative to the Id-Vg curve of the array substrate in its initial state. In the array substrate with a light-shielding layer according to the present disclosure, the green shift is significantly reduced.

[0160] Figure 12 The Wy-Lv correspondences for some array substrates are shown. (Refer to...) Figure 12 Wy represents the yellow-blue axis in the color space, and Lv represents the lightness axis. For example... Figure 12 As shown, if the Wy value is less than 0.45 when the brightness value is less than 0.065 nits, the array substrate is considered to have no green shift. W0 is the Wy-Lv correspondence of the array substrate in its initial state. W1 is the Wy-Lv correspondence of the relevant array substrate without a light-shielding layer. W2 is the Wy-Lv correspondence of the array substrate with a light-shielding layer according to this disclosure. W3 is the Wy-Lv correspondence of the array substrate with a light-shielding layer that only blocks the driving transistors in the array substrate and does not block other transistors. Figure 12 As shown, the array substrate with a light-shielding layer according to this disclosure does not have a green color shift.

[0161] Various alternative layouts of the light-shielding layer can be achieved in this disclosure. Figure 13A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 13B It is shown Figure 13A A schematic diagram of the arrangement of multiple pixel driving circuits in a portion of an array substrate depicted in the figure. Figure 13C It is shown Figure 13AA schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure. Figure 13D It is shown Figure 13A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 13E It is shown Figure 13A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure. Figure 13F It is shown Figure 13A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0162] Reference Figure 13A and Figure 13C In some embodiments, the light-shielding layer includes a light-shielding element LS. (See also...) Figure 2A , Figure 2B , Figure 13A and Figure 13D Each pixel driving circuit is labeled with a number, which indicates the region corresponding to the multiple transistors (including first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and driving transistor Td) in each pixel driving circuit. Each pixel driving circuit is also labeled with a number indicating a component representing each of the multiple transistors in the pixel driving circuit. (See reference...) Figure 2A , Figure 2B , Figure 13A and Figure 13E In some embodiments, the first conductive layer includes a first capacitor electrode Ce1 of a storage capacitor Cst, a plurality of light-emitting control signal lines em, a first gate pad including the gate G1 of a first transistor T1, a second gate pad including the gate G3 of a third transistor T3, and a third gate pad including the gate G6 of a sixth transistor T6. (Refer to...) Figure 2A , Figure 2B , Figure 13A and Figure 13F In some embodiments, the first signal line layer includes a plurality of first reset control signal lines rst1, a plurality of second reset control signal lines rst2, a plurality of gate lines GL, and a plurality of voltage supply lines Vdd.

[0163] In some embodiments, the light-shielding element LS is an integral structure. In some embodiments, the orthographic projection of the integral structure of the light-shielding element LS onto the substrate at least partially overlaps with the orthographic projection of the active layer of each of the driving transistor, data writing transistor, compensation transistor, and reset transistor onto the substrate. Figure 14 yes Figure 13A A schematic diagram depicting the structure of a light-shielding layer and a semiconductor material layer in a portion of an array substrate. (Refer to...) Figure 14In some embodiments, the orthographic projection of the overall structure of the light-shielding element LS onto the substrate at least partially overlaps with the orthographic projections of the active layers of each of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, and the driving transistor Td onto the substrate. Optionally, the orthographic projection of the overall structure of the light-shielding element LS onto the substrate covers the orthographic projections of the active layers of each of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, and the driving transistor Td onto the substrate.

[0164] In some embodiments, the orthographic projection of the light-shielding layer onto the substrate at least partially overlaps with the orthographic projection of the gate of each of the driving transistor, data writing transistor, compensation transistor, and reset transistor onto the substrate. (Refer to...) Figure 13A , Figure 13C and Figure 13E In some embodiments, the orthographic projection of the overall structure of the light-shielding element LS onto the substrate at least partially overlaps with the orthographic projection of the gate of each of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, and the driving transistor Td onto the substrate. Optionally, the orthographic projection of the overall structure of the light-shielding element LS onto the substrate covers the orthographic projection of the gate of each of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, and the driving transistor Td onto the substrate.

[0165] Figure 15 The layout of a light-shielding layer in a portion of an array substrate according to some embodiments of the present disclosure is shown. (Refer to...) Figure 15 In some embodiments, the light-shielding layer is an interconnected light-shielding network extending across a plurality of sub-pixels in the array substrate. The interconnected light-shielding network includes light-shielding lines extending in a direction substantially parallel to a first direction DR1 and light-shielding lines extending in a direction substantially parallel to a second direction DR2. In some embodiments, the light-shielding layer includes a plurality of first islands Is1, a plurality of second islands Is2, a plurality of first bridges Br1, a plurality of second bridges Br2, a plurality of third bridges Br3, and a plurality of branches Ba.

[0166] In some embodiments, the light-shielding layer comprises multiple rows of islands; each row of islands comprises multiple first islands of multiple first islands Is1 arranged in a direction substantially parallel to the first direction DR1, and multiple second islands of multiple second islands Is2 arranged in a direction substantially parallel to the first direction DR1. In some embodiments, a corresponding first bridge of a plurality of first bridges Br1 connects the first islands of multiple first islands Is1 and the second islands of multiple second islands Is2 in two adjacent rows. In some embodiments, a corresponding second bridge of a plurality of second bridges Br2 connects the first islands of multiple first islands Is1 and the second islands of multiple second islands Is2 in the same row. In some embodiments, a corresponding third bridge of a plurality of third bridges Br3 connects two adjacent first islands of multiple first islands Is1 in the same row. In some embodiments, each branch of a plurality of branches Ba extends away from the corresponding first island of the plurality of first islands Is1, for example, along a direction substantially parallel to the second direction DR2.

[0167] Reference Figure 14 , Figure 15 as well as Figures 13A to 13E In some embodiments, the orthographic projection of a corresponding first island among the plurality of first islands Is1 onto the substrate at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor Td onto the substrate. Optionally, the orthographic projection of a corresponding first island among the plurality of first islands Is1 onto the substrate covers the orthographic projection of the active layer ACTd of the driving transistor Td onto the substrate. In some embodiments, the orthographic projection of a corresponding first island among the plurality of first islands Is1 onto the substrate at least partially overlaps with the orthographic projection of the first capacitor electrode Ce1 of the storage capacitor onto the substrate. Optionally, the orthographic projection of a corresponding first island among the plurality of first islands Is1 onto the substrate covers the orthographic projection of the first capacitor electrode Ce1 of the storage capacitor onto the substrate.

[0168] In some embodiments, the orthographic projection of a corresponding second island among the plurality of second islands Is2 onto the substrate at least partially overlaps with the orthographic projection of the active layer ACT3 of the third transistor T3 onto the substrate. Optionally, the orthographic projection of a corresponding second island among the plurality of second islands Is2 onto the substrate covers the orthographic projection of the active layer ACT3 of the third transistor T3 onto the substrate. In some embodiments, the orthographic projection of a corresponding second island among the plurality of second islands Is2 onto the substrate at least partially overlaps with the orthographic projection of the gate G3 of the third transistor T3 onto the substrate. Optionally, the orthographic projection of a corresponding second island among the plurality of second islands Is2 onto the substrate covers the orthographic projection of the gate G3 of the third transistor T3 onto the substrate.

[0169] In some embodiments, the orthographic projection of a corresponding branch of the plurality of branches Ba onto the substrate at least partially overlaps with the orthographic projection of the active layer ACT2 of the second transistor T2 onto the substrate. Optionally, the orthographic projection of a corresponding branch Ba of the plurality of branches Ba onto the substrate covers the orthographic projection of the active layer ACT2 of the second transistor T2 onto the substrate. In some embodiments, the orthographic projection of a corresponding branch Ba of the plurality of branches Ba onto the substrate at least partially overlaps with the orthographic projection of the gate of the second transistor T2 onto the substrate. Optionally, the orthographic projection of each branch Ba of the plurality of branches Ba onto the substrate covers the orthographic projection of the gate of the second transistor T2 onto the substrate.

[0170] In some embodiments, the orthographic projection of a corresponding first bridge among the plurality of first bridges Br1 onto the substrate at least partially overlaps with the orthographic projections of the active layer ACT1 of the first transistor T1 and the active layer ACT6 of the sixth transistor T6 onto the substrate. Optionally, the orthographic projection of a corresponding first bridge among the plurality of first bridges Br1 onto the substrate covers the orthographic projections of the active layer ACT1 of the first transistor T1 and the active layer ACT6 of the sixth transistor T6 onto the substrate. In some embodiments, the orthographic projection of a corresponding first bridge among the plurality of first bridges Br1 onto the substrate at least partially overlaps with the orthographic projections of the gate G1 of the first transistor T1 and the gate G6 of the sixth transistor T6 onto the substrate. Optionally, the orthographic projection of a corresponding first bridge among the plurality of first bridges Br1 onto the substrate covers the orthographic projections of the gate G1 of the first transistor T1 and the gate G6 of the sixth transistor T6 onto the substrate.

[0171] In some embodiments, the light-shielding element for blocking each of the driving transistor, data writing transistor, compensation transistor, and reset transistor is configured to be provided with the same voltage signal. In one example, the light-shielding element for blocking each of the driving transistor, data writing transistor, compensation transistor, and reset transistor is configured to be provided with a voltage supply signal. In another example, the light-shielding element for blocking each of the driving transistor, data writing transistor, compensation transistor, and reset transistor is configured to be provided with a gate scan signal.

[0172] Figure 16A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 16B It is shown Figure 16A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure. Figure 16C It is shown Figure 16A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 16D It is shown Figure 16AA schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure. Figure 16E It is shown Figure 16A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted. (Refer to...) Figures 16A to 16E In some embodiments, the array substrate includes a display area DA and a peripheral area PA.

[0173] In some embodiments, the light-shielding layer includes a peripheral light-shielding signal line PLSL in the peripheral region PA and a plurality of peripheral connection lines PCL connecting the light-shielding element LS in the display region DA to the peripheral light-shielding signal line PLSL in the peripheral region PA. As described above, in some embodiments, the light-shielding element LS in the display region DA includes multiple rows of islands; each row of islands includes a plurality of first islands Is1 arranged in a direction substantially parallel to the first direction DR1 and a plurality of second islands Is2 arranged in a direction substantially parallel to the first direction DR1. Adjacent rows in the multiple rows of islands are connected by a plurality of bridges (e.g., by a plurality of first bridges Br1).

[0174] In some embodiments, corresponding peripheral connection lines in a plurality of peripheral connection lines PCL connect corresponding rows in a multi-row island to peripheral shading signal lines PLSL. Shading elements LS in display area DA are configured to be supplied with the same voltage signal provided by the peripheral shading signal lines PLSL. In one example, the peripheral shading signal lines PLSL in peripheral area PA and the shading elements LS in display area DA are configured to be supplied with voltage supply signals. In another example, the peripheral shading signal lines PLSL in peripheral area PA and the shading elements LS in display area DA are configured to be supplied with a grid scan signal.

[0175] Figure 17A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 17B It is shown Figure 17A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure. Figure 17C It is shown Figure 17A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 17D It is shown Figure 17A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure. Figure 17E It is shown Figure 17A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the figure. Figure 17F It is shown Figure 17A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted. (Refer to...) Figures 17A to 17FIn some embodiments, the light-shielding layer includes a plurality of first light-shielding LSL1, a plurality of second light-shielding LSL2, and a plurality of third light-shielding LSL3.

[0176] In some embodiments, the orthographic projections of the plurality of first shielding rays LSL1 on the substrate at least partially overlap with the orthographic projections of the active layers of the first transistor T1 and the sixth transistor T6 on the substrate. Optionally, the orthographic projections of the plurality of first shielding rays on the substrate cover the orthographic projections of the active layers of the first transistor T1 and the sixth transistor T6 on the substrate.

[0177] In some embodiments, the orthographic projection of a corresponding first shielding light among the plurality of first shielding light LSL1 onto the substrate at least partially overlaps with the orthographic projections of the active layer of the first transistor T1 in the current row pixel driving circuit and the active layer of the sixth transistor T6 in the previous adjacent row pixel driving circuit onto the substrate. Optionally, the orthographic projection of a corresponding first shielding light among the plurality of first shielding light LSL1 onto the substrate covers the orthographic projections of the active layer of the first transistor T1 in the current row pixel driving circuit and the active layer of the sixth transistor T6 in the previous adjacent row pixel driving circuit onto the substrate.

[0178] In some embodiments, the orthographic projection of a corresponding second shielding light among the plurality of second shielding light LSL2 onto the substrate at least partially overlaps with the orthographic projections of the active layers of the second transistor T2 and the third transistor T3 onto the substrate. Optionally, the orthographic projection of a corresponding second shielding light among the plurality of second shielding light LSL2 onto the substrate covers the orthographic projections of the active layers of the second transistor T2 and the third transistor T3 onto the substrate.

[0179] In some embodiments, each of the second light-shielding rays includes a body MB extending along a direction substantially parallel to the first direction DR1, and a light-shielding protrusion LSP protruding away from the body MB along a direction substantially parallel to the second direction DR2. The second direction DR2 is different from the first direction DR1. The orthographic projection of the light-shielding protrusion LSP on the substrate at least partially overlaps with the orthographic projection of one of the two channel portions of the active layer of the third transistor T3 on the substrate. Optionally, the orthographic projection of the light-shielding protrusion LSP on the substrate covers the orthographic projection of one of the two channel portions of the active layer of the third transistor T3 on the substrate.

[0180] In some embodiments, the orthographic projection of a corresponding third shading light among the plurality of third shading light LSL3 onto the substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor Td onto the substrate. Optionally, the orthographic projection of a corresponding third shading light among the plurality of third shading light LSL3 onto the substrate covers the orthographic projection of the active layer of the driving transistor Td onto the substrate.

[0181] In some embodiments, each third shielding light includes a plurality of islands Is and a plurality of bridges Br. Adjacent islands in the plurality of islands Is are connected by corresponding bridges in the plurality of bridges Br. The orthographic projection of a corresponding island in the plurality of islands Is onto the substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor Td onto the substrate. Optionally, the orthographic projection of a corresponding island in the plurality of islands Is onto the substrate covers the orthographic projection of the active layer of the driving transistor Td onto the substrate.

[0182] In some embodiments, the orthographic projections of the plurality of first shielding lines on the substrate at least partially overlap with the orthographic projections of the plurality of reset control signal lines on the substrate. Optionally, the orthographic projections of the plurality of first shielding lines on the substrate cover the orthographic projections of the plurality of reset control signal lines on the substrate.

[0183] In some embodiments, the orthographic projection of each of the plurality of second shielding rays LSL2 onto the substrate at least partially overlaps with the orthographic projection of the corresponding gate line in the plurality of gate lines GL onto the substrate. Optionally, the orthographic projection of each of the plurality of second shielding rays LSL2 onto the substrate covers the orthographic projection of the corresponding gate line in the plurality of gate lines GL onto the substrate.

[0184] In some embodiments, the orthographic projection of the main body MB of each second light-shielding light onto the substrate at least partially overlaps with the orthographic projection of the main portion MP of the corresponding gate line onto the substrate. Optionally, the orthographic projection of the main body MB of each second light-shielding light onto the substrate covers the orthographic projection of the main portion MP of the corresponding gate line onto the substrate.

[0185] In some embodiments, the orthographic projection of the light-shielding protrusion LSP of each second light-shielding line on the substrate at least partially overlaps with the orthographic projection of the gate protrusion GP of the corresponding gate line on the substrate. Optionally, the orthographic projection of the light-shielding protrusion LSP of each second light-shielding line on the substrate covers the orthographic projection of the gate protrusion GP of the corresponding gate line on the substrate.

[0186] In some embodiments, the orthographic projection of a corresponding island among the plurality of islands Is of each third light-shielding element on the substrate at least partially overlaps with the orthographic projection of the first capacitor electrode Ce1 of the storage capacitor on the substrate. Optionally, the orthographic projection of a corresponding island among the plurality of islands Is of each third light-shielding element on the substrate covers the orthographic projection of the first capacitor electrode Ce1 of the storage capacitor on the substrate.

[0187] In some embodiments, the array substrate includes a display area DA and a peripheral area PA. Figures 17A to 17F The array substrate depicted in the image and Figure 8 The difference between the array substrates depicted in the text is: Figures 17A to 17F The light-shielding layer in the array substrate depicted is not connected to the multiple voltage supply lines in the display area DA. Furthermore, Figures 17A to 17F The third light shielding in the array substrate depicted in the figure does not need to include the extension E.

[0188] In some embodiments, the light-shielding layer includes a peripheral light-shielding signal line PLSL in the peripheral region PA, and a plurality of peripheral connection lines PCL connecting a plurality of third light-shielding lines LSL3 in the display region DA to the peripheral light-shielding signal line PLSL in the peripheral region PA.

[0189] In some embodiments, each peripheral connection line in the plurality of peripheral connection lines PCL connects a corresponding third shading line in the plurality of third shading lines LSL3 to a peripheral shading signal line PLSL. Each third shading line in the display area DA is configured to be provided with the same voltage signal supplied by the peripheral shading signal line PLSL. In one example, the peripheral shading signal line PLSL in the peripheral area PA and the plurality of third shading lines LSL3 in the display area DA are configured to be provided with a voltage supply signal. In another example, the peripheral shading signal line PLSL in the peripheral area PA and the plurality of third shading lines LSL3 in the display area DA are configured to be provided with a grid scan signal.

[0190] In some embodiments, a plurality of first shielding light LSL1 and a plurality of second shielding light LSL2 are connected to a gate scanning circuit in a peripheral region PA, and the gate scanning circuit (e.g., an array-on-grid scanning circuit) is configured to provide a gate scanning signal to the plurality of first shielding light LSL1 and the plurality of second shielding light LSL2.

[0191] Figure 18A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 18B It is shown Figure 18A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure. Figure 18C It is shown Figure 18A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 18D It is shown Figure 18A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the diagram. Figure 18E It is shown Figure 18A A schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the diagram. Figure 18F It is shown Figure 18A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure. Figures 18A to 18F The array substrate depicted in the image and Figures 17A to 17F The difference between the array substrates depicted in the text is: Figures 18A to 18FThe light-shielding layer in the array substrate depicted is connected to both the peripheral light-shielding signal line PLSL in the peripheral region PA and multiple voltage supply lines in the display region DA. Furthermore, Figures 18A to 18F Each of the third light-shielding rays in the array substrate depicted includes an extension E.

[0192] Reference Figures 18A to 18F In some embodiments, each third light shield also includes an extension E that extends away from one of the multiple islands. The multiple islands Is and the multiple bridges Br are arranged alternately along a direction substantially parallel to the first direction DR1. The extension E extends away from one of the multiple islands Is along a direction substantially parallel to the second direction DR2. (See also...) Figures 18A to 18F In some embodiments, the extension E is connected to one of a plurality of voltage supply lines Vdd. In one example, this one voltage supply line of the plurality of voltage supply lines Vdd is connected to the extension E via a via. For example, the via extends through the interlayer dielectric layer ILD, the insulating layer IN, the gate insulating layer GI, and the buffer layer BUF. In some embodiments, a corresponding third shielding line is configured to be provided with a voltage supply signal from this one voltage supply line of the plurality of voltage supply lines Vdd.

[0193] Reference Figures 18A to 18F In some embodiments, the light-shielding layer includes a peripheral light-shielding signal line PLSL in the peripheral region PA, and a plurality of peripheral connection lines PCL connecting a plurality of third light-shielding lines LSL3 in the display region DA to the peripheral light-shielding signal line PLSL in the peripheral region PA. In some embodiments, each peripheral connection line in the plurality of peripheral connection lines PCL connects a corresponding third light-shielding line among the plurality of third light-shielding lines LSL3 to the peripheral light-shielding signal line PLSL. Each third light-shielding line in the display region DA is configured to be provided with the same voltage signal provided by the peripheral light-shielding signal line PLSL. In one example, the peripheral light-shielding signal line PLSL in the peripheral region PA and the plurality of third light-shielding lines LSL3 in the display region DA are configured to be provided with a voltage supply signal.

[0194] Figure 19A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 19B It is shown Figure 19A A schematic diagram of the structure of the light-shielding layer in a portion of the array substrate depicted in the figure. Figure 19C It is shown Figure 19A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 19D It is shown Figure 19A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure. Figure 19E It is shown Figure 19AA schematic diagram of the structure of the second conductive layer in a portion of the array substrate depicted in the figure. Figure 19F It is shown Figure 19A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure. Figures 19A to 19F The array substrate depicted in the image and Figures 3A to 3H The difference in the array substrate depicted is that the multiple islands Is are separated from each other and from the rest of the light-shielding layer.

[0195] Reference Figures 19A to 19F In some embodiments, the light-shielding layer includes a plurality of first light-shielding lines LSL1, a plurality of second light-shielding lines LSL2, a plurality of islands Is separated from each other, and a plurality of extensions ET. Each extension of the plurality of extensions ET extends away from a corresponding island of the plurality of islands Is. Each extension extends away from the corresponding island of the plurality of islands Is along a direction substantially parallel to the second direction DR2.

[0196] In some embodiments, each extension is connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd. In one example, each voltage supply line among the plurality of voltage supply lines Vdd is connected to the corresponding extension via a via. For example, the via extends through the interlayer dielectric layer ILD, the insulating layer IN, the gate insulating layer GI, and the buffer layer BUF. In some embodiments, the corresponding extension and the corresponding island are configured to be provided with a voltage supply signal from one of the plurality of voltage supply lines Vdd.

[0197] In some embodiments, the orthographic projection of a corresponding island in the plurality of islands Is onto the substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor Td onto the substrate. Optionally, the orthographic projection of a corresponding island in the plurality of islands Is onto the substrate covers the orthographic projection of the active layer of the driving transistor Td onto the substrate.

[0198] In some embodiments, the orthographic projection of a corresponding island among the plurality of islands Is onto the substrate at least partially overlaps with the orthographic projection of the first capacitor electrode Ce1 of the storage capacitor onto the substrate. Optionally, the orthographic projection of a corresponding island among the plurality of islands Is onto the substrate covers the orthographic projection of the first capacitor electrode Ce1 of the storage capacitor onto the substrate.

[0199] Reference Figures 8 to 10 , Figures 17A to 17F , Figures 18A to 18F as well as Figures 19A to 19FIn some embodiments, the orthographic projection of a first portion of the light-shielding layer onto the substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor onto the substrate, and the orthographic projection of a second portion of the light-shielding layer onto the substrate at least partially overlaps with the orthographic projection of the active layer of at least one of the data write transistor, compensation transistor, and one or more reset transistors onto the substrate. Optionally, the first and second portions are configured to be provided with different signals. Optionally, the first portion is configured to be provided with a constant voltage signal, and the second portion is configured to be provided with a pulse signal. In one example, the first portion is configured to be provided with a voltage supply signal, and the second portion is configured to be provided with a gate scan signal.

[0200] Reference Figures 8 to 10 as well as Figures 17A to 17F In some embodiments, the first portion includes a plurality of third shielding light LSL3, and the second portion includes a plurality of first shielding light LSL2 and a plurality of second shielding light LSL2. Optionally, the plurality of first shielding light LSL2 and the plurality of second shielding light LSL2 are connected to a gate scan circuit configured to provide a gate scan signal. Optionally, the plurality of third shielding light LSL3 are connected to a signal line configured to provide a voltage supply signal.

[0201] In some embodiments, refer to Figures 8 to 10 , Figures 3A to 3H as well as Figures 4A to 4E One of the multiple voltage supply lines Vdd is connected via a via to an extension of the corresponding third shielding light LSL3 among the multiple third shielding light LSL3. Optionally, the multiple third shielding light LSL3 are connected to the same voltage supply line among the multiple voltage supply lines Vdd.

[0202] In some embodiments, refer to Figures 17A to 17F The light-shielding layer also includes a peripheral light-shielding signal line PLSL located in the peripheral region PA of the array substrate, and a plurality of peripheral connection lines PCL connecting a plurality of third light-shielding lines LSL3 in the display region DA of the array substrate and the peripheral light-shielding signal line PLSL in the peripheral region PA.

[0203] In some embodiments, refer to Figures 18A to 18F One of the multiple voltage supply lines Vdd is connected via a via to an extension of a corresponding third shading line among the multiple third shading lines LSL3. Optionally, the multiple third shading lines LSL3 are connected to the same voltage supply line among the multiple voltage supply lines Vdd. Optionally, the light-shielding layer also includes a peripheral light-shielding signal line PLSL located in the peripheral region PA of the array substrate, and multiple peripheral connection lines PCL connecting the multiple third shading lines LSL3 in the display region DA of the array substrate to the peripheral light-shielding signal line PLSL in the peripheral region PA.

[0204] In some embodiments, refer to Figures 19A to 19F The first part includes multiple islands Is separated from each other and multiple extensions ET. The second part includes multiple first shielding light LSL1 and multiple second shielding light LSL2. Optionally, each extension in the multiple extensions ET extends away from the corresponding island in the multiple islands Is. Optionally, each voltage supply line in the multiple voltage supply lines Vdd is connected to the corresponding extension through a via.

[0205] On the other hand, the present invention provides a display device comprising an array substrate manufactured as described herein or by means of the methods described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptops, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device.

[0206] On the other hand, this disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes: forming a plurality of pixel driving circuits. Optionally, forming each pixel driving circuit in the plurality of pixel driving circuits includes: forming a driving transistor, forming a data writing transistor, forming a compensation transistor, forming one or more reset transistors, and forming a storage capacitor. Optionally, the method further includes: forming a light-shielding layer. Optionally, the orthographic projection of the light-shielding layer on the substrate at least partially overlaps with the orthographic projection of the active layer of each of the driving transistor, data writing transistor, compensation transistor, and one or more reset transistors on the substrate.

[0207] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate comprising multiple pixel driving circuits; in, Each pixel driving circuit in the plurality of pixel driving circuits includes a driving transistor, a data writing transistor, a compensation transistor, one or more reset transistors, and a storage capacitor. The array substrate further includes a light-shielding layer, the orthographic projection of which on the substrate at least partially overlaps with the orthographic projection of the active layer of each of the driving transistor, the data writing transistor, the compensation transistor, and the one or more reset transistors on the substrate. The light-shielding layer includes a plurality of first light-shielding layers; The orthographic projection of each of the plurality of first shading rays on the substrate covers the orthographic projection of the active layer of the one or more reset transistors on the substrate; and the orthographic projection of the corresponding first shading ray of the current row of the plurality of first shading rays on the substrate covers the orthographic projection of the active layer of the first reset transistor in the current row pixel driving circuit and the active layer of the second reset transistor in the previous adjacent row pixel driving circuit on the substrate; and the orthographic projection of the corresponding first shading ray of the next adjacent row of the plurality of first shading rays on the substrate covers the orthographic projection of the active layer of the second reset transistor in the current row pixel driving circuit and the active layer of the first reset transistor in the next adjacent row pixel driving circuit on the substrate. The light-shielding layer also includes multiple second light-shielding layers; The current row of the plurality of second shading rays and the next adjacent row of the plurality of first shading rays are connected to each other in the surrounding area to form a ring structure.

2. The array substrate according to claim 1, wherein, The orthogonal projection of the light-shielding layer on the substrate covers the orthogonal projection of the active layer of each of the driving transistor, the data writing transistor, the compensation transistor, and the one or more reset transistors on the substrate.

3. The array substrate according to claim 1 further includes a plurality of reset control signal lines; in, The orthographic projection of each of the first shielding rays on the substrate at least partially overlaps with the orthographic projection of the corresponding reset control signal line among the plurality of reset control signal lines on the substrate.

4. The array substrate according to any one of claims 1 to 3, wherein, The orthographic projection of each of the plurality of second shielding rays onto the substrate covers the orthographic projection of the active layer of the data writing transistor and the active layer of the compensation transistor onto the substrate.

5. The array substrate according to claim 4, wherein, It also includes multiple gate lines; The orthographic projection of each of the second shielding rays on the substrate at least partially overlaps with the orthographic projection of the corresponding grating line among the plurality of grating lines on the substrate.

6. The array substrate according to claim 1, wherein, The plurality of first shielding light rays and the plurality of second shielding light rays are connected to a grid scanning circuit located in the peripheral region and configured to provide a grid scanning signal.

7. The array substrate according to claim 1, wherein, The light-shielding layer includes multiple islands; The orthographic projection of each of the plurality of islands on the substrate overlaps at least partially with the orthographic projection of the first capacitor electrode of the storage capacitor on the substrate.

8. The array substrate according to claim 7 further includes a plurality of voltage supply lines; in, The light-shielding layer also includes multiple extensions; The multiple islands are separated from each other; Each of the plurality of extensions extends away from the corresponding island extension of the plurality of islands; and Each extension is connected to a corresponding voltage supply line among the plurality of voltage supply lines.

9. The array substrate according to claim 7, wherein, The light-shielding layer also includes multiple bridges; Adjacent islands among the plurality of islands are connected by corresponding bridges among the plurality of bridges.

10. The array substrate according to claim 9, further comprising a plurality of voltage supply lines; in, The light-shielding layer also includes an extension extending away from one of the plurality of islands; The extension is connected to one of the plurality of voltage supply lines.

11. The array substrate according to claim 9, comprising a display area and a peripheral area; in, The light-shielding layer includes a plurality of third light-shielding lines located in the display area, a peripheral light-shielding signal line located in the peripheral area, and a plurality of peripheral connection lines located in the peripheral area. Each of the plurality of third shielding rays includes a portion of the plurality of islands and a portion of the plurality of bridges; as well as Each of the plurality of peripheral connection lines connects the corresponding third shading light line to the peripheral shading signal line.

12. The array substrate according to claim 1, comprising K reset signal lines, wherein the K reset signal lines are respectively configured to provide reset signals to reset transistors in K column pixel driving circuits of the array substrate; in, The K reset signal lines include: Multiple third reset signal lines, located in column 2k-1 of column K, where K and k are positive integers, 1≤k≤K / 2; and Multiple fourth reset signal lines, located in the 2kth column of the K columns; Each of the third reset signal lines and each of the fourth reset signal lines has a different line pattern.

13. A display device comprising an array substrate according to any one of claims 1 to 12, and one or more integrated circuits connected to the array substrate.

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