Bandgap reference circuit and power management module

Abstract

The present disclosure relates to a bandgap reference circuit and a power management module, wherein the bandgap reference circuit comprises a reference voltage generation module, an output buffer module and a delay module; the reference voltage generation module is configured to generate a first bandgap reference signal and a delay control signal, wherein the first bandgap reference signal comprises an overshoot phase; the delay module is configured to receive the delay control signal and output a buffer start signal according to the delay control signal; the output buffer module is configured to receive the first bandgap reference signal and the buffer start signal, and output a second bandgap reference signal in response to the buffer start signal, wherein the second bandgap reference signal does not comprise an overshoot phase. The bandgap reference circuit provided by the present disclosure can eliminate the overshoot voltage generated during the power-on process, ensure the safety of the subsequent circuit devices, and also ensure the timing safety and stability during the power-on process of the power supply system. At the same time, the bandgap reference circuit comprising the output buffer module also has strong load current carrying capacity.

Description

Technical Field

[0001] This disclosure relates to the field of electronic circuit technology, and in particular to a bandgap reference circuit and a power management module. Background Technology

[0002] In communication chips, the power management module is fundamental to all other modules, providing power to the receiver, transmitter, clock frequency synthesis module, and digital processing module with varying performance requirements. Within the power module management system, the bandgap reference voltage module is crucial, providing a stable reference voltage to each independent linear regulator, boost converter, and voltage detection circuit. This reference voltage is characterized by its independence from changes in power supply voltage and temperature. Summary of the Invention

[0003] To address the aforementioned technical problems, this disclosure provides a bandgap reference circuit and a power management module.

[0004] This disclosure provides a bandgap reference circuit, including a reference voltage generation module, an output buffer module, and a delay module. The reference voltage generation module is used to generate a first bandgap reference signal and a delay control signal, wherein the first bandgap reference signal includes an overshoot phase. The delay module is used to receive the delay control signal and output a buffer enable signal according to the delay control signal. The output buffer module is used to receive the first bandgap reference signal and the buffer enable signal, and is used to output a second bandgap reference signal in response to the buffer enable signal, wherein the second bandgap reference signal does not include the overshoot phase.

[0005] Optionally, both the delay control signal and the buffer enable signal include a disable phase and an enable phase, with the enable phase following the disable phase; the second bandgap reference signal includes a shielding phase and a constant voltage output phase, with the constant voltage output phase following the shielding phase; in response to a period of time after the delay control signal transitions from the disable phase to the enable phase, the buffer enable signal transitions from the disable phase to the enable phase; in response to the buffer enable signal transitioning from the disable phase to the enable phase, the second bandgap reference signal transitions from the shielding phase to the constant voltage output phase.

[0006] Optionally, the first bandgap reference signal further includes a constant phase, which is located after the overshoot phase; the moment when the buffer enable signal transitions from the disable phase to the enable phase is located after the moment when the first bandgap reference signal transitions from the overshoot phase to the constant phase.

[0007] Optionally, the first bandgap reference signal further includes a constant phase, wherein the voltage peak value of the first bandgap reference signal in the overshoot phase is greater than the voltage peak value of the first bandgap reference signal in the constant phase; the second bandgap reference signal includes a shielding phase and a constant voltage output phase, wherein the voltage peak value of the second bandgap reference signal in the shielding phase is less than the voltage peak value of the second bandgap reference signal in the constant voltage output phase.

[0008] Optionally, the reference voltage generation module includes a reference voltage generation unit and a startup unit; the reference voltage generation unit is used to generate the first bandgap reference signal; the startup unit is used to generate the delay control signal based on the first bandgap reference signal.

[0009] Optionally, the reference voltage generation unit includes: a negative temperature coefficient generation unit, including multiple transistors and resistors, for generating a negative temperature coefficient signal; and a positive temperature coefficient generation unit, including multiple field-effect transistors and resistors, for generating a positive temperature coefficient signal; specifically, the reference voltage generation unit is used to generate the first bandgap reference signal based on the negative temperature coefficient signal and the positive temperature coefficient signal; the reference voltage generation unit further includes a power amplifier, the power amplifier including multiple field-effect transistors, and is used to keep the first bandgap reference signal stable.

[0010] Optionally, the startup unit includes two inverters connected in series; the input terminals of the two inverters connected in series are used to receive the first bandgap reference signal, and the output terminals of the two inverters connected in series are used to output the delay control signal.

[0011] Optionally, the delay module includes a delay capacitor; the delay module is specifically used to: receive the delay control signal, charge the delay capacitor according to the delay control signal, and output the buffer enable signal in response to the delay capacitor being fully charged.

[0012] Optionally, the output buffer module includes an output power amplifier; the input terminal of the output power amplifier is used to receive the first bandgap reference signal, the enable terminal of the output power amplifier is used to receive the buffer enable signal, and the output terminal of the output power amplifier is used to output the second bandgap reference signal.

[0013] Based on the same inventive concept, this disclosure also provides a power management module, including any of the bandgap reference circuits described in any one of the claims.

[0014] Compared with existing technologies, the technical solution provided in this disclosure has the following advantages: The bandgap reference circuit provided in this disclosure can eliminate overshoot voltage generated during power-on, ensuring the safety of subsequent circuit devices and the timing safety and stability of the power supply system during power-on. Simultaneously, the bandgap reference circuit, including the output buffer module, also has a strong load-carrying current capability. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a bandgap reference circuit provided in an embodiment of the present disclosure;

[0018] Figure 2 This is a schematic diagram of another bandgap reference circuit provided in an embodiment of the present disclosure;

[0019] Figure 3 A timing diagram of each signal in a bandgap reference circuit provided in an embodiment of this disclosure;

[0020] Figure 4 A circuit schematic diagram of a reference voltage generation module provided in an embodiment of this disclosure;

[0021] Figure 5 A circuit schematic diagram of a delay module provided in an embodiment of this disclosure;

[0022] Figure 6 This is a circuit schematic diagram of an output buffer module provided in an embodiment of the present disclosure. Detailed Implementation

[0023] To better understand the above-mentioned objectives, features, and advantages of the embodiments of this disclosure, the solutions of the embodiments of this disclosure will be further described below. It should be noted that, unless otherwise specified, the embodiments of this disclosure and the features within them can be combined with each other.

[0024] Numerous specific details are set forth in the following description in order to provide a full understanding of the embodiments of this disclosure, but the embodiments of this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some embodiments of the embodiments of this disclosure, and not all embodiments.

[0025] Power management chips are the foundation of all communication chips, and the bandgap reference circuit is the core circuit module of the power management chip, providing a stable reference voltage for the entire chip.

[0026] The characteristic of a bandgap reference voltage is that it does not change with the power supply voltage or with temperature. A typical way to generate it is to use the positive temperature coefficient of the constructed PTAT current and the negative temperature coefficient of the transistor VBE to cancel each other out in a certain proportion.

[0027] Traditional bandgap reference voltage output values ​​are approximately 1.2V, which is provided as a reference voltage to various circuit sub-modules in the power supply system. Typically, the bandgap reference voltage is connected to the gate of the devices in the subsequent sub-modules. Bandgap reference voltage circuits in related technologies often generate a large overshoot voltage at startup. Output with overshoot voltage can pose a risk of gate breakdown to subsequent circuits and may also affect the normal power-on timing.

[0028] In related technologies, the following methods are used to eliminate the overshoot voltage output of bandgap reference circuits;

[0029] The first method involves adding a capacitor to ground at the output node of the output stage buffer cascaded with the bandgap reference circuit. This capacitor typically requires a large value to eliminate overshoot in the buffer's output voltage, and the size of this capacitor is largely constrained by the overall chip area cost. Furthermore, a large off-chip capacitor results in a slow bandgap reference voltage settling time. A slow settling time often fails to meet system requirements. Therefore, while this method is simple, its high cost and obvious drawbacks are significant.

[0030] The second method involves adding a clamping circuit to the output node of the output stage buffer cascaded with the bandgap reference circuit. When an overshoot occurs in the output voltage, multiple diodes connected in series with ground conduct, pulling the output terminal down through a path to ground. When the output voltage is clamped to the normal value, the multiple diodes connected in series with ground turn off, stabilizing the output value. However, because the turn-on voltage of the transistors connected to the clamping circuit at the output node is easily affected by temperature and process variations, it often impacts the accuracy of the output voltage value.

[0031] The third method involves increasing the capacitance between the output node of the bandgap reference voltage core amplifier and the power supply. When the startup circuit is not operating, the voltage across the capacitor is the power supply value, and the capacitor has no stored charge. Once the startup circuit starts operating, it charges the capacitor, causing the voltage at the lower plate to drop. By controlling the charging current, undervoltage is prevented at the lower plate, thus indirectly ensuring that the bandgap reference voltage output does not generate overshoot. The drawback of this method is that the magnitude of the pull-down current cannot be accurately controlled, making it highly susceptible to overshoot in the bandgap reference voltage output.

[0032] In view of this, embodiments of the present disclosure provide a bandgap reference circuit, such as Figure 1 As shown, it includes a reference voltage generation module 10, an output buffer module 20, and a delay module 30. The reference voltage generation module 10 is connected to the output buffer module 20 and the delay module 30, and the output buffer module 20 is connected to the delay module 30.

[0033] The reference voltage generation module 10 is used to generate a first bandgap reference signal VREF_INTER and a delay control signal DELAY_IN, wherein the first bandgap reference signal VREF_INTER includes an overshoot phase.

[0034] The delay module 30 is used to receive the delay control signal DELAY_IN and output the buffer enable signal READY according to the delay control signal DELAY_IN.

[0035] The output buffer module 20 is used to receive the first bandgap reference signal VREF_INTER and the buffer enable signal READY, and to output the second bandgap reference signal VREF_1P2 in response to the buffer enable signal READY. The second bandgap reference signal VREF_1P2 does not include an overshoot phase. Specifically, the output buffer module 20 receives the buffer enable signal READY later than it receives the first bandgap reference signal VREF_INTER. The overshoot phase of the first bandgap reference signal VREF_INTER occurs at its start time. By the time the output buffer module 20 receives the buffer enable signal READY, the overshoot phase of the first bandgap reference signal VREF_INTER has passed. At this point, the second bandgap reference signal VREF_1P2 output by the output buffer module 20 based on the first bandgap reference signal VREF_INTER does not include an overshoot phase.

[0036] The bandgap reference circuit provided in this disclosure can eliminate overshoot voltage generated during power-on, ensuring the safety of subsequent circuit devices and the timing safety and stability of the power supply system during power-on. Simultaneously, the bandgap reference circuit, including the output buffer module, also has a strong load-carrying current capability.

[0037] Furthermore, the circuit provided in this embodiment eliminates overshoot voltage by delaying the start of the output buffer module 20, rather than directly shutting down the output path of the reference voltage generation module 10. This improves the flexibility of the circuit. In other words, the circuit provided in this embodiment can provide both the first bandgap reference signal VREF_INTER, which includes the overshoot stage, and the second bandgap reference signal VREF_1P2, which does not include the overshoot stage. In actual power system applications, both the first bandgap reference signal VREF_INTER and the second bandgap reference signal VREF_1P2 can have corresponding application scenarios, thereby enabling the bandgap reference circuit to provide a wider range of applications.

[0038] In some embodiments, such as Figure 2 As shown, the reference voltage generation module 10 includes a reference voltage generation unit 11 and a startup unit 12.

[0039] The reference voltage generation unit 11 is used to generate the first bandgap reference signal VREF_INTER.

[0040] The startup unit 12 is used to generate a delay control signal DELAY_IN based on the first bandgap reference signal VREF_INTER.

[0041] In some cases, the reference voltage generation unit may get stuck in a "latch-up" state when generating the bandgap reference signal, meaning the circuit output remains at a low voltage level and cannot rise to the normal reference voltage value on its own. This situation typically occurs during the initial startup phase of the circuit, when all nodes are in a low voltage state, and the negative feedback mechanism may be insufficient to pull the output up to the required operating voltage.

[0042] The aforementioned startup unit provides an initial bias to the reference voltage generation unit, that is, it provides an initial bias voltage or current when the reference voltage generation unit is first powered on, enabling the reference voltage generation unit to smoothly transition from a zero-voltage state to a normal operating state. Simultaneously, the startup circuit helps the reference voltage generation unit quickly reach a stable operating state after power-on, reducing startup time.

[0043] In the above embodiments of this disclosure, the startup circuit also functions as a delay control signal DELAY_IN, which is equivalent to providing a delay control signal to the delay module in response to the reference voltage generation unit reaching a stable working state, thereby realizing the delay output of the circuit.

[0044] In specific implementation, the output of the first bandgap reference signal VREF_INTER from the reference voltage generation unit 11 serves as the input to the startup unit 12. When the initial voltage of the first bandgap reference signal VREF_INTER is 0V, the startup unit 12 starts working, and the output of the first bandgap reference signal VREF_INTER from the reference voltage generation unit 11 also serves as the input to the output buffer module 20. The startup unit 12 establishes the first bandgap reference signal VREF_INTER, and at the same time, the startup unit 12 generates a delay control signal DELAY_IN. The delay control signal DELAY_IN enters the delay module 30 for delay processing. The delay module 30 transmits the buffer enable signal READY, which has undergone delay processing, to the output buffer module 20. The buffer enable signal READY controls the startup of the output buffer module 20, that is, the overshoot voltage of the first bandgap reference signal VREF_INTER is shielded by the buffer enable signal READY. When the overshoot is eliminated, the output buffer module 20 is turned on, and the second bandgap reference signal VREF_1P2, which does not have an overshoot, is transmitted to the next cascaded circuit.

[0045] In some embodiments, the timing diagrams of the first bandgap reference signal VREF_INTER, the delay control signal DELAY_IN, the buffer enable signal READY, and the second bandgap reference signal VREF_1P2 are as follows: Figure 3 As shown.

[0046] The delay control signal DELAY_IN and the buffer enable signal READY both include a closing phase t1 and an enabling phase t2, with the enabling phase t2 following the closing phase t1.

[0047] The second bandgap reference signal VREF_1P2 includes a shielding stage t3 and a constant voltage output stage t4, with the constant voltage output stage t4 located after the shielding stage t3.

[0048] In response to a time interval T0 after the delay control signal DELAY_IN transitions from the off phase t1 to the on phase t2, the buffer enable signal READY transitions from the off phase t1 to the on phase t2; in response to the buffer enable signal READY transitioning from the off phase t1 to the on phase t2, the second bandgap reference signal VREF_1P2 transitions from the shielding phase t3 to the constant voltage output phase t4.

[0049] The first bandgap reference signal VREF_INTER includes an overshoot phase t5 and a constant phase t6, with the constant phase t6 located after the overshoot phase t5.

[0050] The timing of the buffer enable signal READY transitioning from the off phase t1 to the enable phase t2 is after the timing of the first bandgap reference signal VREF_INTER transitioning from the overshoot phase t5 to the constant phase t6. Consequently, the timing of the second bandgap reference signal VREF_1P2 transitioning from the shielding phase t3 to the constant voltage output phase t4 is after the timing of the first bandgap reference signal VREF_INTER transitioning from the overshoot phase t5 to the constant phase t6, thus achieving the elimination of overshoot.

[0051] Understandably, in Figure 3 In the illustrated embodiment, the delay control signal DELAY_IN and the buffer enable signal READY are both represented by a high level to indicate the enable stage t2 and a low level to indicate the disable stage t1. In other embodiments, due to different circuit structures, the disable stage t1 and the enable stage t2 may also be represented by opposite levels, all of which are within the protection scope of this disclosure.

[0052] In one embodiment, such as Figure 3 As shown, the peak voltage of the first bandgap reference signal VREF_INTER in the overshoot phase t5 is greater than the peak voltage of the first bandgap reference signal VREF_INTER in the constant phase t6. That is, the first bandgap reference signal VREF_INTER will have an overshoot voltage in the overshoot phase t5.

[0053] The second bandgap reference signal VREF_1P2 includes a shielding phase t3 and a constant voltage output phase t4. The peak voltage of the second bandgap reference signal VREF_1P2 in the shielding phase t3 is less than the peak voltage of the second bandgap reference signal VREF_1P2 in the constant voltage output phase t4. In specific implementations, the voltage of the second bandgap reference signal VREF_1P2 in the shielding phase t3 is actually close to zero, but it can also be regarded as having a lower peak voltage than the peak voltage of the second bandgap reference signal VREF_1P2 in the constant voltage output phase t4, as a manifestation excluding the aforementioned overshoot voltage.

[0054] In some embodiments, such as Figure 4 As shown, the reference voltage generation unit 11 includes a negative temperature coefficient generation unit 111, a positive temperature coefficient generation unit 112, and a power amplifier AMP1, wherein:

[0055] The negative temperature coefficient generation unit 111 includes multiple transistors and resistors for generating negative temperature coefficient signals; the positive temperature coefficient generation unit 112 includes multiple field-effect transistors and resistors for generating positive temperature coefficient signals.

[0056] The reference voltage generation unit 11 is specifically used for:

[0057] The first bandgap reference signal VREF_INTER is generated based on the negative temperature coefficient signal and the positive temperature coefficient signal.

[0058] Specifically, such as Figure 4 As shown, the reference voltage generation unit 11 is composed of multiple P-type field-effect transistors PM10, PM11, PM12, PM13, PM14, PM15, and PM16, multiple N-type field-effect transistors NM4, NM5, NM6, and NM7, multiple PNP transistors PNP1 and PNP2, multiple resistors R1, R2, R3, and R4, and multiple capacitors C0 and C1. The specific connection method is shown in the figure.

[0059] The positive temperature coefficient generation unit 112 includes PM14, PM15, PM16, and R4, and is used to generate a positive temperature coefficient signal, specifically a positive temperature coefficient current. The negative temperature coefficient generation unit 111 includes PNP1, PNP2, R1, R2, R3, and C1, and is used to generate a negative temperature coefficient signal, specifically a negative temperature coefficient current. The positive and negative temperature coefficient signals cancel each other out at node C according to a certain ratio, thereby generating the aforementioned first bandgap reference signal VREF_INTER.

[0060] The power amplifier AMP1 includes multiple field-effect transistors and is used to stabilize the first bandgap reference signal VREF_INTER. For example... Figure 4 As shown, PM10, PM11, PM12, PM13, NM4, NM5, and NM6 constitute the aforementioned power amplifier. The function of power amplifier AMP1 is to clamp the voltages of nodes A and B to maintain consistency.

[0061] In the reference voltage generation unit 11, the power amplifier AMP1 is mainly used to implement functions such as negative feedback control, current mirroring, improving accuracy and stability, temperature compensation, and startup and self-locking protection. The power amplifier AMP1 ensures that the reference voltage generation unit 11 can generate an accurate, stable, and temperature-independent first bandgap reference signal VREF_INTER.

[0062] In specific implementation, such as Figure 4 As shown, resistor R0 and capacitor CO are used to ensure the stability of the circuit system; N-type field-effect transistor NM7 is a pull-down switch. When the reference voltage generation unit 11 is turned off, NM7 is turned on, pulling the voltage at node C down to 0.

[0063] In some embodiments, such as Figure 4 As shown, the start-up unit 12 includes two inverters INV2 and INV3 connected in series.

[0064] The input terminals of the two series-connected inverters INV2 and INV3 are connected to node C and used to receive the first bandgap reference signal VREF_INTER. The output terminals of the two series-connected inverters INV2 and INV3 are used to output the delay control signal DELAY_IN.

[0065] Specifically, such as Figure 4 As shown, the startup unit 12 is composed of multiple P-type field-effect transistors PM1, PM2, PM3, PM4, PM5, PM6, PM7, PM8, and PM9, multiple N-type field-effect transistors NM1, NM2, and NM3, and multiple inverters INV1, INV2, and INV3. The specific connection method is shown in the figure.

[0066] In specific implementation, when the first bandgap reference signal VREF_INTER is established, the first bandgap reference signal VREF_INTER is 0, PM1, PM2, PM3, and PM4 are not turned on, NM1 is turned on, and the drain of NM1 is pulled low to 0 potential. Through the logic transmission of inverters INV2 and INV3, the gate voltages of PM5, PM6, PM7, and PM8 are 0, and the gate voltage of PM9 is 0. The gate voltage of NM3 is also 0 due to the total enable control. The drain voltage of PM9 is high, so the STUP node (i.e., the node connecting PM9 and NM3) is in a high state. At this time, NM6 in the reference voltage generation unit 11 is in a conducting state, the drain voltage of PM13 is pulled low, PM13 is turned on, and the PM13 and NM6 branches are turned on, creating a path from power supply to ground. PM14, PM15, and PM16 mirror the current of PM13 proportionally. The first bandgap reference signal VREF_INTER is established, and the startup unit 12 is successfully started.

[0067] When the first bandgap reference signal VREF_INTER is established, the gate state of NM1 is high, and NM1 is turned off. At the same time, PM1, PM2, PM3, and PM4 are all pulled up and turned on. The drain voltage of PM4 is high, and PM5, PM6, PM7, and PM8 are turned off through INV2 and INV3. Since the gate voltage of NM3 is controlled by the total enable, the gate voltage of NM3 is 0, so the current of the NM3 branch is 0. The drain voltage STUP of NM3 is not affected by this branch. The voltage of STUP is only controlled by the power amplifier AMP1 of the reference voltage generation unit 11. Thus, the startup unit 12 completes the startup operation.

[0068] The startup unit 12 in the above embodiments of this disclosure adopts an internal bandgap reference voltage feedback structure, thus resulting in a faster startup time.

[0069] In some embodiments, such as Figure 5 As shown, the delay module 30 includes a delay capacitor CT, and the delay module 30 is specifically used for:

[0070] Receive the delay control signal DELAY_IN and charge the delay capacitor CT according to the delay control signal DELAY_IN. In response to the delay capacitor CT being fully charged, output the buffer enable signal READY.

[0071] In specific implementation, the delay module 30 consists of a delay capacitor CT, a NAND gate (or NOR gate), multiple inverters INV4, INV5, and INV6, multiple field-effect transistors P0, N0, and P1, an enable terminal ENP for receiving an enable signal, and a bias circuit IBIAS. The connection method of each component in the delay module 30 is as follows: Figure 5 As shown, the connection method between the delay module 30 and the aforementioned reference voltage generation module 10 and output buffer module 20 is as follows: Figure 4 As shown.

[0072] The delay module 30 controls the charging and discharging of the delay capacitor CT by controlling the opening and closing of P0 and N0. The over-delayed signal passes through the NOR gate NOR0 and multiple inverters INV4, INV5 and INV6, and the output is passed to the buffer enable signal READY. The buffer enable signal READY can be latched by the latching function of P1.

[0073] like Figure 5 As shown, the delay capacitor CT is connected to the VSS level. When the input signal voltage fluctuates, the delay capacitor CT has a discharge path, which supports signal fluctuations and eliminates the risk of failure during secondary power-on, thereby preventing module failure.

[0074] In some embodiments, such as Figure 6 As shown, the output buffer module 20 includes an output power amplifier AMP2.

[0075] The input terminal of the output power amplifier AMP2 is used to receive the first bandgap reference signal VREF_INTER, the enable terminal of the output power amplifier AMP2 is used to receive the buffer enable signal READY, and the output terminal VOUT of the output power amplifier AMP2 is used to output the second bandgap reference signal VREF_1P2. Specifically, the output power amplifier AMP2 includes a first enable terminal ENP and a second enable terminal ENN. The first enable terminal ENP is used to receive the buffer enable signal READY, such as... Figure 6 As shown, the signals received by the first enable terminal ENP and the second enable terminal ENN are in opposite phase.

[0076] In practical implementation, the output buffer module 20 is composed of multiple field-effect transistors P2, P3, P4, P5, P6, N1, N2, N3, N4, N5, N6, and N7, resistors R5 and R6, and capacitor C3. The connection method of each component in the output buffer module 20 is as follows: Figure 6 As shown, the connection method between the output buffer module 20 and the aforementioned reference voltage generation module 10 and delay module 30 is as follows: Figure 4 As shown.

[0077] like Figure 6 As shown, the output power amplifier AMP2 loop consists of P2, P3, N3, N4, and N5. The output of the output power amplifier AMP2 is connected to the gate of N6, and the source of N6 serves as the output of the output buffer module 20. The source of N6 and the gate of N4 are interconnected to form a feedback connection. The opening and closing of the output buffer module 20 is controlled by the signal received from the first enable terminal ENP. In one embodiment, when the first enable terminal ENP receives a high level, the output buffer module 20 is turned on; when the first enable terminal ENP receives a low level, the output buffer module 20 is turned off. When the output buffer module 20 is turned off, the gate of the output branch P4 is at a high level and is in the off state. The output terminal VOUT is directly connected to ground through the resistor series R5 and R6. After the charge on the output terminal VOUT is quickly discharged through the resistor series R5 and R6, the output is at a 0 level. In the output buffer module 20, the first enable terminal ENP is used to receive the buffer enable signal READY. The output buffer module 20 controls the output terminal VOUT to output the second bandgap reference signal VREF_1P2 according to the buffer enable signal READY, thereby eliminating the overshoot voltage of the first bandgap reference signal VREF_INTER. When the overshoot voltage is eliminated and the bandgap reference voltage is stable, the output buffer module 20 is turned on and transmits the stable second bandgap reference signal VREF_1P2.

[0078] In specific implementation, such as Figure 6 As shown, P5 and P6 are transistors used as switches. When the output buffer module 20 is off, the gate of P5 is high, and the gate of N1 is low, preventing the bias current IBIAS path from conducting. When the output buffer module 20 is on, the gate of P5 is low, and the gate of N1 is high, allowing the bias current IBIAS path to conduct. When the output buffer module 20 is off, the gate of P6 is low, P6 conducts, pulling the gates of P2 and P3 high, turning off the current in the P2 and P3 paths. When the output buffer module 20 is on, the gate of P6 is high, P6 is off, the gate voltages of P2 and P3 operate at normal voltages, and the current in the P2 and P3 paths conducts. Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides a power management module, including the bandgap reference circuit of any of the above embodiments.

[0079] The power management module provided in this embodiment can eliminate overshoot voltage generated during power-on, ensuring the safety of downstream circuit devices and the timing stability of the power system during power-on. Simultaneously, the bandgap reference circuit, including the output buffer module, also has a strong load-carrying current capability.

[0080] Specifically, in the aforementioned power management module, the bandgap reference circuit is used to provide a stable reference voltage for each independent linear regulator, boost converter, voltage detection circuit, etc. The characteristic of this reference voltage is that it does not change with the power supply voltage or temperature.

[0081] The apparatus of the above embodiments includes the corresponding bandgap reference circuit that implements any of the foregoing embodiments, and has the beneficial effects of the corresponding embodiments, which will not be repeated here.

[0082] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the aforementioned element.

[0083] The foregoing description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described above, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A bandgap reference circuit, characterized in that, It includes a reference voltage generation module, an output buffer module, and a delay module; The reference voltage generation module is used to generate a first bandgap reference signal and a delay control signal, wherein the first bandgap reference signal includes an overshoot phase; The reference voltage generation module includes a reference voltage generation unit and a startup unit; The input terminal of the startup unit is connected to the output terminal of the reference voltage generation unit, and is used to receive the first bandgap reference signal; the output terminal of the startup unit is connected to the delay module, and is used to generate the delay control signal based on the first bandgap reference signal, and at the same time realize the startup of the reference voltage generation unit. The delay module is used to receive the delay control signal and output a buffer enable signal according to the delay control signal; The output buffer module is used to receive the first bandgap reference signal and the buffer enable signal, and is used to output a second bandgap reference signal in response to the buffer enable signal, wherein the second bandgap reference signal does not include the overshoot phase.

2. The bandgap reference circuit according to claim 1, characterized in that, Both the delay control signal and the buffer enable signal include a closing phase and an enabling phase, with the enabling phase following the closing phase. The second bandgap reference signal includes a shielding stage and a constant voltage output stage, wherein the constant voltage output stage is located after the shielding stage; In response to a certain period of time after the delay control signal changes from the off phase to the on phase, the buffer enable signal changes from the off phase to the on phase; In response to the buffer enable signal changing from the disable phase to the enable phase, the second bandgap reference signal changes from the shielding phase to the constant voltage output phase.

3. The bandgap reference circuit according to claim 2, characterized in that, The first bandgap reference signal further includes a constant phase, which is located after the overshoot phase; The moment when the buffer enable signal transitions from the disable phase to the enable phase is after the moment when the first bandgap reference signal transitions from the overshoot phase to the constant phase.

4. The bandgap reference circuit according to claim 1, characterized in that, The first bandgap reference signal further includes a constant phase, wherein the voltage peak value of the first bandgap reference signal in the overshoot phase is greater than the voltage peak value of the first bandgap reference signal in the constant phase. The second bandgap reference signal includes a shielding stage and a constant voltage output stage. The peak voltage of the second bandgap reference signal in the shielding stage is less than the peak voltage of the second bandgap reference signal in the constant voltage output stage.

5. The bandgap reference circuit according to claim 1, characterized in that, The reference voltage generation unit includes: The negative temperature coefficient generation unit includes multiple transistors and resistors, used to generate negative temperature coefficient signals; The positive temperature coefficient generation unit includes multiple field-effect transistors and resistors, used to generate a positive temperature coefficient signal; The reference voltage generation unit is specifically used for: The first bandgap reference signal is generated based on the negative temperature coefficient signal and the positive temperature coefficient signal; The reference voltage generation unit further includes a power amplifier, which includes multiple field-effect transistors and is used to stabilize the first bandgap reference signal.

6. The bandgap reference circuit according to claim 1, characterized in that, The startup unit includes at least one inverter INV1 and one N-type field-effect transistor NM1. The input terminal of the inverter INV1 is used to receive the first bandgap reference signal, and the output terminal of the inverter INV1 is electrically connected to the gate of the field-effect transistor NM1. One terminal of the field-effect transistor NM1 is used to receive the VSS level. The startup unit also includes two inverters connected in series. The input terminals of the two series-connected inverters are used to receive the signal output from the other terminal of the field-effect transistor NM1, and the output terminals of the two series-connected inverters are used to output the delay control signal.

7. The bandgap reference circuit according to claim 1, characterized in that, The delay module includes a delay capacitor; The delay module is specifically used for: The system receives the delay control signal and charges the delay capacitor according to the delay control signal. In response to the delay capacitor being fully charged, the system outputs the buffer enable signal.

8. The bandgap reference circuit according to claim 1, characterized in that, The output buffer module includes an output power amplifier; The input terminal of the output power amplifier is used to receive the first bandgap reference signal, the enable terminal of the output power amplifier is used to receive the buffer enable signal, and the output terminal of the output power amplifier is used to output the second bandgap reference signal.

9. A power management module, characterized in that, Includes the bandgap reference circuit as described in any one of claims 1 to 8.

Images