Three-dimensional semiconductor device and preparation method thereof

Abstract

The invention discloses a three-dimensional semiconductor device and a preparation method thereof. The three-dimensional semiconductor device includes a plurality of semiconductor layers, a plurality of word lines, a plurality of bit lines, and a plurality of storage nodes. The plurality of semiconductor layers are arranged at intervals along a first horizontal direction and a vertical direction, and the semiconductor layers extend along a second horizontal direction. The plurality of word lines are arranged at intervals in the vertical direction, extend in the first horizontal direction and comprise a pair of wires located on the two opposite surfaces of the semiconductor layer in the vertical direction respectively. The conductive line includes a plurality of first portions and a plurality of second portions arranged alternately. In the second horizontal direction, the size of the first part is larger than that of the second part. The plurality of bit lines are arranged at intervals along a first horizontal direction, extend along a vertical direction, and are coupled to one ends of the plurality of semiconductor layers in the vertical direction. The storage node is coupled to the other end of the semiconductor layer. The three-dimensional semiconductor device at least can improve the current driving capability of the transistor and reduce mutual interference between adjacent storage units.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to three-dimensional semiconductor devices and methods for preparing the same. Background Art

[0002] The development of memory pursues performance indicators such as high speed, high integration density, and low power consumption. As the size of semiconductor device structures shrinks, the technical barriers encountered by existing structures are becoming more and more obvious. Therefore, developing more novel structures based on existing structures is a favorable means to break through existing technical barriers.

[0003] The emergence of three-dimensional memory meets the above requirements. However, the three-dimensional memory has insufficient current driving capability of the storage array transistors and crosstalk between adjacent storage cells caused by the passing-gate effect (PEG), which affects the performance of the device. Summary of the invention

[0004] According to a first aspect of an embodiment of the present disclosure, a three-dimensional semiconductor device is provided, comprising: a plurality of semiconductor layers arranged at intervals along a first horizontal direction and along a vertical direction, each semiconductor layer extending along a second horizontal direction intersecting the first horizontal direction; a plurality of word lines arranged at intervals along the vertical direction, each word line extending along the first horizontal direction, and each word line comprising a pair of conductive wires respectively arranged on two opposite surfaces of each semiconductor layer in the vertical direction; wherein each conductive wire comprises a plurality of first portions and a plurality of second portions arranged alternately, and in the second horizontal direction, a size of the first portion is larger than a size of the second portion; a plurality of bit lines arranged at intervals along the first horizontal direction, each bit line extending along the vertical direction, and each bit line coupled to one end of the plurality of semiconductor layers in the vertical direction; and a plurality of storage nodes, each storage node coupled to the other end of each semiconductor layer.

[0005] In some embodiments, in the vertical direction, a size of the semiconductor layer near one end of the bit line is smaller than a size of the semiconductor layer near one end of the storage node.

[0006] In some embodiments, along the first horizontal direction, a size of the semiconductor layer close to one end of the bit line is smaller than a size of the semiconductor layer close to one end of the storage node.

[0007] In some embodiments, multiple storage nodes are cylindrical, including: multiple lower electrodes, arranged at intervals in a first horizontal direction and a vertical direction, and respectively coupled to one end of a corresponding multiple semiconductor layers; each lower electrode includes two opposite surfaces; a first capacitor dielectric layer, located on one surface of the multiple lower electrodes; a first upper electrode, located on the surface of the first capacitor dielectric layer; a second capacitor dielectric layer, located on another surface of the multiple lower electrodes and connected to the first capacitor dielectric layer; a second upper electrode, located on the surface of the second capacitor dielectric layer, and connected in series with the first upper electrode.

[0008] According to a first aspect of an embodiment of the present disclosure, a method for preparing a three-dimensional semiconductor device is provided, comprising: providing a substrate, and forming a stacked layer of a plurality of first sacrificial layers and a plurality of second sacrificial layers arranged alternately on the substrate; forming a first vertical opening penetrating the stacked layer, the first vertical opening extending along a first horizontal direction; selectively etching the plurality of second sacrificial layers in the stacked layer along the first vertical opening, and forming a plurality of gate dielectric layers and a plurality of word lines, the plurality of word lines being arranged at intervals in a vertical direction, each word line extending along a first horizontal direction and comprising a pair of conductive wires, wherein each conductive wire comprises a plurality of first portions and a plurality of second portions arranged alternately, and along the second horizontal direction, the size of the first portion is larger than the size of the second portion; the first horizontal direction intersects with the second horizontal direction; filling a third sacrificial layer in the first vertical opening, and forming a plurality of second vertical openings penetrating the third sacrificial layer, the plurality of second sacrificial layers extending along a first horizontal direction; Two vertical openings are arranged at intervals along the first horizontal direction; a plurality of bit lines are formed in the plurality of second vertical openings respectively and are arranged at intervals along the first horizontal direction, and each bit line extends in the vertical direction; a third vertical opening is formed that penetrates the stack layer, and the third vertical opening extends along the first horizontal direction; a plurality of first sacrificial layers in the stack layer are selectively etched along the third vertical opening, and a plurality of storage nodes are formed; a plurality of fourth vertical openings are formed that penetrate the stack layer and are located between the first vertical opening and the third vertical opening, and the plurality of fourth vertical openings are arranged at intervals along the first horizontal direction; the remaining first sacrificial layers in the stack layer are selectively etched along the plurality of fourth vertical openings respectively, and a plurality of semiconductor layers are formed that are arranged at intervals along the first horizontal direction and along the vertical direction, and a pair of conductive wires are respectively provided on two opposite surfaces of the semiconductor layer in the vertical direction, and the bit lines and storage nodes are respectively coupled at both ends of the semiconductor layer in the second horizontal direction.

[0009] In some embodiments, the method further includes: etching two opposite surfaces of multiple first sacrificial layers in the stacked layer in the vertical direction along the first vertical opening by a dry etching process to reduce the size of the first sacrificial layer in the vertical direction near one end of the first vertical opening.

[0010] In some embodiments, it also includes: after filling the third sacrificial layer in the first vertical opening, forming a plurality of first vertical openings penetrating the third sacrificial layer, and the plurality of first vertical openings are arranged at intervals along the first horizontal direction; etching the plurality of first sacrificial layers in the stacked layer by a wet etching process along the plurality of first vertical openings respectively, and narrowing the size of the first sacrificial layer near one end of the second vertical opening in the first horizontal direction; removing the third sacrificial layer between the plurality of first vertical openings to form a plurality of second vertical openings; selectively etching the plurality of first sacrificial layers in the stacked layer along the plurality of second vertical openings respectively, and increasing the contact area between the second vertical openings and the first sacrificial layer; and forming a plurality of bit lines in the plurality of second vertical openings respectively.

[0011] In some embodiments, forming a plurality of word lines comprises: depositing a conductor material between a plurality of first sacrificial layers along a first vertical opening to form an initial word line layer, the initial word line layer comprising a first portion and a second portion; removing the sidewalls of the initial word line layer exposed in the first vertical opening along the first vertical opening to form a plurality of first intermediate word line layers spaced apart in a vertical direction; forming a plurality of second vertical openings penetrating the stacked layers, each second vertical opening exposing the sidewalls of the second portions of the plurality of first intermediate word line layers spaced apart in a vertical direction; removing the sidewalls of the second portions of the plurality of first intermediate word line layers along the plurality of second vertical openings respectively to form a plurality of second intermediate word line layers; selectively etching a plurality of first sacrificial layers in the stacked layers along a third vertical opening until the sidewalls of the first portions of the plurality of second intermediate word line layers are exposed; removing the sidewalls of the first portions of the plurality of second intermediate word line layers along the third vertical opening to form a plurality of word lines, each word line comprising a pair of conductors.

[0012] In some embodiments, forming multiple storage nodes includes: forming multiple lower electrodes between multiple second sacrificial layers along a third vertical opening, the multiple lower electrodes respectively contacting one end of the corresponding multiple first sacrificial layers; forming a first capacitor dielectric layer on a surface of the multiple lower electrodes along the third vertical opening; and forming a first upper electrode on the surface of the first capacitor dielectric layer along the third vertical opening.

[0013] In some embodiments, it also includes: forming a plurality of third vertical openings that penetrate the stacked layer and are located between the third vertical opening and a plurality of fourth vertical openings, the plurality of third vertical openings being arranged at intervals along the first horizontal direction; selectively etching the remaining second sacrificial layer in the stacked layer along the plurality of third vertical openings to expose another surface of the plurality of lower electrodes; forming a second capacitor dielectric layer on another surface of the plurality of lower electrodes along the plurality of third vertical openings, the second capacitor dielectric layer also being located on the first capacitor dielectric layer; forming a second upper electrode on the surface of the second capacitor dielectric layer along the plurality of third vertical openings, and connecting the first upper electrode and the second upper electrode in series.

[0014] In an embodiment of the present disclosure, a three-dimensional semiconductor device is provided, wherein a word line includes a pair of conductive wires located on two surfaces opposite to each other in a vertical direction of each semiconductor layer, and each conductive wire includes a plurality of first parts and a plurality of second parts arranged alternately, and in a direction extending along the semiconductor layer, a size of the first part is larger than a size of the second part. A three-dimensional semiconductor device structure of a dual-gate field effect transistor is provided, which can significantly improve the current driving capability of the transistor, and reduce the influence of the PGE effect (passing-gate effect) on adjacent storage cells, thereby improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic perspective view of a three-dimensional semiconductor device according to an exemplary embodiment. ;

[0016] Figure 2A is a partial plan view of a three-dimensional semiconductor device according to an exemplary embodiment;

[0017] Figure 2B is along Figure 2A A longitudinal section taken along the midline A-A';

[0018] Figure 3A is a plan view of a three-dimensional semiconductor device according to another embodiment of the present disclosure;

[0019] Figure 3B is along Figure 3A A longitudinal section taken along the midline A-A';

[0020] Figures 4 to 26 is a schematic structural diagram of each stage in a method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present disclosure;

[0021] Fig. 27 The diagram is a schematic structural diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0022] The technical solutions of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0023] Figure 1 is a schematic perspective view of a three-dimensional semiconductor device according to an exemplary embodiment. Figure 2A is a partial plan view of a three-dimensional semiconductor device according to an exemplary embodiment. Figure 2B is along Figure 2A Longitudinal section taken along the center line A-A'. Please refer to Figures 1 to 2BThe three-dimensional semiconductor device in the embodiment of the present disclosure includes a substrate 10 and a memory cell array having a plurality of memory cells, which includes a plurality of semiconductor layers 100, a plurality of word lines 200, a plurality of bit lines 300, and a plurality of storage nodes 400. These memory cells are arranged in a first horizontal direction X and a vertical direction Z on the substrate 10, that is, arranged in a three-dimensional array. Each memory cell includes a transistor Tr and a storage node Cap coupled to each other in a second horizontal direction Y.

[0024] Please continue to refer to Figure 1 The substrate 100 includes, for example, silicon, such as single crystal silicon, polycrystalline silicon or amorphous silicon, and can also be selected from at least one of germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs) and indium phosphide (InP).

[0025] Please continue to refer to Figure 1 , multiple semiconductor layers 100 are arranged in a first horizontal direction X and a vertical direction Z, each semiconductor layer 100 extends along a second horizontal direction Y intersecting the first horizontal direction X. In some embodiments, the first horizontal direction X, the second horizontal direction Y, and the vertical direction Z are perpendicular to each other. The multiple semiconductor layers 100 are isolated from each other by an isolation structure, and the isolation structure may include at least one of silicon oxide, silicon nitride, or silicon oxynitride ( Figure 1 Part of the isolation structure is omitted), so that the multiple semiconductor layers 100 are arranged in a three-dimensional array on the substrate 10, and thus the multiple memory cells are arranged in a three-dimensional array.

[0026] Please continue to refer to Figure 1 and Figure 2A The semiconductor layer 100 can form an active region of the transistor Tr, and the semiconductor layer 100 includes a first source / drain region 110, a channel region 120, and a second source / drain region 130 arranged in sequence along the second horizontal direction Y. The first source / drain region 110 and the second source / drain region 130 are respectively located at two ends of the semiconductor layer 100. The semiconductor layer 100 also has two surfaces opposite to each other in the vertical direction Z.

[0027] The semiconductor layer 100 is made of semiconductor materials, such as single crystal silicon, polycrystalline silicon, germanium, silicon germanium, or metal oxide semiconductor materials, such as at least one of indium tin oxide (ITO), indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), and indium gallium oxide (IGO). In some embodiments, an insulating dielectric layer, such as a composite layer of silicon oxide, aluminum oxide, and a metal oxide semiconductor material, may be provided, and the metal oxide semiconductor material surrounds the surface of the insulating dielectric layer, which can operate at a relatively small operating current.

[0028] Please continue to refer to Figure 1 and Figure 2B , the three-dimensional semiconductor device further includes a plurality of dielectric layers 140, the plurality of dielectric layers 140 are arranged alternately in the first horizontal direction X and the vertical direction Z, each dielectric layer 140 is in contact with the corresponding semiconductor layer 100, and can form a gate dielectric layer of the transistor Tr. The dielectric layer 140 includes a pair of gate dielectric layers covering two opposite surfaces of the semiconductor layer 100 in the vertical direction Z, for example, at least covering the channel region 120 in the semiconductor layer 100, and the dielectric layer has a relatively flat surface. In this embodiment, the plurality of dielectric layers 140 are arranged in the same manner as the semiconductor layer 100. Of course, in other embodiments, each of the plurality of dielectric layers 140 can extend along the first horizontal direction X and continuously contact the plurality of semiconductor layers 100 in the first horizontal direction X.

[0029] The material of the dielectric layer 140 can be selected from at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k dielectric film having a dielectric constant higher than that of silicon oxide, such as hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO3), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), and zirconium oxide (ZrO).

[0030] Please continue to refer to Figures 1 to 2B , a plurality of word lines 200 are arranged at intervals along the vertical direction Z, each word line 200 extends along the first horizontal direction X, each word line 200 contacts the gate dielectric layer, is disposed on the corresponding semiconductor layer, and forms the gate electrode of the transistor Tr. Each word line 200 includes a pair of conductive wires 210 and 220, which are respectively located on two opposite surfaces of each semiconductor layer 100 in the vertical direction Z, so that the word line 200 is called a horizontal double word line or a horizontal double gate.

[0031] Please continue to refer to Figures 1 to 2B, a pair of conductive wires 210, 200 are symmetrically distributed with respect to the semiconductor layer 100, and the two are paired with each other and coupled to a storage unit. Each of the pair of conductive wires, for example, the conductive wire 210, includes a plurality of first parts 210A and a plurality of second parts 210B arranged alternately, and along the second horizontal direction Y, the size WA of the first part 210A is greater than the size WB of the second part 210B. The first part 210A contacts the gate dielectric layer and is arranged on the semiconductor layer 100 to form the gate part of the transistor Tr to ensure the electrical performance of the transistor. The second part 210B is located between two adjacent semiconductor layers 100 in the first horizontal direction X. A plurality of relatively wide first parts 210A form a conductive wire extending along the first horizontal direction X through a relatively narrow second part 210B. In the embodiment of the present disclosure, by using a horizontal double word line in which the size WA of the first part 210A is greater than the size WB of the second part 210B, the current driving capability of the storage array transistor of the three-dimensional memory can be improved, and the mutual interference between adjacent storage cells caused by the PGE (passing-gate effect) can be reduced. In some embodiments, the width WA of the first portion 210A along the second horizontal direction Y may be greater than or equal to the width of the dielectric layer 140 .

[0032] The material of word line 200 may be selected from at least one of doped polysilicon, metal, metal nitride or metal carbide, such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), titanium aluminum carbide (TiAlC), titanium aluminum carbonitride (TiAlCN), titanium silicon carbonitride (TiSiCN), tantalum aluminum carbonitride (TaAlCN) and tantalum silicon carbonitride (TaSiCN). In some embodiments, word line 200 is, for example, titanium nitride.

[0033] Please continue to refer to Figure 1 and Figure 2B , a plurality of bit lines 300 are arranged at intervals along a first horizontal direction X, and each bit line 300 extends along a vertical direction Z. Figure 1 As shown, each bit line 300 is coupled to one end of a plurality of semiconductor layers 100 in the vertical direction Z, such as the first source / drain region 110 of the semiconductor layer 100. The bit line 300 includes a vertically extending column 310 and a plurality of protrusions 320, wherein the plurality of protrusions 320 are integrally formed with the column 310 and are arranged at intervals on the vertically extending column 310. Each bit line 300 contacts the plurality of semiconductor layers 100 in the vertical direction through the plurality of protrusions 320.

[0034] The material of the bit line 300 may be selected from at least one of doped polysilicon, metal, metal nitride or metal carbide, such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), titanium aluminum carbide (TiAlC), titanium aluminum carbonitride (TiAlCN), titanium silicon carbonitride (TiSiCN), tantalum aluminum carbonitride (TaAlCN) and tantalum silicon carbonitride (TaSiCN). In an embodiment of the present disclosure, the bit line 300 may be a composite layer of polysilicon and titanium nitride, and the titanium nitride is located on the surface of the polysilicon column and surrounds the polysilicon column. The materials of the plurality of protrusions 310 of the column 310 are the same.

[0035] Please continue to refer to Figure 1 Each storage node in the plurality of storage nodes 400 is coupled to the other end of each semiconductor layer 100, such as the second source / drain region 130, that is, the storage node 400 and the bit line 300 are respectively arranged at two opposite ends of the semiconductor layer 100 in the second horizontal direction Y. The storage node 400 can be a cylindrical or columnar capacitor, which can be selected according to actual needs. More specific embodiments will be described later in this disclosure.

[0036] Please refer back to Figure 1 and Figure 2A In some embodiments of the present disclosure, along the first horizontal direction X, the size W of the semiconductor layer close to one end of the bit line 300 110 smaller than the size W of the semiconductor layer near one end of the storage node 400 130 That is, the width of the first source / drain region 110 in the first horizontal direction X may be smaller than the width of the second source / drain region 130 in the first horizontal direction X. Figure 1 At this time, for example, the first source / drain region 110 contacts the protrusion 320 of the bit line 300, the protrusion 320 is located on the pillar 310, and the width of the protrusion 320 in the first horizontal direction X is less than the width of the pillar 310, and then in the direction toward the bit line 300, the width of the semiconductor layer 100 in the first horizontal direction X gradually decreases, and the end of the semiconductor layer 100 contacts the protrusion 320 of the bit line 300. The size of the second source / drain region 130 can be the same as the size of the channel layer 120, and the semiconductor layer 100 extends in the second horizontal direction Y to contact the storage node 400. The morphology of the semiconductor layer 100 toward one end of the bit line 300 becomes narrower, which can increase the distance between adjacent bit lines in the first horizontal direction X, reduce the area of ​​the bit line 300 facing each other in the vertical direction, and reduce the coupling capacitance between the bit lines.

[0037] Please refer back to Figure 1 and Figure 2BIn some other embodiments of the present disclosure, along the vertical direction Z, the size H110 of the semiconductor layer near one end of the bit line 300 is smaller than the size H130 of the semiconductor layer near one end of the storage node 400, that is, the height of the first source / drain region 110 in the vertical direction Z may be smaller than the height of the second source / drain region 130 in the vertical direction Z. Please continue to refer to Figure 2B , the first source / drain region 110 contacts the protrusion 320 of the bit line 300, for example, in the direction toward the bit line 300, the height of the semiconductor layer 100 in the vertical direction Z gradually decreases, and the end of the semiconductor layer 100 contacts the protrusion 320 of the bit line 300. The size of the second source / drain region 130 can be the same as the size of the channel layer 120, and the semiconductor layer 100 extends in the second horizontal direction Y to contact the storage node 400. The semiconductor layer 100 becomes thinner toward one end of the bit line 300, which can increase the distance between the bit line and the word line in the vertical direction Z, and reduce the coupling capacitance between the bit line and the word line.

[0038] Figure 3A is a plan view of a three-dimensional semiconductor device according to yet another embodiment of the present disclosure. Figure 3B is along Figure 3A Longitudinal section taken along the center line A-A'. Please refer to FIG. 3A to FIG. 3B , the present disclosure provides a more specific embodiment of the storage node 400. In this embodiment, the storage node 400 is a cylindrical capacitor, and the multiple storage nodes 400 include multiple lower electrodes 410, a first capacitor dielectric layer 420, and a first upper electrode 430. The multiple lower electrodes 410 are arranged at intervals in the first horizontal direction X and the vertical direction Z, and are respectively coupled to one end of the corresponding multiple semiconductor layers 110, and each lower electrode 410 includes two opposite surfaces. The lower electrode 410 is in the shape of a U-shaped cylinder extending along the second horizontal direction Y. The first capacitor dielectric layer 420 is located on the surface of the multiple lower electrodes 410, for example, it can cover the inner surface and the outer surface of the U-shaped cylindrical lower electrode. The first upper electrode 430 is located on the surface of the first capacitor dielectric layer 420. The first upper electrode 430 is a whole, which leads out the signals of the multiple storage nodes 400.

[0039] Please continue to refer to FIG. 3A to FIG. 3B, further, the plurality of storage nodes 400 may further include a second capacitor dielectric layer 440 and a second upper electrode 450. At this time, the first capacitor dielectric layer 420 is located on one surface of the plurality of lower electrodes 410, such as the inner surface of the U-shaped cylindrical lower electrode, and the second capacitor dielectric layer 440 is located on another surface of the plurality of lower electrodes 410, such as the outer surface of the U-shaped cylindrical lower electrode, and the second capacitor dielectric layer 440 is also located on the surface of the first capacitor dielectric layer 420 not covered by the lower electrode 410, connecting the first capacitor dielectric layer 420. The second upper electrode 450 is located on the surface of the second capacitor dielectric layer 450. The second upper electrode 450 is a whole, which is connected in series with the first upper electrode 430, and can increase the storage capacity of the storage node.

[0040] The material of the lower electrode 410 can be selected from at least one of metal, metal nitride or metal oxide, such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), platinum (Pt), iridium (Ir), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), iridium oxide (IrO2), and titanium oxide (TiO).

[0041] The materials of the first capacitor dielectric layer 420 and the second capacitor dielectric layer 440 can be respectively selected from at least one of high-k dielectric films having a dielectric constant higher than that of silicon oxide, such as hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO3), lanthanum oxide (LaO), aluminum lanthanum oxide (LaAlO), and zirconium oxide (ZrO).

[0042] The materials of the first upper electrode 430 and the second upper electrode 450 can be selected from at least one of doped polysilicon, metal, metal nitride or metal oxide, such as tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), platinum (Pt), iridium (Ir), titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), iridium oxide (IrO2), titanium oxide (TiO). In some embodiments, the upper electrode includes a composite layer of polysilicon and titanium nitride, the polysilicon layer and the titanium nitride are in contact with each other, and the plurality of storage nodes 400 lead out signals through the polysilicon in the upper electrode.

[0043] Please continue to refer to FIG. 3A to FIG. 3B The three-dimensional semiconductor device includes not only a plurality of memory cells arranged in a first horizontal direction X and a vertical direction Z, but also a plurality of memory cells arranged in a second horizontal direction Y, so that the three-dimensional semiconductor device also includes a plurality of memory cell arrays in the second horizontal direction Y. Each memory cell array includes the above Figure 1 , FIG. 2A to FIG. 2BThe multiple semiconductor layers 100, multiple word lines 200, multiple bit lines 300, and multiple storage nodes 400 are shown and described. The adjacent memory cell arrays are mirror-symmetric with respect to the bit lines 300, that is, the bit lines 300 between the adjacent memory cell arrays are shared. In addition, the upper electrodes of the adjacent memory cell arrays with respect to the storage nodes 400 are mirror-symmetric with each other, that is, the upper electrodes between the adjacent memory cell arrays are shared, for example, in this embodiment, the first upper electrode 430 is shared.

[0044] exist FIG. 3A to FIG. 3B In the illustrated embodiment, two memory cell arrays that are mirror-symmetrical to each other in the second horizontal direction Y are described as an example. It can be understood that the two memory cell arrays that are mirror-symmetrical to each other are repeatedly arranged to obtain a three-dimensional semiconductor device with a higher storage density.

[0045] The embodiment of the present disclosure also provides a method for preparing a three-dimensional semiconductor device. Figures 4 to 26 It is a structural schematic diagram of each stage in the method for manufacturing a three-dimensional semiconductor device according to an embodiment of the present disclosure.

[0046] In the embodiment of the present disclosure, two memory cell arrays are formed in a mirror-symmetric manner in the second horizontal direction Y as an example. It can be understood that more memory cell arrays can be formed at the same time. These memory cell arrays are arranged on the substrate 10 at intervals. The memory cell arrays can be isolated from each other by an isolation layer (not all shown) to protect the three-dimensional semiconductor device. Figures 4 to 26 The method for preparing the three-dimensional semiconductor device provided in the embodiment of the present disclosure is described in detail.

[0047] Figure 4 A longitudinal cross-sectional view showing a stage in a method for preparing a three-dimensional semiconductor device. Figure 5 A substrate 10 is provided, and a stacked layer ST of a plurality of first sacrificial layers 11 and a plurality of second sacrificial layers 12 arranged alternately is formed on the substrate 10. The first sacrificial layer 11 is, for example, silicon nitride, and the second sacrificial layer is, for example, silicon oxide, and there is an etching selectivity ratio between the first sacrificial layer 11 and the second sacrificial layer 12. Subsequently, the three-dimensional semiconductor device in the present disclosure can be formed by patterning and pattern filling the first sacrificial layer 11 and the second sacrificial layer 12.

[0048] Figure 5 FIG. 1 is a plan view of a three-dimensional semiconductor device during another stage in a method for preparing the three-dimensional semiconductor device. Figure 5, patterning the stacked layer ST, forming a plurality of vertical openings penetrating the stacked layer ST, and forming a plurality of third sacrificial layers 13 in the plurality of vertical openings. Some of the plurality of third sacrificial layers 13 extend along the first horizontal direction X, and the remaining third sacrificial layers of the plurality of third sacrificial layers are arranged on both sides of the third sacrificial layers along the first horizontal direction X, and are arranged at intervals along the first horizontal direction X. The third sacrificial layer is, for example, a polysilicon layer, which has a larger etching selectivity ratio than the first sacrificial layer 11 and the second sacrificial layer 12.

[0049] Fig. 6A FIG. 1 is a plan view of a three-dimensional semiconductor device during another stage in a method for preparing the three-dimensional semiconductor device. FIG. 6A to FIG. 6C A first mask layer 14 is formed on the surface of the stacked layer ST, for example, the material of the first sacrificial layer 11 is the same as that of silicon nitride. The first mask layer 14 is patterned, and one of the third sacrificial layers 13 extending along the first horizontal direction X is removed to form a first vertical opening 10A penetrating the stacked layer ST. The first vertical opening 10A extends along the first horizontal direction X, and divides the stacked layer ST into a plurality of memory cell arrays arranged at intervals in the second horizontal direction Y. Afterwards, a bit line 300 is formed in the first vertical opening 10A, so that adjacent memory cell arrays are mirror-symmetric with respect to the bit line 300.

[0050] FIG. 6B to FIG. 6C The Fig. 6A The longitudinal section taken along the center line A-A' and line B-B'. Please continue to refer to FIG. 6A to FIG. 6C , a portion of the second sacrificial layer 12 in the stacked layer ST is laterally etched along the first vertical opening 10A, and when the remaining third sacrificial layer 13 in the plurality of sacrificial layers 13 is exposed, a portion of the second sacrificial layer 12 is further laterally etched to form a deposition space 10B of a first comb-shaped opening. The deposition space 10B of the first comb-shaped opening has different widths along the first horizontal direction X, and the width W13 between two adjacent third sacrificial layers 13 in the second horizontal direction Y is smaller than the width W12 between two adjacent second sacrificial layers 12 in the second horizontal direction Y.

[0051] Figure 7 Shown along Fig. 6A The longitudinal section taken along the line A-A' is Figure 6B A longitudinal cross-sectional view of a three-dimensional semiconductor device during another stage in the method for manufacturing the three-dimensional semiconductor device. Figure 7, along the first vertical opening 10A in the deposition space 10B of the first comb-shaped opening, that is, depositing the wire material between the multiple first sacrificial layers 11 to form the initial gate dielectric layer 140a and the initial word line layer 200a. The initial gate dielectric layer 140a conformally covers the surfaces of the first sacrificial layer 11, the second sacrificial layer 12, and the third sacrificial layer 13, and covers the surface of the first mask layer 14. The initial word line layer 200a covers the surface of the initial gate dielectric layer 140a. The initial word line layer 200a includes a first portion Wa and a second portion Wb. Please continue to refer to Figure 7 , a first isolation layer material, such as silicon oxide, is filled in the remaining space of the deposition space 10B of the first comb-shaped opening along the first vertical opening 10A, and then the first vertical opening 10A is exposed again, and the first isolation layer material in the first vertical opening 10A is removed to form a plurality of first isolation layers 101 arranged at intervals along the vertical direction Z, wherein the first isolation layers 101 are located between the initial word line layers 200a and extend along the first horizontal direction X.

[0052] Fig. 8A A plan view of a three-dimensional semiconductor device during another stage in a method of fabricating the three-dimensional semiconductor device is shown. FIG. 8B to FIG. 8D The Fig. 8A Longitudinal section taken along the center line A-A' and B-B'. Please refer to Figures 8A to 8C , continue to etch part of the initial word line layer 200a laterally along the first vertical opening 10A, remove the sidewall portion of the initial word line layer 200a exposed in the first vertical opening 10A, and disconnect the initial word line layer 200a to form a plurality of first intermediate word line layers 200b arranged at intervals in the vertical direction Z. Each first intermediate word line layer 200b extends along the second horizontal direction Y and is in a horizontally oriented U-shaped tube shape with its opening facing the first vertical opening 10A. Please continue to refer to FIG. 8A to FIG. 8C , along the first horizontal direction X, the width of each first intermediate word line layer 200b in the second horizontal direction Y is composed of a first portion width Wa and a second portion width Wb alternately, and the first portion width Wa is greater than the second portion width Wb. That is, the length of the U-shaped first intermediate word line layer 200b has different widths at different positions, such as Figure 8B As shown, between two adjacent third sacrificial layers 13, the first intermediate word line layer 200b is in a short U-shape, such as Figure 8C As shown, the first intermediate word line layer 200b is in a long U shape between two adjacent second sacrificial layers 12 in the second horizontal direction Y. In the disclosed embodiment, the width of the initial / intermediate word line layer in the first horizontal direction X ensures the morphology of the final word line layer and improves the electrical performance of the device.

[0053] Please continue to refer to Figure 8B and Figure 8C, continue to etch part of the initial gate dielectric layer 140a laterally along the first vertical opening 10A, remove the sidewall portion of the initial gate dielectric layer 140a exposed in the first vertical opening 10A, and the portion between two adjacent third sacrificial layers 13 in the adjacent second horizontal direction Y, to form a plurality of first intermediate gate dielectric layers 140b. The plurality of first intermediate gate dielectric layers 140b are arranged in intervals in the first horizontal direction X and in the vertical direction Z, and each intermediate gate dielectric layer 140b is also in a U-shaped cylinder oriented horizontally, with the opening facing the first vertical opening 10A. Please continue to refer to Figure 8B and Figure 8C The U-shaped first intermediate gate dielectric layer 140b is only located between two adjacent second sacrificial layers 12 in the second horizontal direction, covering part of the outer wall of the U-shaped intermediate word line layer 200b, but is not located between two adjacent third sacrificial layers 13 in the second horizontal direction Y. Only the side wall of the U-shaped first intermediate gate dielectric layer 140b exists between the two adjacent third sacrificial layers 13, and the first intermediate gate dielectric layers 140b are disconnected from each other in the first horizontal direction X.

[0054] Fig. 9 Shown along Fig. 8A The longitudinal section taken along the line B-B' is Figure 8B A longitudinal cross-sectional view of a three-dimensional semiconductor device during another stage in the method for manufacturing the three-dimensional semiconductor device. Fig. 9 In some embodiments of the present disclosure, the first sacrificial layer 11 in the stacked layer is etched along the first vertical opening 10A by a dry etching process on two opposite surfaces in the vertical direction Z, and the first sacrificial layer 11 near one end of the first vertical opening 10A is thinned in the vertical direction, thereby increasing the space in the vertical direction Z. The thickness of the first sacrificial layer 11 is inconsistent along the vertical direction Z. More specifically, the distance between the middle word line layer 200b and the first sacrificial layer 11 is inconsistent, and the thickness of the first sacrificial layer 11 near one end of the first vertical opening 10A is narrower, and the distance from the first middle word line layer 200b is greater, which provides a deposition space for the subsequent formation of the semiconductor layer 100.

[0055] Fig.10 Shown along Fig. 8A The longitudinal section taken along the line B-B' is Fig.10A cross-sectional view of a three-dimensional semiconductor device during another stage in the method for preparing a three-dimensional semiconductor device is shown below. A second isolation layer material, such as silicon oxide, is filled in the remaining space in the deposition space 10B of the first comb-shaped opening along the first vertical opening 10A, and then the first vertical opening 10A is exposed again, and the second isolation layer material in the first vertical opening 10A is removed to form a plurality of second isolation layers 102 arranged at intervals along the vertical direction Z, and the third sacrificial layer 13 is filled in the first vertical opening 10A again, and the entire surface is flattened, and the surfaces of the third sacrificial layer 13 and the first mask layer 14 are flush.

[0056] Fig.11 FIG. 1 is a plan view of a three-dimensional semiconductor device during another stage in a method for manufacturing the three-dimensional semiconductor device. Fig.11 In some embodiments of the present disclosure, an isolation structure between the bit lines 300 may be formed before forming the bit lines 300, but this is not limited to this. Fig.11 , patterning the first mask layer 14 to form a plurality of first vertical openings 10C penetrating the third sacrificial layer 13, the plurality of first vertical openings 10C and the remaining third sacrificial layer 13 between the plurality of first vertical openings 10C are arranged at intervals along the first horizontal direction X.

[0057] Fig.12 FIG. 1 is a plan view of a three-dimensional semiconductor device during another stage in a method for manufacturing the three-dimensional semiconductor device. Fig.12 Part of the first sacrificial layer 11 is laterally etched along the first vertical openings 100A to form a deposition space 10D of a second comb-shaped opening. The deposition space 10D of the second comb-shaped opening forms a ring-like opening in each layer of the first sacrificial layer 11.

[0058] In some embodiments, the first sacrificial layer 11 can be etched by a wet etching process, and the isotropic etching of the first sacrificial layer 11 can be controlled by controlling the time, the composition of the etching solution, and the etching rate. The size of the first sacrificial layer 11 along the first horizontal direction X is inconsistent. Specifically, at one end of the third sacrificial layer near the first vertical opening 10C, that is, at one end near the subsequent second vertical opening 20A, the width of the first sacrificial layer 11 is narrower, and the distance between adjacent first sacrificial layers 11 along the first horizontal direction X increases. After the first sacrificial layer is replaced to form the semiconductor layer 100, the size of the semiconductor layer 100 in contact with the bit line 300 is smaller, which increases the distance between the bit line and the bit line, and reduces the coupling capacitance.

[0059] Of course, in other embodiments, Fig.13 FIG. 2 shows a plan view of a three-dimensional semiconductor device during another stage in a method for manufacturing a three-dimensional semiconductor device in another embodiment. Fig.13As shown, the first sacrificial layer 11 may also be etched by a dry etching process, and after dry etching, the second comb-shaped opening space 10D forms a rectangular opening in each layer of the first sacrificial layer 11. In this embodiment, the first sacrificial layer 11 has the same size along the first horizontal direction X. Therefore, when the first sacrificial layer 11 is replaced to form the semiconductor layer 100, the contact area between the semiconductor layer 100 and the bit line 300 is large and the contact resistance is small.

[0060] Fig.14A A plan view of a three-dimensional semiconductor device during another stage in a method of fabricating the three-dimensional semiconductor device is shown. Fig. 14B Shown along Fig.14A Longitudinal section taken along the center line A-A'. Please refer to Fig.14A and Fig. 14B , continue to etch the third sacrificial layer 13 between the first vertical opening 10C along the deposition space 10D of the second comb-shaped opening, and form a third comb-shaped deposition space 10E. And fill the third isolation layer 103, such as silicon oxide, in the third comb-shaped deposition space 10E. The third isolation layer 103 is an isolation layer between the plurality of bit lines 300. At this time, the third isolation layer 103 is flush with the first mask layer 14.

[0061] Please continue to refer to Fig.14A and Fig. 14B After forming the third comb-shaped deposition space 10E and depositing the third isolation layer 103, a portion of the third sacrificial layer 13 between the first vertical openings 10C is narrowed to form a vertically extending column and a plurality of protrusions protruding from the column. The plurality of protrusions are at the same horizontal position as the plurality of first sacrificial layers 11 and are in contact with the corresponding first sacrificial layers 11, which preliminarily reserves space for the subsequent formation of the bit line 300 including the column 310 and the plurality of protrusions 320.

[0062] Fig.15A A plan view of a three-dimensional semiconductor device during another stage in a method of fabricating the three-dimensional semiconductor device is shown. Fig. 15B Shown along Fig.15A Longitudinal section taken along the midline B-B'. Please refer to Fig.15A and Fig. 15B The first mask layer 14 is removed by etching back, and a second mask layer 15 is formed on the surface of the exposed stacked layer ST. The material of the second mask layer 15 can be the same as that of the second sacrificial layer 12, such as silicon oxide. Fig.15A and Fig. 15B, patterning the second mask layer 15, removing the third sacrificial layer 13 between the plurality of first vertical openings 10C to form a plurality of second vertical openings 20A, the plurality of second vertical openings 20A being arranged at intervals in the first horizontal direction X. Afterwards, selectively etching the plurality of first sacrificial layers 11 in the stacked layer along the plurality of second vertical openings 20A, respectively, to form a plurality of deposition spaces 20B of fourth comb-shaped openings arranged at intervals along the first horizontal direction X. This process increases the contact area between the second vertical openings 20A and the first sacrificial layer 11, and further reserves space for forming the bit line 300 including the pillar 310 and the plurality of protrusions 320.

[0063] Fig.16 Shown along Fig.15A The longitudinal section taken along the line B-B' is Fig. 15B A longitudinal cross-sectional view of a three-dimensional semiconductor device during another stage in the method for manufacturing the three-dimensional semiconductor device. Fig.16 , along the plurality of second vertical openings 20A, a plurality of bit lines 300 are formed in the deposition spaces 20B of the plurality of fourth comb-shaped openings, and the plurality of bit lines 300 are arranged at intervals along the first horizontal direction X. In one embodiment of the present disclosure, the bit line 300 includes a composite layer of titanium nitride and polysilicon. The titanium nitride is located on the surface of the polysilicon and surrounds the polysilicon. For details, please refer to Fig.16 , firstly, a titanium nitride layer is deposited in the deposition space 20B of the fourth comb-shaped opening along the second vertical opening 20A, and the titanium nitride layer conformally covers the surfaces of the second mask layer 15, the first isolation layer 101, the second isolation layer 102, the third isolation layer 103, the first sacrificial layer 11, and the second sacrificial layer 12. Polysilicon is also located in the fourth comb-shaped deposition space 20B, located on the surface of the titanium nitride layer, and fills the remaining space of the fourth comb-shaped deposition space 20B. Fig.16 As shown, the bit line 300 includes a vertically extending column 310 and a plurality of protrusions 320, which are integrally formed with the body 310 and arranged at intervals on the vertically extending column 310. At this time, the plurality of protrusions 320 of each bit line 300 are respectively in contact with a plurality of first sacrificial layers 11 in the vertical direction.

[0064] In the embodiment of the present disclosure, two adjacent memory cell arrays are formed simultaneously, and a plurality of bit lines 300 are shared between the two adjacent memory cell arrays, and the two are mirror-symmetric to each other about the bit lines 300 .

[0065] Fig.17A A plan view of a three-dimensional semiconductor device during another stage in a method of fabricating the three-dimensional semiconductor device is shown. Fig. 17B Shown along Fig.17A Longitudinal section taken along the center line A-A'. Please refer to Fig.17A and Fig. 17B, multiple third sacrificial layers 13 spaced apart along the first horizontal direction X are removed to form multiple second vertical openings 20C penetrating the stacked layer ST, the multiple second vertical openings 20C are spaced apart along the first horizontal direction X, and each second vertical opening 20C extends along the second horizontal direction Y, exposing the side walls of the second portions Wb of the multiple first gate dielectric layers 140 b and the multiple first intermediate word line layers 220 b spaced apart in the vertical direction Z.

[0066] Fig.18 Shown along Fig.17A The longitudinal section taken along the line A-A' is Fig. 17B A cross-sectional view of a three-dimensional semiconductor device during another stage in the method for fabricating the three-dimensional semiconductor device is shown below. Fig.18 , selectively etch along the multiple second vertical openings 20C to expose the sidewalls of the first intermediate gate dielectric layer 140b and the first intermediate word line layer 220b, so as to disconnect the first intermediate gate dielectric layer 140b and the first intermediate word line layer 220b at the second vertical openings 20C in the vertical direction Z, and form multiple second intermediate gate dielectric layers 140c and multiple second intermediate word line layers 220c. At this time, the second intermediate gate dielectric layer 140c and the second intermediate word line layer 220c are disconnected in the vertical direction Z at the second portion Wb with a narrower width, while the second intermediate gate dielectric layer 140c and the second intermediate word line layer 220c are still continuous in the vertical direction Z at the first portion Wa with a wider width. At this time, as Fig.18 As shown, the sidewalls of the second intermediate gate dielectric layer 140c that are short U-shaped are removed, while the sidewalls that are long U-shaped are not removed. The second intermediate gate dielectric layer 140c is in the form of a plurality of independent U-shaped tubes, which are arranged at intervals in the first horizontal direction X and in the vertical direction Z. Each second intermediate gate dielectric layer 140c is also in the form of a U-shaped tube oriented horizontally, with an opening facing the bit line 300.

[0067] Fig.19 Shown along Fig.17A The longitudinal section taken along the line A-A' is Fig.18 A longitudinal cross-sectional view of a three-dimensional semiconductor device during another stage in the method for manufacturing the three-dimensional semiconductor device. Fig.19 , multiple third sacrificial layers 13 are respectively backfilled in the multiple second vertical openings 20C. At this time, the surfaces of the multiple third sacrificial layers 13 and the second mask layer 15 are flush.

[0068] Fig. 20A A plan view of a three-dimensional semiconductor device during another stage in a method of fabricating the three-dimensional semiconductor device is shown. Fig. 20B Shown along Fig. 20A The longitudinal section taken along the midline B-B' is Fig.19A cross-sectional view of a three-dimensional semiconductor device during another stage in the method for fabricating the three-dimensional semiconductor device is shown below. FIG. 20A to FIG. 20B The second mask layer 15 is patterned to remove the sacrificial layers 13 extending along the first horizontal direction X from among the plurality of third sacrificial layers 13 , thereby forming a third vertical opening 30A penetrating the stacked layer ST, wherein the third vertical opening 30A extends along the first horizontal direction X.

[0069] Fig.21 Shown along Fig. 20A The longitudinal section taken along the line B-B' is Fig. 20B A longitudinal cross-sectional view of a three-dimensional semiconductor device during another stage in the method for manufacturing the three-dimensional semiconductor device. Fig.21 , selectively etch a portion of the plurality of first sacrificial layers 11 in the stacked layer along the third vertical opening 30A until the sidewalls of the second intermediate gate dielectric layer 140C and the second intermediate word line layer 200c are exposed, forming a deposition space 30B of a fifth comb-shaped opening.

[0070] Fig. 22 Shown along Fig. 20A The longitudinal section taken along the line B-B' is Fig.21 A cross-sectional view of a three-dimensional semiconductor device during another stage in the method for fabricating the three-dimensional semiconductor device is shown below. Fig. 22 , along the vertical direction Z, the side walls of the second intermediate gate dielectric layer 140c and the second intermediate word line layer 200c are etched in sequence, and the second intermediate gate dielectric layer 140c and the second intermediate word line layer 220c, which are continuous at the first portion Wa with a wider width, are disconnected in the vertical direction Z to form a gate dielectric layer 140 and a word line 200.

[0071] Please continue to refer to Fig. 22 And return reference FIG. 2A to FIG. 2B , the word line 200 extends along the first horizontal direction, and each word line 200 includes a pair of conductive wires 210, 220, each conductive wire 210, 220 includes a plurality of first portions 210A and a plurality of second portions 210B arranged alternately, and along the second horizontal direction Y, the size WA of the first portion is greater than the size WB of the second portion. The gate dielectric layer 140 includes a pair of gate dielectric layers, and the pair of gate dielectric layers are located between the first portion 210A and the first sacrificial layer 11. After the remaining first sacrificial layer 11 is replaced with the semiconductor layer 100, the gate dielectric layer 140 is located between the semiconductor layer 100 and the word line 200, the pair of gate dielectric layers covers two opposite surfaces of the semiconductor layer 100 in the vertical direction Z, and the pair of conductive wires 210, 220 respectively cover the surfaces of the pair of gate dielectric layers, so that the pair of conductive wires 210, 220 are respectively located on two opposite surfaces of the semiconductor layer 100 in the vertical direction Z. Please continue to refer to Fig. 22 , along the third vertical opening 30A, a fourth isolation layer 104 is filled in the gap between the word line 200 and the second sacrificial layer 12 .

[0072] Fig.23A A plan view of a three-dimensional semiconductor device during another stage in a method of fabricating the three-dimensional semiconductor device is shown. FIG. 23B to FIG. 23C Shown along Fig.23A The longitudinal section taken along the center line A-A' and the line B-B'. Please refer to FIG. 23A to FIG. 23C , along the third vertical opening 30A, a plurality of storage nodes 400 are formed in the deposition space 30B of the fifth comb-shaped opening. The plurality of storage nodes 400 are in contact with the plurality of first sacrificial layers 11. In some embodiments of the present disclosure, the plurality of storage nodes 400 include a plurality of lower electrodes 410, a first capacitor dielectric layer 420, and a first upper electrode 430. Specifically, a lower electrode material is deposited between the plurality of second sacrificial layers 12 along the third vertical opening 30A, and the lower electrode material is located on the surface of the first sacrificial layer 11 and the second sacrificial layer 12. Then, the lower electrode material exposed in the third vertical opening 30A is removed along the third vertical opening 30A, and a plurality of lower electrodes 410 arranged at intervals in the first horizontal direction X and the vertical direction Z are formed. The plurality of lower electrodes 410 are in a U-shaped cylindrical shape along a horizontal orientation, and the opening faces the third vertical opening 30A. The plurality of lower electrodes 410 in the vertical direction Z are isolated from each other by the second sacrificial layer 12. The plurality of lower electrodes 410 in the first horizontal direction X are isolated from each other by the third sacrificial layer 13. The U-shaped tube sidewall of each lower electrode 410 contacts a first sacrificial layer 11 , and the U-shaped tube sidewalls are respectively located in the space enclosed by two second sacrificial layers 12 and two third sacrificial layers 13 .

[0073] After that, please continue to refer to FIG. 23A to FIG. 23C , continue to form a first capacitor dielectric layer 420 in the fifth comb-shaped deposition space 40B along the third vertical opening 30A, the first capacitor dielectric layer 420 is located on the inner wall surface of the U-shaped cylindrical lower electrode 410, further, as Fig.23C As shown, the first capacitor dielectric layer 420 is a continuous layer, which is also located on the surfaces of the second sacrificial layer 12 and the third sacrificial layer 13 that are not covered by the lower electrode 410, and the surface exposed by the third vertical opening 30A.

[0074] After that, please continue to refer to FIG. 23A to FIG. 23C, continue to form the first upper electrode 430 in the fifth comb-shaped opening deposition space 30B along the third vertical opening 30A, the first upper electrode is, for example, a composite layer of titanium nitride and polysilicon, for example, a titanium nitride layer can be conformally deposited on the surface of the first capacitor dielectric layer 420, and then, a polysilicon layer is deposited in the remaining space of the fifth comb-shaped opening deposition space 30B along the third vertical opening 30A to form the first upper electrode 430. The first upper electrode 430 is an integral layer, and the first upper electrode 430 located in the third vertical opening 30A extends along the first horizontal direction X and penetrates the stacked layer, and the first upper electrode 430 is flush with the surface of the second mask layer 15.

[0075] In the embodiment of the present disclosure, only multiple storage nodes connected to one memory cell array are shown. When multiple memory cell arrays are formed simultaneously, multiple storage nodes 400 of two adjacent memory cell arrays can be formed simultaneously, and the two are mirror-symmetric to each other about the first upper electrode 430.

[0076] Fig.24A A plan view of a three-dimensional semiconductor device during another stage in a method of fabricating the three-dimensional semiconductor device is shown. FIG. 24B to FIG. 24D Shown along Fig.24A The longitudinal cross-sectional view taken along the middle line A-A', the line B-B', and the line CC'. In some other embodiments of the present disclosure, in order to further increase the capacitance, a second upper electrode may be connected in series at the first upper electrode 430. For details, please refer to FIG. 24A to FIG. 24D , a third mask layer 16 is formed on the stacked layer ST, that is, on the common surface of the first upper electrode 430 and the second mask layer 15. For example, the material may be the same as that of the first sacrificial layer 11, such as silicon nitride. Afterwards, the third mask layer 16 is patterned, and part of the remaining third sacrificial layer 13 is removed to form a plurality of third vertical openings 30C that penetrate the stacked layer ST and are located between the third vertical opening 30A and the plurality of fourth vertical openings 40A. The plurality of third vertical openings 30C are arranged at intervals along the first horizontal direction X and the second horizontal direction Y. The plurality of third vertical openings 30C arranged at intervals along the first horizontal direction X are located in the region between the word line 200 (or the first sacrificial layer 11) and the storage node 400. Afterwards, please continue to refer to FIG. 24A to FIG. 24D, selectively etch the remaining second sacrificial layer 12 in the stacked layer along the plurality of third vertical openings 30C, respectively, expose the other surface of the plurality of lower electrodes 410, and form a sixth comb-shaped opening deposition space. The sixth comb-shaped deposition space exposes the outer wall surface of the U-shaped cylindrical lower electrode 410, and exposes part of the first capacitor dielectric layer 420. Afterwards, the second capacitor dielectric layer 440 and the second upper electrode 450 are sequentially formed in the deposition space of the sixth comb-shaped opening along the plurality of third vertical openings 30C. Specifically, the second capacitor dielectric layer 440 is located on the outer wall surface of the U-shaped cylindrical lower electrode 410 and the surface of the first capacitor dielectric layer 420, and is connected to the first capacitor dielectric layer 420 as a whole. The second upper electrode 450 is located on the surface of the second capacitor dielectric layer 440. With the same structure as the first upper electrode 430, in some embodiments, the second upper electrode includes a composite layer of titanium nitride and polysilicon. A titanium nitride layer is conformally deposited on the surface of the second capacitor dielectric layer 440, and then a polysilicon layer is deposited in the remaining space of the sixth comb-shaped opening deposition space along the plurality of third vertical openings 30C to form a second upper electrode 450. The second upper electrode 450 is an integral layer and fills the plurality of third vertical openings 30C. The second upper electrode 450 is flush with the surface of the third mask layer 16 and is higher than the surface of the first upper electrode 430. Afterwards, for example, the first upper electrode 430 and the second upper electrode 450 can be connected through a contact plug (not shown in the figure) to connect the two in series. Of course, in some embodiments of the present disclosure, the two can also be connected in series through a back-end process (BEOL) to form an upper electrode to save process.

[0077] Fig.25A A plan view of a three-dimensional semiconductor device during another stage in a method of fabricating the three-dimensional semiconductor device is shown. Fig.25B Shown along Fig.25A Longitudinal section taken along the center line A-A'. Please refer to Fig.25A and Fig.25B , patterning the third mask layer 16, removing the remaining third sacrificial layers 13, forming a plurality of fourth vertical openings 40A penetrating the stacked layers, which are located between the first vertical opening 10A and the third vertical opening 30A. The plurality of fourth vertical openings 40A are arranged at intervals along the first horizontal direction X and the second horizontal direction Y. The plurality of fourth vertical openings 40A arranged at intervals along the first horizontal direction X are located in the region between the bit line 300 and the storage node 400.

[0078] Please continue to refer to Fig.25A and Fig.25B, selectively etch the remaining first sacrificial layer 11 in the stacked layer along the plurality of fourth vertical openings 40A, respectively, to form a seventh comb-shaped opening deposition space 40B. The deposition space 40B of the seventh comb-shaped opening exposes the surface of the protrusion 320 of the bit line 300, the surface of the word line 200, that is, the surface of the pair of conductive lines 210, 220, and the surface of the lower electrode 410 of the storage node 400.

[0079] Fig.26 Shown along Fig.25A The longitudinal section taken along the line A-A' is Fig.25B A cross-sectional view of a three-dimensional semiconductor device during another stage in the method for fabricating the three-dimensional semiconductor device is shown below. Fig.26 , metal oxide semiconductor materials, such as indium gallium zinc oxide (IGZO), and insulating dielectric materials, such as aluminum oxide, are deposited by atomic layer deposition (ALD) along the plurality of fourth vertical openings 40A in the deposition space 40B of the seventh comb-shaped opening to form a semiconductor layer material. Specifically, indium gallium zinc oxide can be continuously located on the surfaces of the protrusions 320 of the plurality of bit lines exposed in the fourth vertical opening 40A and the seventh comb-shaped deposition space 40B, the surfaces of a pair of wires 210, 220 of the plurality of word lines, and the surfaces of the plurality of first lower electrodes 410. Aluminum oxide is located on the surface of indium gallium zinc oxide, is wrapped by indium gallium zinc oxide, and fills the remaining space of the seventh comb-shaped deposition space 40B.

[0080] Please continue to refer to Fig.26 , and please refer back to Figures 1 to 3B , the fourth vertical opening 40A is exposed again to disconnect the semiconductor layer material, forming a plurality of semiconductor layers 100 arranged at intervals in the first horizontal direction X and the vertical direction Z. A pair of conductive wires 210 and 220 are respectively provided on two opposite surfaces of the semiconductor layer 100 in the vertical direction Z, and the two ends of the semiconductor layer 100 in the second horizontal direction Y are respectively coupled to the bit line 300 and the storage node 400. Afterwards, a fifth isolation layer (not shown in the figure) is filled. The plurality of semiconductor layers 100 in the first horizontal direction X are isolated from each other by the fifth isolation layer. The plurality of semiconductor layers 100 arranged at intervals in the vertical direction Z are isolated from each other by the first isolation layer 101 and the second isolation layer 102.

[0081] In an embodiment of the present disclosure, a three-dimensional semiconductor device is provided, wherein a word line includes a pair of conductive wires located on two surfaces opposite to each other in a vertical direction of each semiconductor layer, and each conductive wire includes a plurality of first parts and a plurality of second parts arranged alternately, and in a direction extending along the semiconductor layer, a size of the first part is larger than a size of the second part. A three-dimensional semiconductor device structure of a dual-gate field effect transistor is provided, which can significantly improve the current driving capability of the transistor, and reduce the influence of the PGE effect (passing-gate effect) on adjacent storage cells, thereby improving device performance.

[0082] Please refer to Fig. 27 The present disclosure also provides an electronic device 1 having a storage function, the electronic device comprising a processor 2 and a storage device 3 electrically connected to the processor, the storage device comprising the above Figures 1 to 26 The three-dimensional semiconductor device 4 described in the figure. The electronic device can be a terminal device, such as a personal computer (Personal Computer), a mobile phone (mobile phone), a tablet computer (pad), consumer electronics (Consumer electronics), such as smart home appliances, autonomous driving (automotive), smart wearable products (for example, smart watches, smart bracelets), virtual reality (virtualreality, VR) devices, augmented reality (augmented reality, AR) devices, and can also be a server (server), a data center (data center), etc. The memory device 3 can be, for example, a high-performance, high-bandwidth, high-density non-volatile dual in-line memory module (Non-Volatile Dual In-Line Memory Module, NVDIMM) or a storage class memory (Storage Class Memory, SCM). The storage function in the electronic device 1 can be realized by these storage devices 3.

[0083] In some embodiments, the processor 2 and the memory 3 can be two independent chips to form an independent memory. In other embodiments, the memory 3 and the processor 2 can also be integrated into the same chip to form an embedded memory. Figures 1 to 26 The described three-dimensional semiconductor device 4 can solve the same technical problem and achieve the same expected effect.

[0084] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A three-dimensional semiconductor device, characterized in that: include: A plurality of semiconductor layers are arranged at intervals along a first horizontal direction and along a vertical direction, and each of the semiconductor layers extends along a second horizontal direction intersecting the first horizontal direction; A plurality of word lines are arranged at intervals along the vertical direction, each of the word lines extends along the first horizontal direction, and each of the word lines comprises a pair of conductive wires, which are respectively arranged on two opposite surfaces of each semiconductor layer in the vertical direction; wherein each of the conductive wires comprises a plurality of first portions and a plurality of second portions which are alternately arranged, and along the second horizontal direction, the size of the first portion is larger than the size of the second portion; A plurality of bit lines are arranged at intervals along the first horizontal direction, each of the bit lines extends along the vertical direction, and each of the bit lines is coupled to one end of a plurality of semiconductor layers in the vertical direction; A plurality of storage nodes, each of the storage nodes is coupled to the other end of each of the semiconductor layers.

2. The three-dimensional semiconductor device according to claim 1, characterized in that In the vertical direction, a size of the semiconductor layer close to one end of the bit line is smaller than a size of the semiconductor layer close to one end of the storage node.

3. The three-dimensional semiconductor device according to claim 1 or 2, characterized in that: In the first horizontal direction, a size of the semiconductor layer close to one end of the bit line is smaller than a size of the semiconductor layer close to one end of the storage node.

4. The three-dimensional semiconductor device according to claim 1, characterized in that: The plurality of storage nodes are cylindrical and include: A plurality of lower electrodes are arranged at intervals in the first horizontal direction and the vertical direction and are respectively coupled to one end of the corresponding plurality of semiconductor layers; each of the lower electrodes comprises two opposite surfaces; A first capacitor dielectric layer is located on a surface of the plurality of lower electrodes; A first upper electrode, located on a surface of the first capacitor dielectric layer; A second capacitor dielectric layer is located on another surface of the plurality of lower electrodes and is connected to the first capacitor dielectric layer; The second upper electrode is located on the surface of the second capacitor dielectric layer and is connected in series with the first upper electrode.

5. A method for preparing a three-dimensional semiconductor device, characterized in that: include: Providing a substrate, and forming a stacked layer of a plurality of first sacrificial layers and a plurality of second sacrificial layers arranged alternately on the substrate; forming a first vertical opening penetrating through the stacked layers, wherein the first vertical opening extends along a first horizontal direction; Selectively etching a plurality of the second sacrificial layers in the stacked layer along the first vertical opening, and forming a plurality of gate dielectric layers and a plurality of word lines, wherein the plurality of word lines are arranged at intervals in the vertical direction, each of the word lines extends along the first horizontal direction and comprises a pair of conductive wires, wherein each conductive wire comprises a plurality of first portions and a plurality of second portions arranged alternately, and along the second horizontal direction, the size of the first portion is larger than the size of the second portion; the first horizontal direction intersects with the second horizontal direction; Filling a third sacrificial layer in the first vertical opening, and forming a plurality of second vertical openings penetrating the third sacrificial layer, wherein the plurality of second vertical openings are arranged at intervals along the first horizontal direction; forming a plurality of bit lines spaced apart along the first horizontal direction in the plurality of second vertical openings, respectively, each of the bit lines extending along the vertical direction; forming a third vertical opening penetrating through the stacked layers, wherein the third vertical opening extends along the first horizontal direction; Selectively etching a plurality of the first sacrificial layers in the stacked layer along the third vertical opening to form a plurality of storage nodes; forming a plurality of fourth vertical openings penetrating the stacked layer and located between the first vertical opening and the third vertical opening, wherein the plurality of fourth vertical openings are arranged at intervals along the first horizontal direction; The remaining first sacrificial layer in the stacked layer is selectively etched along the multiple fourth vertical openings respectively, and a plurality of semiconductor layers arranged at intervals along the first horizontal direction and along the vertical direction are formed, the pair of conductive wires are respectively provided on the two opposite surfaces of the semiconductor layer in the vertical direction, and the two ends of the semiconductor layer in the second horizontal direction are respectively coupled to the bit line and the storage node.

6. The method for preparing a three-dimensional semiconductor device according to claim 5, characterized in that: Also includes: Along the first vertical opening, two surfaces of the plurality of first sacrificial layers in the stacked layer that are opposite to each other in the vertical direction are etched by a dry etching process to reduce the size of the first sacrificial layer in the vertical direction near one end of the first vertical opening.

7. The method for preparing a three-dimensional semiconductor device according to claim 5 or 6, characterized in that: Also includes: After filling the first vertical opening with a third sacrificial layer, forming a plurality of first vertical openings penetrating the third sacrificial layer, wherein the plurality of first vertical openings are arranged at intervals along the first horizontal direction; Etching the plurality of first sacrificial layers in the stacked layer respectively along the plurality of first vertical openings by a wet etching process to narrow the size of the first sacrificial layer near one end of the second vertical opening in the first horizontal direction; removing the third sacrificial layer between the plurality of the first vertical openings to form a plurality of the second vertical openings; Selectively etching a plurality of the first sacrificial layers in the stacked layer along the plurality of second vertical openings respectively to increase a contact area between the second vertical openings and the first sacrificial layers; A plurality of the bit lines are formed in the plurality of the second vertical openings respectively.

8. The method for preparing a three-dimensional semiconductor device according to claim 5, characterized in that: Forming a plurality of the word lines comprises: Depositing a conductive line material between a plurality of the first sacrificial layers along the first vertical opening to form an initial word line layer, wherein the initial word line layer includes the first portion and the second portion; removing the sidewalls of the initial word line layer exposed in the first vertical opening along the first vertical opening to form a plurality of first intermediate word line layers spaced apart in a vertical direction; Forming a plurality of second vertical openings penetrating the stacked layers, each second vertical opening exposing side walls of a second portion of a plurality of first intermediate word line layers spaced apart in a vertical direction; Removing the sidewalls of the second portions of the first middle word line layers along the second vertical openings to form a plurality of second middle word line layers; Selectively etching the first sacrificial layers in the stacked layers along the third vertical opening until the sidewalls of the first portions of the second intermediate word line layers are exposed; A first portion of the sidewalls of the second middle word line layers are removed along the third vertical opening to form a plurality of the word lines, each of which includes a pair of conductive lines.

9. The method for preparing a three-dimensional semiconductor device according to claim 5, characterized in that: Forming a plurality of storage nodes comprises: forming a plurality of lower electrodes between the plurality of second sacrificial layers along the third vertical opening, wherein the plurality of lower electrodes respectively contact one end of the corresponding plurality of first sacrificial layers; forming a first capacitor dielectric layer on one surface of the plurality of lower electrodes along the third vertical opening; A first upper electrode is formed on a surface of the first capacitor dielectric layer along the third vertical opening.

10. The method for preparing a three-dimensional semiconductor device according to claim 9, characterized in that: Also includes: forming a plurality of third vertical openings penetrating the stacked layer and located between the third vertical opening and the plurality of fourth vertical openings, wherein the plurality of third vertical openings are arranged at intervals along the first horizontal direction; Selectively etching the remaining second sacrificial layer in the stacked layer along the plurality of third vertical openings respectively to expose another surface of the plurality of lower electrodes; Forming a second capacitor dielectric layer on the other surface of the plurality of lower electrodes along the plurality of third vertical openings respectively, wherein the second capacitor dielectric layer is also located on the first capacitor dielectric layer; A second upper electrode is formed on the surface of the second capacitor dielectric layer along the plurality of third vertical openings respectively, and the first upper electrode and the second upper electrode are connected in series.

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