Three-dimensional semiconductor memory device

Abstract

A three-dimensional (3D) semiconductor memory device is provided. A 3D semiconductor memory device includes an electrode structure on a substrate. The electrode structure includes a gate electrode stacked on the substrate. The gate electrode includes an electrode pad region. The 3D semiconductor memory device includes a dummy vertical structure penetrating one electrode pad region. The dummy vertical structure includes a dummy vertical semiconductor pattern and a contact pattern extending from a portion of the dummy vertical semiconductor pattern toward the substrate.

Description

[0001] This application is a divisional application of the Chinese invention patent application (application number: 201911014685.4) with a filing date of October 23, 2019 and entitled “Three-dimensional semiconductor memory device”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This patent application claims the priority benefit of Korean Patent Application No. 10-2018-0167569 filed on December 21, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] Embodiments of the inventive concept relate to semiconductor memory devices, and more particularly, to three-dimensional (3D) semiconductor memory devices having memory cells arranged three-dimensionally. Background Art

[0005] Semiconductor devices have been highly integrated to provide superior performance and low manufacturing costs. The integration density of semiconductor devices directly affects the cost of semiconductor devices, resulting in a demand for highly integrated semiconductor devices. The integration density of a typical two-dimensional (2D) or planar semiconductor device can be mainly determined by the area occupied by a unit memory cell. Therefore, the integration density of a typical 2D or planar semiconductor device may be greatly affected by the technology for forming fine patterns. However, since extremely high-priced devices are required to form fine patterns, the integration density of 2D semiconductor devices continues to increase but remains limited. Three-dimensional (3D) semiconductor devices including three-dimensionally arranged memory cells have been developed to overcome these limitations. Summary of the invention

[0006] Embodiments of the inventive concept may provide a three-dimensional (3D) semiconductor memory device capable of improving a pattern profile.

[0007] Embodiments of the inventive concept may also provide a 3D semiconductor memory device capable of improving reliability.

[0008] In some embodiments, a 3D semiconductor memory device may include a substrate and an electrode structure on the substrate. The electrode structure may include a gate electrode stacked in a direction vertical to a top surface of the substrate. The gate electrode may include an electrode pad region. In addition, the 3D semiconductor memory device may include a dummy vertical structure penetrating an electrode pad region. The dummy vertical structure may include a dummy vertical semiconductor pattern extending substantially along the direction and a contact pattern extending from a portion of the dummy vertical semiconductor pattern toward the substrate.

[0009] In some embodiments, a 3D semiconductor memory device may include a substrate, the substrate including a cell array region and a connection region. The 3D semiconductor memory device may include an electrode structure on the substrate. The electrode structure may include a gate electrode stacked in a vertical direction relative to the top surface of the substrate. The gate electrode may include an electrode pad region on the connection region. The 3D semiconductor memory device may include a vertical semiconductor pattern penetrating the electrode structure on the cell array region. The 3D semiconductor memory device may include a dummy vertical semiconductor pattern penetrating an electrode pad region on the connection region. In addition, the 3D semiconductor memory device may include a contact pattern extending from a portion of the dummy vertical semiconductor pattern into the substrate.

[0010] In some embodiments, a 3D semiconductor memory device may include a substrate and an electrode structure on the substrate. The electrode structure may include a gate electrode stacked in a vertical direction relative to the top surface of the substrate. The gate electrode may include an electrode pad area. The 3D semiconductor memory device may include a source conductive pattern between the substrate and the electrode structure. The 3D semiconductor memory device may include a dummy vertical semiconductor pattern that penetrates an electrode pad area, penetrates the source conductive pattern under the electrode pad area, and extends into the substrate. The 3D semiconductor memory device may include a dummy data storage pattern between the dummy vertical semiconductor pattern and the substrate. In addition, the 3D semiconductor memory device may include a contact pattern that penetrates the bottom of the dummy data storage pattern to be electrically connected to the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The inventive concept will become more apparent from the accompanying drawings and detailed description.

[0012] Figure 1 is a schematic circuit diagram illustrating a cell array of a three-dimensional (3D) semiconductor memory device according to some embodiments of the inventive concept.

[0013] Figure 2 is a plan view illustrating a 3D semiconductor memory device according to some embodiments of the inventive concept.

[0014] Figure 3 and Figure 4 are along Figure 2 Cross-sectional views taken along lines II' and II-II'.

[0015] Figure 5 , Figure 6 and Figure 7 It shows Figure 3 and Figure 4 A plan view of the source structure and gate electrode.

[0016] Figure 8 yes Figure 3 Magnified view of section "A".

[0017] Fig. 9A , Fig. 9B , Fig. 9C and Fig.9D FIG. 2 is a diagram showing a 3D semiconductor memory device according to various embodiments of the inventive concept. Figure 4 An enlarged view of a portion of portion "B".

[0018] Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A and Fig.24A is a diagram showing a method of manufacturing a 3D semiconductor memory device according to some embodiments of the inventive concept Figure 2 A cross-sectional view of line II'.

[0019] Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig.21B , Fig. 22B , Fig. 23B and Fig. 24B is a diagram showing a method of manufacturing a 3D semiconductor memory device according to some embodiments of the inventive concept Figure 2 Cross-sectional view along line II-II'.

[0020] Fig.25 is a diagram showing a method of manufacturing a 3D semiconductor memory device according to some embodiments of the inventive concept Figure 2 Cross-sectional view along line II-II'.

[0021] Fig.26 and Fig. 27 is a diagram showing a method of manufacturing a 3D semiconductor memory device according to some embodiments of the inventive concept Figure 2 Cross-sectional view along line II-II'. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0023] Figure 1 is a schematic circuit diagram illustrating a cell array of a three-dimensional (3D) semiconductor memory device according to some embodiments of the inventive concept.

[0024] Reference Figure 1 , a cell array of a 3D semiconductor memory device according to some embodiments may include a common source line CSL, a plurality of bit lines BL0 to BL2, and a plurality of cell strings CSTR connected between the common source line CSL and the bit lines BL0 to BL2. A plurality of cell strings CSTR may be connected in parallel to each of the bit lines BL0 to BL2. The cell strings CSTR may be connected in common to the common source line CSL. Each cell string CSTR may include string selection transistors SST1 and SST2 connected in series to each other, a memory cell transistor MCT, a ground selection transistor GST, and an erase control transistor ECT. Each memory cell transistor MCT may include a data storage element. In some embodiments, each cell string CSTR may include a first string selection transistor SST1 and a second string selection transistor SST2 connected in series to each other, and the second string selection transistor SST2 may be connected to a corresponding one of the bit lines BL0 to BL2. Alternatively, each cell string CSTR may include a single string selection transistor.

[0025] The memory cell transistors MCT may be connected in series between the first string selection transistor SST1 and the ground selection transistor GST. The erase control transistor ECT of each cell string CSTR may be connected between the ground selection transistor GST and the common source line CSL. In some embodiments, each cell string CSTR may further include a dummy cell DMC connected between the first string selection transistor SST1 and the uppermost memory cell transistor MCT and between the ground selection transistor GST and the lowermost memory cell transistor MCT, respectively. The first string selection transistor SST1 may be connected by a first string selection line SSL1 (e.g., SSL1 0 ), the second string selection transistor SST2 may be controlled by a second string selection line SSL2 (eg, SSL2 0). The memory cell transistors MCT may be controlled by word lines WL0 to WLn, respectively, and the dummy cells DMC may be controlled by dummy word lines DWL, respectively. In addition, the ground selection transistor GST may be controlled by a ground selection line GSL (e.g., GSL0, GSL1, or GSL2), and the erase control transistor ECT may be controlled by an erase control line ECL. The common source line CSL may be commonly connected to the source of the erase control transistor ECT. The erase control transistors ECT of different cell strings CSTR may be commonly controlled by the erase control line ECL. The erase control transistor ECT may generate gate-induced drain leakage (GIDL) in an erase operation of the cell array.

[0026] Figure 2 is a plan view illustrating a 3D semiconductor memory device according to some embodiments of the inventive concept. Figure 3 and Figure 4 are along Figure 2 Cross-sectional views taken along lines II' and II-II'. Figure 5 is a plan view showing a source structure SC, Figure 6 is a plan view showing the erase gate electrode EGE and the cell gate electrode CGE. Figure 7 is a plan view showing the ground gate electrode GGE. Figure 8 yes Figure 3 A magnified view of the "A" section, Fig. 9A yes Figure 4 Magnified view of section "B".

[0027] Reference Figures 2 to 4 , the substrate 10 may include a cell array region CAR and a connection region CNR. The substrate 10 may be a semiconductor substrate (e.g., a silicon substrate, a germanium substrate, or a silicon germanium substrate). A well region 10W may be provided in the substrate 10. The substrate 10 may have a first conductivity type, and the well region 10W may include a dopant of a second conductivity type different from the first conductivity type. For example, the first conductivity type may be a P type, and the second conductivity type may be an N type. In some embodiments, the well region 10W may be omitted.

[0028] The source structure SC and the electrode structure ST may be sequentially stacked on the substrate 10. The source structure SC may be disposed between the substrate 10 and the electrode structure ST, and may be disposed on the well region 10W. The source structure SC and the electrode structure ST may be sequentially stacked along a first direction D1 that is vertical (e.g., perpendicular) relative to the top surface 10U of the substrate 10. The electrode structure ST may extend from the cell array region CAR to / on the connection region CNR along a second direction D2 that is parallel to the top surface 10U of the substrate 10. The source structure SC may extend along the second direction D2 under the electrode structure ST. The source structure SC may include a first source conductive pattern SCP1 and a second source conductive pattern SCP2 sequentially stacked on the substrate 10. The first source conductive pattern SCP1 may be in direct contact with the well region 10W. In some embodiments, an insulating layer may be disposed between the first source conductive pattern SCP1 and the well region 10W. The first source conductive pattern SCP1 and the second source conductive pattern SCP2 may include a semiconductor material doped with a second conductive type dopant. The concentration of the dopant in the first source conductive pattern SCP1 may be greater than the concentration of the dopant in the second source conductive pattern SCP2. For example, the first source conductive pattern SCP1 and the second source conductive pattern SCP2 may include polysilicon doped with an N-type dopant (e.g., phosphorus (P) or arsenic (As)), and the concentration of the N-type dopant in the first source conductive pattern SCP1 may be greater than the concentration of the N-type dopant in the second source conductive pattern SCP2.

[0029] Reference Figures 3 to 5 , the first source conductive pattern SCP1 may have a recessed sidewall OP. Each recessed sidewall OP may be recessed toward the inner side of the first source conductive pattern SCP1. The first source conductive pattern SCP1 may have at least one pair of recessed sidewalls OP opposite to each other in a third direction D3, the third direction D3 being parallel to the top surface 10U of the substrate 10 and intersecting the second direction D2. The second source conductive pattern SCP2 may cover the top surface of the first source conductive pattern SCP1, and may extend onto the recessed sidewall OP of the first source conductive pattern SCP1. A portion of the second source conductive pattern SCP2 may cover the recessed sidewall OP of the first source conductive pattern SCP1, and may contact the insulating layer 11 on the substrate 10 or the well region 10W. In some embodiments, the insulating layer 11 may be omitted, and in this case, the portion of the second source conductive pattern SCP2 may directly contact the substrate 10 or the well region 10W.

[0030] In some embodiments, the first source conductive pattern SCP1 may be locally disposed on the cell array region CAR, and the second source conductive pattern SCP2 may extend from the cell array region CAR to / on the connection region CNR along the second direction D2. In this case, the lower sacrificial pattern LSP may be disposed on the connection region CNR of the substrate 10, and may be disposed between the second source conductive pattern SCP2 and the substrate 10. The insulating layer 11 may be disposed on the connection region CNR of the substrate 10, and further disposed between the lower sacrificial pattern LSP and the substrate 10, and the buffer insulating layer 12 may be disposed on the connection region CNR of the substrate 10, and further disposed between the lower sacrificial pattern LSP and the second source conductive pattern SCP2. For example, the lower sacrificial pattern LSP may include at least one of silicon nitride, silicon oxynitride, silicon carbide, or silicon germanium. For example, the insulating layer 11 and the buffer insulating layer 12 may each include a silicon oxide layer. The first source conductive pattern SCP1 may extend along the second direction D2, thereby contacting the sidewalls of the lower sacrificial pattern LSP, the insulating layer 11, and the buffer insulating layer 12.

[0031] Refer again Figures 2 to 4 , the electrode structure ST may include a lower electrode structure LST, an upper electrode structure UST, and a planarization insulating layer 50 disposed between the lower electrode structure LST and the upper electrode structure UST. The lower electrode structure LST may include lower gate electrodes EGE and GGE alternately stacked on the source structure SC along the first direction D1 and a lower insulating layer 110a. The upper electrode structure UST may include upper gate electrodes CGE and SGE alternately stacked on the planarization insulating layer 50 along the first direction D1 and an upper insulating layer 110b. The planarization insulating layer 50 may be disposed between the uppermost lower gate electrode GGE of the lower gate electrodes EGE and GGE and the lowermost upper gate electrode CGE of the upper gate electrodes CGE and SGE. The lower insulating layer 110a, the upper insulating layer 110b, and the planarization insulating layer 50 may have a certain thickness in the first direction D1, respectively. The thickness of the planarization insulating layer 50 may be greater than the thickness of the lower insulating layer 110a and the upper insulating layer 110b. The uppermost insulating layer 110b of the lower insulating layer 110a and the upper insulating layer 110b may be thicker than other insulating layers in the lower insulating layer 110a and the upper insulating layer 110b. For example, the lower gate electrodes EGE and GGE and the upper gate electrodes CGE and SGE may include at least one of a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), or a transition metal (e.g., titanium or tantalum). The lower insulating layer 110a, the upper insulating layer 110b, and the planarization insulating layer 50 may each include a silicon oxide layer and / or a low-k dielectric layer.

[0032] Reference Figure 3 , Figure 4 , Figure 6 and Figure 7The lower gate electrodes EGE and GGE may include an erase control gate electrode EGE and a ground selection gate electrode GGE on the erase control gate electrode EGE. The erase control gate electrode EGE may be adjacent to the source structure SC. The lowermost lower insulating layer 110a may be disposed between the erase control gate electrode EGE and the source structure SC. The erase control gate electrode EGE may be used as Figure 1 The erase control gate electrode EGE may include a linear portion extending along the second direction D2 and a connecting portion connecting the linear portion, such as Figure 6 The ground selection gate electrode GGE may have a linear shape extending along the second direction D2, as shown in FIG. Figure 7 As shown. The ground selection gate electrode GGE may be spaced apart from the adjacent ground selection gate electrode GGE in the third direction D3. The ground selection gate electrode GGE may be respectively disposed on the linear portion of the erase control gate electrode EGE. The ground selection gate electrode GGE may be used as Figure 1 The gate electrode of the ground selection transistor GST.

[0033] The upper gate electrodes CGE and SGE may include a cell gate electrode CGE and a string selection gate electrode SGE. The cell gate electrode CGE may be disposed between the ground selection gate electrode GGE and the string selection gate electrode SGE, and may be disposed at different heights (or levels) from the top surface 10U of the substrate 10. The cell gate electrode CGE may be used as Figure 1 Each cell gate electrode CGE may include a linear portion extending along the second direction D2 and a connecting portion connecting the linear portions, such as Figure 6 The ground selection gate electrodes GGE may be disposed under the line-shaped portions of the lowermost cell gate electrodes CGE, respectively.

[0034] Refer again Figures 2 to 4 , the string selection gate electrode SGE may include a pair of string selection gate electrodes SGE1 and SGE2 that are laterally spaced apart from each other. The pair of string selection gate electrodes SGE1 and SGE2 may be spaced apart from each other in the third direction D3. The pair of string selection gate electrodes SGE1 and SGE2 may be isolated from each other by an isolation insulating pattern 105 interposed therebetween. The isolation insulating pattern 105 may have a line shape extending along the second direction D2. The isolation insulating pattern 105 may include an insulating material (e.g., silicon oxide). The string selection gate electrode SGE (e.g., SGE1 or SGE2) may be used as Figure 1The gate electrode of the string selection transistor SST2. In some embodiments, an additional string selection gate electrode SGE may be provided between the string selection gate electrode SGE and the uppermost cell gate electrode CGE. In this case, the additional string selection gate electrode SGE may include a pair of additional string selection gate electrodes SGE1 and SGE2 spaced apart from each other in the third direction D3, and the additional string selection gate electrode SGE (for example, SGE1 or SGE2) may be used as Figure 1 The gate electrode of the string selection transistor SST1. The lengths of the gate electrodes EGE, GGE, CGE, and SGE of the electrode structure ST (i.e., the lengths in the second direction D2) may be sequentially reduced as the vertical distance from the substrate 10 increases. The gate electrodes EGE, GGE, CGE, and SGE of the electrode structure ST may include an electrode pad (i.e., a pad region of the gate electrode) constituting (i.e., providing) a step structure on the connection region CNR.

[0035] The vertical structure VS may be disposed on the cell array region CAR of the substrate 10, and the dummy vertical structure DVS may be disposed on the connection region CNR of the substrate 10. Each vertical structure VS may extend along the first direction D1 to penetrate the electrode structure ST and the source structure SC. For example, when viewed in a plan view, the vertical structures VS constituting two adjacent rows may be arranged in a zigzag form along the second direction D2. Each dummy vertical structure DVS may penetrate the corresponding electrode pad and the electrode structure ST and the source structure SC under the corresponding electrode pad. In some embodiments, each dummy vertical structure DVS may penetrate the second source conductive pattern SCP2, the lower sacrificial pattern LSP, the insulating layer 11, and the buffer insulating layer 12. Each vertical structure VS and the dummy vertical structure DVS may have a certain width in a direction parallel to the top surface 10U of the substrate 10, and the width of the dummy vertical structure DVS may be greater than the width of the vertical structure VS.

[0036] Reference Figure 2 , Figure 3 and Figure 8 , each vertical structure VS may include a vertical semiconductor pattern VSP. The vertical semiconductor pattern VSP may extend along the first direction D1 to penetrate the electrode structure ST and the source structure SC. The vertical semiconductor pattern VSP may extend into the substrate 10. The bottom surface VSP_B of the vertical semiconductor pattern VSP may be disposed in the substrate 10 or the well region 10W. The vertical semiconductor pattern VSP may have a tubular shape with a closed bottom end. The vertical semiconductor pattern VSP may include a semiconductor material such as silicon (Si), germanium (Ge), or a compound thereof. In addition, the vertical semiconductor pattern VSP may include a semiconductor material doped with a dopant or an intrinsic semiconductor material not doped with a dopant. The vertical semiconductor pattern VSP may be used as a reference Figure 1The erase control transistor ECT, the string selection transistor SST, the ground selection transistor GST, and the channel region of the memory cell transistor MCT are described.

[0037] The sidewall of the lower portion of the vertical semiconductor pattern VSP may be in contact with the first source conductive pattern SCP1. The first source conductive pattern SCP1 may include a horizontal portion HP extending substantially parallel to the top surface 10U of the substrate 10 below the second source conductive pattern SCP2 and a vertical portion SP protruding vertically from the horizontal portion HP. The vertical portion SP may be in contact with a portion of the sidewall of the vertical semiconductor pattern VSP and may surround this portion of the sidewall of the vertical semiconductor pattern VSP. The horizontal portion HP of the first source conductive pattern SCP1 may be disposed between the top surface 10U of the substrate 10 and the second source conductive pattern SCP2. The horizontal portion HP of the first source conductive pattern SCP1 may be in contact with the substrate 10 or the well region 10W. The vertical portion SP of the first source conductive pattern SCP1 may extend between the sidewall of the vertical semiconductor pattern VSP and the sidewall of the substrate 10 (e.g., the well region 10W) ​​and between the sidewall of the vertical semiconductor pattern VSP and the sidewall of the second source conductive pattern SCP2.

[0038] Each vertical structure VS may include a data storage pattern DSP disposed between a vertical semiconductor pattern VSP and an electrode structure ST. The data storage pattern DSP may extend along a first direction D1 and may surround a sidewall of the vertical semiconductor pattern VSP. The data storage pattern DSP may have a tubular shape with a top and a bottom open. The bottom surface DSP_B of the data storage pattern DSP may be in contact with the first source conductive pattern SCP1. The data storage pattern DSP may include a data storage layer of a NAND flash memory device. The data storage pattern DSP may include a charge storage layer 220 between the vertical semiconductor pattern VSP and the electrode structure ST, a blocking insulating layer 210 between the electrode structure ST and the charge storage layer 220, and a tunnel insulating layer 230 between the vertical semiconductor pattern VSP and the charge storage layer 220. For example, the charge storage layer 220 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, or a laminated trap layer. The blocking insulating layer 210 may include a material having a band gap greater than the band gap of the charge storage layer 220. For example, the blocking insulating layer 210 may include a high-k dielectric layer, such as an aluminum oxide layer and / or a hafnium oxide layer. The tunnel insulating layer 230 may include a material having a greater energy bandgap than the charge storage layer 220. For example, the tunnel insulating layer 230 may include a silicon oxide layer.

[0039] Each vertical structure VS may include a residual data storage pattern DSPr disposed between the vertical semiconductor pattern VSP and the substrate 10 (or the well region 10W). The residual data storage pattern DSPr may be disposed in the substrate 10 or the well region 10W, and the vertical semiconductor pattern VSP may be spaced apart from the substrate 10 or the well region 10W by the residual data storage pattern DSPr. The vertical semiconductor pattern VSP may be electrically isolated from the substrate 10 or the well region 10W by the residual data storage pattern DSPr. The residual data storage pattern DSPr may be disposed between the bottom surface VSP_B of the vertical semiconductor pattern VSP and the substrate 10 (or the well region 10W), and may extend onto the sidewall of the vertical semiconductor pattern VSP. When viewed in a cross-sectional view, the residual data storage pattern DSPr may have a U-shape. The data storage pattern DSP may be vertically spaced apart from the residual data storage pattern DSPr.

[0040] The uppermost surface DSPr_U of the residual data storage pattern DSPr may be disposed at a height (or level) lower than the top surface 10U of the substrate 10. The residual data storage pattern DSPr may be vertically spaced apart from the data storage pattern DSP, with the vertical portion SP of the first source conductive pattern SCP1 interposed therebetween. The uppermost surface DSPr_U of the residual data storage pattern DSPr may be in contact with the vertical portion SP of the first source conductive pattern SCP1. The residual data storage pattern DSPr may have a layer structure substantially the same as that of the data storage pattern DSP. For example, the residual data storage pattern DSPr may include a residual charge storage layer 220r between the vertical semiconductor pattern VSP and the substrate 10 (or the well region 10W), a residual blocking insulating layer 210r between the substrate 10 (or the well region 10W) ​​and the residual charge storage layer 220r, and a residual tunnel insulating layer 230r between the vertical semiconductor pattern VSP and the residual charge storage layer 220r. The residual charge storage layer 220 r , the residual blocking insulating layer 210 r , and the residual tunnel insulating layer 230 r may include the same materials as the charge storage layer 220 , the blocking insulating layer 210 , and the tunnel insulating layer 230 , respectively.

[0041] Each vertical structure VS may include an insulating pattern 160 on the inner sidewall of the vertical semiconductor pattern VSP (e.g., filling the inner side of the vertical semiconductor pattern VSP). The insulating pattern 160 may include a first insulating pattern 162 and a second insulating pattern 164, and the first insulating pattern 162 may be disposed between the second insulating pattern 164 and the vertical semiconductor pattern VSP. The first insulating pattern 162 and the second insulating pattern 164 may include, for example, silicon oxide. Each vertical structure VS may include a conductive pad 150 disposed on the vertical semiconductor pattern VSP. The conductive pad 150 may cover the top surface of the insulating pattern 160 and the uppermost surface of the vertical semiconductor pattern VSP. The conductive pad 150 may include a semiconductor material doped with a dopant and / or a conductive material. The data storage pattern DSP may extend from the sidewall of the vertical semiconductor pattern VSP to the sidewall of the conductive pad 150. The data storage pattern DSP may surround the sidewall of the conductive pad 150, and the uppermost surface of the data storage pattern DSP may be substantially coplanar with the top surface of the conductive pad 150.

[0042] Reference Figure 2 , Figure 4 and Fig. 9A , each dummy vertical structure DVS may include a dummy vertical semiconductor pattern DVSP. The dummy vertical semiconductor pattern DVSP may extend substantially along the first direction D1 to penetrate the corresponding electrode pad and the electrode structure ST and source structure SC under the corresponding electrode pad. The term "substantially" used herein for extending along the first direction D1 means that the element (e.g., the dummy vertical semiconductor pattern DVSP) may extend at a slight or moderate angle (e.g., 45 degrees or less) relative to the first direction D1, rather than extending completely vertically. The dummy vertical semiconductor pattern DVSP may penetrate the lower sacrificial pattern LSP, the insulating layer 11, and the buffer insulating layer 12 under the corresponding electrode pad. The dummy vertical semiconductor pattern DVSP may extend into the substrate 10. The bottom surface DVSP_B of the dummy vertical semiconductor pattern DVSP may be disposed in the substrate 10 or the well region 10W. The dummy vertical semiconductor pattern DVSP may have a tubular shape with an open bottom end. The dummy vertical semiconductor pattern DVSP may include the same material as the vertical semiconductor pattern VSP.

[0043] Each dummy vertical structure DVS may include a contact pattern 200 extending from the bottom DVSP_BP of the dummy vertical semiconductor pattern DVSP to the substrate 10 (or the well region 10W). In some embodiments, the contact pattern 200 may include a conductive material. For example, the contact pattern 200 may include the same material as the dummy vertical semiconductor pattern DVSP. The contact pattern 200 may contact the bottom DVSP_BP of the dummy vertical semiconductor pattern DVSP, and the dummy vertical semiconductor pattern DVSP may be electrically connected to the substrate 10 or the well region 10W through the contact pattern 200. The contact pattern 200 may have a columnar shape extending in the first direction D1, for example.

[0044] Each dummy vertical structure DVS may include a dummy data storage pattern DSPd disposed between the dummy vertical semiconductor pattern DVSP and the substrate 10 (or the well region 10W). The dummy data storage pattern DSPd may be disposed in the substrate 10 or the well region 10W, and the dummy vertical semiconductor pattern DVSP may be spaced apart from the substrate 10 or the well region 10W by the dummy data storage pattern DSPd. The bottom DSPd_BP of the dummy data storage pattern DSPd may be disposed between the bottom surface DVSP_B of the dummy vertical semiconductor pattern DVSP and the substrate 10 (or the well region 10W). The dummy data storage pattern DSPd may extend between the sidewall of the dummy vertical semiconductor pattern DVSP and the substrate 10 (or the well region 10W). The contact pattern 200 may penetrate the bottom DSPd_BP of the dummy data storage pattern DSPd so as to be connected to the substrate 10 (or the well region 10W).

[0045] The dummy data storage pattern DSPd may extend substantially along the first direction D1 and may surround the sidewall of the dummy vertical semiconductor pattern DVSP. The dummy data storage pattern DSPd may have a tubular shape with open top and bottom ends. The dummy data storage pattern DSPd may extend between the electrode structure ST and the dummy vertical semiconductor pattern DVSP and between the source structure SC and the dummy vertical semiconductor pattern DVSP. In some embodiments, the dummy data storage pattern DSPd may be disposed between each of the second source conductive pattern SCP2, the lower sacrificial pattern LSP, the insulating layer 11, and the buffer insulating layer 12 and the dummy vertical semiconductor pattern DVSP. The dummy data storage pattern DSPd may have a layer structure substantially the same as that of the data storage pattern DSP. The dummy data storage pattern DSPd may include a charge storage layer 220 between the dummy vertical semiconductor pattern DVSP and the electrode structure ST, a blocking insulating layer 210 between the electrode structure ST and the charge storage layer 220, and a tunnel insulating layer 230 between the dummy vertical semiconductor pattern DVSP and the charge storage layer 220.

[0046] Each dummy vertical structure DVS may include a dummy insulating pattern 160d on the inner sidewall of the dummy vertical semiconductor pattern DVSP (e.g., filling the inner side of the dummy vertical semiconductor pattern DVSP). The dummy insulating pattern 160d may be disposed on the contact pattern 200 and may cover the top surface 200U of the contact pattern 200. The dummy insulating pattern 160d may have a layer structure substantially the same as the insulating pattern 160. The dummy insulating pattern 160d may include a first dummy insulating pattern 162d and a second dummy insulating pattern 164d, and the first dummy insulating pattern 162d may be disposed between the second dummy insulating pattern 164d and the dummy vertical semiconductor pattern DVSP. The first dummy insulating pattern 162d may conformally cover the inner sidewall of the dummy vertical semiconductor pattern DVSP and may expose the top surface 200U of the contact pattern 200. The second dummy insulating pattern 164d may cover the top surface 200U of the contact pattern 200. The first dummy insulating pattern 162d and the second dummy insulating pattern 164d may include the same material as the first insulating pattern 162 and the second insulating pattern 164, respectively. The first dummy insulating pattern 162d and the second dummy insulating pattern 164d may include, for example, silicon oxide. In some embodiments, the contact pattern 200 may include a material different from that of the dummy insulating pattern 160d, and the dummy insulating pattern 160d may contact the top surface 200U of the contact pattern 200.

[0047] Each dummy vertical structure DVS may include a dummy conductive pad 150d disposed on the dummy vertical semiconductor pattern DVSP. The dummy conductive pad 150d may cover the top surface of the dummy insulating pattern 160d and the uppermost surface of the dummy vertical semiconductor pattern DVSP. The dummy conductive pad 150d may include the same material as the conductive pad 150. The dummy data storage pattern DSPd may extend from the sidewall of the dummy vertical semiconductor pattern DVSP to the sidewall of the dummy conductive pad 150d. The dummy data storage pattern DSPd may surround the sidewall of the dummy conductive pad 150d, and the uppermost surface of the dummy data storage pattern DSPd may be substantially coplanar with the top surface of the dummy conductive pad 150d.

[0048] Refer again Figures 2 to 4, the common source plugs CSP may be respectively disposed on both sides of the electrode structure ST and may be connected to the substrate 10 or the well region 10W. The common source plugs CSP may extend along the second direction D2 and may be spaced apart from each other in the third direction D3, with the electrode structure ST interposed therebetween. The common source plugs CSP may be respectively disposed on both sides of the source structure SC and may be spaced apart from each other in the third direction D3, with the source structure SC interposed therebetween. The sidewall insulating spacers SS may be respectively disposed on both side walls of the electrode structure ST. Each sidewall insulating spacer SS may be disposed between the electrode structure ST and each common source plug CSP. Each sidewall insulating spacer SS may extend between the source structure SC and each common source plug CSP and may contact the substrate 10 or the well region 10W. The common source plugs CSP may include a conductive material, and the sidewall insulating spacers SS may include, for example, silicon nitride.

[0049] The first cover insulating layer 110 may be disposed on the connection region CNR of the substrate 10 to cover the electrode pads constituting the step structure. The second cover insulating layer 120 may cover the top surface of the electrode structure ST, the top surface of the conductive pad 150, the top surface of the dummy conductive pad 150d, and the top surface of the first cover insulating layer 110. The top surface of the second cover insulating layer 120 may be located at substantially the same height as the top surface of the common source plug CSP. The interlayer insulating layer 130 may be disposed on the second cover insulating layer 120 to cover the top surface of the common source plug CSP. The first cover insulating layer 110 and the second cover insulating layer 120 and the interlayer insulating layer 130 may include an insulating material (e.g., silicon oxide). A first contact 125 may be disposed on the conductive pad 150. The first contact 125 may penetrate the second cover insulating layer 120 so as to be connected to the conductive pad 150. The second contact 135 may penetrate the interlayer insulating layer 130 so as to be connected to the first contact 125. The first contact 125 and the second contact 135 may include a conductive material. The bit line BL may be disposed on the interlayer insulating layer 130. The bit lines BL may extend along the third direction D3 and may be spaced apart from each other in the second direction D2. At least one of the vertical structures VS may be a unit dummy vertical structure including a unit dummy vertical semiconductor pattern that is not connected to the first contact 125 or the second contact 135. In addition to the unit dummy vertical structure, the vertical semiconductor pattern VSP of each vertical structure VS may be electrically connected to the corresponding bit line BL through the first contact 125 and the second contact 135. The bit line BL may include a conductive material. The conductive contact CT and the conductive wire CL may be connected to the electrode pads of the gate electrodes EGE, GGE, CGE, and SGE. In Figure 1 In the erase operation of the memory cell array, an erase voltage can be applied to the source structure SC, so that Figure 1The gate-induced drain leakage (GIDL) current is generated in the erase control transistor ECT. As a result, Figure 1 The memory cell is erased.

[0050] Fig. 9B FIG. 2 is a diagram showing a 3D semiconductor memory device according to some embodiments of the present inventive concept. Figure 4 In the following, for the sake of convenience, the following will mainly describe Fig. 9B With reference Figures 1 to 8 and Fig. 9A The differences between the above embodiments are described.

[0051] Reference Fig. 9B , each dummy vertical structure DVS may include a contact pattern 200 extending from a bottom DVSP_BP of a dummy vertical semiconductor pattern DVSP into the substrate 10 (or the well region 10W). According to some embodiments, the contact pattern 200 may include an insulating material. The contact pattern 200 (e.g., a sidewall thereof) may contact the bottom DVSP_BP of the dummy vertical semiconductor pattern DVSP, and may penetrate the bottom DSPd_BP of the dummy data storage pattern DSPd so as to be connected to the substrate 10 (or the well region 10W). The contact pattern 200 may have a column shape extending along the first direction D1. The dummy insulating pattern 160d may be disposed on the contact pattern 200. The contact pattern 200 may include the same material as the dummy insulating pattern 160d, and the contact pattern 200 and the dummy insulating pattern 160d may contact each other to constitute (i.e., provide) a whole. For example, the contact pattern 200 may include the same material as the second dummy insulation pattern 164 d of the dummy insulation pattern 160 d , and the contact pattern 200 and the second dummy insulation pattern 164 d may contact each other to constitute one whole body.

[0052] Fig. 9C FIG. 2 is a diagram showing a 3D semiconductor memory device according to some embodiments of the present inventive concept. Figure 4 In the following, for the sake of convenience, the following will mainly describe Fig. 9C With reference Figures 1 to 8 and Fig. 9A The differences between the above embodiments are described.

[0053] Reference Fig. 9C, each dummy vertical structure DVS may include a contact pattern 200 extending from a bottom DVSP_BP of a dummy vertical semiconductor pattern DVSP into the substrate 10 (or the well region 10W). The contact pattern 200 may contact the bottom DVSP_BP of the dummy vertical semiconductor pattern DVSP and may penetrate the bottom DSPd_BP of the dummy data storage pattern DSPd so as to be connected to the substrate 10 (or the well region 10W). According to some embodiments, the contact pattern 200 may include a first portion 200a contacting the bottom DVSP_BP of the dummy vertical semiconductor pattern DVSP and a second portion 200b spaced apart from the dummy vertical semiconductor pattern DVSP (with the first portion 200a interposed therebetween). The first portion 200a may extend between the bottom DSPd_BP of the dummy data storage pattern DSPd and the second portion 200b and between the substrate 10 (or the well region 10W) ​​and the second portion 200b. When viewed in a cross-sectional view, the first portion 200a may have a U-shape. The second portion 200 b may have a column shape extending in the first direction D1 , and the first portion 200 a may cover a bottom surface and sidewalls of the second portion 200 b .

[0054] The dummy insulating pattern 160d may be disposed on the contact pattern 200. The first portion 200a of the contact pattern 200 may include a material different from that of the dummy insulating pattern 160d. The first portion 200a of the contact pattern 200 may include a conductive material. For example, the first portion 200a of the contact pattern 200 may include the same material as the dummy vertical semiconductor pattern DVSP. The dummy vertical semiconductor pattern DVSP may be electrically connected to the substrate 10 or the well region 10W through the first portion 200a of the contact pattern 200. The second portion 200b of the contact pattern 200 may include an insulating material. The second portion 200b of the contact pattern 200 may include the same material as the dummy insulating pattern 160d, and the second portion 200b and the dummy insulating pattern 160d may contact each other to form a whole. For example, the second portion 200 b of the contact pattern 200 may include the same material as the second dummy insulation pattern 164 d of the dummy insulation pattern 160 d , and the second portion 200 b and the second dummy insulation pattern 164 d may contact each other to constitute (ie, provide) one whole.

[0055] Fig.9D FIG. 2 is a diagram showing a 3D semiconductor memory device according to some embodiments of the present inventive concept. Figure 4 In the following, for the sake of convenience, the following will mainly describe Fig.9D With reference Figures 1 to 8 and Fig. 9A The differences between the above embodiments are described.

[0056] Reference Fig.9D , according to some embodiments, Figure 4 The lower sacrificial pattern LSP, the insulating layer 11, and the buffer insulating layer 12 on the connection region CNR shown in FIG. 1 may be replaced with the first source conductive pattern SCP1. In this case, the first source conductive pattern SCP1 may extend from the cell array region CAR to / on the connection region CNR along the second direction D2, and may be disposed between the second source conductive pattern SCP2 and the substrate 10 on the connection region CNR of the substrate 10. Each dummy vertical structure DVS may penetrate the first source conductive pattern SCP1 and the second source conductive pattern SCP2.

[0057] Each dummy vertical structure DVS may include a dummy vertical semiconductor pattern DVSP, and a sidewall of a lower portion of the dummy vertical semiconductor pattern DVSP may be in contact with the first source conductive pattern SCP1. The vertical portion SP of the first source conductive pattern SCP1 may be in contact with a portion of the sidewall of the dummy vertical semiconductor pattern DVSP, and may surround this portion of the sidewall of the dummy vertical semiconductor pattern DVSP. The horizontal portion HP of the first source conductive pattern SCP1 may be disposed between the top surface 10U of the substrate 10 and the second source conductive pattern SCP2. The horizontal portion HP of the first source conductive pattern SCP1 may be in contact with the substrate 10 or the well region 10W. The vertical portion SP of the first source conductive pattern SCP1 may extend between the sidewall of the dummy vertical semiconductor pattern DVSP and the sidewall of the substrate 10 (e.g., the well region 10W) ​​and between the sidewall of the dummy vertical semiconductor pattern DVSP and the sidewall of the second source conductive pattern SCP2. Each of the dummy vertical structures DVS may include a contact pattern 200 extending from a bottom DVSP_BP of the dummy vertical semiconductor pattern DVSP into the substrate 10 (or the well region 10W).

[0058] Each dummy vertical structure DVS may include a dummy data storage pattern DSPd disposed between the dummy vertical semiconductor pattern DVSP and the electrode structure ST. The dummy data storage pattern DSPd may extend along the first direction D1 and may surround the sidewall of the dummy vertical semiconductor pattern DVSP. The dummy data storage pattern DSPd may have a tubular shape with the top and bottom ends open. The bottom surface DSPd_B of the dummy data storage pattern DSPd may contact the first source conductive pattern SCP1. The dummy data storage pattern DSPd may have a layer structure substantially the same as that of the data storage pattern DSP.

[0059] Each dummy vertical structure DVS may include a dummy residual data storage pattern DSPrd disposed between the dummy vertical semiconductor pattern DVSP and the substrate 10 (or the well region 10W). The dummy residual data storage pattern DSPrd may be disposed in the substrate 10 or the well region 10W, and the dummy vertical semiconductor pattern DVSP may be spaced apart from the substrate 10 or the well region 10W by the dummy residual data storage pattern DSPrd. The dummy residual data storage pattern DSPrd may be disposed between the bottom surface DVSP_B of the dummy vertical semiconductor pattern DVSP and the substrate 10 (or the well region 10W), and may extend onto the sidewall of the dummy vertical semiconductor pattern DVSP. The dummy data storage pattern DSPd may be vertically spaced apart from the dummy residual data storage pattern DSPrd.

[0060] The uppermost surface DSPrd_U of the dummy residual data storage pattern DSPrd may be disposed at a height (or level) lower than the top surface 10U of the substrate 10. The dummy residual data storage pattern DSPrd may be vertically spaced apart from the dummy data storage pattern DSPrd, with the vertical portion SP of the first source conductive pattern SCP1 interposed therebetween. The uppermost surface DSPrd_U of the dummy residual data storage pattern DSPrd may be in contact with the vertical portion SP of the first source conductive pattern SCP1. The dummy residual data storage pattern DSPrd may have a layer structure substantially the same as that of the residual data storage pattern DSPr. The contact pattern 200 may penetrate the bottom of the dummy residual data storage pattern DSPrd so as to be connected to the substrate 10 (or the well region 10W).

[0061] According to some embodiments of the inventive concept, each dummy vertical structure DVS may include a contact pattern 200 extending from the bottom DVSP_BP of the dummy vertical semiconductor pattern DVSP to the substrate 10 (or the well region 10W). The contact pattern 200 may be in contact with the bottom DVSP_BP of the dummy vertical semiconductor pattern DVSP and may be connected (e.g., electrically connected) to the substrate 10 (or the well region 10W). The contact pattern 200 may serve as a path for the charge in the dummy vertical semiconductor pattern DVSP to be discharged. In this case, defects (e.g., a poor profile of an adjacent pattern (e.g., a trench)) that may be caused by the charge in the dummy vertical semiconductor pattern DVSP may be minimized / reduced. Therefore, a 3D semiconductor memory device with superior reliability may be provided or implemented.

[0062] Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A and Fig.24A is a diagram showing a method of manufacturing a 3D semiconductor memory device according to some embodiments of the inventive concept Figure 2 Cross-sectional view along line II'. Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B , Fig.21B , Fig. 22B , Fig. 23B and Fig. 24B is a diagram showing a method of manufacturing a 3D semiconductor memory device according to some embodiments of the inventive concept Figure 2 In the following, for the sake of convenience, the cross-sectional view of the line II-II' in the reference Figures 1 to 8 and 9A to 9D Description of the same features described.

[0063] Reference Fig. 10A and Fig. 10B , an insulating layer 11 may be formed on the substrate 10. The insulating layer 11 may cover the cell array region CAR and the connection region CNR of the substrate 10. For example, the insulating layer 11 may include a silicon oxide layer.

[0064] Reference Fig.11A and Fig. 11B , a lower sacrificial pattern LSP and a mask pattern MP may be sequentially formed on the insulating layer 11. Forming the lower sacrificial pattern LSP may include forming a lower sacrificial layer on the insulating layer 11, forming a mask pattern MP on the lower sacrificial layer, and etching the lower sacrificial layer using the mask pattern MP as an etching mask to expose the insulating layer 11. Through the etching process, the lower sacrificial pattern LSP may include an opening OPE exposing the insulating layer 11. The lower sacrificial pattern LSP may include a material having an etching selectivity with respect to the insulating layer 11. For example, the lower sacrificial pattern LSP may include at least one of silicon nitride, silicon oxynitride, silicon carbide, or silicon germanium.

[0065] Reference Fig. 12A and Fig. 12B, the mask pattern MP may be removed after forming the lower sacrificial pattern LSP. Thereafter, a buffer insulating layer 12 and a source conductive layer SCP may be sequentially formed on the lower sacrificial pattern LSP. The buffer insulating layer 12 having a substantially uniform thickness may conformally cover the top surface of the lower sacrificial pattern LSP and the sidewalls of the lower sacrificial pattern LSP exposed by the opening OPE. The source conductive layer SCP having a substantially uniform thickness may conformally cover the top surface of the lower sacrificial pattern LSP and the inner surface of the opening OPE. Since the source conductive layer SCP having a substantially uniform thickness covers the inner surface of the opening OPE, the top surface of the source conductive layer SCP may include a surface RS recessed toward the opening OPE. For example, the buffer insulating layer 12 may include a silicon oxide layer. The source conductive layer SCP may include a polycrystalline silicon layer doped with an N-type dopant.

[0066] Reference Fig.13A and Fig. 13B , a separation layer 13 may be formed to cover the recessed surface RS of the source conductive layer SCP. Forming the separation layer 13 may include forming the separation layer 13 on the source conductive layer SCP and planarizing the separation layer 13 to expose the top surface of the source conductive layer SCP. The separation layer 13 may include, for example, silicon oxide.

[0067] Reference Fig.14A and Fig. 14B , a lower insulating layer 110a and a lower sacrificial layer LSL may be alternately stacked on the source conductive layer SCP. The lower sacrificial layer LSL may include a material having an etching selectivity relative to the lower insulating layer 110a. A planarization insulating layer 50 may be formed on the uppermost lower sacrificial layer LSL. The planarization insulating layer 50 may be thicker than the lower insulating layer 110a, and may include, for example, a silicon oxide layer. An upper insulating layer 110b and an upper sacrificial layer USL may be alternately stacked on the planarization insulating layer 50. The upper sacrificial layer USL may include a material having an etching selectivity relative to the upper insulating layer 110b. In some embodiments, the upper sacrificial layer USL may include the same material as the lower sacrificial layer LSL and the lower sacrificial pattern LSP. For example, the upper sacrificial layer USL and the lower sacrificial layer LSL may each include a silicon nitride layer, and the upper insulating layer 110b and the lower insulating layer 110a may each include a silicon oxide layer. Hereinafter, the upper sacrificial layer USL and the lower sacrificial layer LSL, the upper insulating layer 110b and the lower insulating layer 110a, and the planarization insulating layer 50 may be referred to as a mold structure MS.

[0068] The mold structure MS may extend from the cell array region CAR of the substrate 10 into / on the connection region CNR. The upper sacrificial layer USL and the upper insulating layer 110 b may be patterned so that the mold structure MS has an end of a step structure on the connection region CNR. A first cover insulating layer 110 may be formed to cover the end of the step structure of the mold structure MS. An isolation insulating pattern 105 may be formed to divide the uppermost sacrificial layer USL. In other words, by the isolation insulating pattern 105, the uppermost sacrificial layer USL may be divided into a pair of upper sacrificial layers USL that are laterally spaced apart from each other.

[0069] Reference Fig.15A and Fig. 15B , a vertical hole VH may be formed in the mold structure MS on the cell array region CAR, and a dummy vertical hole DVH may be formed in the mold structure MS on the connection region CNR. Each of the vertical hole VH and the dummy vertical hole DVH may penetrate the mold structure MS, the source conductive layer SCP, the buffer insulating layer 12, the lower sacrificial pattern LSP, and the insulating layer 11, and may expose a portion of the substrate 10. Each of the vertical hole VH and the dummy vertical hole DVH may have a certain width in a direction parallel to the top surface 10U of the substrate 10, and the width of the dummy vertical hole DVH may be greater than the width of the vertical hole VH.

[0070] A data storage layer DSL, a vertical semiconductor layer VSL, and a first insulating layer 162L may be sequentially formed on the mold structure MS. The data storage layer DSL, the vertical semiconductor layer VSL, and the first insulating layer 162L may partially fill each of the vertical holes VH and the dummy vertical holes DVH, and may cover the inner surface of each of the vertical holes VH and the dummy vertical holes DVH with a substantially uniform thickness. In some embodiments, the first insulating layer 162L may fill the dummy vertical holes DVH having a relatively large width and the vertical holes VH having a relatively small width with a substantially uniform thickness. In this case, a thickness 162L_T1 of the first insulating layer 162L filling the lower portion of each vertical hole VH may be greater than a thickness 162L_T2 of the first insulating layer 162L filling the lower portion of each dummy vertical hole DVH. However, embodiments of the inventive concept are not limited thereto.

[0071] Reference Fig.16A and Fig. 16B, a recessed region RR may be formed in each dummy vertical hole DVH. Forming the recessed region RR may include anisotropically etching the first insulating layer 162L to form a first insulating pattern 162 in each vertical hole VH and forming a first dummy insulating pattern 162d in each dummy vertical hole DVH, and anisotropically etching the vertical semiconductor layer VSL and the data storage layer DSL by using the first insulating pattern 162 and the first dummy insulating pattern 162d as an etching mask. In some embodiments, the first insulating pattern 162 may be formed in a tubular shape with a closed bottom end, and the first dummy insulating pattern 162d may be formed in a tubular shape with an open bottom end. This may be because the thickness 162L_T1 of the first insulating layer 162L filling the lower portion of each vertical hole VH is greater than the thickness 162L_T2 of the first insulating layer 162L filling the lower portion of each dummy vertical hole DVH, and / or because the etching rate of the first insulating layer 162L in the dummy vertical hole DVH having a relatively large width is higher than the etching rate of the first insulating layer 162L in the vertical hole VH having a relatively small width. During the anisotropic etching process of the vertical semiconductor layer VSL and the data storage layer DSL, the vertical semiconductor layer VSL and the data storage layer DSL in the vertical hole VH may be protected by the first insulating pattern 162 and thus may not be etched. The recessed region RR may be formed by etching portions of the vertical semiconductor layer VSL and the data storage layer DSL in the dummy vertical hole DVH that are not covered by the first dummy insulating pattern 162d. The recessed region RR may extend from each dummy vertical hole DVH into the substrate 10.

[0072] Reference Fig.17A and Fig. 17B , a contact pattern 200 may be formed to fill the recessed region RR. In some embodiments, forming the contact pattern 200 may include forming a conductive layer filling the recessed region RR and a portion of each vertical hole VH and the dummy vertical hole DVH, and removing a portion of the conductive layer from each vertical hole VH and the dummy vertical hole DVH. The conductive layer may be removed by, for example, a wet etching process.

[0073] Reference Fig.18A and Fig.18B, a second insulating pattern 164 may be formed to fill the remaining portion of each vertical hole VH, and a second dummy insulating pattern 164d may be formed to fill the remaining portion of each dummy vertical hole DVH. Forming the second insulating pattern 164 and the second dummy insulating pattern 164d may include forming a second insulating layer filling the remaining portion of the vertical hole VH and the dummy vertical hole DVH, and planarizing the second insulating layer, the vertical semiconductor layer VSL, and the data storage layer DSL until the top surface of the mold structure MS is exposed. Therefore, the data storage pattern DSP, the vertical semiconductor pattern VSP, and the insulating pattern 160 may be partially formed in each vertical hole VH. In addition, the dummy data storage pattern DSPd, the dummy vertical semiconductor pattern DVSP, and the dummy insulating pattern 160d may be partially formed in each dummy vertical hole DVH. The insulating pattern 160 may include a first insulating pattern 162 and a second insulating pattern 164, and the dummy insulating pattern 160d may include a first dummy insulating pattern 162d and a second dummy insulating pattern 164d. The conductive pad 150 may be formed on the vertical semiconductor pattern VSP in each of the vertical holes VH, and the dummy conductive pad 150 d may be formed on the dummy vertical semiconductor pattern DVSP in each of the dummy vertical holes DVH.

[0074] Reference Fig.19A and Fig.19B , the second cover insulating layer 120 may be formed on the mold structure MS and may cover the top surface of the conductive pad 150 and the dummy conductive pad 150d. A trench T may be formed to penetrate the second cover insulating layer 120 and the mold structure MS. The trench T may expose a portion of the source conductive layer SCP. The trenches T may extend along the second direction D2 and may be spaced apart from each other in the third direction D3. When the dummy vertical semiconductor pattern DVSP is charged with electric charge, a poor profile of the trench T adjacent to the dummy vertical semiconductor pattern DVSP may occur during the etching process for forming the trench T. However, according to some embodiments of the present inventive concept, the contact pattern 200 may be used as a path for the charge in the dummy vertical semiconductor pattern DVSP to be discharged, and thus the poor profile of the trench T adjacent to the dummy vertical semiconductor pattern DVSP may be minimized / reduced. A sacrificial spacer layer 170 may be formed on the inner surface of the trench T. The sacrificial spacer layer 170 may partially fill each trench T and may cover the inner surface of the trench T with a substantially uniform thickness. The sacrificial spacer layer 170 may include a material having an etch selectivity with respect to the mold structure MS. For example, the sacrificial spacer layer 170 may include a polysilicon layer.

[0075] Reference Fig. 20A and Fig. 20B, the sacrificial spacer layer 170 may be anisotropically etched to form a sacrificial spacer 171 on the inner sidewall of the trench T. Portions of the source conductive layer SCP and the buffer insulating layer 12 under each trench T may be etched during the anisotropic etching process of the sacrificial spacer layer 170, thereby forming a through hole H exposing the lower sacrificial pattern LSP in each trench T. The lower sacrificial pattern LSP exposed by the through hole H may be removed by performing an isotropic etching process. In some embodiments, the lower sacrificial pattern LSP on the cell array area CAR may be removed to form a horizontal recessed area HR exposing a portion of the data storage pattern DSP. The lower sacrificial pattern LSP on the connection area CNR may not be removed by the isotropic etching process. Therefore, the dummy data storage pattern DSPd may be covered by the lower sacrificial pattern LSP, and the horizontal recessed area HR may be partially formed on the cell array area CAR.

[0076] Reference Fig.21A and Fig.21B , a portion of the data storage pattern DSP exposed by the horizontal recessed region HR may be removed to expose a portion of the sidewall of the vertical semiconductor pattern VSP. Since a portion of the data storage pattern DSP is removed, a residual data storage pattern DSPr may be formed in the substrate 10. The residual data storage pattern DSPr may be vertically spaced apart from the data storage pattern DSP. Removing a portion of the data storage pattern DSP may include removing a portion of the insulating layer 11 and a portion of the buffer insulating layer 12. Therefore, the bottom surface of the source conductive layer SCP and the top surface of the substrate 10 may be exposed through the horizontal recessed region HR. An undercut region UC may be formed by removing a portion of the data storage pattern DSP. The undercut region UC may be an empty region vertically extending (e.g., along the first direction D1) from the horizontal recessed region HR. The undercut region UC may extend between the sidewall of the vertical semiconductor pattern VSP and the sidewall of the source conductive layer SCP and between the sidewall of the vertical semiconductor pattern VSP and the sidewall of the substrate 10. The undercut region UC may expose the bottom surface of the data storage pattern DSP and the uppermost surface of the residual data storage pattern DSPr.

[0077] Reference Fig.22A and Fig. 22B , a sidewall conductive layer 180 may be formed to fill the undercut region UC, the horizontal recessed region HR, and a portion of the through hole H. The sidewall conductive layer 180 may be a semiconductor layer doped with a dopant, for example, a polysilicon layer doped with an N-type dopant. The sidewall conductive layer 180 may cover the inner surface of the through hole H with a substantially uniform thickness, and may not completely fill the through hole H. The sidewall conductive layer 180 may be in direct contact with the sidewall of the vertical semiconductor pattern VSP and the top surface of the substrate 10.

[0078] Reference Fig.23A and Fig. 23B, an isotropic etching process may be performed on the sidewall conductive layer 180 to form a first source conductive pattern SCP1 in the undercut region UC and the horizontal recessed region HR. The sacrificial spacer 171 may be etched in the isotropic etching process of the sidewall conductive layer 180, and thus a gate isolation region GIR exposing the sidewall of the mold structure MS may be formed. The source conductive layer SCP may be etched in the isotropic etching process of the sidewall conductive layer 180, and thus a second source conductive pattern SCP2 may be formed. The first source conductive pattern SCP1 and the second source conductive pattern SCP2 may be referred to as a source structure SC. The gate isolation region GIR may expose the sidewalls of the mold structure MS, the sidewalls of the source structure SC, and the top surface of the substrate 10. In some embodiments, the lower sacrificial pattern LSP, the insulating layer 11, and the buffer insulating layer 12 on the connection region CNR may be replaced with the first source conductive pattern SCP1, Fig. 23B In this case, the first source conductive pattern SCP1 may extend from the cell array region CAR to / on the connection region CNR along the second direction D2, and may be disposed between the second source conductive pattern SCP2 and the substrate 10 on the connection region CNR of the substrate 10. In this case, the sidewall of the lower portion of the dummy vertical semiconductor pattern DVSP may contact the first source conductive pattern SCP1, as shown in FIG. Fig.9D described.

[0079] Reference Fig.24A and Fig. 24B , the lower sacrificial layer LSL and the upper sacrificial layer USL exposed by the gate isolation region GIR may be removed. Therefore, a gate region GR may be formed between the lower insulating layers 110a and between the upper insulating layers 110b. Forming the gate region GR may include isotropically etching the lower sacrificial layer LSL and the upper sacrificial layer USL. Each gate region GR may extend horizontally from the corresponding gate isolation region GIR, and may expose a portion of the sidewall of each data storage pattern DSP and the dummy data storage pattern DSPd. Thereafter, gate electrodes EGE, GGE, CGE, and SGE may be formed to fill the gate regions GR, respectively.

[0080] Refer again Figure 3 and Figure 4, a common source plug CSP may be formed in the gate isolation region GIR, respectively, and a sidewall insulating spacer SS may be formed in the gate isolation region GIR. The common source plug CSP and the sidewall insulating spacer SS may be partially formed in the gate isolation region GIR. A first contact 125 may be formed in the second cover insulating layer 120 so as to be connected to the conductive pad 150. An interlayer insulating layer 130 may be formed on the second cover insulating layer 120 to cover the top surface of the common source plug CSP. A second contact 135 may be formed in the interlayer insulating layer 130 so as to be connected to the first contact 125. A bit line BL may be formed on the interlayer insulating layer 130.

[0081] Fig.25 is a diagram showing a method of manufacturing a 3D semiconductor memory device according to some embodiments of the inventive concept Figure 2 Hereinafter, for the convenience of explanation, the main description will be given. Fig.25 With reference FIG. 10A to FIG. 24B The differences between the above embodiments are described.

[0082] Reference Fig.18A and Fig.25 , a contact pattern 200 may be formed to fill the recessed region RR. A second insulating pattern 164 may be formed to fill the remaining portion of each vertical hole VH, and a second dummy insulating pattern 164d may be formed to fill the remaining portion of each dummy vertical hole DVH. In some embodiments, the second dummy insulating pattern 164d and the contact pattern 200 may include the same material and may contact each other to form a whole, as shown in FIG. Fig. 9B Forming the contact pattern 200, the second insulating pattern 164 and the second dummy insulating pattern 164d may include forming an insulating layer filling the recessed region RR and the remaining portions of the vertical hole VH and the dummy vertical hole DVH, and planarizing the insulating layer, the vertical semiconductor layer VSL and the data storage layer DSL until the top surface of the mold structure MS is exposed.

[0083] Fig.26 and Fig. 27 is a diagram showing a method of manufacturing a 3D semiconductor memory device according to some embodiments of the inventive concept Figure 2 Hereinafter, for the convenience of explanation, the main description will be given. Fig.26 and Fig. 27 With reference FIG. 10A to FIG. 24B The differences between the above embodiments are described.

[0084] Reference Fig.17A and Fig.26, the first portion 200a of the contact pattern may be formed to partially fill the recessed region RR. In some embodiments, forming the first portion 200a of the contact pattern may include forming a conductive layer that fills a portion of each vertical hole VH and the dummy vertical hole DVH and covers the inner surface of the recessed region RR with a substantially uniform thickness, and removing a portion of the conductive layer from each vertical hole VH and the dummy vertical hole DVH. The conductive layer may be removed by, for example, a wet etching process.

[0085] Reference Fig.18A and Fig. 27 , a second portion 200b of the contact pattern may be formed to fill the remaining portion of the recessed region RR. The first portion 200a and the second portion 200b may constitute the contact pattern 200. A second insulating pattern 164 may be formed to fill the remaining portion of each vertical hole VH, and a second dummy insulating pattern 164d may be formed to fill the remaining portion of each dummy vertical hole DVH. In some embodiments, the second dummy insulating pattern 164d and the second portion 200b of the contact pattern 200 may include the same material and may contact each other to constitute a whole, as shown in FIG. Fig. 9C Forming the second portion 200b of the contact pattern 200, the second insulating pattern 164, and the second dummy insulating pattern 164d may include forming an insulating layer filling the vertical hole VH, the dummy vertical hole DVH, and the remaining portion of the recessed region RR, and planarizing the insulating layer, the vertical semiconductor layer VSL, and the data storage layer DSL until the top surface of the mold structure MS is exposed.

[0086] According to some embodiments of the inventive concept, defects (eg, poor profiles of adjacent patterns) that may occur due to charges in dummy vertical semiconductor patterns may be minimized / reduced. Thus, a 3D semiconductor memory device having superior reliability may be provided or realized.

[0087] Although the inventive concept has been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the inventive concept. Therefore, it should be understood that the above embodiments are not restrictive but illustrative. Therefore, the scope of the inventive concept should be determined by the broadest permissible interpretation of the appended claims and their equivalents, and should not be restricted or limited by the foregoing description.

Claims

1. A three-dimensional 3D semiconductor memory device, comprising: substrate; an electrode structure on the first region of the substrate, the electrode structure comprising gate electrodes stacked along a first direction perpendicular to a top surface of the substrate; A first source conductive pattern is formed in the first region of the substrate and between the electrode structures; a lower sacrificial pattern on the second region of the substrate; an insulating layer between the second region of the substrate and the lower sacrificial pattern; a buffer insulating layer on the lower sacrificial pattern; a vertical semiconductor pattern penetrating the electrode structure and the first source conductive pattern on the first region of the substrate; as well as a dummy vertical pattern penetrating the buffer insulating layer, the lower sacrificial pattern and the insulating layer on the second region of the substrate, Wherein, each of the buffer insulating layer and the insulating layer includes an oxide layer.

2. The 3D semiconductor memory device according to claim 1, wherein: The lower sacrificial pattern includes a material different from a material of each of the buffer insulating layer and the insulating layer.

3. The 3D semiconductor memory device according to claim 2, wherein: Each of the buffer insulating layer and the insulating layer includes a silicon oxide layer, and wherein the lower sacrificial pattern includes silicon.

4. The 3D semiconductor memory device according to claim 1, wherein: The first source conductive pattern contacts sidewalls of the lower sacrificial pattern, the insulating layer, and the buffer insulating layer.

5. The 3D semiconductor memory device according to claim 1, further comprising: a second source conductive pattern, between the first source conductive pattern and the electrode structure, Wherein, the first source conductive pattern and the second source conductive pattern include semiconductor material, wherein the concentration of the dopant in the first source conductive pattern is higher than the concentration of the dopant in the second source conductive pattern, and Wherein, the vertical semiconductor pattern penetrates the second source conductive pattern.

6. The 3D semiconductor memory device according to claim 5, wherein: The first source conductive pattern contacts a sidewall of the vertical semiconductor pattern.

7. The 3D semiconductor memory device according to claim 5, wherein: The second source conductive pattern extends on the buffer insulating layer.

8. The 3D semiconductor memory device according to claim 5, wherein: The vertical semiconductor pattern extends into the substrate.

9. The 3D semiconductor memory device according to claim 1, wherein: The dummy vertical pattern is wider than the vertical semiconductor pattern in a second direction parallel to the top surface of the substrate.

10. The 3D semiconductor memory device according to claim 9, wherein: The dummy vertical pattern extends into the substrate.

11. A three-dimensional 3D semiconductor memory device, comprising: substrate; an electrode structure on the first region of the substrate, the electrode structure comprising gate electrodes stacked along a first direction perpendicular to a top surface of the substrate; a first source conductive pattern, between the first region of the substrate and the electrode structure; a lower sacrificial pattern on the second region of the substrate; an insulating layer between the second region of the substrate and the lower sacrificial pattern; a buffer insulating layer on the lower sacrificial pattern; a vertical semiconductor pattern penetrating the electrode structure and the first source conductive pattern and extending into the first region of the substrate; as well as a dummy vertical pattern penetrating the buffer insulating layer, the lower sacrificial pattern and the insulating layer, and extending into the second region of the substrate, The lower sacrificial pattern includes a material different from a material of each of the buffer insulating layer and the insulating layer.

12. The 3D semiconductor memory device according to claim 11, wherein: The lower sacrificial pattern includes silicon.

13. The 3D semiconductor memory device according to claim 11, wherein: The first source conductive pattern includes a semiconductor material doped with a dopant.

14. The 3D semiconductor memory device according to claim 13, wherein: The first source conductive pattern includes polysilicon doped with an N-type dopant.

15. The 3D semiconductor memory device according to claim 11, wherein: The first source conductive pattern contacts a sidewall of the vertical semiconductor pattern.

16. The 3D semiconductor memory device according to claim 11, wherein: Each of the buffer insulating layer and the insulating layer includes a silicon oxide layer.

17. The 3D semiconductor memory device according to claim 11, further comprising: a second source conductive pattern, between the first source conductive pattern and the electrode structure; Wherein, the vertical semiconductor pattern penetrates the second source conductive pattern.

18. The 3D semiconductor memory device according to claim 17, wherein: The second source conductive pattern extends on the buffer insulating layer.

19. The 3D semiconductor memory device according to claim 17, wherein: The first source conductive pattern and the second source conductive pattern include a semiconductor material.

20. The 3D semiconductor memory device according to claim 11, wherein The first source conductive pattern contacts sidewalls of the lower sacrificial pattern, the insulating layer, and the buffer insulating layer.

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