Method for improving data retention of floating gate type memory and product thereof

Abstract

The invention provides a method for improving data retention of a floating gate type memory and a product thereof. A polycrystalline silicon lattice structure is improved mainly through high-temperature annealing, and grain boundaries are reduced; the grain boundary defect density is reduced through hydrogen passivation; and by introducing a high-k interface layer, the interface quality is optimized. Through the synergistic effect of the methods, a polycrystalline silicon floating gate structure with fewer defects and higher charge storage capacity is finally formed, and the data retention performance of the floating gate type Flash memory is greatly improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of high-end storage devices, and in particular relates to a method for improving the data retention of a floating gate type memory and a product thereof. Background Art

[0002] High-end memory usually refers to storage devices used in mission-critical and high-performance computing environments, which have extremely high requirements for data integrity, reliability, speed and durability. Floating gate Flash memory has performed well in many applications, and with the continuous advancement of technology, its application in the high-end storage market is also increasing.

[0003] Floating gate Flash memory is widely used in various electronic devices due to its advantages such as non-volatility, high integration and low cost. However, with the increase of storage density and the reduction of device size, the data retention capability of floating gate Flash memory has become a key factor restricting its further development.

[0004] Data retention refers to the ability of a memory device to maintain its stored data without losing it when there is no power supply. This performance indicator is particularly important for high-end storage devices, as they are often used in critical applications that require long-term data retention, such as servers, data centers, and industrial control systems. In these applications, the reliability and stability of data are directly related to the safety and reliability of the system.

[0005] Improving the data retention capability of floating gate Flash memory is the key to ensure long-term reliable data storage. Among them, improving polysilicon floating gate materials is an important way to improve the data retention of floating gate Flash memory. The methods to improve the data retention of floating gate memory can be mainly divided into the following aspects: improving floating gate materials, optimizing device structure, controlling process conditions, improving environmental and operating conditions, charge storage management and error correction technology. Among them, optimizing the floating gate layer material is an important method to improve the data retention of memory. Specific improvement methods for polysilicon include increasing grain size, doping optimization, heat treatment optimization, stress engineering, interface layer optimization, composite polysilicon, surface oxide layer control, hydrogen passivation treatment, polysilicon alloying and amorphous silicon layer application. These methods can significantly improve the performance of floating gate Flash memory by improving the material properties, manufacturing process and interface quality of polysilicon, especially in extending data retention time and reducing charge leakage.

[0006] In summary, although there are currently many methods for improving the data retention capability of floating gate Flash memory, in the field of high-end memory, the demand for higher performance and longer-term stable data retention capability still remains a huge challenge. Therefore, developing new materials, structures and processes to further improve the data retention capability of floating gate Flash memory, especially in the application of high-end memory, has important practical significance and broad market prospects. Summary of the invention

[0007] The purpose of the present invention is to provide a method and product for improving the data retention of floating gate memory in view of the deficiencies in the prior art, mainly focusing on the problem of optimizing the floating gate material. Improving the lattice structure of polysilicon is an important way to improve its electrical properties and data retention capabilities.

[0008] In a first aspect, the present invention provides a floating gate memory with high data retention, comprising a substrate, a common source, two drains, a bottom dielectric layer, an erase gate, two floating gates, two select gates, two control gates, and two high dielectric constant layers; The common source and two drains are arranged at the upper end of the substrate, and the two drains are respectively located on both sides of the common source; The bottom dielectric layer is disposed on the upper end of the substrate; The erase gate, two floating gates, two control gates and two selection gates are arranged at the upper end of the bottom dielectric layer; the two selection gates are arranged on both sides of the erase gate respectively; a floating gate and a control gate are arranged between each selection gate and the erase gate, and the control gate is arranged above the floating gate; a high dielectric constant layer is arranged between the floating gate and the erase gate, and between the floating gate and the control gate; A dielectric layer is provided between the select gate and the control gate, the floating gate, and between the control gate and the erase gate; In a second aspect, the present invention provides a method for improving the data retention of a floating gate type memory, using a floating gate layer optimization method, specifically comprising the following steps: Step S1, providing a substrate, and then depositing a floating gate on the substrate.

[0009] Preferably, the floating gate layer is deposited by chemical vapor deposition (CVD) technology to form a smaller grain structure, wherein the deposition temperature of the chemical vapor deposition is 500-600° C. and the precursor gas is silane, SiH4.

[0010] Step S2, performing high temperature annealing treatment on the sample of step S1, thereby improving the polysilicon lattice structure and reducing grain boundaries.

[0011] Preferably, the annealing temperature of the high temperature annealing treatment is 900-1100°C and the duration is 25-35 minutes.

[0012] Step S3, performing hydrogen passivation treatment on the sample after the high temperature annealing treatment in step S2 to reduce the grain boundary defect density.

[0013] Preferably, the temperature of the hydrogen passivation treatment is 300-400° C., and the treatment time is 15-30 minutes.

[0014] Step S4: after the passivation treatment in step S3, a high dielectric constant material is deposited on the sample to optimize the interface layer.

[0015] Preferably, the high dielectric constant material is a high dielectric constant oxide, specifically hafnium oxide (HfO2) or zirconium oxide (ZrO2).

[0016] Preferably, the high dielectric constant material is deposited using atomic layer deposition (ALD) technology.

[0017] Preferably, the thickness of the high dielectric constant material layer is 2-3 nm.

[0018] The beneficial effects of the present invention are: The present invention optimizes the lattice structure of polysilicon by reducing grain boundaries through high-temperature annealing and reducing grain boundary defects through hydrogen passivation. An ultra-thin high-k dielectric material is introduced between the polysilicon floating gate and the tunnel oxide layer. The interface layer can reduce interface traps between the tunnel oxide layer and the polysilicon, further reduce charge traps, reduce leakage current, improve interface quality, and ultimately significantly extend data retention time and improve floating gate performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 Schematic diagram of the 1.5T memory structure with high data retention.

[0021] Figure 2 This is a floating gate layer optimization flow chart for improving data retention according to the present invention.

[0022] Markings in the figure: 1, substrate; 2, common source; 3, drain; 4, bottom dielectric layer; 5, floating gate; 6, high dielectric constant layer; 7, first ONO dielectric layer; 8, select gate; 9, erase gate; 10, second ONO dielectric layer; 11, control gate. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0024] like Figure 1 As shown, the 1.5T memory with high data retention provided by the embodiment of the present invention specifically includes a substrate 1, a common source 2, two drains 3, a bottom dielectric layer 4, an erase gate 9, two floating gates 5, two select gates 8, two control gates 11, and two high dielectric constant layers 6; The common source 2 and two drains 3 are arranged at the upper end of the substrate 1, and the two drains 3 are respectively located on both sides of the common source 2; The bottom dielectric layer 4 is arranged on the upper end of the substrate 1; The erase gate 9, two floating gates 5, two control gates 11, and two selection gates 8 are arranged at the upper end of the bottom dielectric layer 4; the two selection gates 8 are respectively arranged on both sides of the erase gate 9; a floating gate 5 and a control gate 11 are arranged between each selection gate 8 and the erase gate 9, and the control gate 11 is arranged above the floating gate 5; a high dielectric constant layer 6 is arranged between the floating gate 5 and the erase gate 9, and between the floating gate 5 and the control gate 11; A first ONO dielectric layer 7 is disposed between the select gate 8 , the control gate 11 and the floating gate 5 , and a second ONO dielectric layer 10 is disposed between the control gate 11 and the erase gate 9 .

[0025] Figure 2 The present invention is a flowchart of optimizing the floating gate layer for improving data retention; specifically: Step S1: Substrate pretreatment A 300 mm silicon wafer substrate 1 is provided.

[0026] Shallow trench isolation (STI) is built on substrate 1 by photolithography, etching and thin film deposition.

[0027] Subsequently, the select gate 8 (SG) oxide layer is grown after ion implantation, and the bottom oxide layer is formed by dry oxidation or in-situ steam generation (ISSG). After photolithography and etching, the SG polysilicon layer is deposited, and then phosphorus ion implantation is performed. Next, silicon oxide and silicon nitride are deposited, and then the silicon nitride spacer is etched. Then a silicon dioxide layer is deposited to form the SG-FG gap ONO isolation layer, that is, the first ONO dielectric layer 7, while establishing oxide isolation between the substrate and the floating gate 5 (FG), that is, the bottom dielectric layer 4.

[0028] Step S2: depositing polysilicon on the substrate.

[0029] In this embodiment, a polysilicon layer (ie, floating gate 5) is deposited using chemical vapor deposition (CVD) technology to form a smaller grain structure, wherein the deposition temperature of the chemical vapor deposition is 500-600° C., and the precursor gas is silane, SiH4.

[0030] The CVD process usually forms polysilicon thin films by chemically reacting gaseous precursors on the surface of the substrate. In the CVD process, polysilicon is formed by the decomposition and deposition of precursor gases (such as silane, SiH4) on the heated substrate surface. The deposition temperature determines the initial size and structure of the grains. At lower temperatures (500-600°C), the mobility of silicon atoms is low, resulting in the formation of small grains. Since these grains cannot grow when they are formed, a large number of grain boundaries are formed. Grain boundaries are formed when different grains meet during the growth process. The atomic arrangement in the grain boundary region is irregular, and there is a high stress and defect density. These grain boundaries are prone to become traps for charge capture, affecting electrical properties. Although this initial grain structure contains more grain boundaries, subsequent high-temperature annealing can promote the growth and rearrangement of these grains and reduce the grain boundary density.

[0031] Step S3, performing high temperature annealing treatment on the sample of step S2, thereby improving the polysilicon lattice structure and reducing grain boundaries.

[0032] The annealing temperature of the high temperature annealing treatment is 900-1100°C, and the duration is about 25-35 minutes, preferably 30 minutes. Too high a temperature may lead to excessive growth of silicon oxide, while too low a temperature cannot effectively promote grain growth. The length of the annealing time needs to be optimized according to the specific polysilicon thickness and grain size.

[0033] Grain boundaries are the main source of charge traps and leakage currents. Reducing grain boundaries can significantly reduce the resistance and defect density of materials. The atoms at the grain boundaries have higher energy due to their irregular positions. The present invention uses high-temperature annealing after polysilicon deposition to cause the atoms at the grain boundaries to rearrange, causing the small grains in the polysilicon to recrystallize and grow into larger grains, thereby reducing the number of grain boundaries. As the grains grow, the total area of ​​the grain boundaries decreases, so the grain boundary density decreases, resulting in a reduction in charge traps.

[0034] Step S4, performing hydrogen passivation treatment on the sample after the high temperature annealing treatment in step S3 to reduce the grain boundary defect density.

[0035] At the grain boundaries, the dangling bonds of polysilicon material form charge traps, resulting in unstable charge storage. Hydrogen passivation treatment introduces hydrogen atoms and uses them to bind to the dangling bonds at the polysilicon grain boundaries to passivate these defects, thereby reducing the defect density at the grain boundaries.

[0036] The temperature of the hydrogen passivation treatment is 300-400°C, and the treatment time is 15-30 minutes. Too high a temperature may lead to hydrogen desorption, while too low a temperature may not effectively passivate. The treatment time can be adjusted according to the material thickness and the passivation effect. The diffusion depth and distribution of hydrogen atoms in polysilicon are controlled by the hydrogen passivation treatment temperature and time, so that the hydrogen atoms are evenly distributed and stably exist, and the grain boundary defects are effectively passivated for a long time.

[0037] Step S5: After the passivation treatment in step S4, a high dielectric constant layer 6 (ie, high-k material) is deposited on the sample to optimize the interface layer.

[0038] The high dielectric constant layer 6 is made of a high dielectric constant oxide, specifically hafnium oxide (HfO 2 ) or zirconium oxide (ZrO 2 ).

[0039] The high dielectric constant layer 6 is deposited using atomic layer deposition (ALD) technology.

[0040] The thickness of the high dielectric constant material layer is 2-3 nm.

[0041] A layer of high-k material is introduced between the polysilicon floating gate and the tunnel oxide layer. The dielectric constant of high-k material is much higher than that of traditional silicon dioxide, which can more effectively reduce leakage current. The introduction of high-k material can reduce the tunnel effect without significantly increasing the thickness of the oxide layer, and can passivate the trap density at the interface and reduce charge loss.

[0042] The present invention precisely controls the thickness of the high dielectric constant layer 6 to be between 2-3 nm, thereby ensuring effective passivation without affecting the overall device performance.

[0043] Step S6, growing and etching a silicon nitride spacer on the device in step S5, followed by self-aligned etching and arsenic ion implantation to form a common source 2. Subsequently, an additional ONO layer (i.e., the second ONO dielectric layer 10) is deposited, and the control gate 11 (CG) polysilicon and phosphorus ion implantation. After that, an oxide layer (i.e., the second ONO dielectric layer 10) is grown for electrical isolation. Finally, the erase gate 9 is deposited by photolithography and etching. Subsequently, a lightly doped drain (LDD) structure is formed, the drain 3 is implanted, the spacer is formed, and the mid-line (MEOL) and back-end-of-line (BEOL) processes are completed.

[0044] The above methods have a synergistic effect: high temperature annealing reduces the number of grain boundaries in polysilicon, hydrogen passivation further reduces the defect density at the grain boundaries, and the high-k interface layer reduces the tunneling effect and charge traps at the interface. In summary, the electrical properties of the floating gate material can be greatly improved. Through such multiple optimization methods, a polysilicon floating gate structure with good lattice structure, low defect density and high interface quality is formed. This composite structure not only improves the charge storage capacity of the floating gate, but also extends the data retention time and enhances the reliability of the device. The optimized floating gate material needs to go through the standard semiconductor device packaging process, including metallization, wire bonding and packaging shell. After the packaging is completed, a series of performance tests can be carried out. The main performance tests include accelerated aging test (accelerated testing in high temperature and high humidity environment to evaluate the long-term reliability of the material), data retention test (measuring data retention time at different temperatures), charge retention test (measuring the charge storage of the floating gate), etc. These tests can verify the effectiveness and stability of the optimization method.

[0045] In summary, this method improves the polysilicon lattice structure through high-temperature annealing to reduce grain boundaries; reduces the grain boundary defect density through hydrogen passivation; and optimizes the interface quality through the introduction of a high-k interface layer. Ultimately, a polysilicon floating gate structure with fewer defects and higher charge storage capacity is formed, which greatly improves the data retention performance of floating gate Flash memory.

[0046] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A memory with high data retention, characterized in that: It comprises a substrate (1), a common source (2), two drains (3), a bottom dielectric layer (4), an erase gate (9), two floating gates (5), two selection gates (8), two control gates (11), and two high dielectric constant layers (6); Two selection gates (8) are respectively arranged on both sides of the erase gate (9); a floating gate (5) and a control gate (11) are arranged between each selection gate (8) and the erase gate (9); a high dielectric constant layer (6) is arranged between the floating gate (5) and the erase gate (9) and between the floating gate (5) and the control gate (11); A dielectric layer is provided between the selection gate (8) and the control gate (11), between the floating gate (5), and between the control gate (11) and the erase gate (9).

2. The memory according to claim 1, characterized in that: The common source (2) and two drains (3) are arranged at the upper end of the substrate (1), and the two drains (3) are respectively located on both sides of the common source (2).

3. The memory according to claim 1, characterized in that: The bottom dielectric layer (4) is arranged on the upper end of the substrate (1); the one erase gate (9), two floating gates (5), two control gates (11), and two selection gates (8) are arranged on the upper end of the bottom dielectric layer (4); and the control gate (11) is arranged above the floating gate (5).

4. The memory according to claim 1, characterized in that: The material of the high dielectric constant layer (6) is hafnium oxide or zirconium oxide.

5. The memory according to claim 1, characterized in that: The thickness of the high dielectric constant layer (6) is 2-3 nm.

6. A method for improving the data retention of the memory according to any one of claims 1 to 5, using a floating gate optimization method, characterized in that The specific steps include: Step S1, providing a substrate, and then depositing a floating gate (5) on the substrate; Step S2, performing high temperature annealing treatment on the sample of step S1, thereby improving the polysilicon lattice structure and reducing grain boundaries; Step S3, performing hydrogen passivation treatment on the sample after high temperature annealing treatment in step S2 to reduce the grain boundary defect density; Step S4: After the passivation treatment in step S3, a high dielectric constant layer (6) is deposited on the sample to optimize the interface layer.

7. The method according to claim 6, characterized in that: The floating gate (5) is deposited by using chemical vapor deposition technology to form a smaller grain structure, wherein the deposition temperature of the chemical vapor deposition is 500-600°C.

8. The method according to claim 6, characterized in that: The annealing temperature of the high temperature annealing treatment is 900-1100°C and the duration is 25-35 minutes.

9. The method according to claim 6, characterized in that: The temperature of the hydrogen passivation treatment is 300-400° C., and the treatment time is 15-30 minutes.

10. The method according to claim 6, characterized in that: The high dielectric constant layer (6) is deposited using atomic layer deposition technology.

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