A silicon carbide mos memory device and a method of fabricating the same

Abstract

A silicon carbide MOS memory device and a preparation method thereof belong to the field of semiconductor memory devices. The method comprises the following steps: a. organic and inorganic cleaning is performed on a silicon carbide epitaxial wafer; b. a SiO2 film is deposited on the SiC epitaxial wafer through chemical reaction, chemical vapor deposition and physical vapor deposition; c. an Al2O3 / AlN / AlON film is deposited on the SiO2 film (or directly on the SiC epitaxial wafer) through atomic layer deposition; d. argon annealing is performed on the gate medium generated through the above steps and cooling or no annealing; and e. a metal gate electrode and a back electrode are sputtered or evaporated on the gate medium layer to form a MOS device structure. By applying different positive voltages to the gate electrode, electrons are filled into traps in the gate medium layer according to the energy level distribution, and by applying a negative voltage to the gate electrode and applying ultraviolet light at the same time, hole recombination of the electrons in the gate medium is achieved to realize storage and release of a controllable amount of charges.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory devices, and in particular to a silicon carbide MOS memory device and its fabrication method. Background Technology

[0002] Traditional charge-trapping devices use a silicon-based cascaded-gate MOS structure, which is a semiconductor-oxide-nitride-metal structure. In this structure, programming is achieved by applying a forward bias voltage to the gate, where electrons emitted from the substrate to the gate are trapped by nitride traps. Erasure is achieved by applying a negative bias voltage to the gate, where holes tunnel into the nitride and neutralize the electrons. By utilizing these two processes to control the amount of charge in the gate dielectric, the threshold voltage of the transistor is controlled, thereby achieving the two states of "0" and "1".

[0003] In existing technologies, charge trapping devices are typically silicon-based; however, the properties of silicon materials change drastically at high temperatures. Due to silicon's narrow bandgap, more electron-hole pairs are generated at high temperatures, leading to charge leakage in silicon-based memory devices and resulting in data loss. Silicon carbide, as a third-generation semiconductor material, possesses characteristics such as a wide bandgap, high breakdown field strength, high thermal conductivity, and high saturated electron drift velocity. It also exhibits stable chemical properties, strong radiation resistance, and high mechanical strength. These characteristics make silicon carbide a promising candidate for applications in aerospace electronic devices. Summary of the Invention

[0004] The purpose of this invention is to address the aforementioned problems in the prior art by providing a silicon carbide MOS memory device and its fabrication method. This method involves introducing electron traps distributed according to energy levels into the gate oxide. Writing is achieved by filling these traps with electrons when a positive voltage is applied to the gate. Erasing is achieved by applying a negative voltage to the gate and simultaneously applying ultraviolet light to generate holes that enter the gate oxide and neutralize the electrons. Utilizing the superior material properties of silicon carbide, a more heat-resistant memory device can be fabricated. This achieves efficient charge storage and erasure, while simultaneously improving the high-temperature resistance and radiation resistance of the memory device by leveraging the excellent properties of silicon carbide.

[0005] To achieve the above-mentioned objectives, the present invention provides the following technical solutions.

[0006] The present invention provides a silicon carbide MOS memory device comprising an n-type silicon carbide substrate, and a gate dielectric film and a metal gate electrode sequentially grown on the n-type silicon carbide substrate; the gate dielectric film is composed of two or more films, including (1) SiO2 / Al2O3, AlN or AlON; or (2) Al2O3, AlN or AlON, to achieve effective gate control effect and charge storage.

[0007] The n-type silicon carbide substrate is specifically an n-type 4H-SiC substrate; the thickness of the n-type silicon carbide substrate ranges from 100 to 1000 μm, and the doping concentration ranges from 10. 17 ~10 19 cm -3 ;

[0008] The thickness of the SiO2 thin film ranges from 1 to 100 nm.

[0009] The thickness of the Al2O3 / AlN / AlON thin film ranges from 1 to 100 nm.

[0010] This invention provides one method for fabricating a silicon carbide MOS memory device, comprising the following steps:

[0011] a. Perform organic and inorganic cleaning on silicon carbide epitaxial wafers;

[0012] b. Depositing Al2O3 / AlN / AlON thin films on SiC epitaxial wafers via atomic layer deposition;

[0013] c. Anneal and cool the gate dielectric generated through the above steps, or do not anneal it;

[0014] d. Sputter or vapor deposit metal gate electrodes and back electrodes on the gate dielectric layer to form a MOS device structure.

[0015] This invention provides a second method for fabricating a silicon carbide MOS memory device, comprising the following steps:

[0016] a. Perform organic and inorganic cleaning on silicon carbide epitaxial wafers;

[0017] b. Depositing SiO2 thin films on SiC epitaxial wafers via chemical reactions, chemical vapor deposition, and physical vapor deposition;

[0018] c. Deposit Al2O3 / AlN / AlON thin films on SiO2 thin films via atomic layer deposition;

[0019] d. Anneal and cool the gate dielectric produced by the above steps, or do not anneal it;

[0020] e. Sputter or vapor deposit metal gate electrodes and back electrodes on the gate dielectric layer to form a MOS device structure.

[0021] The preferred substrate thickness ranges from 100 to 1000 μm, and the doping concentration ranges from 10. 17 ~10 19 cm -3 The thickness of the SiC epitaxial wafer ranges from 1 to 100 μm, and the doping concentration ranges from 10. 14 ~10 17 cm-3 .

[0022] The preferred thickness range of the generated SiO2 film is 1~100 nm.

[0023] The preferred parameters for atomic layer deposition of SiO2 thin films are: pressure of 0.1~0.3 torr, temperature of 100~500℃, carrier gas of Ar or N2, carrier gas flow rate of 50~500 sccm, pulse time of 0.1~5 s, and time interval of 1~180 s.

[0024] The preferred thickness range of the generated Al2O3 / AlN / AlON film is 1~100 nm.

[0025] The preferred parameters for atomic layer deposition of Al2O3 / AlN / AlON thin films are: pressure 0.1~0.3 torr, temperature 100~500℃, carrier gas Ar or N2, carrier gas flow rate 50~500 sccm, pulse time 0.1~5 s, and time interval 1~180 s.

[0026] In the preferred annealing and cooling process, argon is used for annealing, and the annealing temperature range is 600~1300℃.

[0027] Compared with the prior art, the beneficial effects achieved by the technical solution of this invention are:

[0028] 1. By applying the technical solution of this invention, writing can be accomplished by filling the trap with electrons when a positive voltage is applied to the gate, and erasure can be accomplished by applying a negative voltage to the gate and simultaneously applying ultraviolet light to generate holes that enter the gate oxide to neutralize electrons, thereby controlling the amount of charge in the gate dielectric.

[0029] 2. By applying the technical solution of this invention, due to the radiation resistance, high thermal conductivity, and wide bandgap of silicon carbide material, the prepared memory has better temperature stability and better radiation resistance. Attached Figure Description

[0030] Figure 1 This is a flowchart illustrating the growth process of SiO2 and Al2O3 / AlN / AlON stacked thin films and the fabrication process of MOS devices using Al2O3 / AlN / AlON gate dielectric layers.

[0031] Figure 2 This diagram illustrates the fabrication process of two MOS devices: SiO2 and Al2O3 / AlN / AlON stacks and Al2O3 / AlN / AlON.

[0032] Figure 3 The image shows the hysteresis curve of the CV characteristic of the device in an embodiment of the present invention when the maximum voltage is applied incrementally.

[0033] Figure 4 The hysteresis curves of the CV characteristic after applying a reverse bias voltage for 180 s while adding light, and the hysteresis curves of the CV characteristic after repeatedly applying an increasing maximum voltage.

[0034] Figure 5 As a comparative example of the present invention, the CV curves of a silicon-based MOS device at different temperatures are shown.

[0035] Figure 6 As an embodiment of the present invention, the CV curves of a silicon carbide MOS device at different temperatures are shown. Detailed Implementation

[0036] To make the technical problems, technical solutions and beneficial effects of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0037] Figure 1 This is a flowchart illustrating the growth process of SiO2 and Al2O3 / AlN / AlON stacked thin films and the fabrication process of MOS devices using Al2O3 / AlN / AlON gate dielectric layers. Figure 2 This is a schematic diagram illustrating the fabrication process of two types of MOS devices: SiO2 and Al2O3 / AlN / AlON stacks and Al2O3 / AlN / AlON.

[0038] The following is for reference Figure 1 and Figure 2 In detail, the present invention includes the following steps:

[0039] (1) Cleaning silicon carbide epitaxial wafers

[0040] a. Clean with acetone and ethanol at least once in sequence using ultrasonic cleaning, then rinse with deionized water.

[0041] b. Immerse the rinsed epitaxial wafer in hydrofluoric acid for at least 1 minute.

[0042] c. Place the epitaxial sheet soaked in hydrofluoric acid into solution No. 3 and boil for at least 20 minutes. Solution No. 3 is a mixture of concentrated sulfuric acid and hydrogen peroxide, with a volume ratio of 1:3.

[0043] d. Boil the epitaxial wafers that have been boiled in solution No. 3 in solutions No. 1 and No. 2 for at least 10 minutes each, then rinse them thoroughly with deionized water and dry them with nitrogen gas. Solution No. 1 is a mixture of ammonia, hydrogen peroxide, and deionized water in a volume ratio of 1:2:5. Solution No. 2 is a mixture of hydrochloric acid, hydrogen peroxide, and deionized water in a volume ratio of 1:2:5.

[0044] (2) SiO2 film 2 is grown on the cleaned SiC epitaxial wafer 1 by atomic layer deposition. The thickness of the SiO2 film ranges from 1 to 100 nm, and the process temperature range of atomic layer deposition of SiO2 film is 100 to 500 °C.

[0045] Alternatively, this step can be skipped, and the following step (3) can be performed directly, that is, without depositing SiO2 film, Al2O3 / AlN / AlON film can be deposited directly on SiC epitaxial wafer 1.

[0046] (3) An Al2O3 / AlN / AlON thin film is deposited on the SiO2 thin film 2 by atomic layer deposition (or directly on the silicon carbide epitaxial wafer 1). The thickness of the Al2O3 / AlN / AlON thin film ranges from 1 to 100 nm, and the process temperature ranges from 100 to 500 °C.

[0047] (4) Anneal the two gate dielectric layers and then cool them. The annealing gas is Ar and the annealing temperature is 600~1300℃.

[0048] (5) A MOS device structure is formed by sputtering or evaporating metal electrodes 4 on the two gate dielectric layers and the back of the epitaxial wafer.

[0049] Example 1

[0050] a. Clean the tube three times with acetone and ethanol in sequence using ultrasonic cleaning, and then rinse with deionized water.

[0051] b. Immerse the rinsed epitaxial wafer in diluted hydrofluoric acid (volume ratio HF:deionized water = 1:20) for 10 min.

[0052] c. Place the epitaxial wafer soaked in hydrofluoric acid into solution No. 3 and boil for 20 minutes. Solution No. 3 is a mixture of concentrated sulfuric acid and hydrogen peroxide, with a volume ratio of 1:3.

[0053] d. Boil the epitaxial wafers that have been boiled in solution 3 in sequence with solutions 1 and 2 for at least 10 minutes each, then rinse them thoroughly with deionized water and dry them with nitrogen. Solution 1 is a mixture of ammonia, hydrogen peroxide, and deionized water, with a volume ratio of 1:2:5. Solution 2 is a mixture of hydrochloric acid, hydrogen peroxide, and deionized water, with a volume ratio of 1:2:5.

[0054] Next, an atomic layer deposition method was used to grow a SiO2 film on the cleaned SiC epitaxial wafer, and the thickness of the grown SiO2 film was 5 nm.

[0055] Then, an Al2O3 film with a thickness of 30 nm was grown on the SiO2 film using atomic layer deposition.

[0056] Finally, metal electrodes are sputtered or evaporated onto the SiO2 / Al2O3 gate dielectric layer and the back side to form a MOS structure.

[0057] Example 2

[0058] a. Clean the tube three times with acetone and ethanol in sequence using ultrasonic cleaning, and then rinse with deionized water.

[0059] b. Immerse the rinsed epitaxial wafer in diluted hydrofluoric acid (volume ratio HF:deionized water = 1:20) for 10 min.

[0060] c. Place the epitaxial wafer soaked in hydrofluoric acid into solution No. 3 and boil for 20 minutes. Solution No. 3 is a mixture of concentrated sulfuric acid and hydrogen peroxide, with a volume ratio of 1:3.

[0061] d. Boil the epitaxial wafers that have been boiled in solution 3 in sequence with solutions 1 and 2 for at least 10 minutes each, then rinse them thoroughly with deionized water and dry them with nitrogen. Solution 1 is a mixture of ammonia, hydrogen peroxide, and deionized water, with a volume ratio of 1:2:5. Solution 2 is a mixture of hydrochloric acid, hydrogen peroxide, and deionized water, with a volume ratio of 1:2:5.

[0062] Then, an Al2O3 film with a thickness of 30 nm was grown on the SiO2 film using atomic layer deposition.

[0063] Finally, metal electrodes are sputtered or evaporated onto the SiO2 / Al2O3 gate dielectric layer and the back side to form a MOS structure.

[0064] The present invention performs capacitance-voltage characteristic tests on the silicon carbide MOS memory device of Example 2. The test frequency is 1MHz and the AC voltage signal amplitude is 50mV; the test results are as follows. Figure 3 and 4 As shown; first, the minimum test voltage is fixed at -10 V, and the maximum voltage is increased by 2 V each time from 8 V to 16 V, and the scan is performed sequentially. Each time the capacitance is measured, the scan proceeds from the minimum measurement voltage to the maximum voltage, and then from the maximum voltage back to the minimum voltage; the results are as follows. Figure 3 As shown, the CV hysteresis curve shifted to the right with the maximum test voltage, indicating the presence of electron traps within the gate dielectric. As the maximum test voltage increased, more electrons were trapped, completing the information processing. Next, the device was illuminated with a xenon lamp through an optical fiber while a -10 V bias voltage was applied and maintained for 180 seconds. A voltage scan from -10 V to 5 V was then performed. Afterward, the light source was turned off, and the measurement was repeated with the minimum voltage at -10 V and the maximum voltage increasing by 2 V each time from 8 V to 16 V. The results are shown below. Figure 4As shown, it was found that after the light was applied, the curve shifted back to the initial state, and the phenomenon of the hysteresis curve shifting to the right as the maximum voltage increased could be repeated. This indicates that the holes entered the gate oxide and neutralized the electrons, thus completing the erasure of information.

[0065] Figure 5 For comparison, the CV characteristic curves of silicon-based MOS devices at different temperatures are shown. Figure 6 As an example, the CV characteristic curves of silicon carbide at different temperatures are shown. The CV characteristics of silicon are not stable at high temperatures. However, the present invention uses wide-bandgap semiconductor n-type silicon carbide as a substrate, which makes it difficult for holes to be excited at high temperatures, and the CV characteristics remain unchanged, greatly increasing the high-temperature stability of the device.

[0066] Example 3

[0067] Similar to Example 1, the difference lies in the following: a 50 nm thick SiO2 thin film is deposited on the cleaned silicon carbide epitaxial wafer using atomic layer deposition (ALD); the deposition temperature is 300 °C to ensure film quality and uniformity; a 20 nm thick Al2O3 thin film is deposited on the SiO2 thin film using ALD; the deposition temperature is 200 °C to maintain film density and stability; the deposited SiO2 and Al2O3 gate dielectric layers are annealed using Ar as the annealing gas at 900 °C; after annealing, the layers are allowed to cool naturally to room temperature; metal electrodes are sputtered onto the gate dielectric layer and the back side of the silicon carbide epitaxial wafer to form a MOS device structure.

[0068] Example 4

[0069] Similar to Example 2, the difference is that: an Al2O3 thin film with a thickness of 75 nm is deposited on the cleaned silicon carbide epitaxial wafer using atomic layer deposition technology; the deposition temperature is 400℃ to obtain good film quality and performance; the deposited Al2O3 gate dielectric layer is annealed with Ar as the annealing gas at a temperature of 1100℃; after annealing, it is naturally cooled to room temperature; metal electrodes are sputtered on the gate dielectric layer and the back of the silicon carbide epitaxial wafer to form a MOS device structure.

[0070] Example 5

[0071] The cleaning process is the same as in Example 1. The difference is that: a 25 nm thick SiO2 film is deposited on the cleaned silicon carbide epitaxial wafer using atomic layer deposition (ALD) at a temperature of 250 °C; a 50 nm thick AlN film is deposited on the SiO2 film using ALD at a temperature of 350 °C; the deposited SiO2 and AlN gate dielectric layers are annealed using Ar as the annealing gas at a temperature of 800 °C; after annealing, the layers are allowed to cool naturally to room temperature; metal electrodes are sputtered onto the gate dielectric layer and the back of the silicon carbide epitaxial wafer to form a MOS device structure.

[0072] Example 6

[0073] The cleaning process is the same as in Example 1. The difference is that: instead of depositing a SiO2 film, an AlON film is deposited directly; a 60nm thick AlON film is deposited on the cleaned silicon carbide epitaxial wafer using atomic layer deposition technology; the deposition temperature is 450℃; the deposited AlON gate dielectric layer is annealed using Ar gas at a temperature of 1000℃; after annealing, it is allowed to cool naturally to room temperature; metal electrodes are sputtered onto the gate dielectric layer and the back of the silicon carbide epitaxial wafer to form a MOS device structure.

[0074] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a silicon carbide MOS memory device, characterized in that, Includes the following steps: a. Organic and inorganic cleaning of the silicon carbide epitaxial wafer; the silicon carbide epitaxial wafer substrate thickness is 100~1000 μm, and the substrate doping concentration is 10. 17 ~10 19 cm -3 Epitaxial layer thickness 1~100 μm, epitaxial layer doping concentration 10 14 ~10 17 cm -3 ; b. Deposit 1-100 nm SiO2 thin films on SiC epitaxial wafers via chemical reaction, CVD, or PVD at deposition temperatures of 100-1000℃; c. Deposit 1-100 nm Al2O3 / AlN / AlON thin films on SiO2 films by atomic layer deposition (ALD); the ALD process is performed at a pressure of 0.1-0.3 torr, a temperature of 100-400 ℃, a carrier gas of Ar / N2 with a flow rate of 50-500 sccm, a pulse duration of 0.1-5 s, and an interval of 1-180 s. d. Anneal the SiO2 / Al2O3 / AlN / AlON stacked dielectric layer with argon gas at 600~1300℃ and then cool it, or do not anneal it; e. Sputter / evaporate metal gate electrodes and back electrodes onto the gate dielectric layer to form a MOS device; The device utilizes the wide bandgap characteristics of SiC and the hierarchical controllable charge traps formed by ALD annealing within the gate dielectric to achieve storage and erasure through the following photovoltage coordinated operation: Programming operation: Apply a positive voltage to the gate electrode, inject and trap electrons in the gate dielectric hierarchical trap energy level, and regulate the device threshold voltage to store charge; Erasure operation: A negative voltage is applied to the gate electrode simultaneously with ultraviolet light irradiation. The ultraviolet light excites high-density holes in the SiC substrate, and the negative voltage drives the holes to tunnel into the gate dielectric and recombine with the trapped electrons. The synergistic erasure mechanism, which applies negative gate voltage and ultraviolet light simultaneously, suppresses intrinsic thermally excited carriers in SiC at high temperatures and prevents high-temperature charge leakage and loss.

2. The method for fabricating a silicon carbide MOS memory device according to claim 1, characterized in that, The SiO2 thin film deposition process in step b is omitted, and a 1~100 nm Al2O3 / AlN / AlON thin film is directly deposited on the cleaned silicon carbide epitaxial wafer via atomic layer deposition; the ALD process is performed at a pressure of 0.1~0.3 torr, a temperature of 100~500 ℃, a carrier gas of Ar / N2 with a flow rate of 50~500 sccm, a pulse duration of 0.1~5 s, and an interval of 1~180 s; the gate dielectric layer is annealed in argon at 600~1300 ℃ and then cooled or not annealed.

3. A silicon carbide MOS memory device, manufactured by the method of claim 1 or 2, characterized in that: It includes an n-type 4H-SiC substrate, a gate dielectric layer disposed on the substrate, a metal gate electrode, and a back electrode; The gate dielectric is a single-layer Al2O3 / AlN / AlON thin film, or a composite stack of SiO2 and Al2O3 / AlN / AlON. The gate dielectric is subjected to ALD deposition with limited parameters and argon annealing at 600~1300 °C to generate a graded and controllable density of charge trap energy levels inside. The device employs a negative gate voltage + ultraviolet light synchronous collaborative erasure mechanism, utilizing the wide bandgap of SiC to suppress high-temperature thermally excited carriers, maintaining good capacitance-voltage characteristics at 600 K, and is suitable for extreme high-temperature storage applications.

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