A method for manufacturing MOS capacitor based on SONOS process

Abstract

The present invention provides a method for manufacturing a MOS capacitor based on a SONOS process, providing a semiconductor structure, the semiconductor structure including a SONOS cell region, a MOS capacitor region and other device regions; forming a gate oxide layer on the semiconductor structure, the gate oxide layer covering the SONOS cell region, the MOS capacitor region and other device regions; removing the gate oxide layer on the SONOS cell region and the MOS capacitor region; forming an ONO film layer on the gate oxide layer on other device regions and the SONOS cell region and the MOS capacitor region; etching and removing the ONO film layer on other device regions, and retaining the ONO film layer on the SONOS cell region and the MOS capacitor region. The method of the present invention allows the MOS capacitor region to retain the ONO film layer, performs a write operation on the SONOS capacitor based on demand to increase the threshold voltage of the MOS capacitor itself, reduces the working voltage of the capacitor in the accumulation region, and greatly improves the withstand voltage characteristics of the MOS capacitor; by performing an erasing operation on the SONOS, the threshold voltage of the NMOS capacitor is changed to a negative value, so that the NMOS capacitor can work in a strong inversion region, and the upper and lower plate voltages can be transformed at the same time.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a MOS capacitor based on a SONOS process. Background Art

[0002] At present, the commonly used MOS capacitors have a rapidly decreasing capacitance when operating in the subthreshold region, and a distinct concave area is shown in the capacitance CV curve (the reason for the concave area in the capacitance CV curve of the NMOS tube is that when the gate voltage of the MOS tube rises, the holes are gradually repelled, a depletion layer begins to form, and the NMOS tube enters weak inversion. At this time, the NMOS is equivalent to two capacitors, the gate oxide layer and the depletion layer, in series, and the capacitance decreases. As the depletion layer increases, the total capacitance value continues to decrease).

[0003] Due to the existence of the capacitor depression area, MOS capacitors generally work in the accumulation area, so the voltage of the upper and lower plates of the capacitor cannot be changed. If it is necessary to work in the strong reflection area, in order to avoid the depression area, the capacitor working voltage needs to be far away from the medium reflection area. The MOS capacitor insulation medium uses a thinner gate oxide, resulting in poor voltage resistance characteristics of the MOS capacitor.

[0004] Therefore, a new method needs to be proposed to solve the above problems. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a MOS capacitor manufacturing method based on the SONOS process, which is used to solve the problems in the prior art that the voltage of the upper and lower plates of the capacitor cannot be converted and the MOS capacitor has poor voltage resistance.

[0006] To achieve the above-mentioned and other related purposes, the present invention provides a method for manufacturing a MOS capacitor based on a SONOS process, which at least comprises:

[0007] Step 1: providing a semiconductor structure, wherein the semiconductor structure includes a SONOS cell region, a MOS capacitor region and other device regions;

[0008] Step 2: forming a gate oxide layer on the semiconductor structure, wherein the gate oxide layer covers the SONOS cell area, the MOS capacitor area and other device areas;

[0009] Step 3: removing the gate oxide layer on the SONOS cell area and the MOS capacitor area;

[0010] Step 4: forming an ONO film layer on the gate oxide layer on the other device regions and on the SONOS cell region and the MOS capacitor region;

[0011] Step 5: etching and removing the ONO film layer on the other device regions, and retaining the ONO film layer on the SONOS unit region and the MOS capacitor region.

[0012] Preferably, the semiconductor structure in step one comprises: a substrate; an N-type deep well located on the substrate; the N-type deep well is located in the SONOS unit area; a tunneling oxide layer is provided on the N-type deep well; the ONO film layer is formed on the tunneling oxide layer; one side of the tunneling oxide layer is the other device area; the other device area includes a Core device area and an IO device area.

[0013] Preferably, the Core device area in step 1 includes an N-type Core device area and a P-type Core device area; and the IO device area includes an N-type IO device area and a P-type IO device area.

[0014] Preferably, the N-type Core device area in step one includes the P-well of the Core device located on the substrate; the P-type Core device area includes the N-well of the Core device located on the substrate; the N-type IO device area includes the P-well of the IO device located on the substrate; the P-type IO device area includes the N-well of the IO device located on the substrate; the N-type Core device area, the P-type Core device area, the N-type IO device area, and the P-type IO device area are isolated from each other by STI.

[0015] Preferably, the MOS capacitor region in step one also includes an N-type capacitor region and a P-type capacitor region; wherein the N-type capacitor region includes a P-well located on the substrate; the P-type capacitor region includes an N-well located on one side of the P-well on the substrate; the P-well and the N-well are isolated by STI; and the ONO film layer is formed on the P-well and the N-well.

[0016] Preferably, the ONO film layer on the SONOS cell area in step five includes a first ONO film layer located on the tunnel oxide layer and a second ONO film layer located on the first ONO film layer.

[0017] Preferably, the method for etching and removing the ONO film layer on the other device area in step five includes: forming an anti-reflective coating on the ONO film layer; forming a layer of photoresist on the anti-reflective coating; then photolithography to form a photoresist pattern, and then etching the ONO film layer using the photoresist pattern to remove the ONO film layer located on the other device area.

[0018] Preferably, the ONO film layer formed on the MOS capacitor region in step 4 is used to increase the threshold voltage of the MOS capacitor when performing a write operation on the SONOS capacitor, and to reduce the operating voltage of the MOS capacitor in the accumulation region, thereby improving the voltage resistance of the MOS capacitor.

[0019] Preferably, when the ONO film layer formed on the MOS capacitor region in step 4 is used to erase the SONOS capacitor, the threshold voltage of the NMOS capacitor is changed to a negative value, so that the NMOS capacitor works in a strong inversion region, and the voltages of the upper and lower plates can be changed.

[0020] As described above, the MOS capacitor manufacturing method based on the SONOS process of the present invention has the following beneficial effects: the method of the present invention allows the MOS capacitor area to retain the ONO film layer, and performs a write operation on the SONOS capacitor based on demand to increase the threshold voltage of the MOS capacitor itself, reduce the working voltage of the capacitor in the accumulation area, and greatly improve the withstand voltage characteristics of the MOS capacitor; by performing an erasing operation on the SONOS, the threshold voltage of the NMOS capacitor is changed to a negative value, so that the NMOS capacitor can work in the strong inversion area, and the upper and lower board voltages can be transformed at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Shown is a schematic diagram of the structure of a SONOS unit and a MOS capacitor of the present invention;

[0022] Figure 2 It shows a schematic diagram of the working voltage of the NMOS during the writing operation in the present invention;

[0023] Figure 3 It shows a schematic diagram of the working voltage of the NMOS during the erasing operation in the present invention;

[0024] Figure 4 It is a flow chart of the MOS capacitor manufacturing method based on the SONOS process of the present invention. DETAILED DESCRIPTION

[0025] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] See also Figures 1 to 4 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0027] The present invention provides a method for manufacturing a MOS capacitor based on a SONOS process, such as Figure 4 As shown, Figure 4 The flowchart of the MOS capacitor manufacturing method based on the SONOS process of the present invention is shown, and the method at least includes the following steps:

[0028] Step 1: providing a semiconductor structure, wherein the semiconductor structure includes a SONOS cell region, a MOS capacitor region and other device regions;

[0029] The present invention further comprises: a substrate; an N-type deep well located on the substrate; the N-type deep well is located in the SONOS unit area; a tunneling oxide layer is provided on the N-type deep well; the ONO film layer is formed on the tunneling oxide layer; one side of the tunneling oxide layer is the other device area; the other device area includes a Core device area and an IO device area.

[0030] like Figure 1 As shown, Figure 1 The structure diagram of the SONOS unit and MOS capacitor of the present invention is shown. The semiconductor structure in step 1 includes: a substrate 01; an N-type deep well 02 located on the substrate 01; the N-type deep well 02 is located in the SONOS unit area; a tunneling oxide layer 14 is provided on the N-type deep well 02; the ONO film layer is formed on the tunneling oxide layer 14, and in this embodiment, the ONO film layer located on the tunneling oxide layer 14 includes a first ONO film layer 10 and a second ONO film layer 11 located on the first ONO film layer 10; one side of the tunneling oxide layer 14 is the other device area; the other device area includes a Core device area and an IO device area.

[0031] Furthermore, in the present invention, the Core device area in step 1 of this embodiment includes an N-type Core device area and a P-type Core device area; and the IO device area includes an N-type IO device area and a P-type IO device area.

[0032] The present invention further comprises that the N-type Core device region in step 1 of this embodiment includes a P-well 03 of a Core device located on the substrate 01; the P-type Core device region includes an N-well 04 of a Core device located on the substrate; the N-type IO device region includes a P-well 05 of an IO device located on the substrate; the P-type IO device region includes an N-well 06 of an IO device located on the substrate; and the N-type Core device region, the P-type Core device region, the N-type IO device region, and the P-type IO device region are isolated from each other by STI.

[0033] The present invention further comprises that the MOS capacitor region in step 1 of this embodiment further comprises an N-type capacitor region and a P-type capacitor region; wherein the N-type capacitor region comprises a P-well 07 located on the substrate 01; the P-type capacitor region comprises an N-well 08 located on one side of the P-well 07 on the substrate 01; the P-well 07 and the N-well 08 are isolated by STI; and the ONO film layer is formed on the P-well 07 and the N-well 08.

[0034] Step 2: forming a gate oxide layer on the semiconductor structure, wherein the gate oxide layer covers the SONOS cell area, the MOS capacitor area and other device areas; In step 2, a gate oxide layer 09 is formed on the semiconductor structure, wherein the gate oxide layer 09 covers the SONOS cell area, the MOS capacitor area and other device areas.

[0035] Step 3: removing the gate oxide layer on the SONOS cell area and the MOS capacitor area; Figure 1 As shown, in step three, the gate oxide layer 09 on the SONOS cell area and the MOS capacitor area is removed, leaving only the gate oxide layer 09 on the other device areas.

[0036] Step 4: forming an ONO film layer on the gate oxide layer on the other device regions and on the SONOS cell region and the MOS capacitor region;

[0037] Step 5: etching and removing the ONO film layer on the other device regions, and retaining the ONO film layer on the SONOS unit region and the MOS capacitor region.

[0038] In the present invention, further, the ONO film layer on the SONOS cell area in step five of this embodiment includes a first ONO film layer 10 located on the tunnel oxide layer and a second ONO film layer 11 located on the first ONO film layer 10 .

[0039] The present invention further comprises the following steps: forming an anti-reflective coating on the ONO film layer; forming a layer of photoresist on the anti-reflective coating; then performing photolithography to form a photoresist pattern 13, and at the same time forming an anti-reflective coating pattern 12 in the present embodiment; and then etching the ONO film layer using the photoresist pattern 13 (and using the anti-reflective coating pattern 12 in the present embodiment) to remove the ONO film layer located on the other device region.

[0040] The present invention further comprises that the ONO film layer formed on the MOS capacitor region in step 4 of this embodiment is used to increase the threshold voltage of the MOS capacitor when performing a write operation on the SONOS capacitor, and to reduce the operating voltage of the MOS capacitor in the accumulation region, thereby improving the voltage resistance of the MOS capacitor.

[0041] The present invention further provides that when the ONO film layer formed on the MOS capacitor region in step 4 of this embodiment is used to perform an erasing operation on the SONOS capacitor, the threshold voltage of the NMOS capacitor is changed to a negative value, so that the NMOS capacitor operates in a strong inversion region, and the voltages of the upper and lower plates can be transformed.

[0042] The reason for the concave area of ​​the NMOS tube capacitance CV curve is that when the MOS tube gate voltage rises, the holes are gradually repelled, and a depletion layer begins to form, and the NMOS tube enters weak inversion. At this time, the NMOS is equivalent to two capacitors, the gate oxide layer and the depletion layer, connected in series, and the capacitance decreases. As the depletion layer increases, the total capacitance continues to decrease.

[0043] Therefore, the present invention retains the ONO film layer in the MOS capacitor region, and performs writing or erasing operations on the SONOS capacitor based on needs during use, so that the capacitor reaches the required VT.

[0044] like Figure 2 As shown, Figure 2 The figure shows the working voltage diagram of the NMOS writing operation in the present invention. By writing to the SONOS, the Vt of the MOS capacitor itself is increased, and the working voltage of the capacitor in the accumulation region is reduced (away from the capacitor depression in the depletion region), which greatly improves the withstand voltage characteristics of the MOS capacitor.

[0045] like Figure 3 As shown, Figure 3 The schematic diagram of the working voltage of the NMOS during the erasing operation in the present invention is shown. By performing an erasing operation on the SONOS, the NMOS capacitor Vt is changed to a negative value, so that the NMOS capacitor can work in a strong anti-region, and the upper and lower plate voltages can be transformed at the same time.

[0046] In summary, the method of the present invention allows the MOS capacitor area to retain the ONO film layer, performs a write operation on the SONOS capacitor based on demand to increase the threshold voltage of the MOS capacitor itself, reduces the working voltage of the capacitor in the accumulation area, and greatly improves the withstand voltage characteristics of the MOS capacitor; by performing an erase operation on the SONOS to change the threshold voltage of the NMOS capacitor to a negative value, the NMOS capacitor can work in the strong inversion area, and the upper and lower board voltages can be transformed. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0047] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a MOS capacitor based on a SONOS process, characterized in that: At least: Step 1: providing a semiconductor structure, wherein the semiconductor structure includes a SONOS cell region, a MOS capacitor region and other device regions; Step 2: forming a gate oxide layer on the semiconductor structure, wherein the gate oxide layer covers the SONOS cell area, the MOS capacitor area and other device areas; Step 3: removing the gate oxide layer on the SONOS cell area and the MOS capacitor area; Step 4: forming an ONO film layer on the gate oxide layer on the other device regions and on the SONOS cell region and the MOS capacitor region; Step 5: etching and removing the ONO film layer on the other device regions, and retaining the ONO film layer on the SONOS unit region and the MOS capacitor region.

2. The method for manufacturing a MOS capacitor based on the SONOS process according to claim 1, characterized in that: The semiconductor structure in step 1 includes: a substrate; an N-type deep well located on the substrate; the N-type deep well is located in the SONOS unit area; a tunneling oxide layer is provided on the N-type deep well; the ONO film layer is formed on the tunneling oxide layer; one side of the tunneling oxide layer is the other device area; the other device area includes a Core device area and an IO device area.

3. The method for manufacturing a MOS capacitor based on the SONOS process according to claim 2, characterized in that: The Core device area in step 1 includes an N-type Core device area and a P-type Core device area; the IO device area includes an N-type IO device area and a P-type IO device area.

4. The method for manufacturing a MOS capacitor based on the SONOS process according to claim 3, characterized in that: The N-type Core device area in step one includes the P-well of the Core device located on the substrate; the P-type Core device area includes the N-well of the Core device located on the substrate; the N-type IO device area includes the P-well of the IO device located on the substrate; the P-type IO device area includes the N-well of the IO device located on the substrate; the N-type Core device area, the P-type Core device area, the N-type IO device area, and the P-type IO device area are isolated from each other by STI.

5. The method for manufacturing a MOS capacitor based on the SONOS process according to claim 1, characterized in that: The MOS capacitor region in step one also includes an N-type capacitor region and a P-type capacitor region; wherein the N-type capacitor region includes a P-well located on the substrate; the P-type capacitor region includes an N-well located on one side of the P-well on the substrate; the P-well and the N-well are isolated by STI; and the ONO film layer is formed on the P-well and the N-well.

6. The method for manufacturing a MOS capacitor based on the SONOS process according to claim 2, characterized in that: In step five, the ONO film layer on the SONOS cell area includes a first ONO film layer located on the tunnel oxide layer and a second ONO film layer located on the first ONO film layer.

7. The method for manufacturing a MOS capacitor based on the SONOS process according to claim 1, characterized in that: The method for etching and removing the ONO film layer on the other device area in step 5 includes: forming an anti-reflective coating on the ONO film layer; forming a layer of photoresist on the anti-reflective coating; then photolithography to form a photoresist pattern, and then etching the ONO film layer using the photoresist pattern to remove the ONO film layer located on the other device area.

8. The method for manufacturing a MOS capacitor based on the SONOS process according to claim 1, characterized in that: The ONO film layer formed on the MOS capacitor region in step 4 is used to increase the threshold voltage of the MOS capacitor when performing a write operation on the SONOS capacitor, and to reduce the working voltage of the MOS capacitor in the accumulation region, thereby improving the voltage resistance of the MOS capacitor.

9. The method for manufacturing a MOS capacitor based on the SONOS process according to claim 1, characterized in that: When the ONO film layer formed on the MOS capacitor region in step 4 is used to erase the SONOS capacitor, the threshold voltage of the NMOS capacitor is changed to a negative value, so that the NMOS capacitor works in the strong inversion region, and the voltages of the upper and lower plates can be changed.

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