A method for forming a capacitor structure and a capacitor structure

Abstract

The present invention discloses a method for forming a capacitor structure and a capacitor structure, wherein the method for forming the capacitor structure includes providing a semiconductor substrate, forming a groove in the semiconductor substrate, and forming a metal element layer on the inner wall of the groove and the surface of the semiconductor substrate. The metal element layer located on the inner wall of the groove and the surface of the semiconductor substrate is processed to convert the metal element layer into a first metal compound layer, and the first metal compound layer is processed to convert the first metal compound layer into a second metal compound layer, and the second metal compound layer is formed as a lower plate conductive layer. As a result, the lower plate conductive layer formed by the present invention has uniform material distribution and low resistance, and the capacitor structure formed subsequently has stable charging and discharging under high frequency conditions, and a relatively good capacitance coefficient, and the performance of the silicon capacitor formed is also greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a method for forming a capacitor structure and a capacitor structure. Background Art

[0002] Deep trench capacitors are ideal for high-frequency circuits and high energy density storage due to their high energy density, superior high-frequency performance, low ESR (Equivalent Series Resistance) and high reliability. The core advantage of deep trench capacitors is that they increase energy storage capacity by increasing the surface area of ​​the electrode while reducing internal resistance and energy loss. However, in the manufacturing process of deep trench capacitors, deep etching technology, dielectric material selection, filling, and lower plate injection are the main process difficulties in achieving the above advantages. Among the various solutions to improve deep trench capacitors, the above advantages are generally achieved by increasing the trench depth, but the larger aspect ratio poses great challenges to the regulation of the ESR and capacitance of the capacitor.

[0003] Due to the large aspect ratio, it is difficult to form a lower plate with uniform resistance through ion implantation, which in turn affects device performance. For example, the prior art generally uses angled, multiple, high-dose implantation to achieve ion implantation of trenches with a large aspect ratio. This method has the following disadvantages:

[0004] 1) When using an angled method for ion implantation, on the one hand, in order to ensure effective use of the chip planning area, the deep trenches are placed randomly, and the injection angle selection is more difficult; on the other hand, when ion implantation is performed on the inner wall of the deep trench, it is difficult to control the angle of ion implantation so that the ion implantation at each position is the same, which in turn affects the uniformity of the injection of the deep trench sidewalls.

[0005] 2) Choosing the method of multiple large-dose injections is also prone to the risk of outgassing during the subsequent trap pushing process, and the leaked gas will contaminate the machine or the products in the same tube.

[0006] In addition, after ion implantation, the diffusion of ions will cause Gaussian distribution of impurities, and the impurity concentration will be uneven along the implantation direction, which will also affect the resistance uniformity of the subsequent lower plate structure, thereby affecting the electrical performance of the silicon capacitor. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for forming a capacitor structure and a capacitor structure to form a lower plate structure with uniform resistance and improve device performance.

[0008] In order to achieve the above-mentioned object and other related objects, the present invention provides a method for forming a capacitor structure, comprising:

[0009] Providing a semiconductor substrate;

[0010] forming a trench in a semiconductor substrate;

[0011] forming a metal element layer on the inner wall of the trench and the surface of the semiconductor substrate;

[0012] Processing the metal element layer located on the inner wall of the trench and the surface of the semiconductor substrate to convert the metal element layer into a first metal compound layer;

[0013] The first metal compound layer is processed to transform the first metal compound layer into a second metal compound layer, and the second metal compound layer is formed as a lower plate conductive layer.

[0014] According to one aspect of the present invention, a capacitor structure is further provided. The capacitor structure is formed by using the above-mentioned method for forming the capacitor structure.

[0015] Compared with the prior art, the method for forming a capacitor structure and the capacitor structure of the present invention have at least the following beneficial effects:

[0016] The formation method of the capacitor structure of the present invention includes providing a semiconductor substrate, forming a groove in the semiconductor substrate, and forming a metal element layer on the inner wall of the groove and the surface of the semiconductor substrate. The metal element layer on the inner wall of the groove and the surface of the semiconductor substrate is processed to convert the metal element layer into a first metal compound layer, and the first metal compound layer is processed to convert the first metal compound layer into a second metal compound layer, and the second metal compound layer is formed as a lower plate conductive layer. Thus, the present invention forms a uniform metal element layer in the groove first, and then reacts the metal element layer with the material of the groove sidewall by heat treatment to form a low-resistance conductive layer, and the conductive layer is formed as a lower plate conductive layer. The lower plate conductive layer formed in this way has a uniform material distribution and low resistance. The capacitor structure formed subsequently is stable in high frequency, has a good capacitance coefficient, and the performance of the silicon capacitor formed is also greatly improved, which can meet the needs of capacitors with higher aspect ratios.

[0017] The capacitor structure of the present invention is formed by the above-mentioned method for forming the capacitor structure, and also has the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a flow chart of steps of a method for forming a capacitor structure in an embodiment of the present invention;

[0019] Figure 2 A semiconductor substrate is provided in an embodiment of the present invention, and a schematic structural diagram of the semiconductor substrate after an oxide layer and a hard mask layer are formed;

[0020] Figure 3 For the general Figure 2 Schematic diagram of the structure after the hard mask layer and the oxide layer are patterned;

[0021] Figure 4 Based on Figure 3 A schematic diagram of the structure after etching the semiconductor substrate through the patterned hard mask layer and the oxide layer to form a groove;

[0022] Figure 5 To remove Figure 4 Schematic diagram of the structure after the hard mask layer in FIG.

[0023] Figure 6 For Figure 5 A schematic diagram of the structure after a metal element layer is formed on the surface of the grooves and the oxide layer;

[0024] Figure 7 For the general Figure 6 A schematic diagram of a structure after the first heat treatment and the second heat treatment to form a second metal compound layer;

[0025] Figure 8 For Figure 7 A schematic diagram of a structure after a stacked structure in which dielectric layers and polysilicon layers are alternately formed on the second metal compound layer;

[0026] Fig. 9 For Figure 8 A schematic diagram of a structure after a contact hole is formed in the structure;

[0027] Fig.10 For Fig. 9 A schematic diagram of a structure after an insulating dielectric layer is formed on the structure in FIG.

[0028] Fig.11 For Fig.10 Schematic diagram of the structure after an electrode layer is formed in the contact hole of the structure in FIG.

[0029] List of reference numerals:

[0030] 100 Semiconductor Substrate

[0031] 200 Oxide layer

[0032] 300 Hard mask layer

[0033] 400 Groove / Deep Groove

[0034] 500 Metal Element Layers

[0035] 600 Second metal compound layer / lower plate conductive layer

[0036] 700 laminated structure

[0037] 701 First dielectric layer

[0038] 702 first polycrystalline layer / common plate conductive layer

[0039] 703 Second dielectric layer

[0040] 704 Second polycrystalline layer / upper plate conductive layer

[0041] 801 First contact hole

[0042] 802 second contact hole

[0043] 803 Third contact hole

[0044] 900 Insulation dielectric layer

[0045] 1001 Upper plate layer

[0046] 1002 lower plate layer

[0047] 1003 Common electrode layer DETAILED DESCRIPTION

[0048] The following specific embodiments illustrate the embodiments of the present invention, and those familiar with the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0049] It should be noted that the diagrams provided in the embodiments of the present invention are only used to illustrate the basic concept of the present invention in a schematic manner. Although the diagrams only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of each component can be changed at will during actual implementation, and the layout of the components may also be more complex. The structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions that can be implemented in this application, so they have no technical substantive significance. Any structural modification, change in proportional relationship or adjustment of size should still fall within the scope of the technical content disclosed in this application without affecting the effects and purposes that can be achieved by the present invention.

[0050] In order to form a capacitor bottom plate structure with uniform resistance and improve capacitor performance, this embodiment provides a method for forming a capacitor structure and a capacitor structure.

[0051] Example 1

[0052] This embodiment provides a method for forming a capacitor structure. Figure 1 , the method for forming the capacitor structure includes:

[0053] S1: providing a semiconductor substrate;

[0054] Specifically, refer to Figure 2 , a semiconductor substrate 100 is provided, and the material of the semiconductor substrate 100 may be silicon (Si), germanium (Ge), silicon on insulator (SOI) or germanium on insulator (GOI), etc. When the material of the semiconductor substrate 100 is silicon, it may be one of single crystal silicon, polycrystalline silicon, and amorphous silicon. In addition, the semiconductor substrate 100 may also include an epitaxial layer structure. Optionally, the semiconductor substrate 100 may be a P-type substrate, and a conductive layer may be formed by N-type ion doping in a subsequent process. Of course, the semiconductor substrate 100 may also be an N-type substrate, and a conductive layer may be formed by P-type ion doping in a subsequent process. This embodiment is described by taking the semiconductor substrate 100 as a silicon substrate as an example.

[0055] S2: forming a trench in the semiconductor substrate;

[0056] Reference Figure 5 , forming a trench 400 in the semiconductor substrate 100 provided in step S1. The specific steps of forming the trench 400 include: when forming the trench 400 in the semiconductor substrate 100, referring to Figure 2 First, an oxide layer 200 is formed on the surface of the semiconductor substrate 100, and a hard mask layer 300 is formed on the surface of the oxide layer 200. Figure 3 , patterning the hard mask layer 300, specifically, etching the hard mask layer 300 by photolithography to pattern it, and then removing the photoresist layer. Figure 3 and 4 Based on the patterned hard mask layer 300, the oxide layer 200 and the surface of the semiconductor substrate 100 are sequentially etched to a certain etching depth to form a plurality of trenches 400 arranged at intervals in the semiconductor substrate 100. After etching, the hard mask layer 300 is removed, such as Figure 5 As shown. In this embodiment, the semiconductor substrate 100 is etched by dry etching, and the etching depth is controlled to be greater than or equal to 30μm. After dry etching, it is inevitable that the silicon lattice at the side wall of the groove 400 will be damaged. Therefore, after the groove 400 is formed, a sacrificial oxide layer can be formed on the side wall of the groove 400 to repair the side wall of the groove 400 and ensure the flatness of the groove side wall. After the repair, the sacrificial oxide layer is removed to avoid its influence on the subsequent process. Optionally, the thickness of the sacrificial oxide layer is Of course, the etching damage may also be repaired by introducing nitrogen and performing heat treatment. This embodiment does not limit the method of repairing the etching damage.

[0057] The groove etching in this embodiment is deep groove etching, and the depth of the groove 400 is greater than 30μm, and can even reach 50μm, to meet the needs of high-capacitance silicon capacitors. The deeper the depth of the deep groove 400, the greater the aspect ratio, the larger the surface area of ​​the capacitor structure, the higher the capacitance, and the better the performance of the formed silicon capacitor. However, ion implantation is performed in the sidewall of the deep groove 400 with a large aspect ratio. Since the groove 400 is deep, it is difficult for the ion implantation process to ensure the uniformity of the injection of the sidewall of the deep groove 400, and in order to ensure the effective use of the chip layout planning area, the deep groove 400 is also placed more randomly, and the ion implantation angle is more difficult to select, and it is difficult to form a lower plate structure with uniform resistance in the deep groove 400 by ion implantation.

[0058] In order to solve the technical problem that it is difficult to achieve uniform ion implantation in the deep trench 400, referring to Figure 6 In this embodiment, a uniform metal element layer 500 is formed in the deep trench 400 first, referring to Figure 7 , the sidewall doping of the deep trench 400 is subsequently improved by heat treatment or rapid thermal annealing, so that the metal element layer 500 reacts with the material of the sidewall of the deep trench 400 to form a low-resistance conductive layer, which is formed as the lower plate conductive layer 600. The lower plate conductive layer 600 formed in this way has uniform material distribution and low resistance. The capacitor structure formed subsequently has stable charging and discharging under high frequency conditions and a relatively good capacitance coefficient, and the performance of the formed silicon capacitor is also greatly improved.

[0059] Specifically, the method for forming the capacitor structure of this embodiment includes steps S3 to S5.

[0060] S3: forming a metal element layer on the inner wall of the trench and the surface of the semiconductor substrate;

[0061] Reference Figure 6After the groove 400 is formed in step S2, a metal element layer 500 is formed on the inner wall of the groove 400 and the surface of the semiconductor substrate 100. Optionally, the metal element layer 500 is one of a titanium layer, a nickel layer or a cobalt layer. In order to ensure the uniformity of the formation of the metal element layer 500, the metal element layer 500 can be formed by physical vapor deposition (PVD) or low pressure chemical vapor deposition (LPCVD). The metal element layer 500 formed by these two methods has good uniformity, which is convenient for subsequent uniform reaction with the semiconductor substrate material. In this embodiment, the metal element layer 500 is formed by physical vapor deposition (PVD). The deposition amount of the metal element layer 500 should not be too much or too low, and it is necessary to ensure that the sidewalls of the groove 400 can be deposited as much as possible. In this embodiment, the thickness of the metal element layer 500 deposited on the sidewalls of the groove 400 is between 30 and 60nm to ensure that the metal element layer 500 can be completely deposited to cover the sidewalls of the groove 400.

[0062] S4: treating the metal element layer located on the inner wall of the trench and the surface of the semiconductor substrate to convert the metal element layer into a first metal compound layer;

[0063] Specifically, continue to refer to Figure 6 The structure formed in step S3 is subjected to a first heat treatment, so that the metal element in the metal element layer 500 reacts with the material of the sidewall of the trench 400 and the surface of the semiconductor substrate 100 to form a first metal compound layer. The specific temperature of the heat treatment is set based on the material of the metal element layer 500. For example, when the metal element layer 500 is a Ti layer, the temperature of the first heat treatment is set to 450-650°C. At this temperature, the Ti layer reacts with the silicon in the semiconductor substrate 100 to generate a high-resistance metal silicide Ti. 2 When the metal element layer 500 is a Co layer, the temperature of the first heat treatment is set to 400-550° C. At this temperature, the Co layer reacts with the silicon in the semiconductor substrate 100 to generate a high-resistance metal silicide CoSi 2 Optionally, the first heat treatment may be performed by a rapid annealing process, a thermal annealing process or a rapid thermal oxidation process. In this embodiment, the first heat treatment is performed by a rapid thermal annealing process.

[0064] After the first heat treatment, the unreacted metal element layer is removed. Figure 6After step S4, the metal element layer 500 that has not participated in the reaction is removed to prevent the unreacted metal element layer 500 from subsequently contaminating the machine. Specifically, the metal element layer 500 that has not participated in the reaction can be removed by wet etching. Optionally, the wet etching solution can be sulfuric acid cleaning solution, SC1 cleaning solution or SC2 cleaning solution. In this embodiment, an excess of SC2 cleaning solution is used to etch and remove the unreacted metal element layer 500. SC2 cleaning solution is a mixture of hydrochloric acid, hydrogen peroxide and water, and the volume ratio of the three is 1:1:50. The main function of SC2 cleaning solution is to remove metal ions on the wafer. Its cleaning mechanism is that it can provide an environment with a low pH value, and alkaline metal ions and metal hydrides will be able to dissolve in SC2 cleaning solution. Since SC1 is alkaline, metal adhesion is more likely to occur in SC1 cleaning solution. SC2 is acidic, so this phenomenon is not easy to occur in SC2 solution, and the latter is easier to remove metal on the surface of the wafer. Therefore, this embodiment uses SC2 cleaning solution to remove unreacted metal elements.

[0065] S5: treating the first metal compound layer to transform the first metal compound layer into a second metal compound layer.

[0066] Continue to refer to Figure 6 After removing the metal element layer 500 that does not participate in the reaction, the resulting structure is subjected to a second heat treatment to convert the first metal compound in the first metal compound layer into a second metal compound to form a second metal compound layer. The temperature of the second heat treatment is also set according to the material of the metal element layer 500. For example, when the metal element layer 500 is a Ti layer, the temperature of the second heat treatment is set to be greater than 750°C, at which the high-resistance metal silicide Ti 2 Si is converted into low-resistance metal silicide TiSi 2 When the metal element layer 500 is a Co layer, the temperature of the second heat treatment is set to 700°C or above, at which the high-resistance metal silicide CoSi 2 The second heat treatment may be performed by a rapid annealing process, a thermal annealing process or a rapid thermal oxidation process. In this embodiment, the second heat treatment may be performed by a rapid thermal annealing process.

[0067] Reference Figure 7, the second metal compound layer 600 obtained after the second heat treatment can be used as the lower plate conductive layer 600 of the capacitor structure. Since the metal element layer 500 formed in the early stage of forming the second metal compound layer 600 is formed by physical vapor deposition (PVD), the metal element layer 500 is formed more evenly on the side wall of the groove 400, which is conducive to the uniform reaction when the first metal compound layer and the second metal compound layer 600 are formed by subsequent heat treatment, and then a uniform second metal compound layer 600 is formed. Therefore, after two heat treatment processes, a uniform, low-resistance second metal compound is formed on the side wall of the groove 400, so that the resistance of the lower plate conductive layer 600 is uniform and low, which is more conducive to improving the performance of the device.

[0068] Optionally, refer to Figure 8 , after the step of forming the lower plate conductive layer 600, it also includes: forming a laminated structure 700 in which dielectric layers and polycrystalline layers are alternately arranged on the surface of the lower plate conductive layer 600, and the last polycrystalline layer in the laminated structure 700 is formed as the upper plate conductive layer. Optionally, the laminated structure can be formed by chemical vapor deposition (CVD) or organic vapor phase reaction (FUR). In this embodiment, the laminated structure 700 includes a first dielectric layer 701, a first polycrystalline layer 702, a second dielectric layer 703 and a second polycrystalline layer 704, wherein the second polycrystalline layer 704 is formed as the upper plate conductive layer 704, and the first polycrystalline layer 702 can be used as the common plate conductive layer 702 later. The first dielectric layer 701 can be a single-layer structure or a multi-layer structure. When the first dielectric layer 701 is a single-layer structure, its material can be silicon oxide or silicon nitride. When the first dielectric layer 701 is a multi-layer structure, it can be a double-layer structure formed by silicon oxide and silicon nitride, or it can be an ONO three-layer structure. The ONO three-layer structure is a three-layer structure consisting of an oxide layer-nitride layer-oxide layer, wherein the oxide layer is better bonded to the lower plate layer 1002 than the nitride layer, and the nitride layer is centered to block the extension of defects. Optionally, the oxide layer may be silicon oxide, or may be hafnium oxide or aluminum oxide, and the nitride layer may be silicon nitride. Similarly, the second dielectric layer 703 is configured the same as the first dielectric layer 701, and may also be a single-layer structure or a multi-layer structure, which will not be described in detail herein. The first polycrystalline layer 702 or the second polycrystalline layer 704 is a polycrystalline silicon layer. In the present embodiment, the first polycrystalline layer 702 and the second polycrystalline layer 704 are heavily doped polycrystalline silicon, and the doping ions may be one of the group III elements or the group V elements.

[0069] After forming the stacked structure 700, the method further includes: referring to Fig. 9 , forming a first contact hole 801 and a second contact hole 802, wherein the first contact hole 801 exposes the lower plate conductive layer 600, and the second contact hole 802 exposes the upper plate conductive layer. Fig.11At least a lower electrode layer 1002 is formed in the first contact hole 801, and the lower electrode layer 1002 is in contact with and connected to the lower electrode conductive layer 600 through the second contact hole 802. At least an upper electrode layer 1001 is formed in the second contact hole 802, and the upper electrode layer 1001 is in contact with and connected to the upper electrode conductive layer through the second contact hole 802. In this embodiment, referring to Fig.10 After forming the first contact hole 801 and the second contact hole 802, it also includes forming an insulating dielectric layer 900, the insulating dielectric layer 900 exposing the first contact hole 801 and the second contact hole 802, referring to Fig.11 , the lower electrode plate and the upper electrode plate materials are filled into the two contact holes to form the lower electrode plate layer 1002 and the upper electrode plate layer 1001 respectively. Fig.10 In this embodiment, a third contact hole 803 is further formed, and the third contact hole 803 exposes the first polycrystalline layer 702. Fig.11 The positive plate material deposited in the third contact hole 803 can be used as the subsequent common plate layer 1003. Optionally, the material of the lower plate layer 1002, the lower plate layer 1002 and the common plate layer 1003 can be one or a combination of gold, aluminum, copper, titanium and nickel.

[0070] Example 2

[0071] This embodiment provides a capacitor structure, which is formed by the method for forming the capacitor structure in Embodiment 1. Fig.11 The capacitor structure includes a semiconductor substrate 100, a groove 400 formed in the semiconductor substrate 100, a lower plate conductive layer 600 formed in the groove 400 and on the surface of the semiconductor substrate 100, a stacked structure 700, a lower plate layer 1002, and an upper plate layer 1001. The stacked structure 700 is a dielectric layer and a polycrystalline layer alternately arranged, and the last layer of the polycrystalline layer is formed as an upper plate conductive layer 704. The lower plate layer 1002 is connected to the lower plate conductive layer 600, and the upper plate layer 1001 is connected to the upper plate conductive layer.

[0072] Since the lower plate conductive layer 600 in this embodiment is formed by the formation method in Embodiment 1, the metal element layer 500 formed in the early stage of forming the lower plate conductive layer 600 or the second metal compound layer 600 is formed by physical vapor deposition (PVD), and the metal element layer 500 is formed more evenly on the side wall of the groove 400, which is conducive to the uniform reaction of the subsequent heat treatment process to form a uniform second metal compound layer 600. After two heat treatment processes, a uniform and low-resistance second metal compound is formed on the side wall of the groove 400, and then the second metal compound layer 600 as the lower plate conductive layer 600 has a lower resistance and a more uniform resistance. The capacitor structure formed thereby has stable charging and discharging under high frequency conditions, a better capacitance coefficient, and a more superior device performance.

[0073] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for forming a capacitor structure, characterized in that: include: Providing a semiconductor substrate; forming a trench in the semiconductor substrate; forming a metal element layer on the inner wall of the trench and the surface of the semiconductor substrate; Processing the metal element layer located on the inner wall of the trench and the surface of the semiconductor substrate to convert the metal element layer into a first metal compound layer; The first metal compound layer is processed to transform the first metal compound layer into a second metal compound layer, and the second metal compound layer is formed as a lower plate conductive layer.

2. The method for forming a capacitor structure according to claim 1, wherein The step of forming a groove in the semiconductor substrate comprises: forming an oxide layer on the surface of the semiconductor substrate; forming a hard mask layer on the surface of the oxide layer; patterning the hard mask layer; Sequentially etching the oxide layer and the surface of the semiconductor substrate based on the patterned hard mask layer to form a trench in the semiconductor substrate; The patterned hard mask layer is removed.

3. The method for forming a capacitor structure according to claim 1, wherein: The step of forming a metal element layer on the inner wall of the trench and the surface of the semiconductor substrate includes: A metal element layer is formed on the inner wall of the trench and the surface of the semiconductor substrate by using a physical vapor deposition process or a chemical vapor deposition process.

4. The method for forming a capacitor structure according to claim 1, wherein: The metal element layer is a titanium layer, a nickel layer or a cobalt layer.

5. The method for forming a capacitor structure according to claim 1, wherein: The step of processing the metal element layer located on the inner wall of the trench and the surface of the semiconductor substrate to convert the metal element layer into a first metal compound layer includes: A first heat treatment is performed to make the metal element in the metal element layer react with the material of the sidewall of the trench and the surface of the semiconductor substrate to form a first metal compound layer.

6. The method for forming a capacitor structure according to claim 5, characterized in that: The step of treating the first metal compound layer to convert the first metal compound layer into a second metal compound layer comprises: A second heat treatment is performed to convert the first metal compound in the first metal compound layer into a second metal compound to form a second metal compound layer.

7. The method for forming a capacitor structure according to claim 6, wherein: After processing the metal element layer located on the inner wall of the trench and the surface of the semiconductor substrate and before processing the first metal compound layer to convert the first metal compound layer into a second metal compound layer, the method further includes: The unreacted metal element layer is removed.

8. The method for forming a capacitor structure according to claim 6, wherein: The temperature of the first heat treatment is lower than the temperature of the second heat treatment.

9. The method for forming a capacitor structure according to claim 6, wherein: The first heat treatment step includes: placing the semiconductor substrate having the metal element layer under heat treatment at a temperature of 400° C. to 650° C. to form a first metal compound layer; The steps of performing the second heat treatment include: The semiconductor substrate having the first metal compound layer is subjected to heat treatment at a temperature of 700° C. to 850° C. to form a second metal compound layer.

10. The method for forming a capacitor structure according to claim 1, characterized in that: The first metal compound in the first metal compound layer is a high-resistance metal compound, and the second metal compound in the second metal compound layer is a low-resistance metal compound.

11. The method for forming a capacitor structure according to claim 10, wherein: The metal element layer is a cobalt layer, the semiconductor substrate is a silicon substrate, the first metal compound formed is CoSi2, and the second metal compound formed is CoSi.

12. The method for forming a capacitor structure according to claim 10, characterized in that: The metal element layer is a titanium layer, the semiconductor substrate is a silicon substrate, the first metal compound formed is Ti2Si, and the second metal compound formed is TiSi2.

13. The method for forming a capacitor structure according to claim 1, characterized in that: The first heat treatment is one of a rapid annealing process, a thermal annealing process or a rapid thermal oxidation process; the second heat treatment is one of a rapid annealing process, a thermal annealing process or a rapid thermal oxidation process.

14. The method for forming a capacitor structure according to claim 1, characterized in that After forming a groove in the semiconductor substrate and before forming a metal element layer on the inner wall of the groove and the surface of the semiconductor substrate, the method further includes: forming a sacrificial oxide layer in the trench; The sacrificial oxide layer is removed.

15. The method for forming a capacitor structure according to claim 1, wherein: After the step of forming the lower plate conductive layer, the method further comprises: A laminated structure in which dielectric layers and polycrystalline layers are alternately arranged is sequentially formed on the surface of the lower plate conductive layer, and the last polycrystalline layer in the laminated structure is formed as the upper plate conductive layer.

16. The method for forming a capacitor structure according to claim 15, characterized in that The step of sequentially forming a laminated structure in which dielectric layers and polycrystalline layers are alternately arranged on the surface of the conductive layer of the lower electrode plate comprises: A first dielectric layer, a first polycrystalline layer, a second dielectric layer and a second polycrystalline layer are sequentially formed on the surface of the lower plate conductive layer, and the second polycrystalline layer is formed as the upper plate conductive layer.

17. The method for forming a capacitor structure according to claim 15, characterized in that After the step of sequentially forming a laminated structure in which dielectric layers and polycrystalline layers are alternately arranged on the surface of the lower electrode conductive layer, the method further includes: Forming a first contact hole and a second contact hole, wherein the first contact hole exposes the lower plate conductive layer, and the second contact hole exposes the upper plate conductive layer; At least forming a lower electrode layer in the first contact hole, wherein the lower electrode layer is in contact and connected with the lower electrode conductive layer through the second contact hole; An upper electrode layer is formed at least in the second contact hole, and the upper electrode layer is in contact and connected with the upper electrode conductive layer through the second contact hole.

18. A capacitor structure, characterized in that: The capacitor structure is formed by the method for forming a capacitor structure according to any one of claims 1 to 17.

19. The capacitor structure according to claim 18, characterized in that: The capacitor structure comprises: Semiconductor substrate; at least one trench extending from the surface of the semiconductor substrate toward the interior of the semiconductor substrate; A lower plate conductive layer is formed on the inner wall of the groove and the surface of the semiconductor substrate; A laminated structure is formed on the surface of the lower plate conductive layer, the laminated structure is formed by alternating dielectric layers and polycrystalline layers, and the last polycrystalline layer of the laminated structure is formed as the upper plate conductive layer; A lower electrode layer, electrically connected to the lower electrode conductive layer; The upper electrode layer is electrically connected to the upper electrode conductive layer.

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