Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device and a method for manufacturing the semiconductor device, which can maintain low Vf characteristics, improve surge current tolerance and reduce leakage current by forming an ohmic electrode with low resistance. The semiconductor device includes an active region, a first conductivity type region, and a termination region. The active region has a first second conductivity type region, a silicide film, and a first electrode, and the termination region has a second second conductivity type region. The active region is configured from an ohmic region in which the first electrode is in contact with the silicide film, and a Schottky region in which the first electrode is in contact with the first conductivity type region. When the impurity concentration of the first conductivity type region is low, more ohmic regions are provided in the chip central portion than in the chip outer peripheral portion, and when the impurity concentration of the first conductivity type region is high, more ohmic regions are provided in the chip outer peripheral portion than in the chip central portion.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Conventionally, a semiconductor device has been proposed in which a Schottky junction region and an ohmic junction region are provided in an electrode to improve thermal breakdown resistance against a high current such as a surge current flowing in a forward direction (for example, see Patent Documents 1 and 2 listed below).

[0003] Prior art literature Patent Literature Patent Document 1: Japanese Patent Application Publication No. 2021-93522 Patent Document 2: Japanese Patent Application Publication No. 2014-78660 Summary of the invention

[0004] Technical issues However, when the surge current flows through p + In the case of the type area, sometimes due to p + Contact resistance of the die area, p + The bipolar action of the die region is delayed, causing the semiconductor element to heat up and be damaged.

[0005] The purpose of the present disclosure is to provide a semiconductor device and a method for manufacturing a semiconductor device that can improve surge current tolerance and reduce leakage current while maintaining low Vf characteristics by forming a low-resistance ohmic electrode in order to eliminate the problems caused by the above-mentioned prior art.

[0006] Technical Solution In order to solve the above problems and achieve the purpose of the present disclosure, the semiconductor device of the present disclosure has the following features. The semiconductor device comprises: an active region, which is arranged on a semiconductor substrate; a terminal region, which is arranged on the semiconductor substrate and surrounds the periphery of the active region; a first conductive type region, which is arranged inside the semiconductor substrate and exposed on the first main surface of the semiconductor substrate; a first second conductive type region, which is selectively arranged on the surface area of ​​the first conductive type region on the first main surface side of the semiconductor substrate in contact with the first conductive type region in the active region; a silicide film, which is ohmically bonded to the first second conductive type region; a first electrode, which is in contact with the silicide film, the first second conductive type region, and the first conductive type region; a second electrode, which is arranged on the second main surface of the semiconductor substrate; and a second second conductive type region, which is arranged in the terminal region and surrounds the active region. The active region is composed of an ohmic region and a Schottky region, the ohmic region is a region where the first electrode contacts the silicide film, and the Schottky region is a region where the first electrode contacts the first conductive type region. In the terminal region, the second second conductive type region is connected to the ohmic region. The impurity concentration in the first conductive type region is 1.0×10 15 / cm 3 More than and less than 1.0×10 16 / cm 3 In the case of a low concentration, an ohmic region having a larger area or number than that of the peripheral portion of the chip is provided in the central portion of the chip, and the impurity concentration in the first conductive type region is 1.0×10 16 / cm 3 Above and 9.0×10 16 / cm 3 In the case of a high concentration below 100%, an ohmic region having a larger area or a larger number is provided at the chip periphery than at the chip center.

[0007] According to the above disclosure, in n - When the impurity concentration of the first conductive drift region (first conductive region) is low, the surge current is concentrated on the periphery of the chip. Therefore, by providing a larger area or number of ohmic regions in the center of the chip, it is possible to prevent damage to the periphery of the chip. - When the impurity concentration of the drift region is high, the surge current is concentrated directly below the wire or in the center of the chip. Therefore, by setting up ohmic regions with a larger area or number on the periphery of the chip, damage can be prevented from occurring in the center of the chip.

[0008] Technical Effects According to the semiconductor device and the method for manufacturing the semiconductor device of the present disclosure, by forming a low-resistance ohmic electrode, it is possible to improve surge current tolerance while maintaining low Vf characteristics and reduce leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment when the drift layer has a high concentration.

[0010] Figure 2A FIG. 1 is a diagram showing the first embodiment viewed from the front side of the semiconductor substrate. Figure 1 A plan view of the layout obtained by a silicon carbide semiconductor device.

[0011] Figure 2B FIG. 1 is a diagram showing the first embodiment viewed from the front side of the semiconductor substrate. Figure 1 A plan view of another layout obtained by a silicon carbide semiconductor device.

[0012] Figure 3 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment when the drift layer has a low concentration.

[0013] Figure 4A FIG. 1 is a diagram showing the first embodiment viewed from the front side of the semiconductor substrate. Figure 3 A plan view of the layout obtained by a silicon carbide semiconductor device.

[0014] Figure 4B FIG. 1 is a diagram showing the first embodiment viewed from the front side of the semiconductor substrate. Figure 3 A plan view of another layout obtained by a silicon carbide semiconductor device.

[0015] Figure 5 It is shown that Figure 3 A cross-sectional view of the detailed structure of the area S surrounded by the dotted line.

[0016] Figure 6 It is a plan view showing the chip periphery and the chip center.

[0017] Figure 7 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the second embodiment when the drift layer has a low concentration.

[0018] Fig. 8A FIG. 2 is a diagram showing the second embodiment as viewed from the front side of the semiconductor substrate. Figure 7 A plan view of the layout obtained by a silicon carbide semiconductor device.

[0019] Figure 8B FIG. 2 is a diagram showing the second embodiment as viewed from the front side of the semiconductor substrate. Figure 7A plan view of another layout obtained by a silicon carbide semiconductor device.

[0020] Fig. 9 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the second embodiment when the drift layer has a high concentration.

[0021] Fig. 10A FIG. 2 is a diagram showing the second embodiment as viewed from the front side of the semiconductor substrate. Fig. 9 A plan view of the layout obtained by a silicon carbide semiconductor device.

[0022] Fig. 10B FIG. 2 is a diagram showing the second embodiment as viewed from the front side of the semiconductor substrate. Fig. 9 A plan view of another layout obtained by a silicon carbide semiconductor device.

[0023] Fig.11 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device.

[0024] Fig.12 This is a plan view showing the layout of a conventional silicon carbide semiconductor device as viewed from the front surface side of a semiconductor substrate.

[0025] Explanation of symbols 10, 110 Active area 11, 111 n + Type starting substrate 12, 112 n - Drift zone 13, 113 p constituting the JBS structure + Type Area 14, 114 Positive electrode 15, 115 Field oxide film 19, 119 Back electrode 20, 120 Edge terminal area 20a Connection area 21, 121 Field Limiting Ring (FLR) 22, 122 p that constitutes the JTE structure - Type Area 30, 130 Semiconductor substrate 31,131 Titanium film 32, 132 aluminum alloy film 33 (33a, 33b), 133 Nickel silicide film (first nickel silicide film, second nickel silicide film) 40, 140 Silicon carbide semiconductor device 51 Oxide film 60 Chip center 61 Chip periphery 80 High resistance junction area 81 Ohm Region 81a Low resistance ohmic region 82b High resistance ohmic region 82 Schottky region w1 p constituting the JBS structure + Width of mold area w2a Width of the first nickel silicide film w2b Width of the second nickel silicide film w4 Width of the high resistance junction area of ​​the JBS structure w5 Width of Schottky region DETAILED DESCRIPTION

[0026] <Overview of Embodiments of the Present Disclosure> In order to solve the above problems and achieve the purpose of the present disclosure, the semiconductor device of the present disclosure has the following features. The semiconductor device comprises: an active region, which is arranged on a semiconductor substrate; a terminal region, which is arranged on the semiconductor substrate and surrounds the periphery of the active region; a first conductive type region, which is arranged inside the semiconductor substrate and exposed on the first main surface of the semiconductor substrate; a first second conductive type region, which is selectively arranged on the surface area of ​​the first conductive type region on the first main surface side of the semiconductor substrate in contact with the first conductive type region in the active region; a silicide film, which is ohmically bonded to the first second conductive type region; a first electrode, which is in contact with the silicide film, the first second conductive type region, and the first conductive type region; a second electrode, which is arranged on the second main surface of the semiconductor substrate; and a second second conductive type region, which is arranged in the terminal region and surrounds the active region. The active region is composed of an ohmic region and a Schottky region, the ohmic region is a region where the first electrode contacts the silicide film, and the Schottky region is a region where the first electrode contacts the first conductive type region. In the terminal region, the second second conductive type region is connected to the ohmic region. The impurity concentration in the first conductive type region is 1.0×10 15 / cm 3 More than and less than 1.0×10 16 / cm 3 In the case of a low concentration, an ohmic region having a larger area or number than that of the peripheral portion of the chip is provided in the central portion of the chip, and the impurity concentration in the first conductive type region is 1.0×10 16 / cm 3 Above and 9.0×10 16 / cm 3 In the case of a high concentration below 100%, an ohmic region having a larger area or a larger number is provided at the chip periphery than at the chip center.

[0027] According to the above disclosure, in n - When the impurity concentration of the first conductive type drift region (first conductive type region) is low, the surge current is concentrated on the periphery of the chip. Therefore, by providing a larger area or number of ohmic regions in the center of the chip, it is possible to prevent damage to the periphery of the chip. - When the impurity concentration of the drift region is high, the surge current is concentrated directly below the wire or in the center of the chip. Therefore, by setting up ohmic regions with a larger area or number on the periphery of the chip, damage can be prevented from occurring in the center of the chip.

[0028] In addition, the semiconductor device disclosed in the present invention is characterized in that, in the above disclosure, the chip central portion is an area arranged in the center of the semiconductor device, and is an area ranging from the center of the side of the semiconductor device to more than 1 / 4 and less than 3 / 4 thereof, and the chip peripheral portion is an area arranged at the periphery of the semiconductor device, and is an area excluding the area ranging from the center of the side of the semiconductor device to more than 1 / 4 and less than 3 / 4 thereof.

[0029] In addition, the semiconductor device disclosed in the present invention is characterized in that, in the above disclosure, when the impurity concentration of the first conductive type region is the low concentration, a high-resistance bonding region in which the first electrode contacts the first second conductive type region is provided in the central portion of the chip in the active region, the width of the first second conductive type region is wider than the width of the silicide film, and the width of a single side of the difference between the width of the first second conductive type region and the width of the silicide film is greater than 0.1 μm and less than 5.0 μm.

[0030] According to the above disclosure, by making the width of the first nickel silicide film (silicide film) larger than p + The width of the first second conductivity type region is narrow, so that the p + type region, forming p + A high-resistance Schottky junction is formed between the type region and the titanium film.

[0031] In addition, the semiconductor device disclosed in the present invention is characterized in that, in the above disclosure, when the impurity concentration of the first conductive type region is the low concentration, a high-resistance bonding region in which the first electrode contacts the first second conductive type region is provided in the central portion of the chip in the active region, and in the peripheral portion of the chip, the area ratio of the high-resistance bonding region to the first second conductive type region is greater than 35%.

[0032] In addition, the semiconductor device disclosed in the present invention is characterized in that, in the above disclosure, when the impurity concentration of the first conductive type region is the low concentration, a high-resistance bonding region in contact with the first second conductive type region is provided in the central portion of the chip in the active region, and in the central portion of the chip, the area ratio of the high-resistance bonding region to the active region is greater than 15% and less than 40%.

[0033] According to the above disclosure, by setting the area ratio within these ranges, it is possible to achieve both improvement in surge current tolerance and low Vf characteristics.

[0034] In addition, the semiconductor device disclosed in the present invention is characterized in that, in the above disclosure, when the impurity concentration of the first conductive type region is the high concentration, a high-resistance bonding region in which the first electrode contacts the first second conductive type region is provided at the periphery of the chip in the active region, the width of the first second conductive type region is wider than the width of the silicide film, and the width of a single side of the difference between the width of the first second conductive type region and the width of the silicide film is greater than 0.1 μm and less than 5.0 μm.

[0035] According to the above disclosure, by making the width of the first nickel silicide film (silicide film) larger than p + The width of the first second conductivity type region is narrow, and the p + type region, forming a p + A high-resistance Schottky junction is formed between the type region and the titanium film.

[0036] In addition, the semiconductor device disclosed in the present invention is characterized in that, in the above disclosure, when the impurity concentration of the first conductive type region is the high concentration, a high-resistance bonding region in contact with the first second conductive type region is provided at the periphery of the chip in the active region, and in the periphery of the chip, the area ratio of the high-resistance bonding region to the first second conductive type region is greater than 35%.

[0037] In addition, the semiconductor device disclosed in the present invention is characterized in that, in the above disclosure, when the impurity concentration of the first conductive type region is the high concentration, a high-resistance bonding region in contact with the first second conductive type region is provided at the periphery of the chip in the active region, and in the periphery of the chip, the area ratio of the high-resistance bonding region to the active region is greater than 15% and less than 40%.

[0038] According to the above disclosure, by setting the area ratio within these ranges, it is possible to achieve both improvement in surge current tolerance and low Vf characteristics.

[0039] In addition, the semiconductor device of the present disclosure is characterized in that, in the above disclosure, the silicide film contains nickel, silicon, and aluminum.

[0040] In order to solve the above problems and achieve the purpose of the present disclosure, the semiconductor device of the present disclosure has the following characteristics. The semiconductor device comprises: an active region, which is arranged on a semiconductor substrate; a terminal region, which is arranged on the semiconductor substrate and surrounds the periphery of the active region; a first conductive type region, which is arranged inside the semiconductor substrate and exposed on the first main surface of the semiconductor substrate; a second conductive type region, which is in contact with the first conductive type region in the active region and is selectively arranged on the surface area of ​​the first conductive type region on the first main surface side of the semiconductor substrate; and a silicide film, which is ohmically bonded to a part of the second conductive type region. The impurity concentration in the first conductive type region is 1.0×10 15 / cm 3 More than and less than 1.0×10 16 / cm 3 In the case of low concentration, the contact resistance is set to 5×10 -4 Ω / cm 2 Above and 5×10 -3 Ω / cm 2 The silicide film is provided at the center of the active region with a contact resistance of 5×10 -5 Ω / cm 2 More than and less than 5×10 -4 Ω / cm 2 The silicide film has an impurity concentration of 1.0×10 16 / cm 3 Above and 9.0×10 16 / cm 3 In the case of a high concentration below 50%, the contact resistance is set to 5×10 -5 Ω / cm 2 More than and less than 5×10 -4 Ω / cm 2 The silicide film is provided at the center of the active region with a contact resistance of 5×10 -4 Ω / cm 2 Above and 5×10 -3 Ω / cm 2 The silicide film described below.

[0041] In order to solve the above problems and achieve the purpose of the present disclosure, the manufacturing method of the semiconductor device of the present disclosure has the following characteristics. It is a manufacturing method of a semiconductor device having an active region and a terminal region surrounding the active region on a semiconductor substrate. First, a first step is performed to form a first conductive type region constituting a first main surface of the semiconductor substrate inside the semiconductor substrate. Then, a second step is performed to selectively form a first second conductive type region in contact with the first conductive type region between the first main surface of the semiconductor substrate and the first conductive type region in the active region. Then, a third step is performed to form a second second conductive type region surrounding the active region in the terminal region. Then, a fourth step is performed to form an oxide film covering the first conductive type region and the first second conductive type region on the first main surface of the semiconductor substrate. Then, a fifth step is performed to selectively remove the oxide film and form a first opening portion in the oxide film to expose the first second conductive type region. Then, a sixth step is performed to form a metal material film by sequentially stacking a nickel film, an aluminum film, and a metal film having a melting point higher than that of aluminum in contact with the first main surface of the semiconductor substrate in the first opening portion of the oxide film. Next, a seventh step is performed, wherein the metal material film reacts with the semiconductor substrate by a first heat treatment, and a compound layer is self-matchedly generated on the first main surface of the semiconductor substrate at the first opening of the oxide film, using the oxide film as a mask. Next, an eighth step is performed, wherein the remaining portion of the metal material film other than the compound layer is removed after the seventh step. Next, a ninth step is performed, wherein after the eighth step, a second heat treatment at a temperature higher than that of the first heat treatment is performed, wherein nickel silicide is generated inside the compound layer, thereby forming a silicide film that is ohmically bonded to the semiconductor substrate. Next, a tenth step is performed, wherein after the ninth step, the oxide film sandwiched by the silicide film is removed, thereby forming a contact hole that connects all the first openings. Next, an eleventh step is performed, wherein a titanium film that is in contact with the first conductive type region and is Schottky bonded to the first conductive type region, and a metal electrode film containing aluminum are sequentially stacked on the first main surface of the semiconductor substrate inside the contact hole to form a first electrode. Next, a twelfth step is performed, wherein a second electrode is formed on the second main surface of the semiconductor substrate.

[0042] In the seventh step, the impurity concentration in the first conductive type region is 1.0×10 15 / cm 3 More than and less than 1.0×10 16 / cm 3In the case of a low concentration of , at a position of the active region close to the terminal region, the temperature of the first heat treatment is set to a low temperature of 800° C. or higher and less than 1000° C., and a contact resistance of 5×10 -4 Ω / cm 2 Above and 5×10 -3 Ω / cm 2 The silicide film is formed at a position close to the center of the active region by setting the first heat treatment temperature to a high temperature of 1000° C. to 1200° C. to form a contact resistance of 5×10 -5 Ω / cm 2 More than and less than 5×10 -4 Ω / cm 2 The silicide film has an impurity concentration of 1.0×10 16 / cm 3 Above and 9.0×10 16 / cm 3 In the case of a high concentration of 5×10 -5 Ω / cm 2 More than and less than 5×10 -4 Ω / cm 2 The silicide film is formed at a position close to the center of the active region, and the temperature of the first heat treatment is set to a low temperature of 800° C. or higher and lower than 1000° C., so as to form a contact resistance of 5×10 -4 Ω / cm 2 Above and 5×10 -3 Ω / cm 2 The silicide film described below.

[0043] According to the above disclosure, in n - When the impurity concentration of the type drift region is low, the surge current is concentrated on the periphery of the chip. Therefore, by providing a nickel silicide film as a low resistance ohmic region in the center of the chip, it is possible to prevent damage to the periphery of the chip. - When the impurity concentration in the drift region is high, surge current is concentrated just below the wire or in the center of the chip. Therefore, a nickel silicide film as a low-resistance ohmic region is provided on the periphery of the chip to prevent damage in the center of the chip.

[0044] <Foundation that forms the basis of this disclosure> First, the problems of conventional semiconductor devices are explained. In recent years, silicon carbide (SiC) semiconductors have attracted much attention as semiconductor materials that can produce (manufacture) semiconductor devices that exceed the limits of semiconductor devices using silicon (Si) semiconductors (hereinafter referred to as silicon carbide semiconductor devices). In particular, compared with silicon semiconductors, silicon carbide semiconductors have advantages such as high insulation breakdown field strength and high thermal conductivity, and are expected to be used in high-voltage (e.g., 1200V or more) semiconductor devices.

[0045] When the silicon carbide semiconductor device is a diode (hereinafter referred to as a silicon carbide diode), since n - n - The design specifications of the epitaxial layer can be set to be thinner and have a higher impurity concentration, so silicon carbide diodes with a withstand voltage of around 3300V generally adopt a Schottky barrier diode (SBD: Schottky Barrier Diode) structure.

[0046] Generally, in the SBD structure, the electric field strength at the junction between the semiconductor substrate and the front electrode is high, and when a reverse voltage is applied, the reverse leakage current increases due to electron tunneling through the Schottky barrier, or the reverse leakage current increases due to surface defects inherent in silicon carbide. Therefore, a silicon carbide diode with a junction barrier Schottky (JBS) structure that mixes Schottky junction and pn junction on the front side of the semiconductor substrate has been proposed.

[0047] With respect to the structure of a conventional silicon carbide diode having an SBD structure, the structure of a silicon carbide diode adopting a JBS structure will be described. Fig.11 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device.

[0048] Fig.11 The conventional silicon carbide semiconductor device 140 shown is a vertical silicon carbide diode having a JBS structure in which an active region 110 is located on the front side of a semiconductor substrate 130 and a SBD structure and a pn junction are mixed. The SBD structure is composed of n - The structure formed by the Schottky junction of the type drift region 112 and the titanium film 131 constituting the front electrode 114 is a pn junction. + Type area 113 and n - The pn junction between the front drift region 112. In addition, as the bottom layer of the front electrode 114, the nickel silicide film 133 is provided on the p + Type area 113.

[0049] The Schottky junction of the conventional silicon carbide semiconductor device 140 is formed by an n-type semiconductor layer exposed on the front surface of the semiconductor substrate 130. -The front electrode 114 is formed of a titanium film 131 and an aluminum alloy film 132 provided on the front surface of the semiconductor substrate 130. The semiconductor substrate 130 is formed of an n-type drift region 112 and a front electrode 114. The front electrode 114 is composed of a titanium film 131 and an aluminum alloy film 132 provided on the front surface of the semiconductor substrate 130. + The front surface of the starting substrate 111 is stacked to form n - The n of the drift region 112 - An epitaxial substrate made of a type epitaxial layer. + Type starting substrate 111 is n + A back electrode 119 is provided on the entire back side of the semiconductor substrate 130 and is connected to the n + The JTE structure is electrically connected to the starting substrate 111. Reference numerals 115, 120, 121, and 122 respectively represent a field oxide film, an edge termination region, a field limiting ring (FLR), and a p-type JTE structure. - Type area.

[0050] p + The type region 113 is selectively disposed in the surface area of ​​the front side of the semiconductor substrate 130 in the active region 110. + Between the type regions 113, n - Type drift region 112. p + Type area 113 and n - The type drift region 112 forms a pn junction on the front surface of the semiconductor substrate 130. + n between type area 113 - The type drift region 112 forms a Schottky junction with the lowermost titanium film 131 of the front electrode 114 provided on the front surface of the semiconductor substrate 130 .

[0051] Fig.12 FIG. 1 is a plan view showing the layout of a conventional silicon carbide semiconductor device viewed from the front side of a semiconductor substrate. Fig.12 As shown, in the active region 110, p + The type region 113 and the nickel silicide film 133 are arranged in a stripe shape, and at the end, p + The type region 113 is connected to the FLR 121 , and the nickel silicide film 133 of the active region 110 is connected to the nickel silicide film 133 on the FLR 121 .

[0052] By adopting such a structure, when the rated current flows in the forward direction, the current is divided by p + n outside the type area 113 - Furthermore, when a surge current flows due to lightning strike or the like, the current cannot flow only through the Schottky region, so the p +The type region 113 performs bipolar action to allow current to flow. + A nickel silicide film 133 is provided on the ohmic region 113, and only p + Compared with the stripe structure of the type region 113, it is easier to perform bipolar action.

[0053] However, when the surge current flows through p + In the case of type zone 113, sometimes due to p + Contact resistance of area 113, p + The bipolar action of the type region 113 is delayed, causing the semiconductor element to heat up and be damaged. + The stripe structure of the type area 113 is different. + In the case of type zone 113, n - The area of ​​the Schottky region of the drift region 112 is reduced, and the forward voltage Vf at the rated current increases, resulting in a higher on-state voltage. + There is a trade-off that Vf increases if the area of ​​the die region 113 is increased. Furthermore, in a structure where the ohmic regions on a semiconductor element such as a dot structure are independent of each other, there is a problem that resistance varies, local heating is easily generated, and it is difficult to ensure surge current tolerance.

[0054] Furthermore, in a structure where the ohmic regions on the device are independent of each other (such as a dot structure), the resistance varies, local heat generation is likely to occur, and it is difficult to ensure surge current tolerance. - The difference in impurity concentration in the drift region 112 leads to a difference in impurity concentration in the ohmic region, so that the damage position may change and the surge current tolerance may be reduced.

[0055] For example, due to n - The p-type drift region 112 is implanted with p-type impurity ions to form a p + Type area 113, so there is - When the impurity concentration of the drift region 112 is low, p + The impurity concentration of the type region 113 increases, and the surge current is concentrated on the periphery of the chip, causing damage to the periphery of the chip. - When the impurity concentration of the drift region 112 is high, p + The impurity concentration of the die region 113 decreases, and the surge current is concentrated just below the wire or in the center of the chip, causing damage to the center of the chip. Here, the chip refers to the silicon carbide semiconductor device 140 obtained by dicing (cutting) a semiconductor substrate into individual pieces.

[0056] Hereinafter, with reference to the accompanying drawings, preferred embodiments of the semiconductor device and the method for manufacturing the semiconductor device disclosed in the present invention are described in detail. In the present specification and the accompanying drawings, in the layers and regions prefixed with n or p, it is indicated that electrons or holes are the majority carriers, respectively. In addition, + and - marked on n and p respectively indicate that the impurity concentration is higher and lower than the impurity concentration of the layers and regions not marked with n and p. It should be noted that in the description and drawings of the following embodiments, the same symbols are marked for the same structures, and repeated descriptions are omitted. It should be noted that in the marking of the Miller index, "-" refers to the horizontal line marked on the index immediately following it, and a negative index is indicated by marking "-" before the index. In addition, the same or equivalent records may contain deviations within 5% in consideration of deviations in manufacturing.

[0057] (Implementation method 1) Hereinafter, a semiconductor device according to Embodiment 1 that solves the above-mentioned problems will be described. As the semiconductor device according to Embodiment 1, a structure of a silicon carbide semiconductor device will be described. Figure 1 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment when the drift layer has a high concentration. Figure 2A , Figure 2B 1 is a plan view showing an example of the layout of the p-type region (the first second conductivity type region 13 ), the field limiting ring (the second second conductivity type region 21 ), and the nickel silicide film 33 constituting the JBS structure. Figure 1 The cross-sectional view of the silicon carbide semiconductor device shown corresponds to Figure 2A , Figure 2B A-A' section. Figure 1 The AA' cross-sectional view omits the BC, DE, FG and HI cross-sectional views in the plan view. Figure 3 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment when the drift layer has a low concentration. Figure 4A and Figure 4B The first embodiment is shown as viewed from the front side of the semiconductor substrate. Figure 3 This is a plan view of the layout of a silicon carbide semiconductor device. Figure 4A , Figure 4B FIG. 1 shows an example of the layout of the p-type region (the first second conductivity type region 13), the field limiting ring (the second second conductivity type region 21), and the nickel silicide film 33 constituting the JBS structure. Figure 3 yes Figure 4A and Figure 4B A-A' cross-sectional view. Figure 2A and Figure 4A This is an example of changing the area of ​​the nickel silicide film (ohmic region). Figure 2B and Figure 4B This is an example in which the number of nickel silicide films (ohmic regions) is changed.

[0058] Figure 1 to Figure 4B The silicon carbide semiconductor device 40 of the first embodiment shown is a silicon carbide diode of a JBS structure, in which a front electrode (first electrode) 14 and an n-type semiconductor layer are mixed on the front surface (first main surface) side of the semiconductor substrate 30 in the active region 10. - The SBD structure is composed of a Schottky structure of a type drift region (first conductivity type region) 12, and a p + Type region (first second conductivity type region) 13 and n - The pn diode is formed by the pn junction of the drift region 12.

[0059] n - Type drift region 12 and p + The type regions 13 are arranged substantially evenly in a substantially uniform pattern within the front surface of the active region 10. - Type drift region 12 and p + The die regions 13 are arranged, for example, in stripes extending in the same direction parallel to the front surface of the semiconductor substrate 30, and are alternately and repeatedly arranged so as to be in contact with each other in the short-side direction perpendicular to the long-side direction extending in the stripes. - The drift region 12 is adjacent to the p + The regions 13 are exposed on the front surface of the semiconductor substrate 30 .

[0060] The active region 10 is a region where current flows when the silicon carbide diode is in the on state. The active region 10 has a substantially rectangular planar shape, for example, and is disposed substantially in the center of the semiconductor substrate 30. The edge termination region 20 is a region between the active region 10 and the end of the semiconductor substrate 30, and surrounds the active region 10. The edge termination region 20 is a region that relaxes the n - The drift region 12 is a region that is close to the front side of the semiconductor substrate 30 and maintains a withstand voltage. The withstand voltage refers to the limit voltage that does not cause malfunction or damage to the device.

[0061] A voltage-resistant structure such as a junction termination extension (JTE) structure is arranged in the edge termination region 20. The JTE structure is a structure in which a p-type region whose impurity concentration decreases as it moves away from the inside (the center side of the semiconductor substrate 30) to the outside (the end side of the semiconductor substrate 30) is arranged, so that a plurality of p-type regions with different impurity concentrations (in the semiconductor substrate 30) are arranged. Figure 1 and Figure 3 Only p - The molded region 22 is a voltage-resistant structure having a substantially rectangular planar shape surrounding the active region 10 .

[0062] In addition, a field limiting ring (FLR: Field Limiting Ring (second second conductivity type region)) 21 is disposed in the connection region 20a of the edge termination region 20. The FLR 21 is a substantially rectangular shaped p-type ring surrounding the periphery of the active region 10. + The edge terminal region 20 extends outward from the connection region 20a of the edge terminal region 20 and is connected to the p - FLR 21 can also be connected to the p + The zone 13 extends in a stripe shape and has a long side in the same direction as the p + The mold area 13 is connected.

[0063] The connection region 20a of the edge termination region 20 is a region between the active region 10 and the field oxide film 15 described later, and surrounds the active region 10 and connects the active region 10 to the voltage-resistant structure of the edge termination region 20. The voltage-resistant structure of the edge termination region 20 refers to a portion of the edge termination region 20 from the inner end of the field oxide film 15 to the end of the semiconductor substrate 30 (chip end), and is configured with a JTE structure and / or n + A predetermined voltage-withstanding structure such as a type channel stop region (not shown) is provided.

[0064] The front electrode 14 is disposed on the front surface of the semiconductor substrate 30 in the active region 10. - Type drift region 12 and p + Type area 13 is connected to n - Type drift region 12 and p + The semiconductor substrate 30 is electrically connected to the die region 13. A passivation film (not shown) is provided on the front surface of the semiconductor substrate 30. The passivation film functions as a protective film for protecting the device structure on the front side of the semiconductor substrate 30 and the front electrode 14.

[0065] The passivation film is provided with an opening that exposes a portion of the front electrode 14. The portion of the front electrode 14 exposed in the opening of the passivation film functions as a bonding pad. The bonding pad is arranged, for example, at the center of the semiconductor substrate 30. When current is supplied to the bonding pad, an aluminum (Al) wire, which is the most common wiring connection and is omitted from the illustration, is bonded (joined) to the bonding pad.

[0066] Next, the cross-sectional structure of the silicon carbide semiconductor device 40 according to Embodiment 1 is described. As described above, the silicon carbide semiconductor device 40 according to Embodiment 1 has the SBD structure and the JBS structure of the silicon carbide diode in the active region 10 of the semiconductor substrate 30 made of silicon carbide, and has the JTE structure as a withstand voltage structure in the edge termination region 20.

[0067] The semiconductor substrate 30 is formed of silicon carbide. + On the front surface of the type starting substrate 11, there is stacked a layer of n- Type drift region 12 n - The epitaxial substrate of the type epitaxial layer. + Type starting substrate 11 is n + The semiconductor substrate 30 is n - The main surface of the drift region 12 side (becomes n - Type drift region 12 n - The surface of the n-type epitaxial layer is set as the front side, and the n + The main surface (n + The back side of the starting substrate 11 is set as the back side.

[0068] In the active region 10, one or more p-type semiconductor substrates constituting a JBS structure are selectively provided on the surface region of the front side of the semiconductor substrate 30. + Type area 13. p + The region 13 is disposed between the front surface of the semiconductor substrate 30 and the n - Type drift region 12. + The type region 13 is exposed on the front surface of the semiconductor substrate 30 and is connected to the n - The drift region 12 is connected.

[0069] In the edge termination region 20, the FLR 21 and one or more p-type regions (here, one: p) forming a JTE structure are selectively provided on the surface region of the front side of the semiconductor substrate 30. - Type area 22) and n + The FLR 21 is disposed in the entire connection region 20a of the edge termination region 20 and extends outward from the connection region 20a to contact the p - The active region 10 is located further inward than the inner end of the FLR 21 .

[0070] p - The die region 22 is disposed outside the FLR 21 separately from the connection region 20a of the edge termination region 20 and is adjacent to the FLR 21. + Type channel stop region and p - The molded area 22 is separately arranged at a ratio of p - The molded area 22 is located further outward. + The channel stopper region is exposed at an end portion (chip end portion) of the semiconductor substrate 30 .

[0071] FLR 21, p - Type area 22 and n + The channel stop region is disposed between the front surface of the semiconductor substrate 30 and the n - Between the drift region 12. FLR 21, p - Type area 22 and n +The channel stopper region is exposed on the front surface of the semiconductor substrate 30 and is connected to the n - The FLR 21 and p - Type area 22 and n + The depth of the channel stop region can be as large as, for example, p + The depth of the profiled areas 13 is the same.

[0072] The front surface of the semiconductor substrate 30 is covered with a field oxide film 15. The field oxide film 15 may be, for example, a laminated film in which a thermal oxide film and a deposited oxide film are sequentially laminated. The thermal oxide film can improve the adhesion between the semiconductor substrate 30 and the field oxide film 15. By making the field oxide film 15 include the deposited oxide film, the field oxide film 15 can be formed in a shorter time than when all the field oxide films 15 are made of thermal oxide films.

[0073] The field oxide film 15 is provided with a contact hole 15a that exposes almost the entire surface of the front surface at the active region 10 of the semiconductor substrate 30. The sidewall of the contact hole 15a of the field oxide film 15 (the inner side surface of the field oxide film 15) is substantially orthogonal to, for example, the front surface of the semiconductor substrate 30. The contact hole 15a of the field oxide film 15 is provided in the entire region from the active region 10 to the connection region 20a of the edge termination region 20.

[0074] The contact hole 15a of the field oxide film 15 exposes the n in the active region 10. - Type drift region 12 and p + The field oxide film 15 includes a contact hole 15a of the field oxide film 15 and a front electrode 14 that functions as an anode electrode.

[0075] The front electrode 14 has a stacked structure in which a titanium film 31 and an aluminum alloy film (metal electrode film containing aluminum) 32 are stacked in sequence. In addition, the front electrode 14 has a bottom layer of a nickel silicide (NiSi) film 33 (33a, 33b) selectively provided between the front surface of the semiconductor substrate 30 and the titanium film 31. The nickel silicide film 33 contains aluminum. The nickel silicide film 33 may also contain carbon (C). The front electrode 14 may extend outward on the field oxide film 15.

[0076] The titanium film 31 is provided on the entire front surface of the semiconductor substrate 30 within the contact hole 15a and is in contact with the n - The titanium film 31 is in contact with the n type drift region 12. - The junction position of the drift region 12 is formed with the n -The titanium film 31 may be extended outward on the field oxide film 15, and may be terminated at a position opposite to the FLR 21 in the depth direction, for example.

[0077] The aluminum alloy film 32 covers the entire surface of the titanium film 31 and is electrically connected to the titanium film 31, and is electrically connected to the nickel silicide film 33 via the titanium film 31. The aluminum alloy film 32 may extend to the outside of the titanium film 31 on the field oxide film 15, for example, in the depth direction. - The aluminum alloy film 32 is sealed at a position opposite to the mold region 22. The aluminum alloy film 32 is, for example, an aluminum silicide (AlSi) film. An aluminum film may be provided instead of the aluminum alloy film 32.

[0078] The nickel silicide film 33 has a p + A first nickel silicide film 33a is provided between the p-type region 13 and the titanium film 31, and a second nickel silicide film 33b is provided between the FLR 21 and the titanium film 31. The first nickel silicide film 33a is provided between the p-type region 13 and the titanium film 31. + The first nickel silicide film 33a has the function of increasing the amount of current (extracted amount) drawn from the semiconductor substrate 30 to the front electrode 14 when a surge voltage is applied and the surge current generated in the semiconductor substrate 30 and flowing in the forward direction increases, thereby improving the surge current tolerance.

[0079] The first nickel silicide film 33a may be provided on a surface region of the front surface of the semiconductor substrate 30. The first nickel silicide film 33a may be provided on the surface region of the front surface of the semiconductor substrate 30. + The die region 13 is adjacent to the front surface of the semiconductor substrate 30 and protrudes from the front surface of the semiconductor substrate 30 in a direction away from the front surface of the semiconductor substrate 30 .

[0080] Figure 5 It is shown that Figure 3 A cross-sectional view of the detailed structure of the area S surrounded by the dotted line. Figure 1 p + The same is true for the position where the first nickel silicide film 33a is provided on the mold region 13. Figure 5 As shown, the width w2a of the first nickel silicide film 33a is narrower than that of p + The width w2a of the first nickel silicide film 33a is equal to the width w1 of the p-type region 13. + The width w4 of one side of the difference in the width w1 of the die region 13 is preferably 0.1 μm or more and 5.0 μm or less. + The width w1 of the molded region 13 is narrow, so that the p + Type region 13. Thus, p + A high-resistance Schottky junction is formed between the type region 13 and the titanium film 31.

[0081] The active region 10 is composed of the following: a high resistance junction region 80, which is a titanium film 31 and a p-type junction region 80 forming a JBS structure. + The stripe-shaped region 82 is in contact with the titanium film 31 and the first nickel silicide film 33a; the ohmic region 81 is a region where the titanium film 31 contacts the first nickel silicide film 33a and has a lower resistance than the high resistance junction region 80; the Schottky region 82 is a region where the titanium film 31 and the n - The active region 10 is a stripe-shaped region that contacts the p-type drift region 12 and has a lower resistance than the ohmic region 81. + The stripe extension direction of the type region 13 is a period consisting of two high resistance junction regions 80 connected to the ends of the ohmic region 81 in the vertical direction and the Schottky region 82. Figure 2A , 2B The n shown - The ohmic region 81 may be in the shape of a rectangle that is shorter in the horizontal direction than in the vertical direction, such as the drift region 12. In addition, the ohmic region 81 may also be in the shape of a dot. The dot shape refers to Figure 2B and Figure 4B The nickel silicide film 33 (ohmic region 81) is in a rectangular shape with substantially the same length in the horizontal direction and in the vertical direction as shown in FIG. In the case of a dot shape, the interval between the ohmic regions 81 (nickel silicide film 33) is preferably a narrow interval. For example, the interval is preferably 5 μm or less.

[0082] By adopting such a periodic structure, the ohmic regions 81 can be uniformly and densely arranged throughout the active region 10. Therefore, when a high surge current flows in the forward direction in the semiconductor substrate, the surge current can be dispersed, and the IFSM characteristics can be improved.

[0083] In addition, if Figure 2A , 2B as well as Figure 4A , 4B As shown, p + The molded area 13 and the guard ring set in the edge termination area 20 (in Figure 2A , 2B as well as Figure 4A , 4B In addition, when the guard ring is provided with the second nickel silicide film 33 b, the first nickel silicide film 33 a of the ohmic region 81 can be connected to the second nickel silicide film 33 b. That is, the ohmic region 81 and the high resistance bonding region 80 can be connected to the edge termination region 20.

[0084] In addition, if Figure 1 As shown, in the active region 10, relative to p +The stripes of the type region 13 extend in a vertical direction, and high resistance junction regions 80 are provided on both sides of the ohmic region 81. In the active region 10, the ohmic regions 81 are not connected to each other. That is, the high resistance junction region 80 and the Schottky region 82 exist between the adjacent first nickel silicide films 33a. In this way, in the first embodiment, there is no wide ohmic region such as stripes spanning multiple ohmic regions 81. Therefore, since the area of ​​the ohmic region 81 does not increase, the Vf characteristic can be maintained.

[0085] Such a structure can be formed by using nickel silicide generated by reacting a metal material film formed by stacking nickel, aluminum, and nickel in this order with a surface area of ​​the semiconductor substrate 30 through heat treatment. The low-resistance first nickel silicide film 33a is formed by self-matching (self-alignment), and the self-matching is performed by etching away the non-silicided portion of the metal material film (except for the portion other than the heated reaction layer). By using a metal material film formed by stacking nickel, aluminum, and nickel in this order, a low-resistance p-type ohmic electrode is formed. In addition, by forming an ohmic electrode on the inner side of a JBS structure with a width of several μm by self-alignment, the Vf characteristic can be maintained. In this way, since the low-resistance ohmic region 81 can be formed without reducing the area of ​​the Schottky region 82, the IFSM characteristic can be improved while maintaining the Vf characteristic.

[0086] In addition, by making the width w2a of the first nickel silicide film 33a narrower than p + By reducing the width w1 of the molded region 13, a design margin for improving the alignment accuracy of the mask used when forming the first nickel silicide film 33a can be obtained. As a result, the first nickel silicide film 33a can be arranged with good positional accuracy at a position adjacent to the p-type region 13 in the depth direction. + The position opposite to the mold area 13.

[0087] Figure 6 FIG. 1 is a plan view showing the chip periphery and the chip center of the silicon carbide semiconductor device according to Embodiment 1 when viewed from the front side of the semiconductor substrate. Figure 6 In the description of the chip periphery and the chip center, the structure of the silicon carbide semiconductor device 40 is omitted. The chip center 60 is an area set in the center of the chip, which can be an area on the central side of the chip from the center of the chip side toward the edge and is more than 1 / 4 and less than 3 / 4. The chip periphery 61 is an area set at the periphery of the chip, and is an area of ​​the silicon carbide semiconductor device excluding the chip center 60. In more detail, if the x direction is from the center of the chip (at Figure 6The length from the point where the single-dot dash line in the x direction and the single-dot dash line in the y direction intersect to the end of the chip is set as L2, and the length from the center of the chip in the x direction to the end of the chip central portion 60 is set as L1, then 1 / 4≤L1 / L2≤3 / 4 is satisfied. Similarly for the y direction, if the length from the center of the chip in the y direction to the end of the chip is set as L4, and the length from the center of the chip in the y direction to the end of the chip central portion 60 is set as L3, then 1 / 4≤L3 / L4≤3 / 4 is satisfied.

[0088] In implementation mode 1, according to n - The impurity concentration of the type drift region 12 is different, and the position of the nickel silicide film 33 is different. - The impurity concentration of the drift region 12 is 1.0×10 15 / cm 3 More than and less than 1.0×10 16 / cm 3 In the case of a low concentration, the nickel silicide film 33 is provided more in the chip center portion 60 than in the chip periphery portion 61. + For example, the ohmic region 81 of the ohmic junction of the die region 13 is provided more in the center of the chip than in the periphery of the chip. Figure 4A and Figure 4B As shown, the nickel silicide film 33 may be provided in the central portion of the chip and the ohmic region 81 may be provided only in the central portion of the chip so that the ohmic region 81 is more in the central portion of the chip than in the peripheral portion of the chip.

[0089] On the other hand, in n - The impurity concentration of the drift region 12 is 1.0×10 16 / cm 3 Above and 9.0×10 16 / cm 3 In the case of a high concentration of , the nickel silicide film 33 is provided more at the periphery of the chip than at the center of the chip, and the ohmic region 81 is provided more at the periphery of the chip than at the center of the chip. Figure 2A and Figure 2B As shown, the nickel silicide film 33 may be provided at the chip periphery and the ohmic region 81 may be provided only at the chip periphery, so that the ohmic region 81 may be more at the chip periphery than at the chip center.

[0090] Alternatively, the nickel silicide film 33 may be formed as Figure 2A and Figure 4A Like the stripe shape, or Figure 2B and Figure 4B Therefore, the ohmic region 81 may be in a stripe shape or a dot shape.

[0091] Thus, in the first embodiment, by- By changing the impurity concentration of the type drift region 12 to change the location of the ohmic region 81, the current becomes easier to disperse to the entire chip during surges, which can suppress the increase in local heat. - When the impurity concentration of the drift region 12 is high, the surge current is concentrated directly below the wire or in the center of the chip. Therefore, by providing more ohmic regions 81 in the chip periphery 61, it is possible to prevent damage from occurring in the center of the chip. - When the impurity concentration of the drift region 12 is low, surge current is concentrated on the periphery of the chip. Therefore, by providing more ohmic regions 81 in the chip center portion 60 , it is possible to prevent damage from occurring on the periphery of the chip.

[0092] In addition, in n - When the impurity concentration of the type drift region 12 is high, the high resistance junction region 80 is relatively close to the p + The area ratio of the die area 13 is preferably 35% or more, more preferably 35% or more and 90% or less. In addition, in the chip peripheral portion 61, the area ratio of the high resistance bonding area 80 to the active area 10 is preferably 15% or more and 40% or less. In addition, in the chip peripheral portion 61, the area ratio of the high resistance bonding area 80 relative to the chip area is preferably 15% or more and 40% or less. By making the area ratio within these ranges, it is possible to take into account both the improvement of surge current tolerance and the low Vf characteristics.

[0093] Furthermore, in n - When the impurity concentration of the type drift region 12 is low, in the chip center portion 60, the high resistance junction region 80 is relatively + The area ratio of the die area 13 is preferably 35% or more, more preferably 35% or more and 90% or less. In addition, in the chip center 60, the area ratio of the high resistance bonding area 80 to the active area 10 is preferably 15% or more and 40% or less. In addition, in the chip center 60, the area ratio of the high resistance bonding area 80 to the chip area is preferably 15% or more and 40% or less. By making the area ratio within these ranges, it is possible to achieve both an improvement in surge current tolerance and a low Vf characteristic.

[0094] Here, the high resistance junction region 80 is + The area ratio of the die region 13 is the area of ​​the high resistance bonding region 80 / (p +The area ratio of the high resistance bonding region 80 to the active region 10 is the area of ​​the high resistance bonding region 80 / (the area of ​​the Schottky region 82+the area of ​​the ohmic region 81+the area of ​​the high resistance bonding region 80). Similarly, the area ratio of the high resistance bonding region 80 to the chip area is obtained by the area of ​​the high resistance bonding region 80 / (the area of ​​the Schottky region 82+the area of ​​the ohmic region 81+the area of ​​the high resistance bonding region 80+the area of ​​the edge termination region 20).

[0095] The second nickel silicide film 33b is an ohmic electrode ohmically bonded to the FLR 21. The second nickel silicide film 33b can be provided on almost the entire surface of the surface of the FLR 21 in the connection region 20a of the edge termination region 20. The second nickel silicide film 33b is in contact with the field oxide film 15 at the side wall of the field oxide film 15. The second nickel silicide film 33b has the function of increasing the amount of surge current drawn and improving the surge current tolerance similarly to the first nickel silicide film 33a.

[0096] By providing the second nickel silicide film 33b, an ohmic electrode having the same function as the first nickel silicide film 33a can be arranged in the connection region 20a of the edge terminal region 20. Thus, even when the chip size (the plane size parallel to the front surface of the semiconductor substrate 30) is reduced, the ohmic bonding area between the front electrode 14 and the semiconductor substrate 30 required to obtain a predetermined surge current tolerance can be fully ensured in the total bonding area of ​​the first nickel silicide film 33a, the second nickel silicide film 33b and the semiconductor substrate 30.

[0097] In addition, the ohmic junction area between the FLR 21 and the second nickel silicide film 33b can be maximized by extending the second nickel silicide film 33b outward to a position where it contacts the field oxide film 15. Thus, the width w2b of the second nickel silicide film 33b is substantially the same as the width w3 of the connection region 20a of the edge termination region 20, and the second nickel silicide film 33b can be provided on almost the entire surface of the FLR 21 in the connection region 20a of the edge termination region 20 as described above.

[0098] In addition, by making the width w2b of the second nickel silicide film 33b substantially the same as the width w3 of the connection region 20a of the edge termination region 20, the width w2a of the first nickel silicide film 33a is substantially the same as the width w3 of the connection region 20a of the edge termination region 20. + Similarly, when the width w1 of the second nickel silicide film 33b is substantially the same as that of the second nickel silicide film 33a, the forward voltage of the silicon carbide diode can be reduced. The width w2b of the second nickel silicide film 33b can be narrower than the width w3 of the connection region 20a of the edge termination region 20, for example. The reason is the same as that the width w2a of the first nickel silicide film 33a can be narrower than the width w3 of the connection region 20a of the edge termination region 20. + The reason why the width w1 of the molded area 13 is narrow is the same.

[0099] The second nickel silicide film 33 b is provided in a surface region of the front surface of the semiconductor substrate 30 , is in contact with the FLR 21 in the depth direction, and may protrude from the front surface of the semiconductor substrate 30 in a direction away from the front surface of the semiconductor substrate 30 .

[0100] The front surface of the semiconductor substrate 30 is covered with a field oxide film 15 except for the portion in contact with the front electrode 14. A passivation film made of polyimide is provided on the outermost surface of the front surface of the semiconductor substrate 30. + The upper portion of the channel stop region may be arranged to be aligned with the n + The channel stopper electrode may be, for example, an aluminum alloy film formed simultaneously with the aluminum alloy film 32.

[0101] The passivation film is a protective film that protects the front electrode 14 and the field oxide film 15. The passivation film is provided with an opening that exposes a portion of the aluminum alloy film 32 in the active region 10. The portion of the front electrode 14 exposed in the opening of the passivation film functions as a bonding pad. + The entire surface of the back surface of the starting substrate 11 is provided with a back electrode (second electrode) 19, which is electrically connected to the n + Type starting substrate 11.

[0102] The silicon carbide semiconductor device 40 of the first embodiment is manufactured in the same manner as the manufacturing method described in Patent Document 1. For example, it is formed as follows. First, as n + A starting substrate (semiconductor wafer) 11, for example, a 5×10 18 / cm 3 Next, a four-layer hexagonal silicon carbide (4H-SiC) substrate with nitrogen (N) is prepared. + On the front side of the starting substrate 11, a n - The drift region 12 is doped with 1.8×10 16 / cm 3 The nitrogen n - type epitaxial layer to form a semiconductor substrate 30.

[0103] Next, by photolithography and ion implantation of p-type impurities such as aluminum, one or more p-type impurities constituting a JBS structure are selectively formed in the active region 10 and in the front surface region of the semiconductor substrate 30. + The type region 13 and the FLR 21. Next, after the entire front surface of the semiconductor substrate 30 is covered with a carbon (C) protective film to protect it, the ion-implanted impurities are activated by heat treatment.

[0104] Next, an oxide film is formed on the entire front surface of the semiconductor substrate 30. Next, the oxide film is selectively removed by photolithography and etching to form an opening. Next, a metal material film is formed on the surface from the surface of the oxide film to the front surface (surface) of the semiconductor substrate 30 in the opening of the oxide film by, for example, sputtering.

[0105] Then, the metal material film is first sintered by heat treatment to generate an aluminum-nickel-silicon (Al-Ni-Si) compound in the opening of the oxide film. Next, the excess metal (excess portion) on the oxide film and in the opening of the oxide film is removed.

[0106] Next, the Al-Ni-Si compound is subjected to a second sintering by heat treatment. By this heat treatment, nickel silicide is generated in the Al-Ni-Si compound, so that the Al-Ni-Si compound becomes a nickel silicide film 33 that is ohmically bonded to the semiconductor substrate 30 .

[0107] In the first embodiment, the position of the opening of the oxide film is changed by the manufacturing method described in Patent Document 1, so that - When the impurity concentration of the type drift region 12 is high, a larger amount of nickel silicide film 33 is provided at the chip periphery than at the chip center, and a larger amount of ohmic region 81 is formed at the chip periphery 61 than at the chip center 60. - When the impurity concentration of the drift region 12 is low, more nickel silicide film 33 is set in the central part 60 of the chip than in the peripheral part 61 of the chip, and as for the ohmic region 81, the ohmic region 81 in the central part 60 of the chip is formed to be larger than the ohmic region 81 in the peripheral part 61 of the chip.

[0108] Next, etching is performed using the resist film as a mask to form a contact hole 15a that penetrates the field oxide film 15 in the depth direction. Next, a titanium film 31 is formed on the entire surface from the surface of the field oxide film 15 to the front surface of the semiconductor substrate 30 in the contact hole 15a by a physical vapor deposition method (PVD) such as sputtering. Next, photolithography and etching are performed to leave the titanium film 31 only in the contact hole 15a.

[0109] Next, the titanium film 31 is sintered by heat treatment at a temperature of about 500° C. for about 10 minutes. Next, an aluminum alloy film having a thickness of about 5 μm is formed on the entire surface from the surface of the titanium film 31 to the surface of the field oxide film 15 by a physical vapor deposition method such as sputtering. Next, the aluminum alloy film is selectively removed by photolithography and etching, and remains on the surface of the titanium film 31 as the aluminum alloy film 32 that becomes the front electrode 14.

[0110] Next, a physical vapor deposition method such as sputtering is used to deposit a layer of nanostructured carbon on the back surface (n) of the semiconductor substrate 30. + After nickel and titanium are formed on the entire surface of the semiconductor substrate 30 (the back surface of the starting substrate 11), a back electrode 19 is formed by laser annealing. After that, after removing the protective film on the front surface of the semiconductor substrate 30, the semiconductor substrate 30 is singulated (cut) into individual chips, thereby completing the silicon carbide semiconductor device 40 of the first embodiment.

[0111] As described above, according to Embodiment 1, in n - When the impurity concentration of the drift region is low, the surge current is concentrated on the periphery of the chip. Therefore, by providing more ohmic regions in the center of the chip, it is possible to prevent damage to the periphery of the chip. - When the impurity concentration of the drift region is high, the surge current is concentrated just below the wire or in the center of the chip. Therefore, by providing more ohmic regions on the periphery of the chip, damage can be prevented from occurring in the center of the chip.

[0112] (Implementation method 2) Next, a semiconductor device according to a second embodiment will be described. Figure 7 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the second embodiment when the drift layer has a low concentration. Fig. 8A FIG. 2 is a diagram showing the second embodiment as viewed from the front side of the semiconductor substrate. Figure 7 A plan view of the layout obtained by a silicon carbide semiconductor device. Figure 8B FIG. 2 is a diagram showing the second embodiment as viewed from the front side of the semiconductor substrate. Figure 7 A plan view of another layout obtained by a silicon carbide semiconductor device. Fig. 9 This is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the second embodiment when the drift layer has a high concentration. Fig. 10A FIG. 2 is a diagram showing the second embodiment as viewed from the front side of the semiconductor substrate. Fig. 9 A plan view of the layout obtained by a silicon carbide semiconductor device. Fig. 10B The second embodiment is viewed from the front side of the semiconductor substrate. Fig. 9 A plan view of another layout obtained by a silicon carbide semiconductor device.

[0113] Fig. 8A , Figure 8B , Fig. 10A and Fig. 10B are the ps constituting the JBS structure. + A plan view showing an example of the layout of the die region 13, the field limiting ring 21, and the nickel silicide film 33. Figure 7 The cross-sectional view of the silicon carbide semiconductor device shown corresponds to Fig. 8A , Figure 8B A-A' section. Fig. 9 The cross-sectional view of the silicon carbide semiconductor device shown corresponds to Fig. 10A , Fig. 10B A-A' section.

[0114] In the second embodiment, compared with the conventional silicon carbide semiconductor device 140 (see Fig.12 ) Similarly, the difference from the first embodiment is that the nickel silicide film 33 is provided on the p + The type region 13 and the field limiting ring 21. In the second embodiment, according to n - The contact resistance of the nickel silicide film 33 is different depending on the impurity concentration of the type drift region 12. The structure of the second embodiment except the nickel silicide film 33 is the same as that of the first embodiment.

[0115] In n - The impurity concentration of the drift region 12 is 1.0×10 15 / cm 3 More than and less than 1.0×10 16 / cm 3 In the case of low concentrations, such as Figure 7 , Fig. 8A and Figure 8B As shown, the nickel silicide film 33 is provided as the high resistance ohmic region 81 b in the chip peripheral portion 61 , and the nickel silicide film 33 is provided as the low resistance ohmic region 81 a in the chip central portion 60 .

[0116] On the other hand, in n - The impurity concentration of the drift region 12 is 1.0×10 16 / cm 3 Above and 9.0×10 16 / cm 3 In the case of high concentrations, such as Fig. 9 , Fig. 10A and Fig. 10B As shown in FIG. 1 , a nickel silicide film 33 is provided as a low resistance ohmic region 81a in the chip periphery 61, and a nickel silicide film 33 is provided as a high resistance ohmic region 81b in the chip center 60. The contact resistance of the low resistance ohmic region 81a is 5×10 -5 Ω / cm 2 More than and less than 5×10 -4 Ω / cm 2 , the contact resistance of the high resistance ohmic region 81b is 5×10 -4 Ω / cm 2 Above and 5×10 -3 Ω / cm 2 the following.

[0117] Alternatively, the nickel silicide film 33 may be formed as Fig. 8A and Fig. 10A Like the stripe shape, or Figure 8B and Fig. 10B Therefore, the low resistance ohmic region 81a and the high resistance ohmic region 81b may be in a stripe shape or in a dot shape.

[0118] Thus, in the second embodiment, according to n - The impurity concentration of the type drift region 12 and the contact resistance of the nickel silicide film 33 of the ohmic region 81 are different. As a result, the current becomes easier to be dispersed throughout the chip during a surge, and local heat generation can be suppressed. - When the impurity concentration of the type drift region 12 is low, since the surge current is concentrated on the periphery of the chip, the nickel silicide film 33 as the low resistance ohmic region 81a is provided in the chip center 60 to prevent damage from occurring on the periphery of the chip. - When the impurity concentration of the drift region 12 is high, surge current is concentrated just below the wire or in the center of the chip. Therefore, by providing a nickel silicide film 33 as a low-resistance ohmic region 81a on the periphery 61 of the chip, damage in the center of the chip can be prevented.

[0119] Similar to the first embodiment, the silicon carbide semiconductor device 40 of the second embodiment is manufactured in the same manner as the manufacturing method described in Patent Document 1. In the second embodiment, the low resistance ohmic region 81a and the high resistance ohmic region 81b are formed by changing the temperature at which the metal material film containing Al and Ni is first sintered. The higher the Si composition ratio of the nickel silicide, the lower the resistance. For example, NiSi x (x≥2) has a lower resistance than NiSi. Therefore, the low resistance ohmic region 81a is formed to have a higher Si composition ratio than the high resistance ohmic region 81b by annealing at a temperature higher than the annealing temperature of the high resistance ohmic region 81b.

[0120] In n - When the impurity concentration of the drift region 12 is low, the annealing temperature is set to a low temperature of 800°C to less than 1000°C in the chip periphery 61 to form a nickel silicide film 33 as a high resistance ohmic region 81b, and the annealing temperature is set to a high temperature of 1000°C to less than 1200°C in the chip center 60 to form a nickel silicide film 33 as a low resistance ohmic region 81a.

[0121] On the other hand, in n -When the impurity concentration of the drift region 12 is high, the annealing temperature is set to a high temperature of not less than 1000°C and not more than 1200°C in the chip periphery 61 to form a nickel silicide film 33 as a low resistance ohmic region 81a, and the annealing temperature is set to a low temperature of not less than 800°C and not more than 1000°C in the chip center 60 to form a nickel silicide film 33 as a high resistance ohmic region 81b.

[0122] In the chip center 60 and the chip periphery 61, the annealing temperature can be changed by changing the laser irradiation conditions during laser annealing. Alternatively, low-temperature annealing can be performed in a furnace and high-temperature annealing can be performed by laser annealing. In addition, although the output of laser irradiation varies depending on the metal, etc., it is preferably 1 to 5 J / cm 2 , more preferably 2 to 3 J / cm 2 .

[0123] As described above, according to Embodiment 2, in n - When the impurity concentration of the drift region is low, the surge current is concentrated on the periphery of the chip. Therefore, by providing a nickel silicide film as a low-resistance ohmic region directly below the wire or in the center of the chip, damage to the periphery of the chip can be prevented. - When the impurity concentration of the drift region is high, surge current is concentrated in the center of the chip. Therefore, by providing a nickel silicide film as a low-resistance ohmic region on the periphery of the chip, damage in the center of the chip can be prevented.

[0124] In Embodiments 1 and 2, an aluminum-nickel-silicon (Al-Ni-Si) compound is generated in the opening of the oxide film by first sintering the metal material film, and a nickel silicide is generated in the Al-Ni-Si compound by second sintering the Al-Ni-Si compound. Therefore, the metal material film may contain Ni for silicide formation, and may also contain other Al, Mo (molybdenum), or Ti (titanium) for forming carbides.

[0125] As described above, the present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present disclosure, and can be applied to a semiconductor device including an ohmic electrode that forms an ohmic junction with a p-type region arranged in a predetermined pattern.

[0126] Specifically, for example, the present disclosure provides a method for making a p-type region (or a p-type region arranged between the p-type region and the main surface of a semiconductor substrate) + It is useful to provide a silicon carbide semiconductor device having a structure in which the contact resistance between a p-type contact region and an ohmic electrode is reduced, and a semiconductor device having a structure in which an ohmic electrode ohmically bonded to a p-type region is in contact with an oxide film.

[0127] Industrial Applicability As described above, the semiconductor device and the method for manufacturing the semiconductor device of the present disclosure are useful for power semiconductor devices used in power conversion devices, power supply devices for various industrial machines, and the like.

Claims

1. A semiconductor device, characterized in that: have: An active region disposed on a semiconductor substrate; A terminal region, which is disposed on the semiconductor substrate and surrounds the active region; A first conductive type region is disposed inside the semiconductor substrate and exposed on a first main surface of the semiconductor substrate; A second conductive type region, which is in contact with the first conductive type region in the active region and is selectively disposed in a surface region of the first conductive type region on the first main surface side of the semiconductor substrate; as well as a silicide film that is in ohmic contact with a portion of the second conductive type region; The impurity concentration in the first conductive region is 1.0×10 15 / cm 3 More than and less than 1.0×10 16 / cm 3 In the case of a low concentration, the area or number of the silicide film is set larger at the center of the active region, The impurity concentration in the first conductive region is 1.0×10 16 / cm 3 Above and 9.0×10 16 / cm 3 In the case of the following high concentration, the area or number of the silicide film is set larger at the position of the active region close to the terminal region.

2. The semiconductor device according to claim 1, wherein: have: A first electrode is provided on the first main surface of the semiconductor substrate; and a second electrode disposed on the second main surface of the semiconductor substrate, The active area of ​​the semiconductor substrate has: a Schottky region formed by the first electrode and the first conductive type region; an ohmic region formed by the first electrode and the silicide film; and A high resistance junction region is formed by the first electrode and the second conductive type region.

3. The semiconductor device according to claim 1 or 2, characterized in that: The semiconductor substrate has: a chip central portion, which is disposed in the center of the active area; and a chip peripheral portion surrounding the central portion of the chip, The chip center portion is a region on the center side that is greater than 1 / 4 and less than 3 / 4 of the distance from the center of each side of the semiconductor device to the end of the side.

4. The semiconductor device according to claim 3, wherein: When the impurity concentration of the first conductive type region is the low concentration, The area or number of the ohmic regions provided in the central portion of the chip in the active region is set to be larger than the area or number of the ohmic regions in the peripheral portion of the chip, When the impurity concentration of the first conductive type region is the high concentration, The area or number of the ohmic regions provided at the outer periphery of the chip is set to be larger than the area or number of the ohmic regions provided at the central portion of the chip.

5. The semiconductor device according to claim 2, wherein: In the active region, the high resistance junction region is provided between the ohmic region and the Schottky region, The high-resistance junction region provided between the ohmic region and the Schottky region has a width of 0.1 μm or more and 5.0 μm or less.

6. The semiconductor device according to claim 3, wherein: When the impurity concentration of the first conductive type region is the low concentration, an area ratio of the high resistance junction region to the second conductive type region in the chip center portion of the active region is 35% or more.

7. The semiconductor device according to claim 3, wherein: When the impurity concentration of the first conductive type region is the low concentration, in the chip center portion of the active region, an area ratio of the high resistance junction region to the active region is 15% or more and 40% or less.

8. The semiconductor device according to claim 3, wherein: When the impurity concentration of the first conductive type region is the high concentration, an area ratio of the high resistance junction region to the second conductive type region in the chip periphery of the active region is 35% or more.

9. The semiconductor device according to claim 3, wherein: When the impurity concentration of the first conductive type region is the high concentration, in the chip periphery of the active region, an area ratio of the high resistance junction region to the active region is 15% or more and 40% or less.

10. The semiconductor device according to claim 1, wherein: The silicide film contains nickel, silicon, and aluminum.

11. A semiconductor device, characterized in that: have: An active region disposed on a semiconductor substrate; A terminal region, which is disposed on the semiconductor substrate and surrounds the active region; A first conductive type region is disposed inside the semiconductor substrate and exposed on a first main surface of the semiconductor substrate; A second conductive type region, which is in contact with the first conductive type region in the active region and is selectively disposed in a surface region of the first conductive type region on the first main surface side of the semiconductor substrate; as well as a silicide film that is in ohmic contact with a portion of the second conductive type region; The impurity concentration in the first conductive region is 1.0×10 15 / cm 3 More than and less than 1.0×10 16 / cm 3 In the case of low concentration, the contact resistance is set to 5×10 -4 Ω / cm 2 Above and 5×10 -3 Ω / cm 2 The silicide film is provided at the center of the active region with a contact resistance of 5×10 -5 Ω / cm 2 More than and less than 5×10 -4 Ω / cm 2 the silicide film, The impurity concentration in the first conductive region is 1.0×10 16 / cm 3 Above and 9.0×10 16 / cm 3 In the case of a high concentration below 50%, the contact resistance is set to 5×10 -5 Ω / cm 2 More than and less than 5×10 -4 Ω / cm 2 The silicide film is provided at the center of the active region with a contact resistance of 5×10 -4 Ω / cm 2 Above and 5×10 -3 Ω / cm 2 The silicide film described below.

12. A method for manufacturing a semiconductor device, characterized in that: A method for manufacturing a semiconductor device having an active region and a termination region surrounding the active region on a semiconductor substrate, the method comprising: In a first step, a first conductive type region constituting a first main surface of the semiconductor substrate is formed inside the semiconductor substrate; A second step of selectively forming a first second conductivity type region in contact with the first conductivity type region between the first main surface of the semiconductor substrate and the first conductivity type region in the active region; The third step is to form a second second conductivity type region surrounding the active region in the terminal region; A fourth step is to form an oxide film covering the first conductive type region and the first second conductive type region on the first main surface of the semiconductor substrate; A fifth step is to selectively remove the oxide film and form a first opening in the oxide film to expose the first second conductivity type region; In a sixth step, a nickel film, an aluminum film, and a metal film having a melting point higher than that of aluminum, which are in contact with the first main surface of the semiconductor substrate, are sequentially stacked in the first opening of the oxide film to form a metal material film; In a seventh step, the metal material film is reacted with the semiconductor substrate by a first heat treatment, and a compound layer is self-matchedly generated on the first main surface of the semiconductor substrate at the first opening of the oxide film, using the oxide film as a mask; An eighth step, after the seventh step, removing the remaining portion of the metal material film except the compound layer; A ninth step, after the eighth step, generating nickel silicide inside the compound layer by a second heat treatment at a temperature higher than that of the first heat treatment, thereby forming a silicide film that is ohmically bonded to the semiconductor substrate; a tenth step of removing the oxide film sandwiched by the silicide film after the ninth step, and forming a contact hole connecting all the first openings; an eleventh step of forming a first electrode by laminating a titanium film in contact with the first conductive type region and forming a Schottky bond with the first conductive type region and a metal electrode film containing aluminum in sequence on the first main surface of the semiconductor substrate inside the contact hole; and The twelfth step is to form a second electrode on the second main surface of the semiconductor substrate. In the seventh step, The impurity concentration in the first conductive region is 1.0×10 15 / cm 3 More than and less than 1.0×10 16 / cm 3 In the case of a low concentration of , at a position of the active region close to the terminal region, the temperature of the first heat treatment is set to a low temperature of 800° C. or higher and less than 1000° C., and a contact resistance of 5×10 -4 Ω / cm 2 Above and 5×10 -3 Ω / cm 2 The silicide film is formed at a position close to the center of the active region by setting the first heat treatment temperature to a high temperature of 1000° C. to 1200° C. to form a contact resistance of 5×10 -5 Ω / cm 2 More than and less than 5×10 -4 Ω / cm 2 the silicide film, The impurity concentration in the first conductive region is 1.0×10 16 / cm 3 Above and 9.0×10 16 / cm 3 In the case of a high concentration of 5×10 -5 Ω / cm 2 More than and less than 5×10 -4 Ω / cm 2 The silicide film is formed at a position close to the center of the active region, and the temperature of the first heat treatment is set to a low temperature of 800° C. or higher and lower than 1000° C., so as to form a contact resistance of 5×10 -4 Ω / cm 2 Above and 5×10 -3 Ω / cm 2 The silicide film described below.

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