Power semiconductor device and method for producing power semiconductor device

Abstract

The invention relates to a power semiconductor device and a method of producing a power semiconductor device. The power semiconductor device includes, in a single chip: a semiconductor body configured to conduct a load current between a first load terminal at a first side of the semiconductor body and a second load terminal at a second side of the semiconductor body; a drift region of a first conductivity type within the semiconductor body; trenches extending from the first side toward the second side, each trench including a trench electrode separated from the semiconductor body by a trench insulator; the table tops are transversely limited by the grooves and comprise a first type of table tops and a second type of table tops; and semiconductor structures, each comprising a series connection of: a first region of a first conductivity type coupled to or formed by the drift region; a second region of a second conductivity type; and a third region of the first conductivity type coupled to the first load terminal through at least one of the first ohmic resistor and the Zener diode.

Description

Technical Field

[0001] The present description relates to embodiments of a power semiconductor device and to embodiments of a method of producing a power semiconductor device. Background Art

[0002] Many functions of modern devices in automotive, consumer and industrial applications, such as converting electrical energy and driving electric motors or motors, rely on power semiconductor devices. For example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs) and diodes, to name a few, have been used in a variety of applications including but not limited to switches in power supplies and power converters.

[0003] A power semiconductor device typically includes a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device. The load current is typically conducted by means of an active region of the power semiconductor device. The active region is typically surrounded by an edge termination region that is terminated by the edge of the chip.

[0004] In the case of a controllable power semiconductor device, such as a transistor, the load current path can be controlled by means of an insulated electrode, usually referred to as a gate electrode. For example, upon receiving a corresponding control signal from a driver unit, for example via a control terminal of the device, the control electrode can set the power semiconductor device in one of a forward conducting state and a blocking state.

[0005] In addition, some devices provide reverse load current capability; that is, the active area of ​​the semiconductor body is further configured to conduct reverse load current along a reverse load current path between two load terminals of the device. For example, the RC (reverse current) IGBT is a representative of such a device. In the RC IGBT, a single chip combines the IGBT structure and the diode structure together.

[0006] Regardless of whether the device exhibits an RC configuration or not, the goal is generally to design a power semiconductor device such that it exhibits high robustness, ie, in handling overload conditions during which the load current temporarily exceeds the nominal load current, e.g. due to a short circuit condition or the like. Summary of the invention

[0007] The subject matter of the independent claims is set out. Features of the exemplary embodiments are defined in the dependent claims.

[0008] According to an embodiment, a power semiconductor device includes in a single chip: a semiconductor body configured to conduct a load current between a first load terminal at a first side of the semiconductor body and a second load terminal at a second side of the semiconductor body; a drift region of a first conductivity type in the semiconductor body; a trench extending from the first side toward the second side, each trench including a trench electrode separated from the semiconductor body by a trench insulator; a mesa laterally limited by the trench, wherein the mesa includes a first type mesa and a second type mesa; and a semiconductor structure. Each semiconductor structure includes a series connection of: a first region of a first conductivity type, which is coupled to or formed by the drift region; a second region of a second conductivity type; and a third region of the first conductivity type, which is coupled to the first load terminal through at least one of a first ohmic resistor and a Zener diode. Each first type mesa is configured for load current conduction, is electrically connected to the first load terminal, and is free of any of the semiconductor structures. The semiconductor structure is arranged in the second type mesa.

[0009] According to a further embodiment, a method for producing a power semiconductor device includes forming the following components in a single chip: a semiconductor body configured to conduct a load current between a first load terminal at a first side of the semiconductor body and a second load terminal at a second side of the semiconductor body; a drift region of a first conductivity type in the semiconductor body; trenches extending from the first side toward the second side, each trench including a trench electrode separated from the semiconductor body by a trench insulator; mesas laterally bounded by the trenches, wherein the mesas include first type mesas and second type mesas; and semiconductor structures. Each semiconductor structure includes a series connection of: a first region of a first conductivity type coupled to or formed by the drift region; a second region of a second conductivity type; and a third region of the first conductivity type coupled to the first load terminal via at least one of a first ohmic resistor and a Zener diode. Each first type mesa is configured for load current conduction, is electrically connected to the first load terminal, and is free of any of the semiconductor structures. The semiconductor structure is arranged in the second type mesa.

[0010] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The parts in the figures are not necessarily drawn to scale, but the emphasis is placed on illustrating the principles of the present invention. In addition, in the figures, similar reference numerals designate corresponding parts. In the drawings:

[0012] Figure 1 schematically and exemplarily illustrates a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments;

[0013] Figure 2 schematically and exemplarily illustrates a portion of a horizontal projection of a power semiconductor device according to one or more embodiments;

[0014] Figure 3 schematically and exemplarily illustrates a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments;

[0015] Figure 4 schematically and exemplarily illustrates a portion of a horizontal projection of a power semiconductor device according to one or more embodiments;

[0016] Figure 5 schematically and exemplarily illustrates a portion of a vertical cross-section of a power semiconductor device according to one or more embodiments;

[0017] FIG. 6 includes FIG. 6(B), FIG. 6(A), and FIG. 6(C), schematically and exemplarily illustrating three parts of a horizontal projection of a power semiconductor device according to some embodiments;

[0018] 7-9 each schematically and exemplarily illustrate a portion of a vertical cross-section of a power semiconductor device according to some embodiments;

[0019] Figure 10-19 each schematically and exemplarily illustrates a portion of a horizontal projection of a power semiconductor device according to some embodiments; and

[0020] Figure 20-2 5 each schematically and exemplarily illustrates a portion of a vertical cross section of a power semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0021] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.

[0022] In this regard, directional terms, such as "top", "bottom", "below", "front", "rear", "back", "in front of", "trailing", "above", etc., may be used with reference to the orientation of the figures being described. Because portions of the embodiments may be positioned in many different orientations, the directional terms are used for illustrative purposes and are in no way limiting. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description should not be read in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0023] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the drawings. Each example is provided as an explanation and is not meant to be limiting of the invention. For example, a feature illustrated or described as part of one embodiment may be used on or in combination with other embodiments to produce yet another embodiment. The invention is intended to include such modifications and variations. The examples are described using specific language, which should not be interpreted as limiting the scope of the appended claims. The figures are not drawn to scale and are for illustration purposes only. For clarity, the same elements or manufacturing steps have been designated by the same reference numerals in different drawings if not otherwise stated.

[0024] The term "horizontal" as used in this specification is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. This may be, for example, a surface of a semiconductor wafer or die or chip. For example, the first lateral direction X and the second lateral direction Y mentioned below may both be horizontal directions, wherein the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0025] The term "vertical" as used in this specification is intended to describe an orientation that is arranged substantially perpendicular to a horizontal surface (i.e., parallel to the normal direction of the surface of the semiconductor wafer / chip / die). For example, the extension direction Z mentioned below may be an extension direction that is perpendicular to both the first lateral direction X and the second lateral direction Y. The extension direction Z is also referred to herein as the "vertical direction Z".

[0026] In this specification, n-doping is referred to as the “first conductivity type” and p-doping is referred to as the “second conductivity type.” Alternatively, the opposite doping relationship may be employed, such that the first conductivity type may be p-doped and the second conductivity type may be n-doped.

[0027] In the context of this specification, the terms "in ohmic contact", "in electrical contact", "in ohmic connection" and "electrically connected" are intended to describe the presence of a low-ohmic electrical connection or a low-ohmic current path between two regions, parts, zones, locations or components of a semiconductor device, or between different terminals of one or more devices, or between a terminal or metallization or electrode of a semiconductor device and a part or component of a semiconductor device, where "low ohmic" may mean that the characteristics of the respective contact are substantially unaffected by ohmic resistance. Furthermore, in the context of this specification, the term "contact" is intended to describe the presence of a direct physical connection between two elements of the respective semiconductor device; for example, a transition between two elements in contact with each other may not include additional intermediate elements, etc.

[0028] Additionally, in the context of this specification, if not stated otherwise, the term "electrically insulated" is used in the context in which it is generally understood, and is therefore intended to describe that two or more components are located separately from each other and there is no ohmic connection connecting these components. However, components that are electrically insulated from each other may still be coupled to each other, such as mechanically and / or capacitively and / or inductively and / or electrostatically (e.g., in the case of a junction). For example, two electrodes of a capacitor may be electrically insulated from each other and simultaneously mechanically and capacitively coupled to each other, such as by means of an insulator (e.g., a dielectric).

[0029] The specific embodiments described in this specification relate to, but are not limited to, power semiconductor devices that can be used in power converters or power supplies. Therefore, in an embodiment, such a power semiconductor device can be configured to carry a load current to be fed to a load, and / or, correspondingly, to carry a load current provided by a power supply. For example, a power semiconductor device may include one or more active power semiconductor unit cells, such as a monolithic integrated diode cell, a derivative of a monolithic integrated diode cell, a monolithic integrated transistor cell (e.g., a monolithic integrated IGBT or MOSFET cell) and / or its derivatives. Such a diode / transistor cell can be integrated in a single chip. A plurality of such cells can constitute a cell field arranged in an active region of the power semiconductor device.

[0030] The term "blocking state" of a power semiconductor device may refer to a condition when the power semiconductor device is in a state configured to block the flow of a load current while an external voltage is applied. More particularly, the power semiconductor device may be configured to block a forward load current through the power semiconductor device while a forward voltage bias is applied. In comparison, a power semiconductor device may be configured to conduct a forward load current in a "conducting state" of the power semiconductor device while a forward voltage bias is applied. The transition between the blocking state and the conducting state may be controlled by controlling the electrode, or more particularly, the potential of the control electrode. Of course, the electrical characteristics may only be applicable within a predetermined operating range of an external voltage and current density within the power semiconductor device. Therefore, the term "forward biased blocking state" may refer to a condition in which a power semiconductor device is in a blocking state while a forward voltage bias is applied.

[0031] The term "power semiconductor device" as used in this specification is intended to describe a power semiconductor device on a single chip having a high voltage blocking and / or high current carrying capability. In other words, such a power semiconductor device is intended for high currents, typically in the ampere range, such as up to tens or hundreds of amperes, and / or high voltages, typically above 15 V, more typically 100 V and higher, such as up to at least 400 V or even higher, such as up to at least 3 kV, or even up to 10 kV or higher, depending on the respective application.

[0032] For example, the term "power semiconductor device" as used in this specification does not refer to a logic semiconductor device used for, for example, storing data, computing data, and / or other types of semiconductor-based data processing.

[0033] For example, the power semiconductor device described below may be a single semiconductor chip (eg, exhibiting a stripe cell configuration (or honeycomb / pin cell configuration)) and may be configured for use as a power component in low voltage applications, medium voltage applications, and / or high voltage applications.

[0034] Figure 1 Schematically and exemplarily a portion of a vertical cross section of a power semiconductor device 1 according to one or more embodiments is illustrated. The power semiconductor device 1, also referred to herein as a "device", comprises in a single chip a semiconductor body 10 configured to conduct a load current between a first load terminal 11 at a first side 110 of the semiconductor body 10 and a second load terminal 12 at a second side 120 of the semiconductor body 10.

[0035] The first side 110 and the second side 120 may be arranged opposite to each other. For example, the first side 110 is the front side of the device 1, and the second side 120 is the back side of the device 1. Therefore, the device 1 may exhibit a vertical configuration, according to which the load current in the device 1 follows a path parallel to the vertical direction Z.

[0036] The device 1 further comprises a drift region 100 of the first conductivity type within the semiconductor body 10. In this document, the term "drift region" is used in the sense typically associated with it by a person skilled in the art in the field of power semiconductor devices. For example, the vertical extension of the drift region 100 affects the voltage blocking capability of the device 1.

[0037] The device 1 further comprises trenches 14 , 16 extending from the first side 110 towards the second side 120 , eg along a vertical direction Z. Each trench 14 , 16 comprises a trench electrode 141 , 161 separated from the semiconductor body 10 by a trench insulator 142 , 162 .

[0038] The trench may include a first type trench 14, wherein each trench electrode 141 of the first type trench 14 is electrically insulated from the first load terminal 11 and is configured to receive a control signal. To this end, according to an embodiment, each trench electrode 141 of the first type trench 14 is electrically connected to a (not illustrated) control terminal of the device 1. In this document, the first type trench 14 is also referred to as a "control trench", and the corresponding trench electrode 141 is also referred to as a "control trench electrode".

[0039] The trenches may further include second type trenches 16, wherein each trench electrode 161 of the second type trenches 16 is electrically connected to the first load terminal 11. Herein, the second type trenches 16 are also referred to as "source trenches" and the corresponding trench electrodes 161 are also referred to as "source trench electrodes".

[0040] The device 1 further comprises mesas 15, 18 which are laterally bounded by said trenches 14, 16. The mesas 15, 18 comprise mesas 18 of a first type and mesas 15 of a second type.

[0041] For example, each first type mesa 18 is laterally limited by at least one of the control trenches 14. For example, each first type mesa 18 is electrically connected to the first load terminal 11, for example by means of the illustrated corresponding first contact plug 111. Alternatively, a planar contact can be adopted. Each first type mesa 18 can be configured for load current conduction. For example, each first type mesa 18 includes a semiconductor body region 102 of a second conductivity type electrically connected to the first load terminal 11 (for example, through the first contact plug) and optionally includes a semiconductor source region 101 of a first conductivity type electrically connected to the first load terminal 11, wherein the semiconductor source region 101 is isolated from the drift region 100 by at least the semiconductor body region 102. The adjacent control trench electrode 141 can be configured to induce an inversion channel in the semiconductor body region 102 when subjected to a corresponding ON control signal. This process can set the device 1 to a forward conduction state. The adjacent control trench electrode 141 may be configured to cut off the inversion channel in the semiconductor body region 102 when receiving a corresponding OFF control signal, which may set the device 1 to a forward blocking state.

[0042] The first and second body contact regions 1021 and 1022 exhibiting increased dopant concentrations compared to an average dopant concentration of the body region 102 may be formed as sub-portions of the body region 102 and arranged to contact the first contact plug 111 .

[0043] The configuration of the second type mesas 15 may be different compared to the configuration of the first type mesas 18. For example, the second type mesas 15 are not configured for load current conduction during nominal operating conditions of the device 1, as will be explained in more detail below.

[0044] The above-mentioned features of the power semiconductor device 1 may allow different trench mesa patterns to be designed at the first side 110. Such patterns may include additional trench types and / or additional mesa types, for example, a floating trench whose trench electrode is not connected to a defined potential, or a second type of control trench whose trench electrode is connected to a control terminal different from the control trench electrode 141 to realize a dual-gate or multi-gate configuration, etc. Other types of mesas may also be realized, for example, mesas with different threshold voltages compared to the first type of mesa 18. The following description of the embodiments focuses on a trench mesa pattern employing a first trench 14 and a second trench 16 as well as a first type of mesa 15 and a second type of mesa 18, wherein the presence of additional types of trenches and / or additional types of mesas is not excluded unless explicitly stated.

[0045] The portion of the semiconductor body 10 adjoining the second load terminal 12 at the second side 120 may be configured according to specified characteristics of the device 1. For example, if the device 1 is to exhibit an IGBT configuration, an emitter region 108 of the second conductivity type may be provided between the drift region 100 and the second load terminal 12. The emitter region 108 is arranged in contact with the second load terminal 12. Furthermore, a field stop region 107 of the first conductivity type may be provided between the drift region 100 and the second load terminal 12, wherein the field stop region 107 exhibits a greater dopant concentration than the drift region 100. If the device 1 is to exhibit a MOSFET configuration, the emitter region 108 is omitted, such that the field stop region 107 will adjoin the second load terminal 12. If the device 1 is to exhibit an RCIGBT configuration, the emitter region 108 may exhibit a sub-portion of the first conductivity type, as known to a person skilled in the art.

[0046] In order to minimize the conduction and switching losses, the power semiconductor device (such as the device 1 described above) can be designed so that the total vertical extension of the semiconductor body is relatively small. If it is turned off, that is, when switching from the forward conduction state to the forward blocking state, in particular in an overload condition where the forward load current is higher than the nominal load current, a dynamically increased field strength may occur. Such a dynamically increased field strength may be caused by a hole current flowing in the space charge region, which causes an increased space charge density compared to the static situation due to the positive charge of the holes. A possible consequence may be the occurrence of a so-called dynamic avalanche, in which many electron-hole pairs are generated by impact ionization. Then, when the device is turned off, an unstable state is experienced, during which filamentation of the load current may occur. In such a filament of the load current, the load current density may be more than one order of magnitude higher than the average total current density. Then, the device may be destroyed by latch-up. The risk of such latch-up increases with the reduction of the device thickness.

[0047] In this context, an overload condition typically exists if the forward load current reaches at least 150% or 200% of the nominal load current of the device 1 .

[0048] The embodiments described below exhibit features for preventing dynamic avalanches from occurring.

[0049] For example, the device 1 further comprises semiconductor structures. Each semiconductor structure comprises the following series connection: a first region 151 of a first conductivity type, which is coupled to or formed by the drift region 100; a second region 152 of a second conductivity type; and a third region 153 of the first conductivity type, which is connected via a first ohmic resistor 1531 (see, for example Figure 1 At least one of a resistor "Rn") and a Zener diode 1533 (see, for example, FIG. 7) is coupled to the first load terminal 11. Thus, the semiconductor structure may be an npn semiconductor structure.

[0050] Each first type mesa 18 is configured for load current conduction, is electrically connected to the first load terminal 11 , and is devoid of any of the semiconductor structures. The semiconductor structures are arranged in the second type mesas 15 .

[0051] In an embodiment, the semiconductor structure (see elements 151, 152, 153) is configured to inject electrons into the semiconductor body 10 during an overload condition in order to limit the strength of the electric field in the semiconductor body 10. It may also be provided that the semiconductor structure is configured not to inject a significant amount of electrons into the semiconductor body if the load current is equal to or less than the nominal load current of the power semiconductor device 1, i.e. when there is no overload condition.

[0052] The integration of such a structure as described above can result in that during the switching of the device 1 from the forward conducting state to the forward blocking state in the case of an overload condition, electrons are injected through the structure even during the cut-off of the inversion channel in the first type mesa 18. These electrons at least partially compensate the holes present in the space charge region. Thus, the increase in field strength is limited and the risk of dynamic avalanche is reduced.

[0053] In an embodiment, each second type mesa 15 is laterally bounded by at least one of the source trenches 16. Figure 1 As illustrated, it can be ensured that each second type mesa 15 is not laterally confined by any of the control trenches 14. That is, the above-mentioned semiconductor structure included in the second type mesa is arranged at a relatively high distance from the next control trench electrode 141.

[0054] For example, the semiconductor structure is only active during the cutoff of the overload current, but otherwise has no influence or no significant influence on the characteristics of the device 1 .

[0055] The first region 151 may be formed by a portion of the drift region present within the second type mesa 15. The first region 151 may act as an n collector. The second region 152 may form a p base of the semiconductor structure. The second region 152 may be sandwiched between the first region 151 and the third region 153. The third region 153 may act as an n emitter of the structure.

[0056] For example, each of the semiconductor structures exhibits a vertical configuration according to which the series connection of the first region 151, the second region 152 and the third region 153 is established along a direction pointing from the second side 120 to the first side 110, such as Figure 1. As described above, each of the first region 151, the second region 152, and the third region 153 of each semiconductor structure can be arranged in a corresponding one of the second type mesas 15. In an embodiment, the third region 153 is arranged to contact the insulating layer 19 arranged between the first load terminal 11 and the semiconductor body 10. At its upper surface, the second region 152 can be adjacent to the lower surface of the third region 153 to form a first pn junction. At its lower surface, the second region 152 can be adjacent to the upper surface of the first region 151 to form a second pn junction. For example, each of the first region 151, the second region 152, and the third region 153 exhibits a corresponding width along the first lateral direction X that is the same as the width of the second type mesas 15. Along the second lateral direction Y, the semiconductor structure, i.e., the corresponding first region 151, the corresponding second region 152, and the corresponding third region 153 can be constructed as will be further described below. The second regions 152 in the second type mesas 15 and the body regions 102 in the first type mesas 18 can be jointly produced, for example, based on the same processing steps. Likewise, the third regions 153 in the second type mesas 15 and the source regions 101 in the first type mesas 18 can be jointly produced, for example, based on the same processing steps.

[0057] Still refer to Figure 1 In an embodiment, the second region 152 of at least one or each of the semiconductor structures is connected by at least a second ohmic resistor 1521 (see, for example Figure 1 , resistor "Rp") is coupled to the first load terminal 11. Figure 1 , both the first ohmic resistor 1531 and the second ohmic resistor 1521 are illustrated based on the circuit symbol of the ohmic resistor. In contrast to this schematic illustration, the resistors 1531, 1521 (and similar resistors mentioned below) can be integrated within the chip, for example at least partially integrated between the first load terminal 11 and the semiconductor body 10, or for example integrated within the semiconductor body 10. Different elements can be used to form the resistors 1531, 1521 and determine their size (in terms of ohmic resistance). For example, the first ohmic resistor 1531 and the second ohmic resistor 1521 are integrated within a single chip and close to the corresponding structures 151, 152, 153. For example, the first ohmic resistor 1531 and the second ohmic resistor 1521 are fully or at least partially integrated within one or more second type mesas 15 in the second type mesas 15.

[0058] During the shutdown period of the device 1, a significant part of the load current flows as a hole current to the first side 110. A part of it leads to the body region 102 and therefore directly to the first load terminal 11. The remaining hole current flows into the second region 152 and further flows to the first load terminal 11 via the second ohmic resistor 1521. If the voltage drop at the second ohmic resistor 1521 exceeds the diode threshold of the pn junction between the third region 153 and the second region 152, the third region 152 begins to inject electrons. These electrons diffuse into the drift region 100 through the second region 152 and therefore diffuse into the space charge region. There, the electrons flow to the second side 120 in the high electric field strength region of the space charge region. In the high electric field strength region of the space charge region, electrons and holes flow at speeds close to their respective saturation speeds. Therefore, their concentrations are approximately proportional to the corresponding current density. Therefore, the injected electron current causes a negative contribution to the space charge density and at least partially compensates for the positive contribution made by the charge of the holes. Due to the reduced overall space charge density, reduced electric field gradients and thus reduced maximum field strengths are achieved.

[0059] Therefore, by appropriately determining the size of the first ohmic resistor 1531 and the second ohmic resistor 1521 (examples given below), the risk of dynamic avalanche caused by impact ionization is reduced. Once the injection threshold is exceeded, the voltage between the second region 152 and the third region 153 depends only slightly (e.g., only logarithmically) on the injected electron current. Therefore, the increase in the voltage drop across the first ohmic resistor 1531 and the second ohmic resistor 1521 is approximately the same as the increase in the corresponding current. Therefore, the ratio of the ohmic resistance of the first ohmic resistor 1531 and the ohmic resistance of the second ohmic resistor 1521 also determines the ratio of the increase in the electron current to the hole current entering the second region 152 from the space charge region. Therefore, by determining the size of the ohmic resistance of the first ohmic resistor 1531 and the ohmic resistance of the second ohmic resistor 1521, the degree of charge compensation in the space charge region can be adjusted.

[0060] Regarding the embodiment in which the third region 153 is coupled to the first load terminal 11 via at least the first ohmic resistor 1531 , one or more of the following sizing rules (i) to (v) may be applied:

[0061] (i) The resistance Rn of the first ohmic resistor 1531 is in the range of 0.2 to 2 times the resistance Rp of the second ohmic resistor 1521 .

[0062] (ii) The resistance Rn of the first ohmic resistor 1531 is within a range of 40% to 100% of the resistance Rp of the second ohmic resistor 1521 .

[0063] (iii) The parallel connection of all second ohmic resistors 1521 exhibits a resistance of 1 mOhmcm 2 Up to 0.1Ohmcm 2 The product of the active area within the range multiplied by the resistance Rp*Aact.

[0064] (iv) The parallel connection of all second ohmic resistors 1521 exhibits a resistance of 5 mOhmcm 2 Up to 20Ohmcm 2 The product of the active area within the range multiplied by the resistance Rp*Aact.

[0065] (v) In device 1, the current is 200 A / cm 2 In the case of nominal load current densities in the range of , the sizing rules (iii) and (iv) may be suitable. If the nominal current density jnom deviates significantly from 200 A / cm 2 , then the values ​​given in rules (iii) and (iv) should be scaled inversely proportional to the nominal current density. For example, Rp*Aact is then between 0.2 V / jnom and 20 V / jnom or between 1 V / jnom and 4 V / jnom. These values ​​apply at room temperature and may vary depending on the temperature, for example increasing slightly with higher temperatures.

[0066] Regarding the formation of the first ohmic resistor 1531 and the second ohmic resistor 1521, several examples will now be described with reference to the following figures. Generally, the first ohmic resistor 1531 and the second ohmic resistor 1521 can be integrated into the chip close to the associated semiconductor structure 151, 152, 153. For a large number of semiconductor structures 151, 152, 153, a corresponding large number of first ohmic resistors 1531 and second ohmic resistors 1521 based on a distributed resistance structure can also be provided.

[0067] One way to integrate the first ohmic resistor 1531 and the second ohmic resistor 1521 is to use polysilicon filling of adjacent trenches and arrange the resistors in the third dimension (ie, along the second lateral direction Y). Figure 2 and Figure 3 An example of such a variation is illustrated in Figure 2 and Figure 3 There, the source trench electrode 161 is electrically connected to the first load terminal 11 using the second contact plug 112. Figure 2As illustrated, the semiconductor structures 151, 152, 153 in the second type mesas 15 are laterally structured along the second lateral direction Y, wherein the third region 153 is partially omitted along the second lateral direction Y, resulting in that: in the case of omission, the second region 152 adjoins the insulating layer 19. As a result, both the second region 152 and the third region 153 can be ohmically coupled to the first load terminal 11, for example as follows:

[0068] like Figure 2 and Figure 3 As exemplarily illustrated in FIG. 1 , the first contact bridge 114 may be arranged between the insulating layer 19 and the trench insulator 162 of the source trench 16, so that the first contact bridge 114 connects the third region 153 with the source trench electrode 161, which is electrically connected to the first load terminal 11. Thus, a first ohmic resistor 1531 is formed between the third region 153 and the first load terminal 11.

[0069] Similarly, a second contact bridge 113 may be arranged between the insulating layer 19 and the trench insulator 162 of another of the source trenches 16, such that the second contact bridge 113 connects the second region 152 to a source trench electrode 161 of another of the source trenches 16, which is electrically connected to the first load terminal 11. Thus, a second ohmic resistor 1521 is formed between the second region 152 and the first load terminal 11.

[0070] Therefore, in order to determine the magnitude of the resistance of the first ohmic resistor 1531 and the resistance of the second ohmic resistor 1521 , the resistance of the source trench electrode 161 (eg, based on polysilicon filling) may be adjusted.

[0071] like Figure 4 As illustrated, as an alternative to the second contact bridge 113, the second region 152 may be electrically coupled to the first load terminal 11 based on a third contact plug 115. For example, the third contact plug 115 may be configured in size to be similar to the first contact plug 114 for electrically connecting the first type mesa 18 to the first load terminal, but with a higher resistance so as to form a second resistor 1521. In an embodiment, the third region 153 may also be contacted based on such a contact plug instead of based on the first contact bridge 114.

[0072] Figure 5A vertical cross section of a further embodiment is illustrated. For example, in a third type mesa 15', a second body region 102' of a second conductivity type is arranged. The second body region 102' may include a highly doped sub-portion 1021'. The third type mesa 15' is arranged separately from the second type mesa 15. For example, the mesas 15 and 15' are separated from each other via a third type trench 17, which includes a trench electrode 171 insulated from the semiconductor body 10 by a trench insulator 172. The third region 153 is electrically connected to the trench electrode 171 of the third type trench 17 via a third contact bridge 117. The second body region 102', or correspondingly, its optional highly doped sub-portion 1021' is electrically connected to the trench electrode 171 of the third type trench 17 via a fourth contact bridge 118. The trench electrode 171 of the third type trench 17 may be connected to the first load terminal 11 via a separate contact plug, or may not be connected to the first load terminal 11 via a separate contact plug. Furthermore, according to an embodiment, the second body region 102', or respectively, its optional highly doped sub-portion 1021', is electrically connected to the first load terminal 11, for example via the fourth contact plug 116. Therefore, in one example, a first ohmic resistor 1531 (Rn) may be formed based on the third contact bridge 117, the trench electrode 171 of the third type trench 17, the fourth contact bridge 118 and the second body region 102'.

[0073] Figure 6(A) illustrates the Figure 5 The horizontal projection corresponding to the embodiment illustrated in FIG. Figure 5 The left portion of the grooved mesa pattern is mirrored at the vertical center axis of the third type mesa 15 ′.

[0074] It is noted that, according to an embodiment, in order to determine the magnitude of the resistance of the first ohmic resistor 1531 and the resistance of the second ohmic resistor 1521, the resistance of the third region 153 and the resistance of the second region 152 may also be considered since these resistances contribute to the total resistance of the first ohmic resistor 1531 and the total resistance of the second ohmic resistor 1521.

[0075] FIG6(B) illustrates a variation of the embodiment of FIG6(A) in which shared contact bridges 114' are used to connect the respective regions. For example, some of the shared contact bridges 114' contact the third regions 153 of the two second type mesas 15, the trench electrodes 171 of the two third type trenches 17, and the second body region 102', or, respectively, the optional highly doped sub-portions 1021' thereof. Other of the shared contact bridges 114' contact one of the second regions 152 and one of the source trench electrodes 161.

[0076] FIG. 6(B) also illustrates that the pitch of the structures in the first type mesas 18 in the second lateral direction Y may be different from the pitch of the structures in the second type mesas 15 .

[0077] Fig. 6(C) illustrates a further variant of the embodiment of Fig. 6(A) in which a different lateral structure of the third regions 153 and the second regions 152 in the second type of mesas 15 is proposed. Thus, the total lateral extension of the second regions 152 along the second lateral direction Y is reduced, and the total lateral extension of the third regions 153 along the second lateral direction Y is correspondingly increased.

[0078] Here, it is emphasized that according to an embodiment, the structure of the semiconductor regions in the second type mesas 15 and the contact scheme for the second type mesas 15 are both independent from the structure of the semiconductor regions in the first type mesas 18 and the contact scheme for the first type mesas 18 , respectively.

[0079] According to the embodiments (A) and (B) illustrated in FIG. 7 , the third region 153 is coupled to the first load terminal 11 through the Zener diode 1533. In addition to the coupling of the third region 153 to the first load terminal 11, this embodiment and the embodiments described subsequently may correspond to the embodiment described with respect to Figure 1 As for the embodiment described in FIG. 6 , reference may be made to the above.

[0080] For example, referring to both variants (A) and (B) of FIG. 7 , an npn transistor is integrated based on the third region 153 (acting as an n emitter), the second region 152 (acting as a p base) and the first region 151 (acting as an n collector), wherein the third region 152 is initially floating. When the overcurrent in the device 1 is turned off, the third region 153 emits electrons due to the breakdown of the Zener diode 1533 (also known as an avalanche diode). The breakdown of the Zener diode 1533 electrically connects the third region 153 to the first load terminal 11. Then, even if the control signal supplied to the control trench electrode 141 is an OFF signal for cutting off the inversion channel in the body region 102, electrons are injected, resulting in a reduced risk of dynamic avalanche, as described with respect to FIG. Figure 1 As explained in more detail.

[0081] In an embodiment, the breakdown voltage of the Zener diode 1533 is in the range of 3V to 20V, for example between 5V and 10V.

[0082] In an embodiment, as illustrated in variation (B) of FIG. 7 , the third region 153 is coupled to the first load terminal 11 based on a series connection of a third ohmic resistor 1534 and a Zener diode 1533 .

[0083] Furthermore, the second region 152 can be connected to the first load terminal 11 based on a second ohmic resistor 1521, see variants (A) and (B) of FIG. 8. Figures 6(A) to 6(C) As explained, the third area 153 and the second area 152 in the second type mesa 15 can be laterally structured along the second transverse direction Y. Fig. 8 illustrates different positions along the second transverse direction Y based on variants (A) and (B).

[0084] Note that, according to an embodiment, the second region 152 in the second type mesa 15 and the body region 102 in the first type mesa 18 can both be produced based on a joint processing step. Therefore, the second region 152 in the second type mesa 15 and the body region 102 in the first type mesa 18 can both exhibit the same vertical extension. In addition, as the body region 102, the second region 152 can exhibit a highly doped sub-region 1522. Similarly, in an embodiment, the third region 153 in the second type mesa 15 and the source region 101 in the first type mesa 18 can both be produced based on a joint processing step. Therefore, the third region 153 in the second type mesa 15 and the source region 101 in the first type mesa 18 can both exhibit the same vertical extension.

[0085] according to Fig. 9 In the embodiment illustrated in , the second region 152 is indirectly connected to the first load terminal 11 via the second ohmic resistor 1521 and the third ohmic resistor 1534 .

[0086] Fig.10 Schematically illustrates the same as FIG. 7(A), FIG. 7(B), FIG. 8(A), FIG. 8(B) and Fig. 9 The horizontal projection of the corresponding embodiment. Fig.11 The second type mesa 15 also illustrated in FIG. 1 and comprising semiconductor structures 151, 152, 153 is arranged between two source trenches 16, each source trench 16 being arranged beside an adjacent one of the first type mesas 18. Of course, this trench mesa pattern is described by way of example; other trench mesa patterns may be selected.

[0087] As mentioned above, for example, Figure 6(A)-6(C) The second contact plug 112 electrically connects the source trench electrode 161 to the first load terminal 11 . The third contact plug 115 electrically connects the second region 152 (or correspondingly, the highly doped sub-region 1522 thereof) to the first load terminal 11 .

[0088] The Zener diode 1533 is formed, for example, based on a pn junction formed at the transition between the third region 153 and the highly doped subsection 1522 of the second region 152 (along the second lateral direction Y). The third ohmic resistor 1534 can be formed via a less doped region in the second type mesa 15, for example based on the second region 152. The second region 152 can be connected to the first load terminal 11 via one of the third contact plugs 115, which extends into the further highly doped subsection 1522 of the second region 152 or directly into the second region 152. The highly doped subsection 1522 and the further highly doped subsection 1522 can together form a continuous region.

[0089] Fig.11 Show Fig.10 The portion including the second type mesa 15 and the adjacent source trench 16 . Fig.12 Illustrated with Fig.11 . For example, two laterally displaced highly doped sub-portions 1522 of the second region 152 are each contacted by one of the third contact plugs 115. Two other highly doped sub-portions 1522 arranged separately from these contacted highly doped sub-portions 1522 are adjacent to the first region 153. Again, it is noted that the corresponding two sub-portions 1522 (connected by the corresponding third ohmic resistor R3) may alternatively form a single continuous sub-portion 1522. In either case, the sub-portions 1522 are separated from each other based on the third region 153, wherein the third region 152 may overcompensate the sub-portions 1522.

[0090] The highly doped sub-portion 1522 of the second region 152 in the second type mesa 15 can be formed based on an implantation process step. The same or another implantation process step can be used to form the highly doped sub-portion of the body region 102 in the first type mesa 18. The implantation for the highly doped sub-portion 1522 can also reach the location of the first region 153 or a part thereof. In this case, the first region 153 can overcompensate for the implantation there. This process can be used, for example, for the following description of Fig.15 The described embodiments are advantageous.

[0091] Based on the corresponding Fig.12 The diagram also shows the path of a portion of the load current. Fig.13 , an exemplary function of the semiconductor structure in the second type mesa 15 shall be explained:

[0092] During the switching of the device 1 from the forward conducting state to the forward blocking state, a significant part of the load current flows as a hole current to the first side 110. A part of this current flows into the second type mesa 15 and there further flows laterally in the second region 152 (e.g. p base region) to the next third contact plug 115. The voltage drop across the second ohmic resistor 1521 (Rp) causes the potential of the second region to increase at point 1, for example to about 10V. There, the pn junction with the third region 153 (e.g. n emitter region) is initially only slightly polarized in the forward direction, so that a potential of about 10V (more precisely, slightly lower, about 9.5V) is also present at point 2 in the third region 153. This potential also exists at point 3 in the third region 153, while in the adjacent highly doped sub-portion 1522 of the second region 152, the potential is lower (close to 0V). At point 3, the pn junction of the Zener diode 1533 is therefore reverse biased. If the voltage drop across the pn junction of the Zener diode 1533 exceeds the breakdown voltage of the Zener diode 1533, an electron-hole pair is generated at point 3. The generated electrons then flow to point 2 in the third region 153 (n emitter region) and are injected into the second region 152 (p base region) there. These electrons then continue to flow into the space charge region and flow to the second side 120 in the high electric field region there. As explained above, in the high electric field strength region of the space charge region, electrons and holes flow at speeds close to their corresponding saturation speeds. Therefore, their concentrations are approximately proportional to the corresponding current densities. Therefore, the injected electron current results in a negative contribution to the space charge density and at least partially compensates for the positive contribution made by the charge of the holes. Due to the reduced total space charge density, a reduced electric field gradient and thus reduced maximum field strength are achieved.

[0093] With regard to embodiments in which the third region 153 is coupled to the first load terminal 11 via at least the Zener diode 1533 , one or more of the following sizing rules (vi) to (viii) may apply:

[0094] (vi) The parallel connection of all second ohmic resistors 1521 exhibits at least 10 mOhmcm 2 or at least 0.1Ohmcm 2 The product of the active area multiplied by the resistance Rp*Aact.

[0095] (vii) The parallel connection of all third ohmic resistors 1534 exhibits a resistance of 0.2 mOhmcm 2 Up to 100mOhmcm 2 within the range of 1mOhmcm 2 Up to 10mOhmcm 2 The active area within the range is multiplied by the resistance R3*Aact.

[0096] (viii) In device 1, the current is 200 A / cm 2 In the case of nominal load current densities in the range of , the sizing rules (vi) and (vii) may be suitable. If the nominal current density jnom deviates significantly from 200 A / cm 2 , then the values ​​given in rules (vi) and (vii) should be scaled inversely proportional to the nominal current density. For example, Rp*Aact then reaches at least 2 V / jnom or at least 20 V / jnom. And, R3*Aact then is between 0.04 V / jnom and 20 V / jnom or between 0.2 V / jnom and 2 V / jnom. These values ​​apply at room temperature and may vary depending on the temperature, for example increasing slightly with higher temperatures.

[0097] Regarding the formation of the third ohmic resistor 1534 (R3) and the second ohmic resistor 1521 (Rp) (when provided in an embodiment where the third region 153 is coupled to the first load terminal 11 via at least the Zener diode 1533), several examples will now be described with reference to the following figures.

[0098] As explained above, in an embodiment, a significant portion of the total resistance of the third ohmic resistor 1534 is formed by the second region 152 and / or by one or more of the highly doped sub-portions 1522 of the second region 1522, Fig.11 and Fig.12 The latter variant of the embodiment illustrated in Fig.14 and Fig.15 , where the highly doped sub-portion 1522 uninterruptedly couples the third region 153 to the third contact plug 115. As explained above, the third region 153 (of the first conductivity type) can overcompensate the sub-portion 1522 (of the second conductivity type). To achieve this effect, in an embodiment and as shown Fig.15 As illustrated, the third region 153 may extend further than the subportion 1522 of the second region 152 along the vertical direction Z. For example, such a configuration may result in advantages in producing the device 1, since, for example, the highly doped subportion 1522 may be implanted without using a mask before the third region 153 is implanted with a mask. Additionally or alternatively, the lateral extension of the regions 1522 and 153 may be selected such that the third region 153 (of the first conductivity type) overcompensates the subportion 1522 (of the second conductivity type) in the overlapping region.

[0099] Another variant in Figure 18-19. There, the path between the highly doped sub-portion 1522 contacted by the third contact plug 115 and the highly doped sub-portion 1522 contacted by the third region 153 comprises a further region 1538 of the first conductivity type. The further region 1538 of the first conductivity type may be a floating region. The further region 1538 of the first conductivity type may exhibit the same dopant concentration as the third region 153, but a smaller total lateral extension along the second lateral direction Y, e.g. up to less than half of the total lateral extension of the third region 153 along the second lateral direction Y, e.g. in order to avoid that the further region 1538 of the first conductivity type acts as an emitter region. The further region 1538 of the first conductivity type may overcompensate the sub-portion 1522 (of the second conductivity type), e.g. so that the third ohmic resistor 1534 consists only of a portion of the second region 152 below the further region 1538 of the first conductivity type and therefore has a correspondingly increased resistance value.

[0100] The third region 153 may be arranged to be in contact with two adjacent highly doped sub-portions 1522 (e.g., Fig.12 and Fig.13 as illustrated) or spaced apart therefrom (as Fig.16 and Fig.17 Via the (possible) distance between the third region 153 and the highly doped subsection 1522 adjacent to the third region 153 , the breakdown voltage of the Zener diode 1533 can be influenced.

[0101] In an embodiment, the total extension of the region corresponding to the third ohmic resistor 1534 (e.g., the further region 1538 of the first conductivity type or the distance between the highly doped sub-portions 1522) is in the range of 0.5 μm to 20 μm. Furthermore, the total extension of the third region 153 may be in the range of 5 μm to 100 μm. The exact value may be selected depending on the specified resistance R3 of the third ohmic resistor 1534 and the specified resistance Rp of the second ohmic resistor 1521.

[0102] The above-mentioned embodiments comprising semiconductor structures 151, 152, 153 in the second type mesas 15 can be used in devices in which the emitter region 108 at the second side 120 is laterally structured, such as Fig. 20 shown.

[0103] For example, the emitter region 108 includes one or more first sub-regions 1081 and one or more second sub-regions 1082 that differ in average dopant concentration and / or in emitter efficiency. The difference in dopant concentration of the emitter region 108 at the second side 120 can be reflected by a corresponding change in the magnitude of the breakdown voltage of the Zener diode 1533 and / or the resistance of the third ohmic resistor 1534 and / or the resistance of the second ohmic resistor 1521. For example, the resistance R3 of the third ohmic resistor 1534 is higher in a region of lateral overlap with increased emitter efficiency (e.g., the first sub-region 1081) than in a region of lateral overlap with reduced emitter efficiency (e.g., the second sub-region 1082).

[0104] like Figure 21-22 As illustrated, for example, due to the higher current density during turn-off in the region close to the junction termination, the semiconductor structures 151, 152, 153 can be arranged exclusively in or close to the edge termination region 1-3 surrounding the active region 1-2 (which includes the cell field, which in particular includes the first type mesas 18 and the control trenches 14), see Fig.21 , or arranged in both the active area 1-2 and the edge termination area 1-3, see Fig. 22 For example, refer to Fig.21 , the semiconductor structures 151, 152, 153 are not necessarily arranged in one of the second type mesas 15, but are adjacent to one of the source trenches 16 at the transition between the active region 1-2 and the edge termination region 1-3. There, the second region 152 can laterally adjoin the well region 13 of the second conductivity type. On the other side, a region 159 of the second conductivity type adjacent to the second region 152, for example a so-called p-ring, can be laterally connected to the first load terminal 11 via one or more further contact plugs 119. In another embodiment, as Fig. 22 As illustrated, the semiconductor structures 151, 152, 153 are arranged in one of the second type mesas 15 in the edge termination region 1-3. The third ohmic resistor 1534 may be connected via (at Figure 21-22 The first load terminal 11 is connected to a contact (not illustrated in the figure), for example, arranged in the rightmost mesa 15.

[0105] If the device 1 is embodied as an RC IGBT, the semiconductor structures 151, 152, 153 may be arranged in both the IGBT region of the RC IGBT and the diode region of the RC IGBT. Fig.23, the emitter region 108 includes one or more first portions 1083 and one or more second portions 1084 that differ in dopant type. For example, the one or more first portions 1083 are part of the IGBT region and therefore have the second conductivity type. The one or more second portions 1084 are part of the diode region and therefore have the first conductivity type. The difference in the dopant type of the emitter region 108 at the second side 120 can be reflected by a corresponding change in the magnitude of the breakdown voltage of the Zener diode 1533 and / or the resistance of the third ohmic resistor 1534. For example, the resistance R3 of the third ohmic resistor 1534 is higher or lower in the region portion of the diode region (which overlaps laterally with the one or more first portions 1083) than in the region portion of the IGBT region (which overlaps laterally with the one or more first portions 1083) because the current density in the diode region can be different from the current density in the IGBT region.

[0106] The device 1 can also be embodied as a diode, see Fig.24 , wherein the emitter region 108 is completely of the first conductivity type. Then, the source region 101 is not included in the first type mesa 18. If embodied as a diode, the device 1 may not be provided with a trench electrode.

[0107] Figure 25 illustrates Fig. 9 Three variants (A) to (C) of embodiments. According to these variants, the device 1 also includes a barrier region 105 of the first conductivity type. The barrier region 105 exhibits a greater dopant concentration than the drift region. In an embodiment, referring to variant (A), the barrier region 105 is arranged in both the first type mesa 18 and the second type mesa 15. There, it can be arranged in contact with the body region 102 and the second region 152, or, as illustrated, spaced apart from it along the vertical direction Z. The lower surface of the barrier region 105 can still be arranged within the mesas 15, 18; that is, in one example, the barrier region 105 does not extend below the bottom of the trenches 14, 16. In addition, the barrier region 105 can be laterally constructed, for example, where it extends only into the first type mesa 18 (variant (B)) or only into the second type mesa 15 (variant (C)).

[0108] Furthermore, in another embodiment, such a structure may be realized in a region of the back emitter where the local doping is enhanced, which may be the case, for example, for improving the softness of the device or for improving the current-induced short circuit robustness.

[0109] A method for producing a power semiconductor device is also proposed herein. The method includes forming the following components in a single chip: a semiconductor body configured to conduct a load current between a first load terminal at a first side of the semiconductor body and a second load terminal at a second side of the semiconductor body; a drift region of a first conductivity type in the semiconductor body; a trench extending from the first side toward the second side, each trench including a trench electrode separated from the semiconductor body by a trench insulator; a mesa laterally limited by the trench, wherein the mesa includes a first type mesa and a second type mesa; and a semiconductor structure. Each semiconductor structure includes a series connection of the following: a first region of a first conductivity type, which is coupled to or formed by a drift region; a second region of a second conductivity type; and a third region of a first conductivity type, which is coupled to a first load terminal through at least one of a first ohmic resistor and a Zener diode. Each first type mesa is configured for load current conduction, is electrically connected to the first load terminal, and is free of any of the semiconductor structures. The semiconductor structure is arranged in a second type mesa.

[0110] Embodiments of the production method correspond to the embodiments of the power semiconductor device 1 described above. Therefore, these embodiments of the method will not be described verbatim in this article, but reference may be made to the above. For example, as described, the body region 102 in the first type mesa 18 and the second region 152 in the second type mesa 15 can both be formed based on a joint processing step. Similarly, the source region 101 in the first type mesa 18 and the third region 153 in the second type mesa 15 can both be formed based on a joint processing step.

[0111] In the above, embodiments concerning a power semiconductor device and a corresponding production method were explained.

[0112] For example, these power semiconductor devices are based on silicon (Si). Therefore, a single crystal semiconductor region or layer, such as a semiconductor body and a region / region thereof, such as a region, etc., can be a single crystal Si region or Si layer. In other embodiments, polycrystalline silicon or amorphous silicon can be used.

[0113] However, it should be understood that the semiconductor body and its regions / areas can be made of any semiconductor material suitable for manufacturing semiconductor devices. Examples of such materials include, but are not limited to, basic semiconductor materials such as silicon (Si) or germanium (Ge), IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenic phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few. The aforementioned semiconductor materials are also referred to as "homojunction semiconductor materials". When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x), and silicon-SiGe heterojunction semiconductor materials. For power semiconductor switch applications, Si, SiC, GaAs and GaN materials are currently used.

[0114] For ease of description, spatial relative terms such as "below", "below", "lower", "above", "above", etc. are used to explain the positioning of one element relative to a second element. In addition to orientations different from those depicted in the figures, these terms are also intended to cover different orientations of the corresponding devices. In addition, terms such as "first", "second", etc. are also used to describe various elements, regions, parts, etc., and are not intended to be limiting. Throughout the description, similar terms may refer to similar elements.

Claims

1. A power semiconductor device (1), comprising in a single chip: - a semiconductor body (10) configured to conduct a load current between a first load terminal (11) at a first side (110) of the semiconductor body (10) and a second load terminal (12) at a second side (120) of the semiconductor body (10); - a drift region (100) of a first conductivity type within the semiconductor body (10); - trenches (14, 16) extending from the first side (110) towards the second side (120), each trench (14, 16) comprising a trench electrode (141, 161) separated from the semiconductor body (10) by a trench insulator (142, 162); - terraces (15, 18) laterally bounded by said grooves (14, 16), wherein said terraces (15, 18) comprise terraces of a first type (18) and terraces of a second type (15); - semiconductor structures (151, 152, 153), wherein each semiconductor structure comprises a series connection of: o a first region (151) of the first conductivity type, which is coupled to the drift region (100) or is formed by the drift region (100); o a second region (152) of a second conductivity type; and o a third region (153) of the first conductivity type coupled to the first load terminal (11) via at least one of a first ohmic resistor (1531; 1534) and a Zener diode (1533); in: - each first type mesa (18) is configured for load current conduction, is electrically connected to the first load terminal (11), and is free of any of the semiconductor structures (151, 152, 153); and - the semiconductor structure (151, 152, 153) is arranged in a mesa (15) of the second type.

2. The power semiconductor device (1) according to claim 1, wherein: The trenches include first type trenches (14), wherein each trench electrode (141) of the first type trenches (14) is electrically insulated from the first load terminal (11) and is configured to receive a control signal.

3. The power semiconductor device (1) according to claim 1 or 2, wherein: The trenches include second type trenches (16), wherein each trench electrode (161) of the second type trenches (16) is electrically connected to the first load terminal (11).

4. The power semiconductor device (1) according to claim 2 or 3, wherein: - each mesa (18) of the first type is laterally bounded by at least one of the grooves (14) of the first type; and / or - Each second type mesa (15) is laterally delimited by at least one of said second type grooves (16).

5. The power semiconductor device (1) according to one or more of the preceding claims 2 to 4, wherein: Each second type mesa (15) is not laterally bounded by any of the first type grooves (14).

6. The power semiconductor device (1) according to one or more of the preceding claims, wherein: The semiconductor structure (151, 152, 153) is configured to inject electrons into the semiconductor body (10) during an overload condition to limit the strength of an electric field in the semiconductor body (10).

7. The power semiconductor device (1) according to one or more of the preceding claims, wherein: The semiconductor structure (151, 152, 153) is configured not to inject a significant amount of electrons into the semiconductor body (10) if the load current is equal to or less than a nominal load current of the power semiconductor device.

8. The power semiconductor device (1) according to one or more of the preceding claims, wherein: The second region (152) of at least one or each of the semiconductor structures is coupled to the first load terminal (11) via at least a second ohmic resistor (1521).

9. The power semiconductor device (1) according to claim 8, wherein: The first ohmic resistor (1531) and the second ohmic resistor (1521) are both integrated in the single chip and are close to the corresponding semiconductor structures (151, 152, 153).

10. The power semiconductor device (1) according to claim 8 or 9, wherein: The first ohmic resistor (1531) and the second ohmic resistor (1521) are both at least partially integrated in one or more second type mesas (15) of the second type mesas (15).

11. The power semiconductor device (1) according to one or more of the preceding claims, wherein: Each of the semiconductor structures exhibits a vertical configuration according to which the series connection is established along a direction pointing from the second side (120) to the first side (110).

12. The power semiconductor device (1) according to one or more of the preceding claims, wherein: Each first type mesa (18) comprises a semiconductor body region (102) of the second conductivity type electrically connected to the first load terminal (11), and optionally comprises a semiconductor source region (101) of the first conductivity type electrically connected to the first load terminal (11), wherein the semiconductor source region (101) is isolated from the drift region (100) by at least the semiconductor body region (102).

13. The power semiconductor device (1) according to one or more of the preceding claims, wherein: Each of the first region (151), the second region (152) and the third region (153) of each semiconductor structure is arranged in a second type mesa (18).

14. The power semiconductor device (1) according to claim 12 and 13, wherein: The body region (102) in the first type of mesas (15) and the second region (152) in the second type of mesas (18) are jointly produced, and / or the source region (101) in the first type of mesas (15) and the third region (153) in the second type of mesas (18) are jointly produced.

15. The power semiconductor device (1) according to one or more of the preceding claims, wherein: The third region (153) is coupled to the first load terminal (11) via the Zener diode (1533) and the third ohmic resistor (1534).

16. The power semiconductor device (1) according to one or more of the preceding claims, wherein: The second region (152) includes one or more highly doped sub-portions (1522) of the second conductivity type.

17. The power semiconductor device (1) according to one or more of the preceding claims, wherein: - the third region (153) is arranged in contact with an insulating layer (19), the insulating layer (19) being arranged between the first load terminal (11) and the semiconductor body (10); and The second region (152) isolates the third region (153) from the remainder of the semiconductor body (10).

18. The power semiconductor device (1) according to claim 15 to 17, wherein: The pn junction of the Zener diode (1533) is formed based on the transition between one of the highly doped sub-portions (1522) and the third region (153), and wherein the second region (152) is connected to the first load terminal (11).

19. The power semiconductor device (1) according to one or more of the preceding claims, wherein: The power semiconductor device (1) is one of an IGBT, an RC IGBT or a diode.

20. A method of producing a power semiconductor device (1), the method comprising forming the following components in a single chip: - a semiconductor body (10) configured to conduct a load current between a first load terminal (11) at a first side (110) of the semiconductor body (10) and a second load terminal (12) at a second side (120) of the semiconductor body (10); - a drift region (100) of a first conductivity type within the semiconductor body (10); - trenches (14, 16) extending from the first side (110) towards the second side (120), each trench (14, 16) comprising a trench electrode (141, 161) separated from the semiconductor body (10) by a trench insulator (142, 162); - a terrace (15; 18) laterally delimited by said grooves (14, 16), wherein The table top (15; 18) comprises a first type table top (18) and a second type table top (15); - semiconductor structures (151, 152, 153), wherein each semiconductor structure comprises a series connection of: o a first region (151) of the first conductivity type, which is coupled to the drift region (100) or is formed by the drift region (100); o a second region (152) of a second conductivity type; and o a third region (153) of the first conductivity type coupled to the first load terminal (11) via at least one of a first ohmic resistor (1531; 1534) and a Zener diode (1533); in: - each first type mesa (18) is configured for load current conduction, is electrically connected to the first load terminal (11), and is free of any of the semiconductor structures (151, 152, 153); and - the semiconductor structure (151, 152, 153) is arranged in a mesa (15) of the second type.

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