A medium and low voltage SIC IGBT device

Abstract

The present application provides a medium-low voltage SIC IGBT device, comprising: a substrate of a first doping type of silicon material, the substrate being used as a collector region; an epitaxial layer of a second doping type of SIC material, the epitaxial layer being located on the substrate; and a front structure of the SIC IGBT device formed in the epitaxial layer; wherein the substrate of the silicon material and the epitaxial layer of the SIC material form a heterogeneous PN junction. The present application provides a medium-low voltage SIC IGBT device to solve the technical problem that the structure of a traditional SIC IGBT device cannot be applied to a medium-low voltage SIC IGBT device and the conduction loss is large.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a medium-low voltage SIC IGBT device. Background Art

[0002] IGBT devices have the advantages of low on-state voltage, high saturation current density, short turn-off time and simple driving circuit, making them an ideal choice for switching devices in high temperature, high voltage, high power and high frequency fields. Thanks to the excellent physical properties of silicon carbide (SiC) materials, SiC power devices have become high-voltage and high-speed switching devices with great potential. Compared with Si-based devices, power devices represented by SiC MOSFET have lower on-resistance and smaller chip size. The above advantages make the devices competent for high voltage, high current and high frequency application requirements.

[0003] Due to the advantages of high temperature, high voltage and high current of SIC IGBT devices, in some 10kV-25kV high voltage scenarios, such as PET power electronic transformer (Power Electronic Transformer), silicon carbide IGBT devices are unrivaled with their superior on-state characteristics and switching speed.

[0004] However, medium and low voltage SIC IGBT devices are rare, mainly because the cost of SIC IGBT devices is relatively high. At present, the mass production price is about 3 to 5 times that of silicon-based IGBT devices.

[0005] The production efficiency of SIC substrates is low, and the mainstream wafer sizes are still 4 inches and 6 inches, resulting in high raw material costs. In addition, low yields in the manufacturing and packaging processes also increase costs. The SIC industry chain mainly includes substrates, epitaxy, device design, wafer manufacturing, and module packaging. The costs of substrates and epitaxy account for 40% and 30% respectively, and device manufacturing accounts for 19%. The Si substrate process is mature and low-cost.

[0006] The thinning process also limits the application of medium and low voltage SIC IGBT devices. After the front process is completed, the traditional IGBT device uses the back thinning process to reduce the substrate thickness to the required thickness, and then forms the P+ collector through the back injection process. SiC material causes the device to withstand a pressure of about 150V with a thickness of 1μm. The effective thickness of low-voltage SiC IGBT devices (≤1200V) is only 10μm. The thinning process is difficult to prepare and there are no mature products. Most of the existing SiC IGBT devices have a voltage specification of more than 10kV. For example, for traditional 650V Si IGBT devices, the thickness of the silicon wafer after thinning is about 60μm. For medium and low voltage SIC IGBT devices, even 1000V IGBT devices only need a thickness of about 10μm, which cannot be supported by the existing thinning process.

[0007] In addition, the biggest structural difference between SIC IGBT devices and SIC MOSFET devices is that there is an additional SIC PN junction on the back, and the junction voltage of the SIC PN junction on the back is about 3V. When the SIC IGBT device is forward-conducting, the conduction current needs to pass through the SIC PN junction on the back. Under low current conditions, the SIC PN junction on the back has a forward voltage drop of more than 3V, and the conduction loss is large. This feature limits its application in fields below 10kV.

[0008] Therefore, the structure of the traditional SIC IGBT device cannot be applied to medium and low voltage SIC IGBT devices and has large conduction loss, which is a technical problem that technical personnel in this field urgently need to solve.

[0009] The above information disclosed in the background section is only for enhancing understanding of the background of the present application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Summary of the invention

[0010] The present application provides a medium and low voltage SIC IGBT device to solve the technical problem that the structure of a traditional SIC IGBT device is not applicable to medium and low voltage SIC IGBT devices and the conduction loss is large.

[0011] The present application provides a medium-low voltage SIC IGBT device, including:

[0012] A substrate of a first doping type of silicon material, the substrate being used as a collector region;

[0013] an epitaxial layer of a second doping type of a SIC material, the epitaxial layer being located on the substrate;

[0014] A front structure of a SIC IGBT device is formed in the epitaxial layer;

[0015] Wherein, the substrate of silicon material and the epitaxial layer of SIC material form a heterogeneous PN junction.

[0016] Due to the adoption of the above technical solution, this application has the following technical effects:

[0017] The medium and low voltage SIC IGBT device of the present application has a substrate 1 made of silicon material and an epitaxial layer made of SIC material. The silicon substrate 1 and the SIC epitaxial layer form a heterojunction, that is, a heterogeneous (silicon material and SIC material) PN junction.

[0018] The silicon material substrate 1 and the epitaxial layer of the SIC material of the medium and low voltage SIC IGBT device of the present application form a heterogeneous PN junction, which has the following advantages:

[0019] The back of the medium and low voltage SIC IGBT device of the present application adopts a heterogeneous PN junction to make a PN collector structure. By controlling the doping concentration of the substrate 1 of the silicon material and the epitaxial layer of the SIC material, the barrier of the heterogeneous PN junction on the back can be controlled to be low, thereby making the turn-on voltage drop of the medium and low voltage SIC IGBT device of the present application low and the conduction loss small. In addition, the defects on the contact surface of the heterogeneous PN junction can be used as the recombination center of minority carriers at the time of turning off the IGBT device, which is conducive to the rapid recombination of minority carriers at the time of turning off and reducing the turn-off loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0021] Figure 1 A schematic diagram of a medium and low voltage SIC IGBT device of the present application;

[0022] Figure 2 A schematic diagram of completing step S1 of the method for preparing a medium- and low-voltage SIC IGBT device of the present application;

[0023] Figure 3 A schematic diagram of completing step S2 of the method for preparing a medium- and low-voltage SIC IGBT device of the present application;

[0024] Figure 4 A schematic diagram of completing step S4 of the method for preparing a medium- and low-voltage SIC IGBT device of the present application;

[0025] Figure 5 A schematic diagram of completing step S5 of the method for preparing a medium- and low-voltage SIC IGBT device of the present application;

[0026] Figure 6 A schematic diagram of completing step S7 of the method for preparing a medium- and low-voltage SIC IGBT device of the present application;

[0027] Figure 7 It is a comparison diagram of the drain current variation curve with the drain voltage of the medium and low voltage SIC IGBT device of the present application and the SIC IGBT device in the prior art.

[0028] Reference numerals:

[0029] Substrate 1, shallow trench 11, electric field stop layer 2, drift region 3,

[0030] body region 4, first doping type source region 51, second doping type source region 52,

[0031] Gate 61 , gate oxide layer 62 , first doping type shielding region 7 , back metal 8 . DETAILED DESCRIPTION

[0032] In order to make the technical solutions and advantages of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0033] Embodiment 1

[0034] like Figure 1 As shown, the medium and low voltage SIC IGBT device of the present application includes:

[0035] A substrate 1 of a first doping type of silicon material, wherein the substrate 1 serves as a collector region;

[0036] an epitaxial layer of a second doping type of a SIC material, the epitaxial layer being located on the substrate;

[0037] A front structure of a SIC IGBT device is formed in the epitaxial layer;

[0038] The substrate 1 of silicon material and the epitaxial layer of SIC material form a heterogeneous PN junction.

[0039] SiC material's own characteristics SiC material 1μm thickness can withstand about 150V. In the existing SIC IGBT device field, the SIC IGBT device's own structural characteristics must have a PNP structure, in which a part of the PNP structure is a back homogeneous (i.e., all SIC) PN junction formed by a P-type SIC collector region and an N-type SIC epitaxial layer.

[0040] The medium and low voltage SIC IGBT device of the present application has a substrate 1 made of silicon material and an epitaxial layer made of SIC material. The silicon substrate 1 and the SIC epitaxial layer form a heterojunction, that is, a heterogeneous (silicon material and SIC material) PN junction.

[0041] The back of the medium and low voltage SIC IGBT device of the present application adopts a heterogeneous PN junction to make a PN collector structure. By controlling the doping concentration of the substrate 1 of the silicon material and the epitaxial layer of the SIC material, the barrier of the heterogeneous PN junction on the back can be controlled to be low, thereby making the turn-on voltage drop of the medium and low voltage SIC IGBT device of the present application low and the conduction loss small. In addition, the defects on the contact surface of the heterogeneous PN junction can be used as the recombination center of minority carriers at the time of turning off the IGBT device, which is conducive to the rapid recombination of minority carriers at the time of turning off and reducing the turn-off loss.

[0042] In implementation, such as Figure 1 As shown, the upper surface of the substrate has a plurality of shallow grooves 11;

[0043] Correspondingly, the epitaxial layer is formed on the substrate 1, the epitaxial layer fills the shallow groove 11 and the upper surface of the epitaxial layer is higher than the top of the substrate;

[0044] The contact surface between the substrate 1 and the epitaxial layer is the bottom, wall and top of the shallow trench.

[0045] The substrate 1 and the epitaxial layer with shallow grooves have a larger contact surface of the heterogeneous PN junction due to the presence of the shallow grooves, and the larger contact surface makes the contact surface have more defects. The larger contact surface can control the barrier of the heterogeneous PN junction on the back side to be lower, thereby making the turn-on voltage drop of the medium and low voltage SIC IGBT device of the present application lower and the conduction loss lower. More defects, as the recombination center of minority carriers during the shutdown process of the IGBT device, are conducive to the rapid recombination of minority carriers at the shutdown moment and reduce the shutdown loss.

[0046] In implementation, such as Figure 1 As shown, the epitaxial layer includes:

[0047] An electric field cutoff layer 2, located on the substrate 1, filling the shallow groove and higher than the top of the substrate 1;

[0048] A drift region 3 formed on the electric field stop layer 2;

[0049] The substrate 1 of silicon material and the electric field stop layer 2 of SIC material form a heterogeneous PN junction, and the contact surfaces between the substrate 1 and the electric field stop layer 2 are the bottom, wall and top of the shallow trench.

[0050] The substrate 1 and the electric field stop layer 2 with shallow grooves have a larger contact surface of the heterogeneous PN junction due to the presence of the shallow grooves, and the larger contact surface leads to more defects on the contact surface. More defects serve as recombination centers of minority carriers during the shutdown process of the IGBT device, which is conducive to the rapid recombination of minority carriers at the shutdown moment and reduces the shutdown loss.

[0051] In implementation, the ratio of the sum of the areas of the bottom, the wall and the top of each shallow groove to the area of ​​the back side of the substrate is in the range of greater than or equal to 1.5 and less than or equal to 3.

[0052] In implementation, such as Figure 1 As shown, each of the shallow grooves 11 is arranged adjacent to and in parallel.

[0053] In this way, the preparation of the shallow trench is relatively convenient, and the areas of the bottom, wall and top of the shallow trench are relatively large, thereby making the contact area between the substrate 1 and the electric field stop layer 2 forming the heterogeneous PN junction relatively large.

[0054] In implementation, such as Figure 1 As shown, the shallow groove depth ranges from greater than or equal to 0.3 μm to less than or equal to 0.6 μm;

[0055] The width of the upper end of the shallow groove 11 ranges from 0.7 μm to 1.4 μm.

[0056] The angle between the bottom and the wall of the shallow groove 11 is in the range of greater than 90 degrees and less than or equal to 120 degrees.

[0057] In implementation, such as Figure 1 As shown, the doping concentration of the substrate ranges from greater than or equal to 1×10 17 cm -3 Less than or equal to 5×10 19 cm -3 ;

[0058] The doping concentration of the electric field cutoff layer 2 is in the range of greater than or equal to 1×10 16 cm -3 Less than or equal to 10 17 cm -3 .

[0059] That is, the substrate 1 is heavily doped, and the electric field stop layer 2 is also heavily doped.

[0060] Specifically, as an optional manner, the first doping type is P type, and the second doping type is N type.

[0061] Specifically, as another optional manner, the first doping type is N-type, and the second doping type is P-type.

[0062] In implementation, medium and low voltage SIC IGBT devices also include:

[0063] A body region 4 of a first doping type, located on the drift region 3;

[0064] A first doping type source region 51 and a second doping type source region 52 are located on the body region 4;

[0065] A groove, wherein the groove enters into the drift region 3;

[0066] A gate oxide layer 62 formed on the inner bottom and sidewalls of the trench;

[0067] The gate 61 is filled in the space surrounded by the gate oxide layer 62;

[0068] A first doping type shielding region 7, located below the gate oxide layer 62;

[0069] A back metal 8 is formed on the back side of the substrate 1 .

[0070] The silicon material substrate 1 and the epitaxial layer of the SIC material of the medium and low voltage SIC IGBT device of the present application form a heterogeneous PN junction, which has the following advantages:

[0071] First, the silicon substrate 1 and the epitaxial layer of the SIC material form a heterogeneous PN junction as a necessary back PN junction in the PNP structure of the medium and low voltage SIC IGBT device, which is an essential part of the IGBT device.

[0072] Second: The back of the medium and low voltage SIC IGBT device of the present application adopts a heterogeneous PN junction to make a PN collector structure. By controlling the doping concentration of the substrate 1 of the silicon material and the epitaxial layer of the SIC material, the barrier of the heterogeneous PN junction on the back can be controlled to be low, thereby making the turn-on voltage drop of the medium and low voltage SIC IGBT device of the present application low and the conduction loss small. That is, the junction voltage of the heterogeneous PN junction on the back of the medium and low voltage SIC IGBT device of the present application can be much lower than the junction voltage 3V of the homogeneous junction SIC structure, so the conduction loss is small.

[0073] When the medium and low voltage SIC IGBT device of the present application is turned on and the on-current is small, the on-state voltage drop of the back heterogeneous PN junction is low.

[0074] Under the condition of the same doping concentration, the on-state voltage drop of the heterogeneous PN junction at a small current is much lower than that of the homogeneous PN junction in the prior art.

[0075] Third: The defects at the contact surface of the heterogeneous PN junction formed by the silicon substrate 1 and the epitaxial layer of the SIC material can serve as the recombination center of minority carriers when the IGBT device is turned off, which is conducive to the rapid recombination of minority carriers at the turn-off moment and reduces the turn-off loss.

[0076] That is, the heterogeneous PN junction in the medium and low voltage SIC IGBT device of the present application, which plays a role in reducing the conduction loss and the turn-off loss, does not need to set a separate structure heterogeneous PN junction, but is realized by using the necessary structure (substrate 1 and epitaxial layer) in the medium and low voltage SIC IGBT device, so that the structure of the medium and low voltage SIC IGBT device of the present application is simple and easy to prepare.

[0077] Fourth: The thickness of the epitaxial layer using SIC material can be controlled to be relatively small, such as 6-15μm, so that the medium and low voltage SIC IGBT devices of this application can achieve medium and low voltage; in addition, the thickness of the SIC material with higher cost is relatively small, which realizes cost control. The substrate of silicon material has mature technology and low cost. The cost brought by the thinning thickness of the substrate itself and the back of the substrate is also relatively low. For the medium and low voltage SIC IGBT device of this application with a breakdown voltage of 1000V, only a 10μm epitaxial layer of SIC material is required, which is relatively low in cost.

[0078] Fifth, since the back heterogeneous PN junction uses silicon material as a relatively thick substrate, about several hundred μm, that is, the thickness of the silicon material substrate does not need to be too thin, the requirements for the substrate back thinning process are relatively low, and the cost is also relatively low.

[0079] The method for preparing the medium and low voltage SIC IGBT device of the present application comprises the following steps in chronological order:

[0080] like Figure 2 As shown, step S1: provide a substrate 1 of Si material, wherein the Si material substrate is a highly doped P-type substrate 1. The substrate 1 serves as the P+ collector region of the IGBT collector, with a doping concentration of 5×10 19 cm -3 The thickness of the initial Si material substrate 1 is in the range of 650 μm to 725 μm.

[0081] like Figure 3 As shown, step S2: etching a shallow groove 11 on the substrate 1, the depth of the shallow groove 11 is about 0.5 μm.

[0082] like Figure 4 As shown, step S3: growing a heavily N+ doped first SIC epitaxial layer on the substrate 10 as the electric field stop layer 2. The design of the electric field stop layer 2 should ensure that the electric field inside the device is completely cut off therein to prevent the P+ collector region from being punched through; at the same time, attention should be paid to selecting a suitable thickness of the electric field stop layer to improve the forward conduction IV characteristics of the device.

[0083] Here, the thickness of the electric field cutoff layer 2 is selected to be 1-3 μm, and the doping concentration is 1×10 17 cm -3 The substrate 1 of P+Si material and the N+SiC electric field stop layer 2 form a back heterogeneous PN junction.

[0084] like Figure 4 As shown, step S4: growing a lightly doped N-second SIC epitaxial layer 30 on the electric field stop layer 2. A drift region 3 of N-SIC material. .

[0085] like Figure 5As shown, step S5: fabricate the front structure of the SIC IGBT device in the lightly doped N-second SIC epitaxial layer 30, including the first doping type body region 4 (corresponding to the P-body region), the first doping type source region 51 (corresponding to the P+ source region), the second doping type source region 52 (corresponding to the N+ source region), the gate oxide layer 62, the gate 61, and the first doping type shielding region 7 (corresponding to the P+ shielding region); correspondingly, the portion of the lightly doped N-second SIC epitaxial layer 30 where the front structure of the SIC IGBT device is not fabricated is used as the drift region 3. The thickness of the drift region 3 is determined by the BV parameter of the breakdown voltage of the device. For medium and low voltage 600-1500V devices, the thickness of the drift region 3 is about 6-15μm. The doping concentration is 1×10 15 cm -3 .

[0086] like Figure 6 As shown, step S6: after the front structure of the SIC IGBT device is manufactured, a back thinning process is used to thin the Si material substrate to about 60-300 μm.

[0087] like Figure 6 As shown, step S7: fabricate a back metal 8 as the collector metal connection layer of the IGBT.

[0088] Figure 7 It is a comparison diagram of the drain current variation curve along the drain voltage during the conduction process of the medium and low voltage SIC IGBT device of the present application and the SIC IGBT device in the prior art.

[0089] Figure 7 In the figure, the horizontal axis is the drain voltage in V, and the vertical axis is the drain current in A. Curve ① is a curve showing the change of drain current with drain voltage of the SIC IGBT device in the prior art; curve ② is a curve showing the change of drain current with drain voltage of the medium and low voltage SIC IGBT device of the present application.

[0090] From curve ①, we can see that the drain current starts to be positive only when the drain voltage is more than 3V, that is, the turn-on voltage is more than 3V.

[0091] From curve ②, it can be seen that when the drain voltage is less than 1V, the drain current has already started to be positive, that is, the turn-on voltage is less than 1V.

[0092] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0093] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0094] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0095] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0096] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0097] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A medium and low voltage SIC IGBT device, characterized in that: include: A substrate (1) of a first doping type of silicon material, wherein the substrate (1) serves as a collector region; an epitaxial layer of a second doping type of a SIC material, the epitaxial layer being located on the substrate; A front structure of a SICIGBT device, formed in the epitaxial layer; The silicon material substrate (1) and the epitaxial layer of the SIC material form a heterogeneous PN junction.

2. The medium and low voltage SICIGBT device according to claim 1, characterized in that: The upper surface of the substrate has a plurality of shallow grooves (11); Correspondingly, the epitaxial layer is formed on the substrate (1), the epitaxial layer fills the shallow groove (11) and the upper surface of the epitaxial layer is higher than the top of the substrate; The contact surfaces between the substrate (1) and the epitaxial layer are the bottom, wall and top of the shallow groove.

3. The medium and low voltage SICIGBT device according to claim 1, characterized in that: The epitaxial layer comprises: An electric field stop layer (2), located on the substrate (1), filling the shallow groove and higher than the top of the substrate (1); A drift region (3) formed on the electric field stop layer (2); The silicon material substrate (1) and the electric field stop layer (2) of the SIC material form a heterogeneous PN junction, and the contact surfaces between the substrate (1) and the electric field stop layer (2) are the bottom, wall and top of the shallow trench.

4. The medium and low voltage SICIGBT device according to claim 3, characterized in that: The ratio of the sum of the areas of the bottom, the wall and the top of each shallow groove to the area of ​​the back side of the substrate is in the range of greater than or equal to 1.5 and less than or equal to 3.

5. The medium and low voltage SICIGBT device according to claim 3, characterized in that: The shallow grooves (11) are arranged adjacent to each other and in parallel.

6. The medium-low voltage SICIGBT device according to claim 5, characterized in that: The shallow groove depth has a value range of greater than or equal to 0.3 μm and less than or equal to 0.6 μm; The width of the upper end of the shallow groove (11) has a value range of greater than or equal to 0.7 μm and less than or equal to 1.4 μm.

7. The medium-low voltage SICIGBT device according to claim 6, characterized in that: The value range of the angle between the groove bottom and the groove wall of the shallow groove (11) is greater than 90 degrees and less than or equal to 120 degrees.

8. The medium-low voltage SIC IGBT device according to any one of claims 1 to 7, characterized in that: The doping concentration of the substrate is in the range of greater than or equal to 1×10 17 cm -3 Less than or equal to 5×10 19 cm -3 .

9. The medium-low voltage SIC IGBT device according to any one of claims 1 to 7, characterized in that: The doping concentration of the electric field cutoff layer (2) is in the range of greater than or equal to 1×10 16 cm -3 Less than or equal to 10 17 cm -3 .

10. The medium and low voltage SIC IGBT device according to claim 4, characterized in that: Also includes: A body region (4) of a first doping type, located above the drift region (3); A first doping type source region (51) and a second doping type source region (52), located on the body region (4); A groove, the groove entering into the drift region (3); A gate oxide layer (62) formed on the inner bottom and sidewalls of the trench; A gate (61) is filled in the space surrounded by the gate oxide layer (62); A first doping type shielding region (7) located below the gate oxide layer (62); A back metal (8) is formed on the back side of the substrate (1).

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