A medium and low voltage SIC IGBT device
By setting the collecting area and epitaxial layer on the front of the substrate of the SIC IGBT device and connecting the collecting area from the back, the problem that the traditional SIC IGBT device structure cannot be suitable for medium and low voltage devices is solved, and the effect of low breakdown voltage and cost reduction is achieved.
Patent Information
- Application Number
- CN202411735889.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-29
- Publication Date
- 2025-04-01
AI Technical Summary
The traditional SIC IGBT device structure cannot be suitable for medium and low voltage SIC IGBT devices, resulting in increased process difficulty and increased cost.
By providing a collector region and epitaxial layer on the front of the substrate and connecting the collector region from the back of the device, the thickness of the SIC material that holes need to pass through is reduced, thereby reducing the breakdown voltage.
It realizes low breakdown voltage of medium and low voltage SIC IGBT devices, is suitable for SIC IGBT devices in the medium and low voltage range, and reduces production costs.
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Figure CN119743965A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a medium- and low-voltage SIC IGBT device. Background Art
[0002] Compared with SIC MOS devices, SIC IGBT devices have a twin conduction mechanism due to the increase of collector area, which further reduces the conduction voltage drop of SIC MOS devices. Figure 1 The schematic diagram of the structure of a conventional trench gate SIC IGBT device with a withstand voltage of more than 4500V includes a collector metal 1-1, a P-type heavily doped collector region 1-2, an N-type SIC material drift region 1-3, a P-body region 1-4 (P-type lightly doped body region 1-4), an ILD dielectric 1-5, an emitter metal 1-6, a gate 1-7, a gate oxide layer 1-8, and an N+ emitter region 1-9; wherein, an ILD (Inter-Layer Dielectric) is a dielectric located between different metal layers and is used to isolate adjacent metal layers.
[0003] Since SIC materials have a wide bandgap and high critical breakdown field strength, the withstand voltage of SIC IGBT devices manufactured according to the thickness allowed by normal processes (above 50μm) is above 4500V. The thicker the thickness, the larger the saturation voltage Vcesat of the IGBT device. Figure 1 As shown, due to the large thickness of the drift region 1 - 3 , the drift region 1 - 3 can already play a supporting role, that is, the drift region 1 - 3 also serves as a substrate.
[0004] For the manufacture of medium and low voltage SIC IGBT devices with voltage levels of 1700V and below, the actual effective withstand voltage SIC drift region thickness only needs to be 10μm or less. However, due to the limitation of thinning process capabilities, a relatively thick SIC substrate is actually required for process support. Because the drift region of medium and low voltage SIC IGBT devices is too thin, the process cannot be implemented and it is very easy to cause fragmentation. Therefore, a thicker SIC substrate needs to be set up separately as a supporting structure for the device. On the one hand, a thicker SIC substrate will bring about a significant increase in cost, and on the other hand, it will increase the difficulty of process implementation.
[0005] Therefore, the structure of the traditional SIC IGBT device cannot be applied to medium and low voltage SIC IGBT devices, which is a technical problem that those skilled in the art urgently need to solve.
[0006] The above information disclosed in the background section is only for enhancing understanding of the background of the present application and therefore it may contain information that does not form the prior art known to a person of ordinary skill in the art. Summary of the invention
[0007] The present application provides a medium-low voltage SIC IGBT device to solve the technical problem that the structure of a traditional SIC IGBT device cannot be applied to medium-low voltage SIC IGBT devices.
[0008] The present application provides a medium-low voltage SIC IGBT device, including:
[0009] substrate;
[0010] An epitaxial layer of a second doping type is formed on the substrate;
[0011] A collector region of a first doping type formed in the epitaxial layer;
[0012] a collector metal formed on the back side of the substrate;
[0013] A collector region connection hole connecting the lower surface of the collector region to the upper surface of the collector metal;
[0014] The collector region lead-out metal is filled in the collector region connection hole, the upper end of the collector region lead-out metal is connected to the lower surface of the collector region, and the lower end of the collector region lead-out metal is connected to the upper surface of the collector metal.
[0015] Due to the adoption of the above technical solution, this application has the following technical effects:
[0016] In the medium and low voltage SIC IGBT device of the present application, the substrate 3 is the supporting structure of the entire SIC IGBT device, and the collector region 5 and the epitaxial layer are sequentially arranged on the front side of the substrate 3 from bottom to top, that is, the collector region 5 is located on the front side of the substrate 3. The medium and low voltage SIC IGBT device of the present application adopts a method of connecting the collector region from the back side of the device, and the specific method is the collector region connection hole and the collector region lead-out metal 4. The collector region connection hole connects the lower surface of the collector region 5 to the upper surface of the collector metal 1; the collector region lead-out metal 4 is filled in the collector region connection hole, the upper end of the collector region lead-out metal is connected to the lower surface of the collector region 5, and the lower end of the collector region lead-out metal 4 is connected to the upper surface of the collector metal 1. Thereby, the collector region 3 is connected from the back side of the device.
[0017] The substrate of the traditional SIC IGBT device ( Figure 1The front side of the drift region 1-3 (also serving as the substrate) is the P-body region 1-4, and the collector region 1-2 is arranged on the back side of the substrate. When the collector region 1-2 is connected to the positive potential and the collector region 1-2 injects holes into the N+ emitter region 1-9 serving as the emitter, the holes need to pass through the substrate before reaching the emitter. The substrate is a SIC material, and the substrate as a supporting structure of the device requires a large thickness, even if the thinning process is limited to about 50 microns. In this way, the thickness of the SIC material (the thickness of the substrate) that the holes need to pass through is large. In addition, the characteristic of the SIC material itself that the critical breakdown electric field is strong, which leads to the breakdown voltage of the traditional SIC IGBT device being generally greater than 4500V.
[0018] Compared with the traditional SIC IGBT device, the medium and low voltage SIC IGBT device of the present application realizes the upward lifting of the collector region 5, the collector region 5 is located above the substrate 3, and the epitaxial layer is above the collector region. In the process of the collector region 5 being connected to the positive potential and injecting holes into the emitter region 13 as the emitter, the holes do not need to pass through the substrate, but need to pass through the epitaxial layer before reaching the emitter, that is, the thickness of the SIC material that the holes need to pass through no longer includes the thickness of the substrate 3. In this way, the breakdown voltage of the medium and low voltage SIC IGBT device of the present application can be relatively low, and it is suitable for SIC IGBT devices in the medium and low voltage range.
[0019] The structure of the medium and low voltage SIC IGBT device of the present application is suitable for medium and low voltage SiC IGBT devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0021] Figure 1 It is a schematic diagram of the structure of a conventional trench gate SIC IGBT device with a withstand voltage of more than 4500V;
[0022] Figure 2 A schematic diagram of a specific implementation of the medium and low voltage SIC IGBT device of the present application;
[0023] Figure 3 A schematic diagram of another specific implementation of the medium and low voltage SIC IGBT device of the present application;
[0024] Figure 4 A schematic diagram of another specific implementation of the medium and low voltage SIC IGBT device of the present application;
[0025] Figure 5A schematic diagram of completing step S1 of the method for preparing a medium- and low-voltage SIC IGBT device of the present application;
[0026] Figure 6 A schematic diagram of completing step S2 of the method for preparing a medium- and low-voltage SIC IGBT device of the present application;
[0027] Figure 7 A schematic diagram of completing step S3 of the method for preparing a medium- and low-voltage SIC IGBT device of the present application;
[0028] Figure 8 A schematic diagram of completing step S4 of the method for preparing a medium- and low-voltage SIC IGBT device of the present application;
[0029] Fig. 9 A schematic diagram of completing step S5 of the method for preparing a medium- and low-voltage SIC IGBT device of the present application;
[0030] Fig.10 A schematic diagram of completing step S6 of the method for preparing a medium- and low-voltage SIC IGBT device of the present application;
[0031] Fig.11 This is a schematic diagram of completing step S7 of the method for preparing a medium- and low-voltage SIC IGBT device of the present application.
[0032] Reference numerals:
[0033] In the background technology:
[0034] Collector metal 1-1, collector region 1-2, drift region 1-3, P-body region 1-4,
[0035] ILD dielectric 1-5, emitter metal 1-6, gate 1-7, gate oxide 1-8, N+ emitter region 1-9;
[0036] In this application:
[0037] Collector metal 1, collector metal insulating layer 2, substrate 3, collector region lead metal 4,
[0038] Collector region 5, electric field stop layer 6, drift region 7, base region 8, dielectric layer 9, emitter metal 10,
[0039] Gate electrode 11, gate oxide layer 12, emitter region 13. DETAILED DESCRIPTION
[0040] In order to make the technical solutions and advantages of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.
[0041] Embodiment 1
[0042] like Figure 2 , Figure 3 and Figure 4 As shown, the medium and low voltage SIC IGBT device of the present application includes:
[0043] Substrate 3;
[0044] An epitaxial layer of a second doping type is formed on the substrate;
[0045] A collector region 5 of a first doping type is formed in the epitaxial layer, and correspondingly, the collector region 5 is located on the substrate 3;
[0046] A collector metal 1 formed on the back side of the substrate;
[0047] A collector region connection hole connecting the lower surface of the collector region 5 to the upper surface of the collector metal 1;
[0048] The collector region lead-out metal 4 is filled in the collector region connection hole, the upper end of the collector region lead-out metal is connected to the lower surface of the collector region 5 , and the lower end of the collector region lead-out metal 4 is connected to the upper surface of the collector metal 1 .
[0049] In the medium and low voltage SIC IGBT device of the present application, the substrate 3 is the supporting structure of the entire SIC IGBT device, and the collector region 5 and the epitaxial layer are sequentially arranged on the front side of the substrate 3 from bottom to top, that is, the collector region 5 is located on the front side of the substrate 3. The medium and low voltage SIC IGBT device of the present application adopts a method of connecting the collector region from the back side of the device, and the specific method is the collector region connection hole and the collector region lead-out metal 4. The collector region connection hole connects the lower surface of the collector region 5 to the upper surface of the collector metal 1; the collector region lead-out metal 4 is filled in the collector region connection hole, the upper end of the collector region lead-out metal is connected to the lower surface of the collector region 5, and the lower end of the collector region lead-out metal 4 is connected to the upper surface of the collector metal 1. Thereby, the collector region 3 is connected from the back side of the device.
[0050] The substrate of the traditional SIC IGBT device ( Figure 1The front side of the drift region 1-3 (also serving as the substrate) is the P-body region 1-4, and the collector region 1-2 is arranged on the back side of the substrate. When the collector region 1-2 is connected to the positive potential and the collector region 1-2 injects holes into the N+ emitter region 1-9 serving as the emitter, the holes need to pass through the substrate before reaching the emitter. The substrate is a SIC material, and the substrate as a supporting structure of the device requires a large thickness, even if the thinning process is limited to about 50 microns. In this way, the thickness of the SIC material (the thickness of the substrate) that the holes need to pass through is large. In addition, the characteristic of the SIC material itself that the critical breakdown electric field is strong, which leads to the breakdown voltage of the traditional SIC IGBT device being generally greater than 4500V.
[0051] Compared with the traditional SIC IGBT device, the medium and low voltage SIC IGBT device of the present application realizes the upward lifting of the collector region 5, the collector region 5 is located above the substrate 3, and the epitaxial layer is above the collector region. In the process of the collector region 5 being connected to the positive potential and injecting holes into the emitter region 13 as the emitter, the holes do not need to pass through the substrate, but need to pass through the epitaxial layer before reaching the emitter, that is, the thickness of the SIC material that the holes need to pass through no longer includes the thickness of the substrate 3. In this way, the breakdown voltage of the medium and low voltage SIC IGBT device of the present application can be relatively low, and it is suitable for SIC IGBT devices in the medium and low voltage range.
[0052] The structure of the medium and low voltage SIC IGBT device of the present application is suitable for medium and low voltage SiC IGBT devices.
[0053] In implementation, such as Figure 2 , Figure 3 and Figure 4 As shown, the lower surface of the collector region 5 is flush with the lower surface of the epitaxial layer.
[0054] Such a structure is convenient for processing and manufacturing.
[0055] As an alternative, Figure 2 and Figure 3 As shown, there are multiple collector regions 5, and each collector region 5 is located in the same layer and is arranged at intervals;
[0056] One of the collector regions 5 and one of the collector region lead-out metals 4 are connected correspondingly.
[0057] In implementation, such as Figure 2 and Figure 3 As shown, the doping concentration of the collector region 5 has a value range of greater than or equal to 10 17 cm -3 Less than or equal to 10 19 cm -3The thickness of the collector region 5 ranges from greater than or equal to 0.1 micrometer to less than or equal to 0.5 micrometer.
[0058] By reasonably controlling the doping concentration and thickness of the collector region, the conductivity and depletion layer width of the collector region can be optimized, thereby improving the overall performance of the semiconductor device.
[0059] In implementation, such as Figure 2 and Figure 3 As shown, the ratio of the connection area of one collector region 5 and one collector region lead-out metal 4 to the area of the lower surface of one collector region 5 is greater than or equal to 50% and less than or equal to 100%.
[0060] In this way, a good connection between the collector region 5 and the collector region lead-out metal 4 is achieved.
[0061] As an alternative, Figure 4 As shown, the collector region 5 is a whole layer of collector region 5; and the collector region lead-out metal 4 is multiple;
[0062] The collector region 5 of the entire layer and each collector region lead-out metal 4 are connected correspondingly.
[0063] In implementation, such as Figure 4 As shown, the doping concentration of the collector region 5 of the entire layer has a value range of greater than or equal to 10 17 cm -3 Less than or equal to 10 19 cm -3 The thickness of the collector region 5 ranges from greater than or equal to 0.1 micrometer to less than or equal to 0.5 micrometer.
[0064] In practice, the ratio of the sum of the connection areas of the collector region 5 of the entire layer and each collector region lead-out metal 4 to the area of the lower surface of the collector region 5 of the entire layer is greater than or equal to 50% and less than 100%.
[0065] In implementation, the substrate is an intrinsic semiconductor silicon substrate or a first doping type silicon substrate;
[0066] The epitaxial layer is a drift region of the second doping type of the SIC material.
[0067] The medium and low voltage SIC IGBT device substrate of the present application adopts a silicon substrate, and the epitaxial layer adopts a SIC material. Since the SIC material is expensive, while the silicon price is relatively cheap. The silicon substrate as a supporting structure does not affect the performance of the SIC IGBT device, but can greatly reduce the cost of the SIC IGBT device, which is conducive to improving the competitiveness of the SIC IGBT device.
[0068] In implementation, such as Figure 2 , Figure 3 and Figure 4 As shown, the epitaxial layer includes:
[0069] An electric field stop layer 6 of a second doping type is formed on the substrate 3;
[0070] A drift region 7 of a second doping type is formed on the electric field stop layer 6; wherein the doping concentration of the electric field stop layer 6 is greater than the doping concentration of the drift region 7;
[0071] The collector region 5 is formed in the electric field stop layer 6, and correspondingly, the lower surface of the collector region 5 is flush with the lower surface of the electric field stop layer 6;
[0072] Among them, Figure 2 , Figure 3 and Figure 4 As shown, the substrate 3 is a silicon substrate of an intrinsic semiconductor or a silicon substrate of a first doping type; the first doping type is P-type doping, and the second doping type is N-type doping;
[0073] The drift region 7 is an N-type doped drift region of a SIC material, and the electric field stop layer 6 is an N-type doped electric field stop layer of a SIC material.
[0074] The medium and low voltage SIC IGBT device substrate of the present application adopts a silicon substrate, and the drift region 7 and the electric field stop layer 6 adopt SIC materials. Since the SIC material is expensive, while the silicon price is relatively cheap. The silicon substrate as a supporting structure does not affect the performance of the SIC IGBT device, but can greatly reduce the cost of the SIC IGBT device, which is conducive to improving the competitiveness of the SIC IGBT device.
[0075] It is a better implementation method to simultaneously set the drift region 7 of the second doping type and the electric field stop layer 6 of the second doping type. In this way, the various parameters of the drift region 7 with a lower doping concentration are used to meet the requirements of the withstand voltage of the SIC IGBT device, and the various parameters of the electric field stop layer 6 with a higher doping concentration are used to meet the requirements of the electric field cutoff of the SIC IGBT device. Therefore, the withstand voltage of the medium and low voltage SIC IGBT device of the present application can be kept low, and the electric field can be cut off in the electric field cutoff layer 6, and the thickness of the entire SIC IGBT device is kept small.
[0076] In implementation, such as Figure 2 , Figure 3 and Figure 4 As shown, the medium and low voltage SIC IGBT device of the present application also includes:
[0077] A collector metal insulating layer 2 is formed between the substrate 1 and the collector metal 1;
[0078] The collector region connection hole penetrates the substrate 3 and the collector metal insulation layer 2 .
[0079] The upper end of the collector region lead metal is connected to the lower surface of the collector region 5, and the collector region lead metal 4 penetrates the substrate 3 and the collector metal insulating layer 2 to achieve the connection between the lower end of the collector region lead metal 4 and the upper surface of the collector metal 1. The collector metal insulating layer 2 insulates and separates the collector metal 1 from the substrate 3 to protect the substrate 3.
[0080] In the implementation, the thickness of the electric field cutoff layer 6 is in the range of 2 μm or more and 3 μm or less; the doping concentration of the electric field cutoff layer 6 is in the range of 1×10 16 cm -3 Less than or equal to 1×10 17 cm -3 ;
[0081] The thickness of the drift region 7 is in the range of 650 μm or more and 1700 μm or less, and the doping concentration of the drift region 7 is in the range of 2×10 14 cm -3 Less than or equal to 1×10 15 cm -3 .
[0082] The doping concentration and thickness of the drift region are matched to meet the requirements of low withstand voltage of the SIC IGBT device, and the breakdown voltage of the SIC IGBT device can be in the range of greater than or equal to 650V and less than or equal to 1700V.
[0083] The doping concentration and thickness of the electric field cutoff layer are matched to meet the electric field cutoff requirements of the SIC IGBT device.
[0084] Specifically, Figure 2 , Figure 3 and Figure 4 As shown, the medium and low voltage SIC IGBT device of the present application also includes:
[0085] A base region 8 of a first doping type, formed on the drift region 7;
[0086] A gate trench is formed in the base region 8 and the drift region 7;
[0087] A gate oxide layer 12 is formed on the bottom and sidewalls of the gate trench;
[0088] A gate electrode 11 is formed in a gate oxide layer 12;
[0089] An emitter region 13 of a second doping type is formed on one side or both sides of the gate trench;
[0090] A dielectric layer 9 formed on the gate electrode 11;
[0091] The emitter metal 10 covers the base region 8 , the emitter region 13 , and the dielectric layer 9 .
[0092] Figure 2 and Figure 4 In the embodiment, the emitter region 13 is formed on one side of the gate trench. Figure 3 In the embodiment, the emitter region 13 is formed on both sides of the gate trench.
[0093] In chronological order, the method for preparing the medium and low voltage SIC IGBT device of the present application comprises the following steps:
[0094] Step S1: Provide a substrate 3 of intrinsic silicon material, such as Figure 5 As shown,
[0095] Step S2: forming an electric field stop layer 6 and a drift region 7 of a first doping type SIC material on the upper surface of the substrate 3, such as Figure 6 As shown;
[0096] Step S3: On the surface of the drift region 7 of the first doping type SIC material, a cell region structure gate oxide layer 12, a gate electrode 11, a base region 8 and an emitter region 13 are sequentially formed, such as Figure 7 As shown;
[0097] Step S4: Back thinning is performed on the lower surface of the substrate 3 to form a collector metal insulating layer 2, and then deep trench etching is performed, such as Figure 8 As shown;
[0098] Step S5: After that, the through hole is injected and metal is filled in sequence to form a structural collector region 5 and a collector region lead-out metal 4, such as Fig. 9 As shown;
[0099] Step S6: On the upper surface of the substrate 3, an emitter metal 10 is formed, such as Fig.10 As shown;
[0100] Step S7: On the lower surface of the substrate 3, a collector metal 1 is formed, such as Fig.11 shown.
[0101] The medium and low voltage SIC IGBT devices of this application and Figure 1 The simulation data of traditional SIC IGBT devices are shown in the following table:
[0102] Structural comparison Thickness of drift zone BV(Withstand Voltage) Figure 1 Traditional SIC IGBT Devices 50μm 5700V Medium and low voltage SIC IGBT devices of this application 12μm 1340V
[0103] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.
[0104] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0105] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.
[0106] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.
[0107] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.
[0108] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A medium and low voltage SIC IGBT device, characterized in that: include: Substrate (3); An epitaxial layer of a second doping type is formed on the substrate (3); A collector region (5) of a first doping type formed in the epitaxial layer; A collector metal (1) formed on the back side of the substrate; A collector region connection hole connecting the lower surface of the collector region (5) to the upper surface of the collector metal (1); The collector region lead-out metal (4) is filled in the collector region connection hole, the upper end of the collector region lead-out metal is connected to the lower surface of the collector region (5), and the lower end of the collector region lead-out metal (4) is connected to the upper surface of the collector electrode metal (1).
2. The medium and low voltage SIC IGBT device according to claim 1, characterized in that: The lower surface of the collector region (5) is flush with the lower surface of the epitaxial layer.
3. The medium and low voltage SIC IGBT device according to claim 2, characterized in that: There are a plurality of collector regions (5), each of which is located in the same layer and is arranged at intervals; One of the collector regions (5) and one of the collector region lead-out metals (4) are connected correspondingly.
4. The medium and low voltage SIC IGBT device according to claim 2, characterized in that: The collector region (5) is a whole-layer collector region (5), and the collector region lead-out metal (4) is a plurality of metals; The collector region (5) of the entire layer and each collector region lead-out metal (4) are connected correspondingly.
5. The medium-low voltage SIC IGBT device according to any one of claims 1 to 4, characterized in that: The substrate is an intrinsic semiconductor silicon substrate or a first doping type silicon substrate; The epitaxial layer is a drift region of the second doping type of the SIC material.
6. The medium-low voltage SIC IGBT device according to claim 3 or 4, characterized in that: The doping concentration of the collector region (5) has a value range of greater than or equal to 10 17 cm -3 Less than or equal to 10 19 cm -3 The thickness of the collector region (5) is in the range of greater than or equal to 0.1 micrometer and less than or equal to 0.5 micrometer.
7. The medium and low voltage SICIGBT device according to claim 3, characterized in that: The ratio of the connection area of a collector region (5) and a collector region lead-out metal (4) to the area of the lower surface of a collector region (5) is greater than or equal to 50% and less than 100%.
8. The medium-low voltage SIC IGBT device according to any one of claims 2 to 4, characterized in that: The epitaxial layer comprises: An electric field stop layer (6) of a second doping type, formed on the substrate (3); A drift region (7) of a second doping type is formed on the electric field stop layer (6); wherein the doping concentration of the electric field stop layer (6) is greater than the doping concentration of the drift region (7); The collector region (5) is formed in the electric field stop layer (6); The substrate (3) is an intrinsic semiconductor silicon substrate or a silicon substrate of a first doping type; the first doping type is P-type doping, and the second doping type is N-type doping; The drift region (7) is an N-type doped drift region of a SIC material, and the electric field stop layer (6) is an N-type doped electric field stop layer of a SIC material.
9. The medium-low voltage SICIGBT device according to claim 8, characterized in that: Also includes: A collector metal insulating layer (2) formed between the substrate (3) and the collector metal (1); Wherein, the collector region connection hole penetrates the substrate (3) and the collector metal insulation layer (2).
10. The medium and low voltage SIC IGBT device according to claim 9, characterized in that: The thickness of the electric field cutoff layer (6) is in the range of greater than or equal to 2 μm and less than or equal to 3 μm; the doping concentration of the electric field cutoff layer (6) is in the range of greater than or equal to 1×10 16 cm -3 Less than or equal to 1×10 17 cm -3 ; The thickness of the drift region (7) is in the range of greater than or equal to 650 μm and less than or equal to 1700 μm, and the doping concentration of the drift region (7) is in the range of greater than or equal to 2×10 14 cm -3 Less than or equal to 1×10 15 cm -3 .