IGBT device and preparation method thereof
By providing a specific trench and a fill layer on the upper surface of the P-type body region of the IGBT device, and setting the first emitter contact hole in the region close to the first emitter trench, the discrete electrical parameter distribution and performance degradation caused by wafer warping are solved, and more stable and consistent device performance is achieved.
Patent Information
- Application Number
- CN202411991939.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-04-01
AI Technical Summary
During the preparation process, the electrical parameter distribution and performance degradation caused by wafer warping.
By providing a gate trench extending to the substrate layer and a plurality of emitter trenches extending to the substrate layer on the upper surface of the P-type body region of the IGBT device, and filling a control gate and emitter fill layer on the upper surface of the gate oxide layer, the first emitter contact hole is arranged in the region close to the first emitter trench.
It effectively avoids the problem of device performance degradation caused by the emitter contact hole being close to the gate trench, improves the stability and consistency of the threshold voltage and saturation voltage drop parameters of the device, and improves the yield.
Smart Images
Figure CN119743967A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to an IGBT device and a preparation method thereof. Background Art
[0002] The Insulate-Gate Bipolar Transistor (IGBT) combines the advantages of the bipolar transistor BJT and the field-effect transistor MOSFET. It has the characteristics of low driving power, fast switching speed and small on-resistance. It is widely used in industrial electronics, automotive electronics and consumer electronics fields, such as inverters, photovoltaics, energy storage, charging piles, etc., to realize the control and conversion of electric energy.
[0003] With the continuous advancement of process technology, the cell pitch of modern micro-groove IGBT devices is getting smaller and smaller, and the vertical thickness of the device is getting thinner and thinner. During the processing of the wafer, after the front groove is etched, there is still a process of thermal oxidation growth of the gate oxide layer and high-temperature push-in of the P base region impurities. Due to the stress imbalance between the front and back of the wafer, the wafer warps, making the wafer surface no longer flat during subsequent processing, and the upper and lower layers of the pattern appear to be misaligned at the edge of the wafer. For micro-groove IGBT devices, the mesa structure is reduced to the sub-micron level. If wafer warpage occurs, the emitter contact hole position deviates from the center of the mesa. The P-type impurities injected after the emitter contact hole is opened will cause the channel doping concentration of the trench near the hole to be too high, resulting in the threshold voltage V of the IGBT device. th and the on-state voltage drop V ce(sat) Drift causes problems such as poor consistency of electrical parameters of IGBT devices within the wafer and discrete parameter distribution. Summary of the invention
[0004] The embodiment of the present invention provides an IGBT device and a method for manufacturing the same, which can solve the problem of discrete distribution of device electrical parameters and degradation of device performance caused by wafer warping during device manufacturing, and improve the parameter consistency and yield rate within the wafer of the IGBT device.
[0005] In a first aspect, an IGBT device provided by an embodiment of the present invention includes:
[0006] A substrate layer, a carrier storage layer and a P-type body region are stacked in sequence from bottom to top, wherein a gate trench and a plurality of emitter trenches extending to the substrate layer are provided on the upper surface of the P-type body region, wherein the gate trench is located on one side of the IGBT device and is adjacent to only one emitter trench;
[0007] A continuous gate oxide layer, the gate oxide layer is arranged on the upper surface of the P-type body region and covers the surface of the gate trench and the emitter trench, wherein a control gate filling the gate trench is also arranged on the upper surface of the gate oxide layer in the gate trench, and an emitter filling layer filling the emitter is also arranged on the upper surface of the gate oxide layer in the emitter trench;
[0008] An interlayer dielectric layer, the interlayer dielectric layer is arranged on the upper surfaces of the gate oxide layer, the control gate and the emitter filling layer, and a plurality of emitter contact holes extending to the P-type body region are arranged on the upper surface of the interlayer dielectric layer, wherein the first emitter contact hole is arranged between the gate trench and the first emitter trench and is close to the first emitter trench, and the first emitter trench is adjacent to the gate trench.
[0009] In a second aspect, an embodiment of the present invention provides a method for preparing an IGBT device, comprising:
[0010] Performing ion implantation in the active region of the substrate to form a carrier storage layer in the active region of the substrate, forming a substrate layer below the active region of the substrate, and forming a P-type body region above the active region of the substrate, wherein the active region is located in the middle of the substrate;
[0011] Etching a gate trench and a plurality of emitter trenches extending to the substrate layer on the upper surface of the P-type body region, wherein the gate trench is located on one side of the IGBT device and is adjacent to only one emitter trench;
[0012] A continuous gate oxide layer is grown on the upper surface of the P-type body region and covers the surface of the gate trench and the emitter trench;
[0013] Depositing polysilicon on the upper surface of the gate oxide layer in the gate trench and the upper surface of the gate oxide layer in the emitter trench to fill the gate trench and the emitter trench, so as to form a control gate in the gate trench and an emitter filling layer in the emitter trench;
[0014] Depositing an interlayer dielectric layer on the upper surfaces of the gate oxide layer, the control gate and the emitter filling layer;
[0015] A plurality of emitter contact holes extending to the P-type body region are etched on the upper surface of the interlayer dielectric layer, wherein the first emitter contact hole is arranged between the gate trench and the first emitter trench and is close to the first emitter trench, and the first emitter trench is adjacent to the gate trench; and the second emitter contact hole is arranged between the two emitter trenches.
[0016] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: according to the IGBT device provided by the present invention, by setting the first emitter contact hole in the area close to the first emitter trench, the problem of device performance degradation caused by the first emitter contact hole being close to the gate trench can be avoided. Furthermore, by reducing the bottom area of the emitter contact hole and thus reducing the area of the high-doping concentration P+ contact area covering the emitter contact hole, the high-doping concentration P+ contact area can be further avoided from being close to the gate trench, and the P+ doping area can be avoided from affecting the impurity distribution in the device channel area, thereby further improving the stability and consistency of the device threshold voltage and saturation voltage drop parameters and the yield. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 A schematic diagram of the structure of an IGBT device provided by an embodiment of the present invention;
[0018] Figure 2 A schematic diagram of a gate groove and an emitter groove provided by an embodiment of the present invention;
[0019] Figure 3 A schematic diagram of a specific structure of an IGBT device provided by an embodiment of the present invention;
[0020] Figure 4 A schematic diagram of the specific structure of another IGBT device provided by an embodiment of the present invention;
[0021] Figure 5 A flowchart of a method for manufacturing an IGBT device provided by an embodiment of the present invention;
[0022] Figure 6a-Figure 6i A schematic diagram of a preparation scenario of an IGBT device provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0023] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.
[0024] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.
[0025] It should also be understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
[0026] As used in the present specification and the appended claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]", depending on the context.
[0027] In addition, in the description of the present specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.
[0028] References to "one embodiment" or "some embodiments" etc. described in the present specification mean that one or more embodiments of the present invention include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.
[0029] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.
[0030] Example 1
[0031] Figure 1 The structure diagram of an IGBT device provided by an embodiment of the present invention is shown. As an example but not limitation, the IGBT device may include: a substrate layer 1, a carrier storage layer 2, a P-type body region 3, a gate oxide layer 4, and an interlayer dielectric layer 5.
[0032] In some embodiments, see Figure 1 , the substrate layer 1, the carrier storage layer 2 and the P-type body region 3 are stacked in sequence from bottom to top. Figure 2, a gate trench extending to the substrate layer 1 and a plurality of emitter trenches (only three are shown here) are provided on the upper surface of the P-type body region 3. A continuous gate oxide layer 4 is provided on the upper surface of the P-type body region 3 and covers the surfaces of the gate trench and the emitter trench. A control gate 41 is also filled on the upper surface of the gate oxide layer 4 of the gate trench, and an emitter filling layer 42 is also filled on the upper surface of the gate oxide layer of the emitter trench. An interlayer dielectric layer 5 is also provided on the upper surfaces of the gate oxide layer 4, the control gate 41 and the emitter filling layer 42. See FIG. Figure 1 A plurality of emitter contact holes 51 are also provided on the upper surface of the interlayer dielectric layer 5 .
[0033] In one possible implementation, see Figure 1 , the trenches (including gate trenches and emitter trenches) and the emitter contact holes 51 may be arranged in a staggered manner. Figure 1 and Figure 2 , the first emitter contact hole (see Figure 1 101) is disposed in the gate trench and the first emitter trench (see Figure 2 201) in the middle and the spacing with the first emitter trench is close.
[0034] Exemplarily, the first emitter trench is an emitter trench adjacent to the gate trench.
[0035] Exemplarily, the first emitter contact hole is an emitter contact hole between the gate trench and the first emitter trench.
[0036] Since the current IGBT device usually sets the first emitter contact hole between the gate trench and the first emitter trench, and the performance of the gate trench is more easily affected by the emitter contact hole; if the first emitter contact hole is etched near the gate contact hole due to process or other reasons. When ion implantation is performed near the bottom surface of the emitter contact hole, the channel doping concentration on one side of the gate trench will be too high, resulting in the threshold voltage and on-resistance of the device being too large, causing the consistency of electrical parameters in the wafer to deteriorate, the parameter distribution to be discrete, and other problems, resulting in the performance of the device to decline. However, the present invention sets the first emitter contact hole in the area close to the first emitter trench, even if there is an error in the processing that causes it to deviate from the gate trench, within a reasonable error range, the distance between the gate trench and the first emitter contact hole still meets the process requirements, which can avoid a series of subsequent problems and improve device performance.
[0037] In one example, see Figure 1 The bottom inner diameter of the emitter contact hole 51 may be smaller than the top inner diameter of the emitter contact hole, for example, the inner diameter of the portion thereof in the P-type body region may gradually decrease.
[0038] Optionally, the inner diameter of the bottom of the emitter contact hole 51 may be half of the inner diameter of the top.
[0039] In one possible implementation, see Figure 3 The P-type body region 3 may include an N+ emitter region 31 , a P+ contact region 32 and a P body region 33 .
[0040] Specifically, the N+ emitter region 31 can be arranged on the upper surface of the P-type body region 3 on both sides of the gate trench, and on the upper surface of the P-type body region on the side of the second emitter trench away from the gate trench. The P+ contact region 32 can include the bottom surface of the emitter contact hole, and the P-body region 33 can be the region of the P-type body region 3 except the N+ emitter region 31 and the P+ contact region 32.
[0041] Exemplarily, the second emitter trench (see Figure 2 202) is the emitter trench farthest from the gate trench.
[0042] In one example, both the P+ contact region 32 and the P body region 33 may be P-type impurity doped regions, and the N+ emitter region 31 may be N-type impurity doped region.
[0043] Optionally, the doping concentration of the P+ contact region 32 may be higher than that of the P body region 33 .
[0044] In one possible implementation, see Figure 3 The substrate layer 1 may include a back collector region 11 and a buffer layer 12 .
[0045] Specifically, see Figure 3 The back collector region 11 extends upward from the lower surface of the substrate layer 1 , and the buffer layer 12 is arranged on the upper surface of the back collector region 11 ; and the sum of the thicknesses of the two is less than the thickness of the substrate layer 1 .
[0046] In one example, the back collector region may be a P-type impurity doped region, and the buffer layer may be a hydrogen ion doped region.
[0047] According to the IGBT device provided by the present invention, by arranging the first emitter contact hole in the area close to the first emitter trench, the problem of device performance degradation caused by the first emitter contact hole being close to the gate trench can be avoided. Furthermore, by reducing the bottom area of the emitter contact hole and thus reducing the area of the high-doping concentration P+ contact area covering the emitter contact hole, the high-doping concentration P+ contact area can be further avoided from being close to the gate trench, thereby further improving the device performance.
[0048] Example 2
[0049] Based on Example 1, Figure 4FIG. 1 is a schematic diagram showing a specific structure of an IGBT device provided by an embodiment of the present invention. Figure 4 The IGBT device may further include a front metal layer 6 and a back metal layer 7 .
[0050] For example, see Figure 4 The front metal layer 6 can be disposed on the upper surface of the interlayer dielectric layer 5 and fill the emitter contact hole 51. The back metal layer 7 can be disposed on the lower surface of the substrate layer 1.
[0051] Example 3
[0052] Based on Example 1, Figure 5 The flowchart shown is a method for manufacturing an IGBT device according to an embodiment of the present invention. As an example but not a limitation, the method may include steps S501-S505, each of which is described below.
[0053] S501, ion implantation is performed in the active region of the substrate to form a carrier storage layer in the active region of the substrate, a substrate layer is formed below the active region of the substrate, and a P-type body region is formed above the active region of the substrate.
[0054] For example, see Figure 6a , the active region can be located in the middle of the substrate, not necessarily in the middle of the substrate.
[0055] In one example, if an N-type IGBT device is to be prepared, an N-type substrate can be prepared, a P+ guard ring is implanted in the middle of the N-type substrate and debonded at high temperature to form a terminal guard ring structure, and then a field oxide layer is thermally grown on the upper surface of the substrate to obtain a structure such as Figure 6b The structure shown in FIG. Then the field oxide layer can be etched away to form an active region in the middle of the device. After that, N-type impurities are injected into the active region at high energy, and a carrier storage layer 2 is formed in the active region after high-temperature junction. The substrate below the carrier storage layer 2 (i.e., below the active region) forms a substrate layer 1; the substrate above the carrier storage layer 2 (i.e., above the active region) forms a P-type body region 3, and the structure shown in FIG. Figure 6c The structure shown.
[0056] S502 , etching a gate trench and a plurality of emitter trenches extending to the substrate layer on the upper surface of the P-type body region.
[0057] In one example, a hard mask process can be used to deposit oxide in the non-groove area on the P-type body region 3 to prepare a hard mask; then the groove area is etched until the substrate layer to form a gate groove and an emitter groove, and the hard mask is obtained. Figure 2 The structure shown.
[0058] S503, growing a continuous gate oxide layer on the upper surface of the P-type body region and covering the surface of the gate trench and the emitter trench.
[0059] In one example, a sacrificial oxide layer can be thermally grown on the upper surface of the P-type body region, the gate trench and the emitter trench and then removed. After removing the sacrificial oxide layer, a gate oxide layer 4 can be thermally grown to obtain Figure 6d The structure shown.
[0060] S504, depositing polysilicon on the upper surface of the gate oxide layer in the gate trench and the upper surface of the gate oxide layer in the emitter trench to fill the gate trench and the emitter trench, so as to form a control gate in the gate trench and an emitter filling layer in the emitter trench.
[0061] In one example, you can Figure 6d In the structure shown in FIG. 1 , in-situ doped polysilicon is deposited in the gate trench and the emitter trench, and then etched back to the upper surface of the P-type body region to form a control gate 41 in the gate trench and an emitter filling layer 42 in the emitter trench, thereby forming a structure as shown in FIG. Figure 6e The structure shown.
[0062] Exemplarily, the control gate 41 may be connected to the gate of the IGBT device, and the emitter filling layer 42 may be connected to the emitter of the IGBT device.
[0063] S505 , depositing an interlayer dielectric layer on the upper surfaces of the gate oxide layer, the control gate and the emitter filling layer, and etching a plurality of emitter contact holes extending to the P-type body region on the upper surface of the interlayer dielectric layer.
[0064] In one example, before the interlayer dielectric layer 5 is formed, P-type impurities may be firstly implanted into the P-type body region 3 and then debonded at high temperature; then N-type impurities may be implanted into the N+ emitter region in the P-type body region 3 to form an N+ emitter region 31 in the N+ emitter region. Afterwards, oxide and borophosphosilicate glass may be deposited on the upper surfaces of the gate oxide layer 4, the control gate 41 and the emitter filling layer 42 to form the interlayer dielectric layer 5, and the following is obtained: Figure 6f The structure shown in Figure 1 is then etched to obtain the emitter contact hole. Figure 6g Finally, a high concentration of P-type ions can be implanted at the bottom of the emitter contact hole 51 to form a P+ contact region 32 that wraps the bottom surface of the emitter contact hole 51, and a P-body region 33 is formed in the remaining area of the P-type body region 3, so as to obtain the structure shown in FIG. Figure 6h The structure shown.
[0065] Exemplarily, the N+ emitter region may be distributed on the upper surface of the P-type body region 3 on both sides of the gate trench and the upper surface of the P-type body region 3 on one side of the gate trench of the second emitter trench.
[0066] Optionally, based on Example 2, the preparation method may further include steps S506-S508.
[0067] S506, depositing metal in the emitter contact hole and on the upper surface of the interlayer dielectric layer to form a front metal layer.
[0068] In one example, AlSiCu may be deposited on the emitter contact hole 51 and the upper surface of the interlayer dielectric layer 5 to form the front metal layer 6 .
[0069] S507, performing ion implantation on the lower surface of the substrate layer to form a back collector region, and performing hydrogen ion implantation on the substrate layer above the back collector region to form a buffer layer.
[0070] In one example, P-type impurities can be implanted into the lower surface of the substrate layer to form a back collector region 11, and then hydrogen ions are implanted into the substrate layer above the back collector region 11 and thermally annealed to form a buffer layer 12 to obtain the following: Figure 6i The structure shown.
[0071] S508, depositing metal on the lower surface of the substrate layer to form a back metal layer.
[0072] For example, after depositing the back metal layer 7, the following can be obtained: Figure 4 The IGBT device shown.
[0073] In the above embodiments, the description of each embodiment has its own emphasis. For the part that is not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.
Claims
1. An IGBT device, characterized in that: include: A substrate layer, a carrier storage layer and a P-type body region are stacked in sequence from bottom to top, wherein the upper surface of the P-type body region is provided with a gate trench and a plurality of emitter trenches extending to the substrate layer, wherein the gate trench is located on one side of the IGBT device and is adjacent to only one emitter trench; A continuous gate oxide layer, the gate oxide layer is arranged on the upper surface of the P-type body region and covers the surfaces of the gate trench and the emitter trench, wherein a control gate filling the gate trench is also arranged on the upper surface of the gate oxide layer in the gate trench, and an emitter filling layer filling the emitter is also arranged on the upper surface of the gate oxide layer in the emitter trench; An interlayer dielectric layer, wherein the interlayer dielectric layer is arranged on the upper surfaces of the gate oxide layer, the control gate and the emitter filling layer, and a plurality of emitter contact holes extending to the P-type body region are arranged on the upper surface of the interlayer dielectric layer, wherein the first emitter contact hole is arranged between the gate trench and the first emitter trench and is close to the first emitter trench, and the first emitter trench is adjacent to the gate trench.
2. The IGBT device according to claim 1, characterized in that: The inner diameter of the bottom of the emitter contact hole is smaller than the inner diameter of the top of the emitter contact hole.
3. The IGBT device according to claim 2, characterized in that: The inner diameter of the bottom of the emitter contact hole is half of the inner diameter of the top of the emitter contact hole.
4. The IGBT device according to claim 1, characterized in that: The P-type body region comprises: N+ emitter region, the N+ emitter region is arranged on the upper surface of the P-type body region on both sides of the gate trench and the upper surface of the P-type body region on the side of the second emitter trench away from the gate trench, wherein the second emitter trench is the emitter trench farthest from the gate trench, and the thickness of the N+ emitter region is less than the thickness of the P-type body region; A P+ contact area, wherein the P+ contact area wraps the bottom surface of the emitter contact hole; A P body region, wherein the region other than the N+ emitter region and the P+ contact region in the P type body region is the P body region.
5. The IGBT device according to claim 4, characterized in that: The P body region and the P+ contact region are both P-type impurity doped regions, and the doping concentration of the P+ contact region is higher than that of the P body region; the N+ emitter region is an N-type impurity doped region.
6. The IGBT device according to claim 1, characterized in that: The IGBT device further comprises: A front metal layer, the front metal layer is arranged on the upper surface of the interlayer dielectric layer and fills the emitter contact hole; A back metal layer is disposed on the lower surface of the substrate layer.
7. A method for preparing an IGBT device, characterized in that: include: Performing ion implantation in an active region of a substrate to form a carrier storage layer in the active region of the substrate, forming a substrate layer below the active region of the substrate, and forming a P-type body region above the active region of the substrate, wherein the active region is located in the middle of the substrate; Etching a gate trench and a plurality of emitter trenches extending to the substrate layer on the upper surface of the P-type body region, wherein the gate trench is located on one side of the IGBT device and is adjacent to only one emitter trench; Growing a continuous gate oxide layer on the upper surface of the P-type body region and covering the surface of the gate trench and the emitter trench; Depositing polysilicon on the upper surface of the gate oxide layer in the gate trench and the upper surface of the gate oxide layer in the emitter trench to fill the gate trench and the emitter trench, so as to form a control gate in the gate trench and an emitter filling layer in the emitter trench; Depositing an interlayer dielectric layer on the upper surfaces of the gate oxide layer, the control gate and the emitter filling layer; A plurality of emitter contact holes extending to the P-type body region are etched on the upper surface of the interlayer dielectric layer, wherein a first emitter contact hole is arranged between the gate trench and the first emitter trench and is close to the first emitter trench, and the first emitter trench is adjacent to the gate trench; and a second emitter contact hole is arranged between the two emitter trenches.
8. The method according to claim 7, characterized in that Before depositing an interlayer dielectric layer on the upper surfaces of the gate oxide layer, the control gate and the emitter filling layer, the method further comprises: Injecting P-type impurities into the P-type body region, and injecting N-type impurities into the N+ emitter region in the injected P-type body region to form an N+ emitter region in the N+ emitter region, wherein the N+ emitter region is distributed on the upper surface of the P-type body region on both sides of the gate trench and on the upper surface of the P-type body region on the side of the second emitter trench away from the gate trench; Wherein, after etching a plurality of emitter contact holes extending to the P-type body region on the upper surface of the interlayer dielectric layer, the method further comprises: P-type ion implantation is performed at the bottom of the emitter contact hole to form a P+ contact region wrapping the bottom surface of the emitter contact hole, and a P body region is formed in the P-type body region except the N+ emitter region and the P+ contact region.
9. The method according to claim 8, characterized in that After performing P-type ion implantation at the bottom of the emitter contact hole, the method further includes: Depositing metal in the emitter contact hole and on the upper surface of the interlayer dielectric layer to form a front metal layer; Metal is deposited on the lower surface of the substrate layer to form a back metal layer.