Minority carrier enhanced micro-trigger silicon controlled rectifier device

Abstract

The invention relates to the technical field of silicon controlled devices, in particular to a minority carrier enhanced micro-trigger silicon controlled device, which comprises a front base region, a back base region and a top base region, a buried layer with a second doping type is formed in the front base region; and the buried layer and the front base regions on the upper and lower sides form a triode amplification structure, and minority carrier enhancement is performed on the front base regions below the buried layer when the device is switched on. In order to solve the problem of unstable performance of a micro-trigger silicon controlled rectifier device in the prior art, a triode amplification structure is introduced into a front base region through a buried layer in the scheme, and due to the fact that the area, away from an emitter region, of the buried layer is fixed and the doping concentration is fixed, stable trigger control precision can also be achieved under micro current. And minority carriers in the front base region below the buried layer can generate a multiplication effect due to the amplification structure based on the buried layer above, so that the trigger current can be effectively reduced. After the device is triggered, the equivalent resistance after conduction can be effectively reduced through the enhancement of the conductivity modulation effect.

Description

Technical Field

[0001] The present invention relates to the technical field of thyristor devices, and in particular to a minority-carrier enhanced micro-trigger thyristor device. Background Art

[0002] Silicon controlled rectifier (SCR), also known as thyristor, is a component composed of four layers of PNPN semiconductor materials, with three PN junctions and three electrodes. It is a high-power electrical component. Bidirectional thyristor is developed on the basis of ordinary thyristor. It can replace two thyristors connected in parallel with opposite polarity, and only requires one trigger circuit. It is an ideal AC switching device. Thyristor is widely used in power electronics technology. In automatic control systems, it can be used as a high-power driver to control high-power equipment with a small-power control. It has been widely used in AC and DC motor speed control systems, power control systems and follow-up systems. According to the size of the trigger current, it can be divided into micro-trigger, ordinary trigger and high-trigger thyristor devices. Generally speaking, a trigger current greater than 50mA is a high trigger, and less than 1mA is a micro trigger. There are different trigger requirements in practical applications. Minority carriers, also known as minority carriers. In N-type semiconductors, holes are called minority carriers, referred to as minority carriers. In P-type semiconductors, electrons are called minority carriers. Minority carriers are a concept in semiconductor physics. There are two types of carriers in semiconductor materials: electrons and holes. If a certain type of carrier is the majority in a semiconductor material and plays a major role in conduction, it is called the majority carrier. Otherwise, it is called the minority carrier.

[0003] In the prior art, there are many designs of thyristor devices. For example, Chinese patent CN202011349302.1 discloses a thyristor device. In this structure, a first blank doped region is provided on the upper part of the N-type well region; any equivalent structure includes a first N-type heavily doped region and a second P-type heavily doped region arranged side by side in the left and right directions; any equivalent structure is correspondingly provided with a second polysilicon; a second blank doped region is provided on the upper part of the P-type well region; the first polysilicon and the first blank doped region have an overlapped region, and cover the top of the second blank doped region; the silicide barrier layer has an overlapped region with the first P-type heavily doped region, and has an overlapped region with the first polysilicon, and also covers the top of the second blank doped region. A silicide barrier layer is provided on the N-type well region, and the good current limiting ability of the silicide barrier layer is utilized, and an equivalent diode region is provided in the N-type well region, so as to achieve the purpose of increasing the holding voltage of the SCR, effectively reduce the leakage risk of the SCR, and improve the electrostatic discharge protection performance of the SCR.

[0004] For another example, Chinese patent CN202211342900.5 discloses a thyristor device in the field of integrated circuits, comprising a substrate and a device area formed on the substrate, wherein a first N-well area and a first P-well area are arranged in the device area; a first N+ injection area, a first isolation groove and a first P+ injection area are arranged on the first N-well area; a second N+ injection area, a second isolation groove and a second P+ injection area are arranged on the first P-well area; the first N+ injection area and the first P+ injection area are connected by metal and connected to the anode; the second N+ injection area and the second P+ injection area are connected by metal and connected to the cathode; a third P+ injection area is arranged at the junction of the first P-well area and the first N-well area; a reverse P+ / Nwell diode is formed by the first N+ injection area, the first N-well area, the third P+ injection area, the first P-well area and the second P+ injection area; the holding voltage is improved, and the high robustness of the thyristor device is maintained.

[0005] However, in the actual implementation process, the inventors found that when designing a micro-trigger current for a thyristor device, problems such as poor trigger accuracy control, a smaller VDRM parameter, an excessively large VTM parameter, and poor IT (RMS) parameters may easily occur when the micro-trigger thyristor reduces the trigger current. Summary of the invention

[0006] In view of the above problems existing in the prior art, a minority carrier enhanced micro-trigger thyristor device is now provided.

[0007] The specific technical scheme is as follows: a minority carrier enhanced micro-trigger thyristor device, wherein the front base region of the minority carrier enhanced micro-trigger thyristor device has a first doping type; a buried layer with a second doping type is formed in the front base region; the buried layer and the front base region on the upper and lower sides form a triode amplification structure, and the front base region under the buried layer is minority carrier enhanced when the device is turned on.

[0008] On the other hand, the minority-carrier enhanced micro-trigger thyristor device also includes: a substrate having a second doping type; the front base region is formed above the substrate; a front emitter region, the front emitter region has the second doping type; the front emitter region is partially formed in the upper surface of the front base region, located above the buried layer; the front emitter region and the buried layer are spaced apart by the front base region; the front emitter region partially covers the upper surface of the front base region, so that part of the front base region is exposed; a front base region electrode, the front base region electrode is formed above the exposed part of the front base region; a front emitter region electrode, the front emitter region electrode is formed above the front emitter region; a back base region, the back base region is formed below the substrate; the back base region has the first doping type; a back electrode, the back electrode is formed below the back base region.

[0009] On the other hand, the left and right sides of the minority-carrier enhanced micro-trigger thyristor device are respectively formed with through-isolation diffusion regions.

[0010] On the other hand, trenches are respectively formed between the front base region and the through isolation diffusion region; the depth of the trenches reaches the substrate; and the trenches are filled with a glass passivation layer.

[0011] On the other hand, a voltage divider ring structure is formed in the region of the substrate between the front base region and the through isolation diffusion region.

[0012] On the other hand, a passivation layer is formed in the area between the front base electrode and the front emitter electrode; on the other hand, at least one back emitter is formed in the back base region, and the bottom of the back emitter is in contact with the back electrode.

[0013] On the other hand, when the number of the buried layers is at least two, the multiple buried layers are sequentially stacked in the front base region along the height direction; and the multiple buried layers are spaced apart by the front base region.

[0014] On the other hand, the left and right ends of the buried layer are located in the front base region; or, the left and right ends of the buried layer respectively reach the groove and are covered by the glass passivation layer.

[0015] In another aspect, the buried layer has a thickness less than 4 μm.

[0016] On the other hand, when the second doping type is N-type, the doping concentration of the buried layer is greater than 3E19; when the second doping type is P-type, the doping concentration of the buried layer is greater than 5E19.

[0017] On the other hand, the breakdown voltage VDRM of the minority carrier enhanced micro-triggered thyristor device is greater than 800V; the trigger current of the minority carrier enhanced micro-triggered thyristor device is less than 1mA; and the thickness of the substrate is between 250μm and 450μm.

[0018] On the other hand, the distance between the upper surface of the buried layer and the lower surface of the front emitter region is greater than 1 / 10 of the thickness of the front base region; the distance between the lower surface of the buried layer and the bottom of the front base region is greater than 2 / 10 of the thickness of the front base region.

[0019] A preparation method for preparing the above-mentioned minority-carrier enhanced micro-trigger thyristor device; the preparation method comprises: performing epitaxy above a substrate of a first doping type to obtain a front base region having a second doping type; performing implantation in the front base region to form a buried layer, and then further performing epitaxy on the front base region above the buried layer; performing implantation at a predetermined position of the front base region to obtain a front emitter region; sequentially preparing a front base region electrode, a passivation layer and a front emitter region electrode above the front base region and the front emitter region; performing epitaxy below the substrate to obtain a back base region; and making a back electrode below the back base region.

[0020] The above technical solution has the following advantages or beneficial effects: In view of the problem of unstable performance of micro-triggered thyristor devices in the prior art, a transistor amplification structure is introduced in the front base region through a buried layer in this solution. When the device is turned on, since the area of ​​the buried layer away from the emission region is fixed and the doping concentration is fixed, stable trigger control accuracy can also be achieved under micro-current. And the minority carriers in the front base region below the buried layer will produce a multiplication effect due to the amplification structure based on the buried layer above, which can effectively reduce the trigger current. After the device is triggered, the enhancement of the conductivity modulation effect can effectively reduce the equivalent resistance after conduction. Thereby reducing the VTM voltage drop and improving the IT (RMS) parameter. When there is no trigger current in the trigger pole, the buried transistor amplification effect does not exist, so the VDRM parameter can be effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The embodiments of the present invention will be described more fully with reference to the attached drawings, which are provided for illustration and description only and are not intended to limit the scope of the present invention.

[0022] Figure 1 This is a schematic diagram of the structure of a device according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the circuit principle of a device according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the device structure of Embodiment 2 of the present invention; Figure 4 This is a schematic diagram of the circuit principle of the device in Embodiment 2 of the present invention; Figure 5 This is a schematic diagram of the structure of a device according to Embodiment 3 of the present invention; Figure 6 This is a schematic diagram of the circuit principle of the device in Embodiment 3 of the present invention; Figure 7 This is a schematic diagram of the structure of a device according to a fourth embodiment of the present invention; Figure 8 This is a schematic diagram of the circuit principle of the device in Embodiment 4 of the present invention; Fig. 9 This is a schematic diagram of the structure of a device in Embodiment 5 of the present invention; Fig.10 Schematic diagram of the through-isolation diffusion region in an embodiment of the present invention; Fig.11 A schematic diagram of an epitaxial base region in an embodiment of the present invention; Fig.12 A schematic diagram of a buried layer in an embodiment of the present invention; Fig.13 Schematic diagram of epitaxial coating in an embodiment of the present invention; Fig.14 Schematic diagram of the isolation of complement and penetration in an embodiment of the present invention; Fig.15 Schematic diagram of the back base region in an embodiment of the present invention; Fig.16 This is a schematic diagram of the front emission area in an embodiment of the present invention; Fig.17 This is a schematic diagram of the complete preparation results in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this specification and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on this specification.

[0025] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0026] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0027] The present invention mainly provides a minority-carrier enhanced micro-trigger thyristor device, in which a buried layer is added to the front base region, the buried layer and the front base regions on the upper and lower sides form a triode amplification structure, and when the device is turned on, the front base region below the buried layer is minority-carrier enhanced.

[0028] Specifically, the following embodiments may exist depending on the device type: Embodiment 1: A minority-carrier enhanced micro-triggered thyristor device, such as Figure 1 and Figure 2 As shown, it includes: a substrate 1 with a second doping type; a front base region 2 is formed above the substrate 1; the front base region 2 has a first doping type; a buried layer 3 is formed in the front base region 2; the buried layer 3 has a second doping type different from the front base region 2; the buried layer 3 is located in the middle part of the front base region 2 and is completely wrapped by the front base region 2 in the height direction; the part of the front base region 2 below the buried layer 3, the buried layer 3, and the part of the front base region 2 above the buried layer form a group of NPN or PNP transistor amplification structures in sequence according to the current channel.

[0029] It also includes a front emitter region 4, which has the second doping type; the front emitter region 4 is partially formed in the upper surface of the front base region 2 and is located above the buried layer 3; the front emitter region 4 and the buried layer 3 are spaced apart by the front base region 2; the front emitter region 4 partially covers the upper surface of the front base region so that a part of the front base region 2 is exposed; the front base region electrode 5, which is formed above the exposed part of the front base region 2; the front emitter region electrode 6, which is formed above the front emitter region 4; the back base region 7, which is formed below the substrate 1; the back base region 7 has the first doping type; and the back electrode 8, which is formed below the back base region 7.

[0030] Specifically, in order to address the problem of unstable performance of micro-triggered thyristor devices in the prior art, a transistor amplification structure is introduced in the front base region 2 through a buried layer 3 in the present solution. When the device is turned on, since the distance between the buried layer 3 and the front emitter region 4 is fixed and the doping concentration is fixed, stable trigger control accuracy can also be achieved under micro-current.

[0031] Furthermore, the minority carriers in the front base region 2 below the buried layer 3 will produce a multiplication effect due to the amplification structure based on the buried layer 2 above, which can effectively reduce the trigger current.

[0032] After the device is triggered, the enhancement of the conductivity modulation effect can effectively reduce the equivalent resistance after conduction, thereby reducing the VTM voltage drop and improving the IT (RMS) parameter.

[0033] When there is no trigger current at the trigger electrode, the amplification effect of the buried transistor does not exist, so the VDRM parameter can be effectively improved.

[0034] The first doping type is P type, and the second doping type is N type; in other embodiments, the first doping type may be N type, and the second doping type may be P type.

[0035] Specifically, the above structure is formed by adding a buried layer 3 to a typical unidirectional thyristor device.

[0036] The front base region 2 and the front emitter region 4 are both formed on the front side of the substrate 1 .

[0037] A front base region 2 having the first conductivity type is formed at a predetermined depth above the substrate 1 having the second conductivity type by epitaxial growth and doping.

[0038] The typical thickness of the substrate 1 is usually 250 μm-450 μm, and the doping concentration is less than 4E14.

[0039] The predetermined depth is usually smaller than the actual depth of the front base region 2 , but greater than the height of the upper surface of the buried layer 3 relative to the substrate 1 .

[0040] After the predetermined depth is epitaxially grown, photolithography implantation and doping may be performed in a predetermined window in the front base region 2 to form a buried layer 3 with a specific thickness.

[0041] Generally speaking, the typical thickness of the buried layer 3 is generally less than 4 μm.

[0042] Specifically, when the thickness of the buried layer 3 is too large, the minority carriers in the front emitter region 4 cannot penetrate the buried layer 3 to modulate the PN junction of the front base region 2 and the substrate 1, which may lead to a population inversion problem.

[0043] Generally speaking, when the doping type of the buried layer 3 is N-type, the doping concentration is generally greater than 3E19; when the doping type of the buried layer 3 is P-type, the doping concentration is generally greater than 5E19.

[0044] Among them, considering that the buried layer 3 and the front base region 2 below will form a reverse biased junction structure, when the doping concentration of the buried layer 3 is too light, the withstand voltage of the reverse biased junction structure will be too high; after forming a specific buried layer 3, the front base region 2 is further epitaxially extended, so as to further form a front base region 2 above the buried layer 3 to wrap it, so as to finally obtain a front base region 2 that completely wraps the buried layer 3.

[0045] On this basis, a predetermined window in the front base region 2 is doped by diffusion or ion implantation to form a front emitter region 3 having a second doping type.

[0046] The front emitter region 3 may be located to the left or right of the front base region 2 , and partially covers the upper surface of the front base region 2 , so that a portion of the front base region 2 is exposed.

[0047] The distance between the upper surface of the buried layer 3 and the lower surface of the front emitter region 3 is greater than 1 / 10 of the thickness of the front base region 2; the distance between the lower surface of the buried layer 3 and the bottom of the front base region 2 is greater than 2 / 10 of the thickness of the front base region 2.

[0048] The above position setting can meet the requirements of breakdown voltage and reverse bias electric field of the buried layer 3.

[0049] After the front emitter region 3 is formed, the upper surfaces of the front base region 2 and the front emitter region 3 may be passivated to form a passivation layer 9 to completely cover the surfaces of the front base region 2 and the front emitter region 3 .

[0050] Subsequently, two windows are etched above the front base region 2 and the front emitter region 3 respectively, and metal materials are evaporated or deposited to form the front base region electrode 5 and the front emitter region electrode 6.

[0051] The front base region electrode 5 and the front emitter region electrode 6 are electrically connected to the front base region 2 and the front emitter region 3 below, respectively.

[0052] A portion of the passivation layer 9 is retained between the front base electrode 5 and the front emitter electrode 6 for isolation.

[0053] The final product breakdown voltage VDRM is greater than 800V, and the trigger current is less than 1mA. The substrate thickness is 250μm-450μm. The product breakdown voltage is determined by the above settings. Low-voltage thyristors cannot be enlarged because there is no large electric field to accelerate ions.

[0054] It should be noted that, during the passivation process, a continuous passivation layer 9 is usually formed on the upper surfaces of the front base region 2 and the front emitter region 3, and two windows are opened in the passivation layer 9 for electrode preparation.

[0055] At this time, the passivation layer 9 at the corner part is retained, and after the electrode preparation is completed, it is located in the area between the front base electrode 5 and the front emitter electrode 6 and the front base 2 and the front emitter 3 below.

[0056] In an additional embodiment, a pair of isolation diffusion regions 10 are formed on the left and right sides of the minority-carrier enhanced micro-trigger thyristor device, respectively.

[0057] Specifically, in order to achieve a better isolation and protection effect on the device, in this embodiment, through isolation diffusion regions 10 are formed on the left and right sides of the thyristor device respectively.

[0058] Specifically, in the process of processing the substrate 1, a protective layer can be made on the front and back sides of the device in advance, and then a diffusion area window can be processed at the corners. Subsequently, a through diffusion process is used to form a through isolation diffusion area 10 on the left and right sides of the thyristor device, and on this basis, structures such as the front base area 2, the buried layer 3, and the front emitter area 4 are made.

[0059] It should be noted that, since the front base region 2 and the buried layer 3 are manufactured through an epitaxial process, the left and right sides of the newly grown front base region 2 of the epitaxial part do not have the through isolation diffusion region 10 .

[0060] Therefore, after forming a specific buried layer 3 and further epitaxy of the front base region 2, it is necessary to re-passivate and process the diffusion region windows on both sides of the front base region 2, and then form new through-diffusion isolation diffusion regions 10 on the left and right sides of the front base region 2 through a through-diffusion process, and connect them to the original through-diffusion isolation diffusion region 10 below.

[0061] In an additional embodiment, trenches 11 are respectively formed between the front base region 2 and the through isolation diffusion region 10 ; the depth of the trenches 11 reaches the substrate 1 ; and the trenches 11 are filled with a glass passivation layer 12 .

[0062] Specifically, when the thyristor device is prepared using the mesa process, grooves 11 are formed between the front base region 2 and the through isolation diffusion region 10, so that the positions of the front base region 2, the front emitter region 4 and the upper front base region electrode 5 and the front emitter region electrode 6 are limited.

[0063] Generally speaking, in the process of preparing the front base region 2 , trenches 11 are opened on both sides, and other parts of the active region are prepared in the area defined by the trenches 11 , thereby limiting the width of the active region.

[0064] At the same time, in order to prevent moisture from entering and affecting the life of the device, after the groove 11 is opened, SiO2 or other equivalent materials are backfilled inside to form a glass passivation layer 12, thereby achieving effective protection for the substrate 1 at the bottom of the groove 11 and the joints on both sides.

[0065] Embodiment 2: A minority-carrier enhanced micro-triggered thyristor device, such as Figure 3 and Figure 4As shown, it includes: a substrate 1 with a second doping type; a front base region 2 is formed above the substrate 1; the front base region 2 has a first doping type; a plurality of buried layers 3 are formed in the front base region 2, and the buried layers 3 have a second doping type different from that of the front base region 2; all the buried layers 3 are located in the middle part of the front base region 2 and are completely wrapped by the front base region 2 in the height direction; a plurality of buried layers 3 are stacked in the front base region 2 in sequence along the height direction, and each buried layer 3 is spaced by the front base region 2.

[0066] For each buried layer 3, the portion of the front base region 2 below the buried layer 3, the buried layer 3, and the portion of the front base region 2 above the buried layer sequentially form a group of NPN or PNP transistor amplification structures according to the current channel.

[0067] By introducing a plurality of buried layers 3, a plurality of amplifying structures are formed in sequence.

[0068] It also includes a front emitter region 4, which has the second doping type; the front emitter region 4 is partially formed in the upper surface of the front base region 2 and is located above the buried layer 3; the front emitter region 4 and the buried layer 3 are spaced apart by the front base region 2; the front emitter region 4 partially covers the upper surface of the front base region so that a part of the front base region 2 is exposed; the front base region electrode 5, which is formed above the exposed part of the front base region 2; the front emitter region electrode 6, which is formed above the front emitter region 4; the back base region 7, which is formed below the substrate 1; the back base region 7 has the first doping type; and the back electrode 8, which is formed below the back base region 7.

[0069] Specifically, in order to address the problem of unstable performance of micro-triggered thyristor devices in the prior art, a transistor amplification structure is introduced in the front base region 2 through a buried layer 3 in the present solution. When the device is turned on, since the distance between the buried layer 3 and the front emitter region 4 is fixed and the doping concentration is fixed, stable trigger control accuracy can also be achieved under micro-current.

[0070] Furthermore, the minority carriers in the front base region 2 below the buried layer 3 will produce a multiplication effect due to the amplification structure based on the buried layer 2 above, which can effectively reduce the trigger current.

[0071] After the device is triggered, the enhancement of the conductivity modulation effect can effectively reduce the equivalent resistance after conduction, thereby reducing the VTM voltage drop and improving the IT (RMS) parameter.

[0072] When there is no trigger current at the trigger electrode, the amplification effect of the buried transistor does not exist, so the VDRM parameter can be effectively improved.

[0073] Accordingly, in order to achieve a further amplification effect, in this embodiment, a multi-layer buried layer 3 is introduced into the front base region 2. During the preparation process, the buried layer 3 can be formed in the front base region 2 of a certain thickness and the front base region 2 can be further grown on the buried layer 3 by repeating the epitaxy and ion implantation processes.

[0074] Through the above preparation process, each buried layer 3 can be separated by the front base region 2, and the part of the front base region 2 below the buried layer 3, the buried layer 3, and the part of the front base region 2 above the buried layer form a group of NPN or PNP transistor amplification structures in sequence according to the current channel, thereby forming multiple amplification structures.

[0075] Embodiment three: A minority-carrier enhanced micro-triggered thyristor device, such as Figure 5 and Figure 6 As shown, it includes: a substrate 1 with a second doping type; a front base region 2 is formed above the substrate 1; the front base region 2 has a first doping type; a buried layer 3 is formed in the front base region 2, and the buried layer 3 has a second doping type different from the front base region 2; the buried layer 3 is located in the middle part of the front base region 2 and is completely wrapped by the front base region 2 in the height direction; the part of the front base region 2 below the buried layer 3, the buried layer 3, and the part of the front base region 2 above the buried layer form a group of NPN or PNP transistor amplification structures in sequence according to the current channel.

[0076] The buried layer 3 has a width in the lateral direction that covers the front base region 2, thereby separating the front base region 2 into two independent upper and lower parts.

[0077] It also includes a front emitter region 4, which has the second doping type; the front emitter region 4 is partially formed in the upper surface of the front base region 2 and is located above the buried layer 3; the front emitter region 4 and the buried layer 3 are spaced apart by the front base region 2; the front emitter region 4 partially covers the upper surface of the front base region so that a part of the front base region 2 is exposed; the front base region electrode 5, which is formed above the exposed part of the front base region 2; the front emitter region electrode 6, which is formed above the front emitter region 4; the back base region 7, which is formed below the substrate 1; the back base region 7 has the first doping type; and the back electrode 8, which is formed below the back base region 7.

[0078] Specifically, in order to address the problem of unstable performance of micro-triggered thyristor devices in the prior art, a transistor amplification structure is introduced in the front base region 2 through a buried layer 3 in the present solution. When the device is turned on, since the distance between the buried layer 3 and the front emitter region 4 is fixed and the doping concentration is fixed, stable trigger control accuracy can also be achieved under micro-current.

[0079] Furthermore, the minority carriers in the front base region 2 below the buried layer 3 will produce a multiplication effect due to the amplification structure based on the buried layer 2 above, which can effectively reduce the trigger current.

[0080] After the device is triggered, the enhancement of the conductivity modulation effect can effectively reduce the equivalent resistance after conduction, thereby reducing the VTM voltage drop and improving the IT (RMS) parameter.

[0081] When there is no trigger current at the trigger electrode, the amplification effect of the buried transistor does not exist, so the VDRM parameter can be effectively improved.

[0082] Furthermore, in this embodiment, the width of the buried layer 3 is extended so that the width of the buried layer 3 reaches the left and right end points of the active region, thereby separating the front base region 2 into two independent upper and lower parts.

[0083] In an additional embodiment, a trench 11 is formed between the front base region 2 and the through isolation diffusion region 10 of the thyristor device; the depth of the trench 11 reaches the substrate 1; and the trench 11 is filled with a glass passivation layer 12 .

[0084] At this time, the width of the buried layer 3 in the lateral direction completely covers the front base region 2 , and both ends respectively reach and contact the glass passivation layer 12 , thereby completely blocking the front base region 2 .

[0085] In another additional embodiment, the left and right end points of the buried layer 3 in the lateral direction respectively reach the through isolation diffusion region 10 to block the front base region 2 .

[0086] Embodiment 4: A minority-carrier enhanced micro-triggered thyristor device, such as Figure 7 and Figure 8 As shown, it includes: a substrate 1 with a second doping type; a front base region 2 is formed above the substrate 1; the front base region 2 has a first doping type; a buried layer 3 is formed in the front base region 2; the buried layer 3 has a second doping type different from the front base region 2; the buried layer 3 is located in the middle part of the front base region 2 and is completely wrapped by the front base region 2 in the height direction; the part of the front base region 2 below the buried layer 3, the buried layer 3, and the part of the front base region 2 above the buried layer form a group of NPN or PNP transistor amplification structures in sequence according to the current channel.

[0087] On the outer side of the front base region 2 , a group of voltage divider rings 13 are introduced into the substrate 1 through a planar process. The voltage divider rings 13 are formed through an implantation and doping process, and their depth is greater than that of the front base region 2 .

[0088] It also includes a front emitter region 4, which has the second doping type; the front emitter region 4 is partially formed in the upper surface of the front base region 2 and is located above the buried layer 3; the front emitter region 4 and the buried layer 3 are spaced apart by the front base region 2; the front emitter region 4 partially covers the upper surface of the front base region so that a part of the front base region 2 is exposed; the front base region electrode 5, which is formed above the exposed part of the front base region 2; the front emitter region electrode 6, which is formed above the front emitter region 4; the back base region 7, which is formed below the substrate 1; the back base region 7 has the first doping type; and the back electrode 8, which is formed below the back base region 7.

[0089] Specifically, in order to address the problem of unstable performance of micro-triggered thyristor devices in the prior art, a transistor amplification structure is introduced in the front base region 2 through a buried layer 3 in the present solution. When the device is turned on, since the distance between the buried layer 3 and the front emitter region 4 is fixed and the doping concentration is fixed, stable trigger control accuracy can also be achieved under micro-current.

[0090] Furthermore, the minority carriers in the front base region 2 below the buried layer 3 will produce a multiplication effect due to the amplification structure based on the buried layer 2 above, which can effectively reduce the trigger current.

[0091] After the device is triggered, the enhancement of the conductivity modulation effect can effectively reduce the equivalent resistance after conduction, thereby reducing the VTM voltage drop and improving the IT (RMS) parameter.

[0092] When there is no trigger current at the trigger electrode, the amplification effect of the buried transistor does not exist, so the VDRM parameter can be effectively improved.

[0093] Furthermore, the thyristor device in this embodiment is manufactured using a planar process. After the front base region 2 is formed, a voltage divider ring 13 is introduced outside the front base region 2 . The voltage divider ring 13 usually has the same doping type as the front base region 2 .

[0094] Embodiment five: A minority-carrier enhanced micro-triggered thyristor device, such as Fig. 9 As shown, it includes: a substrate 1 with a second doping type; a front base region 2 is formed above the substrate 1; the front base region 2 has a first doping type; a buried layer 3 is formed in the front base region 2; the buried layer 3 has a second doping type different from the front base region 2; the buried layer 3 is located in the middle part of the front base region 2 and is completely wrapped by the front base region 2 in the height direction; the part of the front base region 2 below the buried layer 3, the buried layer 3, and the part of the front base region 2 above the buried layer form a group of NPN or PNP transistor amplification structures in sequence according to the current channel.

[0095] It also includes multiple front emitter regions 4; the front emitter region 4 has a second doping type; the front emitter region 4 is partially formed in the upper surface of the front base region 2, and is located above the buried layer 3; the front emitter region 4 and the buried layer 3 are spaced apart by the front base region 2; the front emitter region 4 is defined by multiple spaced windows, and injection is performed in each window to form multiple front emitter regions 4.

[0096] The lateral coverage of multiple front emitter regions 4 partially covers the upper surface of the front base region, so that part of the front base region 2 is exposed; the front base region electrode 5, the front base region electrode 5 is formed above the exposed part of the front base region 2; the front emitter region electrode 6, the front emitter region electrode 6 is formed above the front emitter region 4; the back base region 7, the back base region 7 is formed below the substrate 1; the back base region 7 has a first doping type; multiple back emitter regions 14 are formed in the back base region 7, the back emitter regions 14 have a second doping type; the back electrode 8, the back electrode 8 is formed below the back base region 7 and is electrically connected to the back emitter region 14.

[0097] Specifically, in order to address the problem of unstable performance of micro-triggered thyristor devices in the prior art, a transistor amplification structure is introduced in the front base region 2 through a buried layer 3 in the present solution. When the device is turned on, since the distance between the buried layer 3 and the front emitter region 4 is fixed and the doping concentration is fixed, stable trigger control accuracy can also be achieved under micro-current.

[0098] Furthermore, the minority carriers in the front base region 2 below the buried layer 3 will produce a multiplication effect due to the amplification structure based on the buried layer 2 above, which can effectively reduce the trigger current.

[0099] After the device is triggered, the enhancement of the conductivity modulation effect can effectively reduce the equivalent resistance after conduction, thereby reducing the VTM voltage drop and improving the IT (RMS) parameter.

[0100] When there is no trigger current at the trigger electrode, the amplification effect of the buried transistor does not exist, so the VDRM parameter can be effectively improved.

[0101] Furthermore, in order to realize the preparation of a bidirectional thyristor device, in this embodiment, a back-side emitting region 14 is introduced into the back-side base region by ion implantation and doping, thereby forming a bidirectional thyristor device.

[0102] The above five embodiments are five typical embodiments. In the actual preparation process, the combination of technical features in each embodiment can be adjusted as needed. For example, the position and quantity of the front emission area, the back emission area, the voltage divider ring and the buried layer can be appropriately adjusted, or part of the passivation layer, the groove, the through isolation diffusion area, etc. can be omitted.

[0103] A preparation method is also provided for preparing a minority-carrier enhanced micro-triggered thyristor device similar to the first embodiment; the preparation method comprises: Fig.10 As shown, take the substrate A1, when it is necessary to make the through isolation diffusion region A2, first use silicon oxide to make a mask, and then use AL diffusion to prepare the through isolation diffusion region A2.

[0104] like Fig.11 As shown, epitaxy is performed on a substrate A1 of the first doping type to obtain a front base region A3 of the second doping type; during the epitaxy process, a boron-doped epitaxy method can be selected with a thickness of 60 μm.

[0105] like Fig.12 As shown, implantation is performed in the front base region A3 to form a buried layer A4, and then Fig.13 As shown, the front base region A3 is further epitaxially grown above the buried layer A4; wherein, the specific implantation steps of the buried layer A4 include photolithography implantation, RTA annealing activation, the typical junction depth after annealing is 1.5 μm, the doping concentration is 5e23, and phosphorus is doped.

[0106] Then CMP removes 1 μm thickness of the front surface, leaving 0.5 μm of buried layer.

[0107] If the through isolation diffusion region A2 is prepared in the previous step, then Fig.14 As shown, it is necessary to re-extend the corresponding thickness and then perform isolation expansion.

[0108] The AL injection method is used to supplement and expand the isolation.

[0109] Implantation is performed at a predetermined position of the front base region A3 to obtain a front emitter region A5; Fig.15 As shown, it includes first diffusing the back base region A8; Fig.16 As shown, the front emission area A5 is then implanted and annealed.

[0110] like Fig.17 As shown, a front base electrode A6, a passivation layer A7, a front emitter electrode A10 and a groove glass passivation layer A11 are prepared in sequence above the front base region A3 and the front emitter region A5; wherein, after the front emitter region A5 is formed, the upper surfaces of the front base region A3 and the front emitter region A5 can be passivated to form a passivation layer A7 to completely cover the surfaces of the front base region A3 and the front emitter region A5.

[0111] Subsequently, two windows are etched above the front base region A3 and the front emitter region A5 respectively, and metal materials are evaporated or deposited to form the front base region electrode A6 and the front emitter region electrode A10.

[0112] The front base region electrode A6 and the front emitter region electrode A10 are electrically connected to the front base region A3 and the front emitter region A5 below, respectively.

[0113] A portion of the passivation layer A7 is retained between the front base electrode A6 and the front emitter electrode A10 for isolation.

[0114] A back electrode A9 is formed below the back base region A8.

[0115] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A minority-carrier enhanced micro-trigger thyristor device, characterized in that: The front base region of the minority-carrier enhanced micro-trigger thyristor device has a first doping type; a buried layer with a second doping type is formed in the front base region; the buried layer and the front base regions on the upper and lower sides form a triode amplification structure, and the front base region under the buried layer is minority-carrier enhanced when the device is turned on.

2. The minority-carrier enhanced micro-triggered thyristor device according to claim 1, characterized in that: The minority-carrier enhanced micro-trigger thyristor device also includes: a substrate having a second doping type; the front base region is formed above the substrate; a front emitter region, the front emitter region has the second doping type; the front emitter region is partially formed in the upper surface of the front base region, located above the buried layer; the front emitter region and the buried layer are spaced apart by the front base region; the front emitter region partially covers the upper surface of the front base region, so that part of the front base region is exposed; a front base region electrode, the front base region electrode is formed above the exposed part of the front base region; a front emitter region electrode, the front emitter region electrode is formed above the front emitter region; a back base region, the back base region is formed below the substrate; the back base region has the first doping type; and a back electrode is formed below the back base region.

3. The minority-carrier enhanced micro-triggered thyristor device according to claim 2, characterized in that: The left and right sides of the minority-carrier enhanced micro-trigger thyristor device are respectively formed with through diffusion isolation regions.

4. The minority-carrier enhanced micro-triggered thyristor device according to claim 3, characterized in that: Grooves are formed between the front base region and the through diffusion isolation region respectively; the depth of the grooves reaches the substrate; and the grooves are filled with a glass passivation layer.

5. The minority-carrier enhanced micro-triggered thyristor device according to claim 3, characterized in that: The substrate further forms a voltage divider ring structure in a region between the front base region and the through diffusion isolation region.

6. The minority-carrier enhanced micro-triggered thyristor device according to claim 2, characterized in that: A passivation layer is formed in a region between the front base electrode and the front emitter electrode.

7. The minority-carrier enhanced micro-triggered thyristor device according to claim 2, characterized in that: At least one back-side emitting region is also formed in the back-side base region, and the bottom of the back-side emitting region is in contact with the back-side electrode.

8. The minority-carrier enhanced micro-triggered thyristor device according to claim 1, characterized in that: When the number of the buried layers is at least two, the plurality of buried layers are sequentially stacked in the front base region in a height direction; The front base region is used to space the multiple buried layers.

9. The minority-carrier enhanced micro-triggered thyristor device according to claim 4, characterized in that: The left and right ends of the buried layer are located in the front base region; or, the left and right ends of the buried layer reach the groove respectively and are covered by the glass passivation layer.

10. The minority-carrier enhanced micro-triggered thyristor device according to claim 1, characterized in that: The buried layer has a thickness less than 4 μm.

11. The minority-carrier enhanced micro-triggered thyristor device according to claim 1, characterized in that: When the second doping type is N-type, the doping concentration of the buried layer is greater than 3E19; when the second doping type is P-type, the doping concentration of the buried layer is greater than 5E19.

12. The minority-carrier enhanced micro-triggered thyristor device according to claim 2, characterized in that: The breakdown voltage VDRM of the minority carrier enhanced micro-triggered thyristor device is greater than 800V; the trigger current of the minority carrier enhanced micro-triggered thyristor device is less than 1mA; and the thickness of the substrate is between 250μm and 450μm.

13. The minority-carrier enhanced micro-triggered thyristor device according to claim 2, characterized in that: The distance between the upper surface of the buried layer and the lower surface of the front emitter region is greater than 1 / 10 of the thickness of the front base region; the distance between the lower surface of the buried layer and the bottom of the front base region is greater than 2 / 10 of the thickness of the front base region.

14. A preparation method, characterized in that: Used to prepare a minority-carrier enhanced micro-triggered thyristor device as described in any one of claims 1 to 13; the preparation method comprises: performing epitaxy above a substrate of a first doping type to obtain a front base region having a second doping type; performing injection into the front base region to form a buried layer, and then further performing epitaxy on the front base region above the buried layer; performing injection into a predetermined position of the front base region to obtain a front emitter region; sequentially preparing a front base region electrode, a passivation layer and a front emitter region electrode above the front base region and the front emitter region; performing epitaxy below the substrate to obtain a back base region; and making a back electrode below the back base region.

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