A LDMOS device and a method for manufacturing the same

Abstract

The embodiment of the present disclosure provides an LDMOS device and a method for preparing the same. The LDMOS device includes a drift region, a body region, a drain region, a source region, a gate structure and a single contact field plate. The doping types of the body region and the drift region are opposite. The drain region is located in the drift region and on a side away from the body region. The gate structure covers part of the drift region and part of the body region and is isolated from the drain region. The gate structure includes a gate and a side wall covering the side of the gate. The single contact field plate is located in a partial area between the drain region and the side surface of the side wall close to the drain region. The projection of the single contact field plate on the surface of the drift region does not overlap with the projection of the side wall on the surface of the drift region. The length of the single contact field plate in the direction from the body region to the drift region ranges from 0.1 microns to 0.8 microns. The source region is located in the body region and extends to the surface of the body region. The source region is electrically connected to the single contact field plate. The LDMOS device can be provided with a single contact field plate of a smaller size, which can improve the pressure resistance, and is easy to implement in the process, and can also improve the conductivity.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor process technology, and in particular, to an LDMOS device and a method for manufacturing the same. Background Art

[0002] Contact Field Plate (CFP) technology is widely used in electric field optimization of Lateral Diffused Metal Oxide Semiconductor (LDMOS) devices. By adding a contact field plate to generate a voltage difference between the drain terminal and the contact field plate, the voltage difference makes the electric field under the contact field plate evenly distributed, which can reduce the peak value of the device surface electric field without changing the device's specific on-resistance, thereby improving the device's withstand voltage performance. At the same time, the contact field plate can improve the device's hot carrier injection effect.

[0003] LDMOS of different voltages usually require contact field plates of different sizes. To a certain extent, the higher the breakdown voltage, the larger the size of the contact field plate. The large-sized contact field plate is very difficult to prepare and there are many problems. For example, the different stop heights at the bottom of the etching are difficult to control, the etching load effect is generated, the bottom key dimensions are not easy to achieve, the top key dimensions are too large and a thicker metal filling thickness is required, which makes it impossible to align the first layer of metal during the subsequent lithography. As a result, it is difficult to take into account both the voltage resistance and process difficulty of LDMOS. Summary of the invention

[0004] The embodiments of the present disclosure provide an LDMOS device and a method for manufacturing the same, which can improve voltage resistance, are easy to implement in terms of process, and can also improve electrical conductivity.

[0005] In a first aspect, the present disclosure provides an LDMOS device, comprising:

[0006] A drift region and a body region, wherein the body region and the drift region have opposite doping types;

[0007] a drain region, located in the drift region and away from the body region, wherein the drain region extends from the inside of the drift region to the surface of the drift region;

[0008] A gate structure, covering part of the drift region and part of the body region and isolated from the drain region; the gate structure comprises a gate and a sidewall covering a side of the gate;

[0009] a single contact field plate, located in a partial area between the drain region and a surface of a side of the sidewall close to the drain region, wherein a projection of the single contact field plate on the surface of the drift region does not overlap with a projection of the sidewall on the surface of the drift region; a length of the single contact field plate in a direction from the body region to the drift region ranges from 0.1 micrometers to 0.8 micrometers;

[0010] A source region is located in the body region and extends to a surface of the body region, wherein the source region is electrically connected to the single contact field plate.

[0011] In some embodiments of the present disclosure, a projection of the single contact field plate on the surface of the drift region is isolated from a projection of the spacer on the surface of the drift region.

[0012] In some embodiments of the present disclosure, the position of the surface of one side of the single contact field plate close to the drain region depends on the breakdown voltage of the LDMOS device.

[0013] In some embodiments of the present disclosure, the LDMOS device further includes:

[0014] A drain contact portion, located on the surface of the drain region;

[0015] A source contact portion, located on the surface of the source region;

[0016] Wherein, the drain contact portion, the source contact portion and the single contact field plate are formed based on the same photomask.

[0017] In some embodiments of the present disclosure, the LDMOS device further includes:

[0018] A blocking layer is located between the drift region and the single contact field plate, and a partial area of ​​a surface of the gate structure away from the drift region, and the blocking layer extends to the drain region.

[0019] In some embodiments of the present disclosure, the source region includes a first source region and a second source region of the same doping type, and the first source region is located on a side of the second source region close to the drain region.

[0020] The LDMOS device further comprises:

[0021] A body contact region is located between the first source region and the second source region to separate the first source region from the second source region, and the body contact region and the first source region have opposite doping types.

[0022] In some embodiments of the present disclosure, the drift region is N-type doped, the body region is P-type doped, the drain region is N-type doped, the first source region and the second source region are N-type doped, and the body contact region is P-type doped.

[0023] In some embodiments of the present disclosure, the drift region is P-type doped, the body region is N-type doped, the drain region is P-type doped, the first source region and the second source region are P-type doped, and the body contact region is N-type doped.

[0024] In a second aspect, the present disclosure provides a method for preparing an LDMOS device, comprising:

[0025] A drift region and a body region with opposite doping types are formed; ions are injected into the surface of the drift region on a side away from the body region to form a drain region; ions are injected into the surface of the body region to form a source region; a gate structure isolated from the drain region is prepared on part of the drift region and part of the body region, the gate structure comprising a gate and a side wall covering the side of the gate; a single contact field plate is prepared in a partial area between the drain region and a surface of the side of the side wall close to the drain region, the projection of the single contact field plate on the surface of the drift region does not overlap with the projection of the side wall on the surface of the drift region, and the length of the single contact field plate in the direction from the body region to the drift region ranges from 0.1 micron to 0.8 micron; the source region is electrically connected to the single contact field plate.

[0026] In some embodiments of the present disclosure, preparing a single contact field plate in a partial area between the drain region and a surface of a side of the spacer close to the drain region includes:

[0027] Based on the same photomask, the single contact field plate is prepared in a partial area between the drain region and a surface of the spacer close to the drain region, a drain contact is prepared on the surface of the drain region, and a source contact is prepared on the surface of the source region.

[0028] The technical solution of the embodiment of the present disclosure includes a drift region, a body region, a drain region, a source region, a gate structure and a single contact field plate. The doping types of the body region and the drift region are opposite. The drain region is located in the drift region and on a side away from the body region. The drain region extends from the inside of the drift region to the surface of the drift region. The gate structure covers part of the drift region and part of the body region and is isolated from the drain region. The gate structure includes a gate and a side wall covering the side of the gate. The source region is located in the body region and extends to the surface of the body region. The source region is electrically connected to the single contact field plate. The single contact field plate is located in a partial area between the drain region and a surface of the side of the side wall close to the drain region. The projection of the single contact field plate on the surface of the drift region does not overlap with the projection of the side wall on the surface of the drift region. The surface of the formed single contact field plate away from the drift region is located in the same horizontal plane, which can avoid the problem of difficult control of etching stop caused by different heights of the single contact field plate, making it easier to implement in the process. The length of a single contact field plate in the direction from the body region to the drift region ranges from 0.1 micron to 0.8 micron. A single contact field plate of smaller size can be set to enhance the electric field at the deep depletion, making the depletion more complete, thereby improving the voltage resistance. In addition, a single contact field plate of smaller size has less effect on the electric field when the device is turned on, so that the current increases, the on-resistance can be reduced, and the conductive performance is improved. In addition, the process of a single contact field plate of small size is simple, that is, it is easy to implement in terms of process.

[0029] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0031] Figure 1 The present invention provides a structural schematic diagram of an LDMOS device provided by the prior art.

[0032] Figure 2 The present invention is a schematic diagram of the structure of another LDMOS device provided in the prior art.

[0033] Figure 3 The present invention is a schematic diagram of the structure of another LDMOS device provided in the prior art.

[0034] Figure 4A schematic diagram of the structure of an LDMOS device provided in an embodiment of the present disclosure.

[0035] Figure 5 A schematic diagram of the structure of another LDMOS device provided in an embodiment of the present disclosure.

[0036] Figure 6 A schematic diagram comparing the electric fields of the LDMOS device provided in the embodiment of the present disclosure and the LDMOS device provided in the prior art.

[0037] Figure 7 A schematic diagram comparing the breakdown voltages of the LDMOS device provided in the embodiment of the present disclosure and the LDMOS device provided in the prior art.

[0038] Figure 8 A schematic diagram of the structure of another LDMOS device provided in an embodiment of the present disclosure.

[0039] Fig. 9 A schematic flow chart of a method for preparing an LDMOS device provided in an embodiment of the present disclosure.

[0040] Figures 10A-10F A schematic diagram of a preparation process of an LDMOS device provided in an embodiment of the present disclosure.

[0041] Fig.11 A schematic flow chart of another method for preparing an LDMOS device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the disclosed subject matter belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0044] Reference to "embodiments" in this disclosure means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiments" in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0045] In addition, the terms "first", "second", etc. in the specification and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0046] The term "and / or" in this disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0047] In the description of the present disclosure, unless otherwise specified, "plurality" and "at least two" mean more than two (including two), and similarly, "multiple groups" and "at least two groups" mean more than two groups (including two).

[0048] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0049] CFP technology is widely used in electric field optimization of LDMOS devices. By adding a contact field plate, a voltage difference is generated between the drain terminal and the contact field plate. This voltage difference makes the electric field under the contact field plate evenly distributed. It can reduce the peak value of the electric field on the device surface without changing the device's specific on-resistance, thereby improving the device's withstand voltage performance. At the same time, the contact field plate can improve the device's hot carrier injection effect.

[0050] Figure 1 A schematic diagram of the structure of an LDMOS device provided by the prior art, such as Figure 1 As shown, the LDMOS device includes a source region 11, a drain region 12, a single large-sized contact field plate 13, a gate 14 and a spacer 15. The width of the large-sized contact field plate 13 in the direction from the source region 11 to the drain region 12 is usually greater than 0.8 microns.

[0051] Exemplarily, a source region 11 and a drain region 12 are arranged in an area from the inside of the substrate to the front side of the substrate, the source region 11 and the drain region 12 are separated by a channel, a gate 14 is arranged in a partial area of ​​the front side of the substrate opposite to the channel, the side of the gate 14 is covered by a side wall 15, and a single large-size contact field plate 13 is arranged on the surface of the substrate from the surface of the gate 14 close to the drain region 12 to the area between the drain region 12.

[0052] LDMOS with different voltages usually require contact field plates of different sizes. To a certain extent, the higher the breakdown voltage, the larger the contact field plate size. Figure 1 As shown, the larger the size of the contact field plate 13 is, the higher the breakdown voltage of the LDMOS device is, that is, the higher the withstand voltage is.

[0053] However, the manufacturing process of large-sized contact field plates is very difficult and there are many problems. For example, the different bottom heights of etching make it difficult to stop and produce etching load effects, the bottom key dimensions are not easy to achieve and the top key dimensions are too large, and the thicker metal filling thickness is required, which makes it difficult to align the first layer of metal in the back-end lithography. As a result, it is difficult for a large-sized single contact field plate to meet the process requirements.

[0054] In order to solve the above problems, a technical solution of replacing a single large-sized contact field plate with multiple small-sized contact field plates and a technical solution of replacing a single large-sized contact field plate with shallow trench isolation (STI) are proposed.

[0055] Figure 2 A schematic diagram of the structure of another LDMOS device provided in the prior art, Figure 1 The LDMOS device shown differs in that Figure 2 In the DMOS device shown, a plurality of small-sized contact field plates 16 are arranged in the area between the surface of the substrate and the side surface of the gate electrode 14 close to the drain region 12 and the drain region 12. Figure 2 The LDMOS device shown can solve the problem that a single large-sized contact field plate is difficult to meet the process requirements, but the process implementation of multiple small-sized contact field plates is relatively complicated.

[0056] Figure 3 A schematic diagram of the structure of another LDMOS device provided in the prior art, Figure 1 The LDMOS device shown differs in that Figure 3 In the DMOS device shown, a shallow isolation trench 17 is provided in a portion of the area between the surface of the substrate from the side surface of the gate electrode 14 close to the drain region 12 to the drain region 12. Figure 3The LDMOS device shown can solve the problem that a large-sized single contact field plate is difficult to meet the process requirements, but the resistance of the shallow isolation trench 17 is relatively high, resulting in poor electrical performance of the LDMOS device.

[0057] In view of this, an embodiment of the present disclosure provides an LDMOS device, including a drift region, a body region, a drain region, a source region, a gate structure and a single contact field plate, wherein the doping types of the body region and the drift region are opposite, the drain region is located in the drift region and on a side away from the body region, the drain region extends from the inside of the drift region to the surface of the drift region, the gate structure covers part of the drift region and part of the body region and is isolated from the drain region, the gate structure includes a gate and a side wall covering the side of the gate, the source region is located in the body region and extends to the surface of the body region, the source region is electrically connected to the single contact field plate, the single contact field plate is located in a partial area between the drain region and a surface of a side of the side wall close to the drain region, the projection of the single contact field plate on the surface of the drift region does not overlap with the projection of the side wall on the surface of the drift region, and the surface of the formed single contact field plate away from the drift region is located in the same horizontal plane, which can avoid the problem of difficult control of etching stop caused by different heights of the single contact field plate, making it easier to implement in process. The length of a single contact field plate in the direction from the body region to the drift region ranges from 0.1 micron to 0.8 micron. A single contact field plate of smaller size can be set to enhance the electric field at the deep depletion, making the depletion more complete, thereby improving the voltage resistance. In addition, a single contact field plate of smaller size has less effect on the electric field when the device is turned on, so that the current increases, the on-resistance can be reduced, and the conductive performance is improved. In addition, the process of a single contact field plate of small size is simple, that is, it is easy to implement in terms of process.

[0058] Figure 4 A schematic diagram of the structure of an LDMOS device provided in an embodiment of the present disclosure is shown in FIG. Figure 5 A schematic diagram of the structure of another LDMOS device provided in an embodiment of the present disclosure is shown in FIG. Figure 4 and Figure 5 As shown, the LDMOS device 100 includes a substrate 110 , a drift region 120 , a body region 130 , a drain region 140 , a source region 170 , a gate structure 150 , and a single contact field plate 160 .

[0059] The drift region 120 and the body region 130 are located inside the substrate 110 and extend to the front side of the substrate 110. The doping types of the drift region 120 and the body region 130 are opposite. The drain region 140 is located inside the drift region 120 and away from the body region 130. The drain region 140 extends from the inside of the drift region 120 to the surface of the drift region 120 of the substrate 110.

[0060] The gate structure 150 is located on the front side of the substrate 110, covers part of the drift region 120 and part of the body region 130 and is isolated from the drain region 140, and the gate structure 150 includes a gate 151 and a sidewall 152 covering the side of the gate 151. The source region 170 is located in the body region 130 and extends to the surface of the body region 130, and the source region 170 is electrically connected to a single contact field plate 160.

[0061] A single contact field plate 160 is disposed on the front surface of the substrate 110 and is located in a partial area between the drain region 140 and a side surface of the sidewall 152 close to the drain region 140. The projection of the single contact field plate 160 on the surface of the drift region 120 contacts the edge of the projection of the sidewall 152 on the surface of the drift region 120. Figure 4 Alternatively, the projection of the single contact field plate 160 on the surface of the drift region 120 is isolated from the projection of the sidewall 152 on the surface of the drift region 120, as shown in FIG. Figure 5 As shown, the projection of the single contact field plate 160 on the surface of the drift region 120 does not overlap with the projection of the spacer 152 on the surface of the drift region 120 .

[0062] Exemplarily, the material of the substrate 110 may be a semiconductor material such as silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP).

[0063] Ions of the first conductivity type with a relatively low concentration are implanted into a specific area on the front surface of the substrate 110 . After the ions of the first conductivity type diffuse, a drift region 120 is formed from the inside of the substrate 110 to the front surface of the substrate 110 .

[0064] Ions of the second conductivity type with a lower concentration are implanted into another specific region on the front surface of the substrate 110 . After the ions of the second conductivity type diffuse, a body region 130 is formed from the inside of the substrate 110 to the front surface of the substrate 110 .

[0065] The first conductivity type is P type and the second conductivity type is N type, or the first conductivity type is N type and the second conductivity type is P type. For example, the P type ions are boron ions and the N type ions are phosphorus ions.

[0066] A high concentration of first conductive type ions is implanted into a region on the surface of the drift region 120 away from the body region 130. After the first conductive type ions diffuse, a drain region 140 is formed from the inside of the drift region 120 to the surface of the drift region 120. The drain region 140 can be led out through a drain region contact hole to connect to an external drain terminal electrode.

[0067] A high concentration of first conductive type ions are implanted on the surface of the body region 130. After the first conductive type ions diffuse, a source region 170 is formed from the inside of the body region 130 to the surface of the body region 130. The source region 170 can be led out through the drain region contact hole to connect the external drain terminal electrode and the single contact field plate 160.

[0068] For example, the gate 151 may be made of polysilicon, and the sidewall 152 may be made of silicon dioxide (SiO 2 ) and / or silicon nitride (SiN).

[0069] A gate 151 is formed on the surface at the junction of the drift region 120 and the body region 130 by deposition, etching, photolithography and other processes, and a sidewall 152 is formed on the side of the gate 151 by deposition and etching and other processes, and the sidewall 152 covers the side of the gate 151 .

[0070] In other embodiments, the gate structure 150 also includes a gate oxide layer 153. The gate oxide layer 153 is first formed on the surface at the junction of the drift region 120 and the body region 130, and then the gate 151 is formed on the surface of the gate oxide layer 153 by deposition, etching, photolithography and other processes. Finally, the side wall 152 covering the side of the gate 151 is formed on the side of the gate 151 by deposition and etching and other processes.

[0071] Exemplarily, the material of the single contact field plate 160 is a conductive material, for example, a metal material such as tungsten and / or aluminum, or a semiconductor material such as polysilicon.

[0072] The side surface of the sidewall 152 close to the drain region 140 is usually a curved surface, and the section at the position of the curved surface closest to the drain region 140 ( Figure 4 A single contact field plate 160 is disposed in a partial area between the left dotted line in the figure and the side surface of the drain region 140 close to the side wall 152, so that the side surface of the single contact field plate 160 close to the drain region 140 is isolated from the drain region 140, and the side surface of the single contact field plate 160 close to the side wall 152 is in contact with the side surface of the side wall 152 close to the drain region 140, that is, the projection of the single contact field plate 160 on the surface of the drift region 120 is in contact with the edge of the projection of the side wall 152 on the surface of the drift region 120, as shown in FIG. Figure 4 shown.

[0073] Alternatively, a surface of the single contact field plate 160 close to the side wall 152 is isolated from a surface of the side wall 152 close to the drain region 140, that is, a projection of the single contact field plate 160 on the surface of the drift region 120 is isolated from a projection of the side wall 152 on the surface of the drift region 120. Figure 5 The isolation of the surface of the single contact field plate 160 close to the spacer 152 and the surface of the spacer 152 close to the drain region 140 is easier to control and realize in the process, making it easier to realize in the process.

[0074] In this way, the surface of the formed single contact field plate 160 away from the drift region 120 is located in the same horizontal plane, which can avoid the problem of uncontrollable etching stop caused by different heights of the single contact field plate 160, making it easier to implement in the process.

[0075] At this time, a single contact field plate 160 of a smaller size can be set, that is, the length W of the single small-sized contact field plate 160 in the direction from the body region 130 to the drift region 120 satisfies: 0.1μm≤W≤0.8μm, for example, the length W of the single small-sized contact field plate 160 in the direction from the body region 130 to the drift region 120 is 0.6μm.

[0076] Exemplarily, the length W of the single large-size contact field plate 13 in the LDMOS device with a single large-size contact field plate structure in the prior art in the direction from the body region 130 to the drift region 120 is set to 1.7 μm, and the length W of the single small-size contact field plate 160 in the LDMOS device 100 with a single small-size contact field plate structure provided by the present disclosure in the direction from the body region 130 to the drift region 120 is set to 0.5 μm, and the electric fields of the above two LDMOS devices are simulated, and the following are obtained: Figure 6 The electric field distribution shown is Figure 6 A schematic diagram comparing the electric fields of the LDMOS device provided in the embodiment of the present disclosure and the LDMOS device provided in the prior art.

[0077] Figure 6 The ordinate in represents the electric field strength. Figure 6 The area within the red dashed line corresponds to Figure 1 The LDMOS devices shown and Figure 4 The area within the red dashed line in the LDMOS device 100 shown in FIG. Figure 6 As shown in the electric field distribution within the red dashed line, compared with the LDMOS device with a single large-sized contact field plate structure provided by the prior art, the LDMOS device 100 with a single small-sized contact field plate structure provided by the present disclosure has a higher electric field strength.

[0078] In this way, the LDMOS device 100 provided by the present disclosure can enhance the electric field at the deep depletion, making the depletion more complete, thereby having a larger breakdown voltage.

[0079] The breakdown voltages of the two LDMOS devices provided in the above embodiment are simulated and the following are obtained: Figure 7 The breakdown voltage shown, Figure 7 A schematic diagram comparing the breakdown voltages of the LDMOS device provided in the embodiment of the present disclosure and the LDMOS device provided in the prior art.

[0080] Figure 7 The horizontal axis in represents the breakdown voltage. Figure 7 As shown, the breakdown voltage of the LDMOS device with a single large-size contact field plate structure provided by the prior art is 61.5 V, and the breakdown voltage of the LDMOS device 100 with a single small-size contact field plate structure provided by the present disclosure can reach 66.2 V. Obviously, compared with the LDMOS device with a single large-size contact field plate structure provided by the prior art, the LDMOS device 100 with a single small-size contact field plate structure provided by the present disclosure has a higher voltage and can improve the withstand voltage.

[0081] In summary, since the single contact field plate 160 is located in the area between the drain region 140 and the side surface of the sidewall 152 close to the drain region 140, and the projection of the single contact field plate 160 on the surface of the drift region 120 does not overlap with the projection of the sidewall 152 on the surface of the drift region 120, the surface of the single contact field plate 160 formed away from the drift region 120 is located in the same horizontal plane, which can avoid the problem of uncontrollable etching stop caused by different heights of the single contact field plate 160, making it easier to implement in the process. Since the length of the single contact field plate 160 in the direction from the body region 130 to the drift region 120 ranges from 0.1 micron to 0.8 micron, that is, a single contact field plate 160 of a smaller size can be set, so the electric field at the deep depletion of the LDMOS device 100 can be improved, making the depletion more complete, thereby improving the voltage resistance. In addition, the small-sized single contact field plate 160 has a small effect on the electric field when the LDMOS device 100 is turned on, so that the current increases, and the on-resistance of the LDMOS device 100 can be reduced, thereby improving the conductive performance. In addition, the process of the small-sized single contact field plate 160 is simple, that is, the LDMOS device 100 is easy to implement in terms of process.

[0082] In some embodiments, the position of the side surface of the single small-sized contact field plate 160 close to the drain region 140 can be set to the position of the side surface of the single large-sized contact field plate close to the drain region 140, and the length W of the single small-sized contact field plate 160 in the direction from the body region 130 to the drift region 120 can be set to any value between 0.1 micrometers and 0.8 micrometers. For example, the length W of the single small-sized contact field plate 160 in the direction from the body region 130 to the drift region 120 can be 0.6 micrometers.

[0083] In this way, only one side of the existing single large-size contact field plate mask needs to be modified, which is simple and quick to implement.

[0084] In some embodiments, the location of the single contact field plate 160 close to the surface of one side of the drain region 140 depends on the breakdown voltage of the LDMOS device 100 .

[0085] Exemplarily, a surface of the single contact field plate 160 away from the drain region 140 is isolated from or in contact with the sidewall 152 . The closer the surface of the single contact field plate 160 close to the drain region 140 is to the drain region 140 , the greater the breakdown voltage of the LDMOS device 100 .

[0086] In some embodiments, the LDMOS device 100 further includes a drain contact and a source contact, wherein the drain contact is located on the surface of the drain region 140 and the source contact is located on the surface of the drain region 170. The drain contact, the source contact and the contact field plate 160 are formed based on the same photomask.

[0087] Exemplarily, an interlayer dielectric layer of a certain thickness is provided on the surface of the side of the drain region 140 in the LDMOS device 100 away from the substrate 110, and a through hole is formed by etching in the area of ​​the interlayer dielectric layer directly opposite to the drain region 140 to provide a drain contact hole. A conductive material is filled in the drain contact hole, and the conductive material filled in the drain contact hole forms a drain contact portion, and the drain region 140 is connected to an external drain terminal electrode through the drain contact portion.

[0088] An interlayer dielectric layer of a certain thickness is provided on the surface of the side of the source region 170 in the LDMOS device 100 away from the substrate 110, and a through hole is formed by etching in the area of ​​the interlayer dielectric layer directly facing the source region 170 to provide a source contact hole. A conductive material is filled in the source contact hole, and the conductive material filled in the source contact hole forms a source contact portion, and the source region 170 is electrically connected to an external source terminal electrode and a single contact field plate 160 through the source contact portion.

[0089] A single field plate contact hole is also provided in the LDMOS device 100, and a conductive material is filled in the single field plate contact hole, and the conductive material in the single field plate contact hole forms a single contact field plate 160. Based on the same photomask, a single field plate contact hole, a source contact hole, and a drain contact hole can be formed at the same time, and conductive material is filled in the single field plate contact hole, the source contact hole, and the drain contact hole to form a drain contact portion, a source contact portion, and a single contact field plate 160.

[0090] In this way, the number of masks for the LDMOS device 100 can be reduced, thereby reducing the number of process steps, and the process is easy to implement.

[0091] In some embodiments, Figure 4 and Figure 5 As shown, the LDMOS device 100 further includes a barrier layer 180 , which is located between the drift region 120 and the single contact field plate 160 , and a portion of a surface of the gate structure 150 away from the drift region 120 . The barrier layer 180 extends to the drain region 140 .

[0092] Exemplarily, first, a barrier layer 180 is formed on a partial area of ​​the surface of the gate 151 away from the substrate 110 and on the surface of the substrate 110 between the gate structure 150 and the drain region 140. Then, an interlayer dielectric layer is formed on the surface of the barrier layer 180 away from the substrate 110, and a through hole is formed in the interlayer dielectric layer to set a single field plate contact hole. Finally, a conductive material is filled in the single field plate contact hole to set a single contact field plate 160.

[0093] In some embodiments, Figure 8 A structural diagram of another LDMOS device provided in an embodiment of the present disclosure is shown in FIG. Figure 8 As shown, the source region 170 includes a first source region 171 and a second source region 172 having the same doping type, and the first source region 171 is located on a side of the second source region 172 close to the drain region 140 .

[0094] Ions of the first conductive type are implanted at a higher concentration in two regions at a certain distance from the surface of the body region 130, wherein after the diffusion of the ions of the first conductive type in the region close to the drain region 140, a first source region 171 is formed from the interior of the body region 130 to the surface of the body region 130, and after the diffusion of the ions of the first conductive type in the region far from the drain region 140, a second source region 172 is formed from the interior of the body region 130 to the surface of the body region 130.

[0095] An interlayer dielectric layer is disposed on the surface of the first source region 171 and the second source region 172. The interlayer dielectric layer is etched in the area facing the first source region 171 and the second source region 172 to form a through hole to set a source contact hole. The source contact hole is filled with a conductive material. The conductive material filled in the source contact hole forms a source contact portion. The first source region 171 and the second source region 172 are electrically connected to the external source terminal electrode and the single contact field plate 160 through the source contact portion.

[0096] Continue to see Figure 8 The LDMOS device 100 further includes a body contact region 190 , which is located between the first source region 171 and the second source region 172 to separate the first source region 171 from the second source region 172 . The body contact region 190 and the first source region 171 have opposite doping types.

[0097] Illustratively, a higher concentration of second conductive type ions are implanted into the region between the first source region 171 and the second source region 172 on the surface of the body region 130 . After the second conductive type ions diffuse, a body contact region 190 is formed from the inside of the body region 130 to the surface of the body region 130 .

[0098] In other embodiments, a higher concentration of second conductive type ions may be first implanted into a specific surface area of ​​the body region 130 . After the second conductive type ions diffuse, a body contact region 190 is formed from the inside of the body region 130 to the surface of the body region 130 .

[0099] Then, higher concentrations of first conductive type ions are injected into both sides of the body contact region 190 respectively. After the first conductive type ions on the side of the body contact region 190 close to the drain region 140 diffuse, a first source region 171 is formed from the inside of the body region 130 to the surface of the body region 130. After the first conductive type ions on the side of the body contact region 190 away from the drain region 140 diffuse, a second source region 172 is formed from the inside of the body region 130 to the surface of the body region 130.

[0100] In some embodiments, the LDMOS device 100 is an N-type LDMOS, the first conductivity type is N-type, and the second conductivity type is P-type.

[0101] Exemplarily, the drift region 120 is N-type doped, the body region 130 is P-type doped, the drain region 140 is N-type doped, the first source region 171 and the second source region 172 are N-type doped, and the body contact region 190 is P-type doped. In this way, the drift region 120 is an N-type drift region, the body region 130 is a P-type body region, the drain region 140 is an N-type drain region, the first source region 171 and the second source region 172 are N-type source regions, and the body contact region 190 is a P-type body contact region.

[0102] In some other embodiments, the LDMOS device 100 is a P-type LDMOS, and the first conductivity type is P-type, and the second conductivity type is N-type.

[0103] Exemplarily, the drift region 120 is P-type doped, the body region 130 is N-type doped, the drain region 140 is P-type doped, the first source region 171 and the second source region 172 are P-type doped, and the body contact region 190 is N-type doped. In this way, the drift region 120 is a P-type drift region, the body region 130 is an N-type body region, the drain region 140 is a P-type drain region, the first source region 171 and the second source region 172 are P-type source regions, and the body contact region 190 is an N-type body contact region.

[0104] The embodiments of the present disclosure further provide a method for preparing an LDMOS device, which is used to prepare the LDMOS device 100 provided in any of the above embodiments.

[0105] Fig. 9 A schematic diagram of a process for preparing a LDMOS device provided in an embodiment of the present disclosure is provided. Figures 10A-10F A schematic diagram of a manufacturing process of an LDMOS device provided in an embodiment of the present disclosure. Fig. 9 As shown, the specific steps of the method for preparing the LDMOS device include:

[0106] S101, forming a drift region and a body region with opposite doping types.

[0107] Exemplarily, a substrate 110 is provided, and ions of a first conductivity type with a relatively low concentration are implanted in a specific region on the front side of the substrate 110. After the ions of the first conductivity type diffuse, a drift region 120 is formed from the inside of the substrate 110 to the front side of the substrate 110. ions of a second conductivity type with a relatively low concentration are implanted in another specific region on the front side of the substrate 110. After the ions of the second conductivity type diffuse, a body region 130 is formed from the inside of the substrate 110 to the front side of the substrate 110. Fig. 10A shown.

[0108] The first conductivity type is P type and the second conductivity type is N type, or the first conductivity type is N type and the second conductivity type is P type. For example, the P type ions are boron ions and the N type ions are phosphorus ions.

[0109] S102, ions are implanted on a side of the surface of the drift region away from the body region to form a drain region.

[0110] Exemplarily, a higher concentration of first conductive type ions is implanted into a region on the surface of the drift region 120 away from the body region 130. After the first conductive type ions diffuse, a drain region 140 is formed from the inside of the drift region 120 to the surface of the drift region 120. Fig. 10B shown.

[0111] S103, implanting ions on the surface of the body region to form a source region.

[0112] Exemplarily, a higher concentration of first conductive type ions is implanted on the surface of the body region 130. After the first conductive type ions diffuse, a source region 170 is formed from the inside of the body region 130 to the surface of the body region 130. Fig. 10C shown.

[0113] S104, preparing a gate structure isolated from the drain region on a portion of the drift region and a portion of the body region.

[0114] The gate structure includes a gate and a sidewall covering the side of the gate.

[0115] Exemplarily, a gate oxide layer 153 is formed on the surface at the junction of the drift region 120 and the body region 130, and then a gate 151 is formed on the surface of the gate oxide layer 153 by deposition, etching, photolithography and other processes, and finally a sidewall 152 covering the side of the gate 151 is formed on the side of the gate 151 by deposition and etching and other processes, such as Fig. 10D shown.

[0116] In other embodiments, the gate 151 is formed on the surface at the junction of the drift region 120 and the body region 130 by deposition, etching, photolithography and other processes, and the sidewall 152 covering the side of the gate 151 is formed on the side of the gate 151 by deposition and etching and other processes.

[0117] S105, preparing a single contact field plate in a partial area between the drain region and a surface of a side wall close to the drain region.

[0118] The projection of the single contact field plate 160 on the surface of the drift region 120 does not overlap with the projection of the sidewall 152 on the surface of the drift region 120 , and the length of the single contact field plate 160 in the direction from the body region 130 to the drift region 120 ranges from 0.1 micrometers to 0.8 micrometers.

[0119] Exemplarily, the side surface of the side wall 152 close to the drain region 140 is generally a curved surface, and a single contact field plate 160 is disposed in the region between the section where the curved surface is closest to the drain region 140 and the side surface of the drain region 140 close to the side wall 152, such as Fig. 10E and Fig.10F shown.

[0120] A surface of the single contact field plate 160 close to the side wall 152 contacts a surface of the side wall 152 close to the drain region 140, that is, a projection of the single contact field plate 160 on the surface of the drift region 120 contacts an edge of a projection of the side wall 152 on the surface of the drift region 120, and a surface of the single contact field plate 160 close to the drain region 140 is isolated from the drain region 140. Fig. 10E Alternatively, a surface of the single contact field plate 160 close to the spacer 152 is isolated from a surface of the spacer 152 close to the drain region 140, a projection of the single contact field plate 160 on the surface of the drift region 120 is isolated from a projection of the spacer 152 on the surface of the drift region 120, and a surface of the single contact field plate 160 close to the drain region 140 is isolated from the drain region 140, as shown in FIG. Fig.10F shown.

[0121] S106 , electrically connecting the source region to the single contact field plate.

[0122] Exemplarily, an interlayer dielectric layer of a certain thickness is set on the surface of the source region 170, and the area opposite to the interlayer dielectric layer and the source region 170 is etched to form a through hole to set a source contact hole, and a conductive material is filled in the source contact hole to form a source contact portion, and the source region 170 is electrically connected to a single contact field plate 160 through the source contact portion.

[0123] In the disclosed embodiment, a drift region and a body region with opposite doping types are formed, ions are injected into the surface of the drift region away from the body region to form a drain region, ions are injected into the surface of the body region to form a source region, a gate structure isolated from the drain region is prepared on part of the drift region and part of the body region, the gate structure includes a gate and a sidewall covering the side of the gate, a single contact field plate is prepared in a partial area between the drain region and the side surface of the side wall close to the drain region, the projection of the single contact field plate on the surface of the drift region does not overlap with the projection of the sidewall on the surface of the drift region, the source region is electrically connected to the single contact field plate, and the surface of the formed single contact field plate away from the drift region is located in the same horizontal plane, which can avoid the problem of difficult control of etching stop caused by different heights of the single contact field plate, making it easier to implement in the process. The length of the single contact field plate in the direction from the body region to the drift region ranges from 0.1 micron to 0.8 micron, and a single contact field plate of smaller size can be set, which can enhance the electric field at the deep depletion, make the depletion more complete, and thus improve the voltage resistance. In addition, a small-sized single contact field plate has a small effect on the electric field when the device is turned on, so that the current increases, the on-resistance can be reduced, and the conductive performance is improved. In addition, the process of a small-sized single contact field plate is simple, that is, it is easy to implement in terms of process.

[0124] In some embodiments, Fig.11 A schematic diagram of a process for preparing another LDMOS device provided in an embodiment of the present disclosure, Fig.11 for Fig. 9 Based on the illustrated embodiment, a possible implementation method when executing S105 is specifically described as follows:

[0125] S105', based on the same photomask, a single contact field plate is formed in a partial area between the drain region and a surface of the sidewall close to the drain region, a drain contact is formed on the surface of the drain region, and a source contact is formed on the surface of the source region.

[0126] Exemplarily, an interlayer dielectric layer of a certain thickness is disposed on the surface of the drain region 140 and the surface of the source region 170, and an interlayer dielectric layer of a certain thickness is also disposed on the surface of the drift region 120. Etching is performed on the interlayer dielectric layer based on the same photomask to simultaneously form a single field plate contact hole, a source contact hole, and a drain contact hole, and conductive materials are filled in the single field plate contact hole, the source contact hole, and the drain contact hole to simultaneously form a drain contact portion, a source contact portion, and a single contact field plate 160.

[0127] In this way, the number of masks required in the preparation process of the LDMOS device can be reduced, thereby reducing the number of process steps, making the LDMOS device easier to implement in terms of technology.

[0128] In some embodiments, before executing S105, the following steps are also included:

[0129] A blocking layer is formed on a partial area of ​​the surface of the gate away from the substrate and on an area between the gate structure and the drain region on the surface of the substrate.

[0130] Exemplarily, first, a barrier layer 180 is formed on a partial area of ​​the surface of the gate 151 away from the substrate 110 and on the surface of the substrate 110 between the gate structure 150 and the drain region 140. Then, an interlayer dielectric layer is formed on the surface of the barrier layer 180 away from the substrate 110, and a through hole is formed in the interlayer dielectric layer to set a single field plate contact hole. Finally, a conductive material is filled in the single field plate contact hole to set a single contact field plate 160, as shown in FIG. Figure 4 and Figure 5 shown.

[0131] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0132] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present application.

[0133] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. An LDMOS device, characterized in that: include: A drift region and a body region, wherein the body region and the drift region have opposite doping types; a drain region, located in the drift region and away from the body region, wherein the drain region extends from the inside of the drift region to the surface of the drift region; A gate structure, covering part of the drift region and part of the body region and isolated from the drain region; the gate structure comprises a gate and a sidewall covering a side of the gate; a single contact field plate, located in a partial area between the drain region and a surface of a side of the sidewall close to the drain region, wherein a projection of the single contact field plate on the surface of the drift region does not overlap with a projection of the sidewall on the surface of the drift region; a length of the single contact field plate in a direction from the body region to the drift region ranges from 0.1 micrometers to 0.8 micrometers; A source region is located in the body region and extends to a surface of the body region, wherein the source region is electrically connected to the single contact field plate.

2. The LDMOS device according to claim 1, characterized in that: A projection of the single contact field plate on the surface of the drift region is isolated from a projection of the spacer on the surface of the drift region.

3. The LDMOS device according to claim 1, characterized in that: The position of the surface of one side of the single contact field plate close to the drain region depends on the breakdown voltage of the LDMOS device.

4. The LDMOS device according to claim 1, characterized in that: The LDMOS device further comprises: A drain contact portion, located on the surface of the drain region; A source contact portion, located on the surface of the source region; Wherein, the drain contact portion, the source contact portion and the single contact field plate are formed based on the same photomask.

5. The LDMOS device according to claim 1, characterized in that: The LDMOS device further comprises: A barrier layer is located between the drift region and the single contact field plate, and a partial area of ​​a surface of the gate structure away from the drift region, and the barrier layer extends to the drain region.

6. The LDMOS device according to claim 1, characterized in that: The source region comprises a first source region and a second source region of the same doping type, wherein the first source region is located on a side of the second source region close to the drain region; The LDMOS device further comprises: A body contact region is located between the first source region and the second source region to separate the first source region from the second source region, and the body contact region and the first source region have opposite doping types.

7. The LDMOS device according to claim 6, characterized in that: The drift region is N-type doped, the body region is P-type doped, the drain region is N-type doped, the first source region and the second source region are N-type doped, and the body contact region is P-type doped.

8. The LDMOS device according to claim 6, characterized in that: The drift region is P-type doped, the body region is N-type doped, the drain region is P-type doped, the first source region and the second source region are P-type doped, and the body contact region is N-type doped.

9. A method for preparing an LDMOS device, characterized in that: include: forming a drift region and a body region of opposite doping types; Implanting ions on a side of the surface of the drift region away from the body region to form a drain region; Implanting ions on the surface of the body region to form a source region; Preparing a gate structure isolated from the drain region on part of the drift region and part of the body region, wherein the gate structure comprises a gate and a sidewall covering a side of the gate; A single contact field plate is prepared in a partial area between the drain region and a surface of a side of the spacer close to the drain region, wherein a projection of the single contact field plate on the surface of the drift region does not overlap with a projection of the spacer on the surface of the drift region; The length of the single contact field plate in the direction from the body region to the drift region is in a range of 0.1 micrometer to 0.8 micrometer; The source region is electrically connected to the single contact field plate.

10. The preparation method according to claim 9, characterized in that: The step of preparing a single contact field plate in a partial area between the drain region and a surface of the side wall close to the drain region comprises: Based on the same photomask, the single contact field plate is prepared in a partial area between the drain region and a surface of the side wall close to the drain region, a drain contact is prepared on the surface of the drain region, and a source contact is prepared on the surface of the source region.

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