Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device includes an epitaxial layer, a first trench, a first field plate, a first trench gate, a first planar gate, and a first conductive connection portion. The epitaxial layer has a first conductivity type. The first trench is disposed in the epitaxial layer and extends along a first direction. The first field plate is disposed within the first trench and extends along a first direction. The first trench gate is disposed in the first trench and extends along a first direction, where the first trench gate is laterally separated from the first field plate, and a top surface of the first field plate is higher than a top surface of the first trench gate. The first planar gate is disposed on the first field plate and the first trench gate and extends along a second direction. A first conductive connection portion is disposed within the first trench between the first trench gate and the first planar gate, the first trench gate being electrically connected to the first planar gate through the first conductive connection portion.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and in particular to a semiconductor device of a power transistor including a trench gate and a planar gate and a manufacturing method thereof. Background Art

[0002] A power transistor refers to a transistor that works under high voltage and high current conditions. The most common power transistor is, for example, a power metal oxide semiconductor field effect transistor (power MOSFET), which can be used in many different fields, such as power supplies, DC-to-DC converters, low voltage motor controllers, etc.

[0003] In recent years, in response to the development of various electronic products, the power and layout density of power MOSFETs have also increased, and the frequency of application in DC-DC transformers has also increased significantly. However, the current power MOSFET technology, such as split gate trench (SGT), laterally diffused metal-oxide semiconductor (LDMOS), U-groove metal-oxide semiconductor (UMOS) and other power transistors, is difficult to fully meet the needs of electronic products in all aspects, such as it is difficult to simultaneously reduce chip area, increase component layout density, increase current and reduce switching loss. Therefore, the industry is in urgent need of developing new power transistors to overcome the above problems. Summary of the invention

[0004] In view of this, the present invention proposes a semiconductor device of a power transistor including a trench gate and a planar gate to meet various requirements when applied in electronic products.

[0005] According to one embodiment of the present invention, a semiconductor device is disclosed, comprising an epitaxial layer, a first trench, a first field plate, a first trench gate, a first planar gate, and a first conductive connection portion. The epitaxial layer has a first conductivity type. The first trench is arranged in the epitaxial layer and extends along a first direction. The first field plate is arranged in the first trench and extends along the first direction. The first trench gate is arranged in the first trench and extends along the first direction, wherein the first trench gate is laterally separated from the first field plate, and the top surface of the first field plate is higher than the top surface of the first trench gate. The first planar gate is arranged above the first field plate and the first trench gate, and extends along a second direction, and the second direction is not parallel to the first direction. The first conductive connection portion is arranged in the first trench and is located between the first trench gate and the first planar gate, and the first trench gate is electrically connected to the first planar gate through the first conductive connection portion.

[0006] According to one embodiment of the present invention, a method for manufacturing a semiconductor device is disclosed, comprising: providing a first trench structure, the first trench structure is located in an epitaxial layer and extends along a first direction, the first trench structure comprising: a first trench, a first field plate arranged in the first trench, and a trench dielectric layer arranged between the first trench and the first field plate; etching the trench dielectric layer to form a first groove, the first groove extending along the first direction; forming a conductive layer to fill the first groove, the conductive layer covering the first field plate and the epitaxial layer; etching the conductive layer to form a first trench gate, a first planar gate, and a first conductive connection portion. The first trench gate extends along the first direction and laterally separates the first field plate. The first planar gate extends along a second direction, the second direction is not parallel to the first direction, wherein the first planar gate is arranged on the first field plate and the first trench gate. The first conductive connection portion is arranged in the first groove and is located between the first trench gate and the first planar gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to make the following easier to understand, the drawings and their detailed text descriptions can be referred to at the same time when reading the present invention. Through the specific embodiments in this article and with reference to the corresponding drawings, the specific embodiments of the present invention are explained in detail and the working principles of the specific embodiments of the present invention are explained. In addition, for the sake of clarity, the features in the drawings may not be drawn according to the actual scale, so the size of some features in some drawings may be deliberately enlarged or reduced.

[0008] Figure 1 FIG. 4 is a three-dimensional schematic diagram of a local area of ​​a semiconductor device according to an embodiment of the present invention.

[0009] Figure 2 is a diagram according to an embodiment of the present invention. Figure 1 The cross-sectional diagram shown by the section line AA'.

[0010] Figure 3 is a diagram according to an embodiment of the present invention. Figure 1 The cross-sectional diagram shown by the section line BB'.

[0011] Figure 4 is a diagram according to an embodiment of the present invention. Figure 1 The cross-sectional diagram shown by the section line CC'.

[0012] Figure 5 is a diagram according to an embodiment of the present invention. Figure 1 The cross-sectional diagram shown by the section line DD'.

[0013] Figure 6 FIG. 4 is a schematic perspective view of a semiconductor device including two repeating units according to an embodiment of the present invention.

[0014] Figure 7 is a diagram according to an embodiment of the present invention. Figure 6 The cross-sectional diagram shown by the section line EE'.

[0015] Figure 8 and Fig. 9 FIG. 4 is a three-dimensional schematic diagram of various stages of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0016] Fig.10 FIG. 4 is a schematic top view of a semiconductor device including at least two repeating units according to an embodiment of the present invention.

[0017] The reference numerals are described as follows:

[0018] 100: Semiconductor devices

[0019] 102: Base

[0020] 105: Drain electrode

[0021] 107: Epitaxial layer

[0022] 108-1: First Groove

[0023] 108-2: Second Groove

[0024] 110: Field board

[0025] 110-1: First board

[0026] 110-2: Second board

[0027] 112: Trench dielectric layer

[0028] 114-1: First groove

[0029] 114-2: Second groove

[0030] 116: Gate dielectric layer

[0031] 120: Trench gate

[0032] 120-1: First trench gate

[0033] 120-2: Second trench gate

[0034] 120-1a: Top surface

[0035] 130: Planar gate

[0036] 130-1: First planar gate

[0037] 130-2: Second planar gate

[0038] 140: substrate doping region

[0039] 142: Substrate contact area

[0040] 144-1: Horizontal channel area

[0041] 144-2: Vertical Passage Area

[0042] 150: Source doping region

[0043] 160: Conductive compound

[0044] 160-1: First conductive compound

[0045] 160-2: Second conductive compound

[0046] 160-3: The third conductive compound

[0047] 170: Conductive connection part

[0048] 170-1: First conductive connection portion

[0049] 170-2: Second conductive connection portion

[0050] 170-1b: Side

[0051] 182: Trench gate capping layer

[0052] 182a: Concave top surface

[0053] 184: Planar gate spacer

[0054] 190: First groove structure

[0055] 200: Conductive contact structure

[0056] 302, 304, 306, 308, 310, 312: Steps

[0057] U1: Repeating unit

[0058] U2: Repeating unit DETAILED DESCRIPTION

[0059] The present invention provides several different embodiments that can be used to implement different features of the present invention. For the sake of simplicity of description, the present invention also describes examples of specific components and arrangements. The purpose of providing these embodiments is only for illustration, not for any limitation. For example, the description below for "a first feature is formed on or above a second feature" may refer to "a first feature is in direct contact with a second feature" or "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact. In addition, various embodiments of the present invention may use repeated reference symbols and / or text annotations. The use of these repeated figure marks and annotations is to make the description more concise and clear, rather than to indicate the association between different embodiments and / or configurations.

[0060] In addition, for the spatially related descriptive words mentioned in the present invention, such as "under", "low", "down", "above", "on", "top", "bottom" and similar words, for the convenience of description, their usage is to describe the relative relationship between one component or feature and another (or multiple) components or features in the drawings. In addition to the swing direction shown in the drawings, these spatially related words are also used to describe the possible swing direction of the semiconductor device during use and operation. As the swing direction of the semiconductor device is different (rotated 90 degrees or other orientations), the spatially related descriptions used to describe its swing direction should also be interpreted in a similar manner.

[0061] Although the present invention uses the terms first, second, third, etc. to describe various components, parts, regions, layers, and / or sections, it should be understood that these components, parts, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish a certain component, part, region, layer, and / or block from another component, part, region, layer, and / or block, and they themselves do not mean or represent any previous ordinal number of the component, nor do they represent the arrangement order of a certain component and another component, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first component, part, region, layer, or block discussed below can also be referred to as the second component, part, region, layer, or block.

[0062] The terms "about" or "substantially" mentioned in the present invention generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of a specific description of "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

[0063] The terms "coupling", "coupling" and "electrical connection" mentioned in the present invention include any direct and indirect electrical connection means. For example, if the text describes that a first component is coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0064] Although the invention of the present invention is described below by specific embodiments, the inventive principle of the present invention can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, certain details will be omitted, and these omitted details belong to the knowledge scope of those skilled in the art.

[0065] Figure 1 FIG. 1 is a three-dimensional schematic diagram of a local area of ​​a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, in one embodiment, the semiconductor device 100 includes a substrate 102, the substrate 102 has a first conductivity type, such as an n-type heavily doped silicon substrate (N+substrate), an epitaxial layer 107 is disposed on the substrate 102 and has a first conductivity type, such as an n-type silicon epitaxial layer (N epitaxial layer), and the epitaxial layer 107 can be used as a carrier drift region.

[0066] The semiconductor device 100 further includes a first trench 108 - 1 disposed in the epitaxial layer 107 and extending along a first direction, such as direction Y. According to one embodiment, the first trench 108 - 1 includes a first field plate 110 - 1, at least one first trench gate 120 - 1 (such as two first trench gates 120 - 1), and a trench dielectric layer 112 .

[0067] The first field plate 110-1 is disposed in the first trench 108-1 and extends along a first direction, such as the Y direction. The first trench gate 120-1 ( Figure 5 ), disposed in the first trench 108-1 and extending along the first direction, wherein the first trench gate 120-1 is laterally (e.g., in the X direction) separated from the first field plate 110-1, and the top surface of the first field plate 110-1 is higher than the top surface of the first trench gate 120-1. According to one embodiment, the first trench 108-1 includes two first trench gates 120-1, which are respectively disposed on both sides of the first field plate 110-1.

[0068] The trench dielectric layer 112 is disposed in the first trench 108-1 and between the inner surface of the first trench 108-1 and the first field plate 110-1. The trench dielectric layer 112 may be formed of silicon oxide, silicon nitride, silicon oxynitride or a dielectric material with a high dielectric constant.

[0069] The first planar gate 130-1 is disposed on the first field plate 110-1 and the first trench gate 120-1, and extends along a second direction, such as along the X direction, and the second direction is not parallel to the first direction. The first planar gate 130-1 can be connected to the first trench 108-1 through a conductive connection portion (such as Figure 2 The first conductive connection portion 170-1 is electrically connected to the first trench gate 120-1, so that the first planar gate 130-1 and the first trench gate 120-1 can synchronously turn on and off the channel region of the semiconductor device.

[0070] According to one embodiment, the first trench gate 120-1, the first planar gate 130-1, and the first conductive connection portion 170-1 are all made of conductive materials, such as doped conductive polysilicon or other conductive semiconductors, and the first trench gate 120-1, the first planar gate 130-1, and the first conductive connection portion 170-1 are made of the same material, but are not limited thereto.

[0071] According to an embodiment, the semiconductor device 100 further includes a body doping region 140, which is disposed in the epitaxial layer 107 and has a second conductivity type opposite to the first conductivity type, for example, a p-type body region (P body), wherein the doping concentration of the second conductivity type dopant in the body doping region 140 is higher than the doping concentration of the first conductivity type dopant in the epitaxial layer 107. The body doping region 140 extends outside the sidewall of the first trench 108-1 in the second direction (for example, the X direction), so that a portion of the body doping region 140 covers the side surface of the first trench gate 120-1, and another portion of the body doping region 140 is covered by the first planar gate 130-1 in the vertical direction (for example, the Z direction).

[0072] The semiconductor device 100 further includes at least one source doping region 150 disposed on the upper portion of the epitaxial layer 107 and adjacent to the first trench 108-1, and the source doping region 150 has a first conductivity type. According to one embodiment, the semiconductor device 100 includes two source doping regions 150 disposed in the substrate doping region 140 and adjacent to the first trench 108-1. The source doping regions 150 are separated from each other along a first direction (e.g., a Y direction), and the source doping regions 150 have a first conductivity type, such as an n-type heavily doped region. One of the source doping regions 150 is adjacent to the first planar gate 130-1, and the other of the source doping regions 150 is adjacent to another planar gate (not shown). Since the source doping region 150 occupies the upper portion of the base doping region 140 through ion implantation, the source doping region 150 can be considered to be disposed in the base doping region 140, or to be disposed on the base doping region 140 (that is, the base doping region 140 is considered to be disposed under the source doping region 150).

[0073] The conductor device 100 further includes a body contact region 142 sandwiched between the two source doping regions 150. The body contact region 142 has a second conductivity type, such as a heavily p-type doped region, whose p-type dopant concentration is higher than the p-type dopant concentration of the body doping region 140. The body contact region 142 is electrically connected to the body doping region 140 to control the potential of the body doping region 140.

[0074] The semiconductor device 100 further includes a plurality of conductive compounds 160 separated laterally from each other, such as a first conductive compound 160-1, a second conductive compound 160-2, and a third conductive compound 160-3; wherein the first conductive compound 160-1 is electrically connected to the first field plate 110-1, the second conductive compound 160-2 is electrically connected to the first planar gate 130-1, and the third conductive compound 160-3 is electrically connected to the source doping region 150 and the body contact region 142. The conductive compound 160 may be a compound including a metal and a semiconductor, such as a nickel-containing silicide or other metal silicide. The resistivity of the conductive compound 160 is lower than the resistivity of the first field plate 110-1, the first planar gate 130-1, the source doping region 150, and the body contact region 142, thereby reducing on-resistance, signal delay, and switching loss. By providing the conductive compound 160 with low resistivity, even if the vertical projection area of ​​the semiconductor device 100 continues to shrink, current can still be transmitted in the conductive compound 160 without causing current transmission loss due to component shrinkage.

[0075] Regarding the first conductive compound 160-1, the first conductive compound 160-1 covers the top surface of the first field plate 110-1 and extends along a first direction, such as the Y direction. The two first trench gates 120-1 on both sides of the first field plate 110-1 are laterally separated from the first conductive compound 160-1 (for example, in the X direction) and are not electrically connected to the first trench gates 120-1.

[0076] Regarding the second conductive compound 160-2, the second conductive compound 160-2 covers the top surface of the first planar gate 130-1 and extends along a second direction, such as the X direction. The second conductive compound 160-2 is separated from the first conductive compound 160-1 in vertical height (such as the Z direction) and in a lateral direction (such as the X direction), and is not electrically connected to the first conductive compound 160-1.

[0077] Regarding the third conductive compound 160-3, the third conductive compound 160-3 is a single conductive compound that is continuously distributed, covers the top surface of the source doping regions 150 separated from each other in the first direction, and covers the top surface of the substrate contact region 142 located between the source doping regions 150. The third conductive compound 160-3 laterally separates the first trench gate 120-1 and the first conductive compound 160-1. Further, the third conductive compound 160-2 is laterally (e.g., in the X direction) separated from the first conductive compound 160-1, and is not electrically connected to the first conductive compound 160-1. In addition, the third conductive compound 160-3 is laterally (e.g., in the Y direction) separated from the second conductive compound 160-2, and is not electrically connected to the second conductive compound 160-2.

[0078] The semiconductor device 100 further includes a plurality of conductive contact structures 200, which are disposed separately from each other. By disposing the conductive contact structures 200, external signals can be transmitted to the corresponding first field plate 110-1, the first planar gate 130-1, and the source doping region 150. Specifically, at least one of the conductive contact structures 200 is electrically connected to the first conductive compound 160-1, and further electrically connected to the first field plate 110-1. At least another one of the conductive contact structures 200 is electrically connected to the second conductive compound 160-2, and further electrically connected to the first planar gate 130-1. At least another two of the conductive contact structures 200 are respectively disposed on the corresponding source doping region 150, and are electrically connected to the third conductive compound 160-3, and are further electrically connected to the source doping region 150 and the body contact region 142.

[0079] For the conductive contact structure 200 electrically connected to the source doping region 150, since the conductive contact structure 200 can be electrically connected to the source doping region 150 and the substrate contact region 142 through the second conductive compound 160-2 set on the epitaxial layer 107, the bottom surface of the conductive contact structure 200 does not need to penetrate into the epitaxial layer 107. Therefore, the conductive contact structure 200 can be integrated into other semiconductor device processes, such as complementary field effect transistors or bipolar transistor processes, which is beneficial to simplifying the process.

[0080] When the semiconductor device 100 is in an on-state, a positive bias is applied to the first planar gate 130-1 and the first trench gate 120-1, so that a channel region in an on-state is generated in the adjacent substrate doping region 140, for example, a horizontal channel region 144-1 adjacent to the first planar gate 130-1 and a vertical channel region 144-2 adjacent to the first trench gate 120-1. Therefore, the current originating from the drain can flow from bottom to top through the epitaxial layer 107, the channel region (the horizontal channel region 144-1 and the vertical channel region 144-2), and enter the source doping region 150, and finally enter the corresponding conductive contact structure 200. In addition, a positive bias is applied to the first field plate 110-1, and the value of the positive bias can be the same as or different from the positive bias applied to the first planar gate 130-1 and the first trench gate 120-1. By applying a positive bias voltage to the first field plate 110 - 1 , the electric field distribution around the first trench 108 - 1 can be adjusted to avoid electrical breakdown of the semiconductor device 100 or to further reduce the on-resistance.

[0081] Figure 2 is a diagram according to an embodiment of the present invention. Figure 1 The cross-sectional diagram shown by the section line AA'. Figure 2 As shown, the first trench gate 120-1 extends along a first direction, such as the Y direction, and the first conductive connection portion 170-1 is disposed between the first trench gate 120-1 and the first planar gate 130-1, so that the first conductive connection portion 170-1 is electrically connected to the first planar gate 130-1 through the first conductive connection portion 170-1. The top surface of the first planar gate 130-1 is covered by the second conductive compound 160-2, so that the current can be transmitted to each region of the first planar gate 130-1 along the second direction through the second conductive compound 160-2.

[0082] In addition, the semiconductor device 100 further includes a trench gate capping layer 182, which covers the top surface 120-1a of the first trench gate 120-1 and covers the side surface 170-1b of the first conductive connection portion 170-1. The semiconductor device 100 further includes a planar gate spacer 184, which covers two opposite sides of the first planar gate 130-1. The planar gate spacer 184 extends along a second direction, such as an X direction, and is disposed on the first trench 108-1. The trench gate capping layer 182 and the planar gate spacer 184 can be formed by depositing a dielectric layer and self-aligned etching, so the trench gate capping layer 182 and the planar gate spacer 184 can include the same material, such as silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.

[0083] Figure 3 is a diagram according to an embodiment of the present invention. Figure 1 The cross-sectional diagram shown by the section line BB'. Figure 3 As shown, the first field plate 110-1 extends along a first direction, such as the Y direction, and the top surface of the first field plate 110-1 is covered by the first conductive compound 160-1 and electrically connected to the conductive contact structure 200. By providing the first conductive compound 160-1 to cover, the current can be transferred to each region of the first field plate 110-1 along the first direction through the first conductive compound 160-1.

[0084] The first planar gate 130-1 is disposed on the first field plate 110-1, and a gate dielectric layer 116 is included between the first planar gate 130-1 and the first field plate 110-1. The first planar gate 130-1 can be prevented from being electrically connected to the first field plate 110-1 by disposing the gate dielectric layer 116. The gate dielectric layer 116 can include silicon oxide, silicon nitride, silicon oxynitride, or a dielectric material with a high dielectric constant.

[0085] Planar gate spacers 184 are disposed on two opposite sides of the first planar gate 130-1 to separate the first conductive compound 160-1 and the second conductive compound 160-2 from each other. Since the planar gate spacers 184 are made of insulating material, the first conductive compound 160-1 can be prevented from being electrically connected to the second conductive compound 160-2.

[0086] Figure 4 is a diagram according to an embodiment of the present invention. Figure 1 The cross-sectional schematic diagram is shown by the section line CC'. As shown in the later process steps, the trench dielectric layer 112 is disposed in the lower section of the first trench 108-1, and the upper section of the first trench 108-1 is not covered by the trench dielectric layer 112, and two first grooves 114-1 are formed on both sides of the first field plate 110-1. The inner surface of the first groove 114-1 is provided with a continuously distributed gate dielectric layer 116, and the gate dielectric layer 116 extends from the first groove 114-1 and covers the top surface of the substrate doping region 140. Each first groove 114-1 also includes a first trench gate 120-1 and a first conductive connection portion 170-1. Through the first conductive connection portion 170-1, the first trench gate 120-1 can be electrically connected to the first planar gate 130-1. The conductive contact structure 200 is disposed on the first planar gate 130-1 and is electrically connected to the first planar gate 130-1.

[0087] Figure 5 is a diagram according to an embodiment of the present invention. Figure 1 The cross-sectional diagram shown by the section line DD'. Figure 5As shown, each first groove 114-1 includes a gate dielectric layer 116, a first trench gate 120-1, and a trench gate capping layer 182. The trench gate capping layer 182 covers the top surface of the first trench gate 120-1, and the trench gate capping layer 182 includes a recessed top surface 182a.

[0088] Two substrate doping regions 140, two source doping regions 150, and two third conductive compounds 160-3 are respectively disposed on both sides of the first trench 108-1. The bottom surface of the substrate doping region 140 is higher than the bottom surface of the first trench gate 120-1, and the bottom surface of the source doping region 150 is lower than the top surface of the first trench gate 120-1; thus, in the depth direction (e.g., Z direction) of the semiconductor device 100, the top surface of the upper end of the first trench gate 120-1 is higher than the top surface of the upper end of the substrate doping region 140, and the bottom surface of the lower end of the first trench gate 120-1 is lower than the bottom surface of the lower end of the substrate doping region 140.

[0089] The first conductive compound 160 - 1 and the third conductive compound 160 - 3 are separated from each other in a laterally direction (eg, X direction) and are electrically insulated from each other.

[0090] Figure 6 FIG. 4 is a schematic perspective view of a semiconductor device including two repeating units according to an embodiment of the present invention. Figure 7 is a diagram according to an embodiment of the present invention. Figure 6 The cross-sectional diagram shown by the section line EE'. Fig.10 is a schematic top view of a semiconductor device including at least two repeating units according to an embodiment of the present invention.

[0091] like Figure 6 , Figure 7 and Fig.10 As shown, the semiconductor device component 100 includes two repeating units, such as a repeating unit U1 and a repeating unit U2, and the structures and functions of the repeating unit U1 and the repeating unit U2 are substantially the same. The number of repeating units in the semiconductor device 100 is not limited to two, but can also be any integer greater than 2, such as 2 to 100 or any number therebetween, depending on actual needs. In addition, the repeating units can be repeatedly arranged along a first direction (such as a Y direction) and / or a second direction (such as an X direction) to present an array arrangement layout. Figure 1 Can be regarded as Figure 2 This is a partial stereogram of the repeating unit U1, so the same parts are not repeated here.

[0092] like Figure 6 , Figure 7 and Fig.10As shown, the repeating unit U1 at least includes a first trench 108-1, a first field plate 110-1, two first trench gates 120-1, a first planar gate 130-1, a second planar gate 130-2, two substrate doping regions 140 (refer to Fig.10 , the substrate doping regions 140 are respectively arranged on both sides of the first trench 108-1), two substrate contact regions 142 (refer to Fig.10 , the substrate contact regions 142 are respectively arranged on both sides of the first trench 108-1), four source doping regions 150 (refer to Fig.10 , each side of the first trench 108-1 includes a source doping region 150 that is separated and arranged in pairs), a first conductive compound 160-1, a second conductive compound 160-2, a third conductive compound 160-3, and a plurality of conductive contact structures 200. The second planar gate 130-2 is disposed on the first field plate 110-1 and the first trench gate 120-1, and is parallel to the first planar gate 130-1.

[0093] Still Figure 6 , Figure 7 and Fig.10 As shown, the repeating unit U2 includes at least a second trench 108-2, a second field plate 110-2, two second trench gates 120-2, a first planar gate 130-1, a second planar gate 130-2, two substrate doping regions 140 (refer to Fig.10 , the substrate doping regions 140 are respectively arranged on both sides of the second trench 108-1), two substrate contact regions 142 (refer to Fig.10 , the substrate contact regions are respectively arranged on both sides of the second trench 108-1), four source doping regions 150 (refer to Fig.10 , each side of the first trench 108 - 1 includes source doping regions 150 that are separately arranged in pairs), a first conductive compound 160 - 1 , a second conductive compound 160 - 2 , a third conductive compound 160 - 3 , and a plurality of conductive contact structures 200 .

[0094] Reference Figure 7 , and with reference Figure 6 and Fig.10, the second trench 108-2 is disposed in the epitaxial layer 107 and extends along the first direction, such as the Y direction. The second field plate 110-2 is disposed in the second trench 108-2 and extends along the first direction. The second trench gate 120-2 is disposed in the second groove 114-2 and extends along the first direction, and the second trench gate 120-2 laterally separates the second field plate 110-2; in the area where the second conductive connection portion 170-2 is not disposed, the top surface of the second field plate 110-2 is higher than the top surface of the second trench gate 120-2. The second conductive connection portion 170-2 is disposed in the second trench 108-2 and is located on the second trench gate 120-2. The first planar gate 130-1 and the second planar gate 130-2 extend continuously along a second direction (e.g., X direction), and the second direction is not parallel to the first direction (e.g., substantially vertical); so that the first planar gate 130-1 and the second planar gate 130-2 extend across the top surface of the first field plate 110-1 and the first trench gate 120-1, and also extend across the second field plate 110-2 and the second trench gate 120-2.

[0095] Figure 8 and Fig. 9 is a three-dimensional schematic diagram of various stages of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and Figure 8 and Fig. 9 Roughly corresponds to Figure 1 Stereoscopic diagram.

[0096] Reference Figure 8 In step 302, a first trench structure 190 is first provided. The first trench structure 190 is located in the epitaxial layer 107 and extends along a first direction (Y direction). The first trench structure 190 includes a first trench 108-1, a first field plate 110-1, and a trench dielectric layer 112. The first field plate 110-1 is disposed in the first trench 108-1, and the trench dielectric layer 112 is disposed between the inner wall surface of the first trench 108-1 and the first field plate 110-1.

[0097] Next, refer to Figure 8 In step 304, the trench dielectric layer 112 is etched to form at least one first groove 114-1, for example, a pair of first grooves 114-1, each of which extends along the first direction.

[0098] Next, refer to Figure 8 In step 306, a gate dielectric layer 116 is formed. The gate dielectric layer 116 is disposed along the inner surface of the first groove 114-1 and the top surface of the first field plate 110-1. The gate dielectric layer 116 may be formed by performing a thermal oxidation process or a deposition process, but is not limited thereto.

[0099] Next, refer to Fig. 9In step 308, a conductive layer (not shown) is formed to fill the first groove 114-1, and the conductive layer covers the first field plate 110-1 and the epitaxial layer 107. Afterwards, the conductive layer is etched to form the first trench gate 120-1, the first planar gate 130-1, and the first conductive connection portion 170-1. The first trench gate 120-1 extends along the first direction and laterally separates the first field plate 110-1. The first trench gate 120-1 does not fill the first groove 114-1, so in the subsequent process, a trench gate capping layer 182 can be formed on the top surface of the first trench gate 120-1. The first planar gate 130-1 extends along the second direction (X direction), and the second direction is not parallel to the first direction. The first planar gate 130-1 extends across the first field plate 110-1 and the first trench gate 120-1. The first conductive connection portion (not shown) is disposed in the first groove 114-1 and is located between the first trench gate 120-1 and the first planar gate 130-1. The first trench gate 120-1 is electrically connected to the first planar gate 130-1 through the first conductive connection portion 170-1. A portion of the gate dielectric layer 116 is located between the first field plate 110-1 and the first planar gate 130-1, and another portion of the gate dielectric layer 116 is located between the trench dielectric layer 112 and the first trench gate 120-1.

[0100] By performing step 308 , since the first trench gate 120 - 1 , the first planar gate 130 - 1 , and the first conductive connection portion 170 - 1 can be formed through the same deposition process and etching process, the process can be simplified.

[0101] Next, refer to Fig. 9 In step 310, a dielectric layer (not shown) is formed to fill the first groove 114-1. The dielectric layer covers the top surface of the first trench gate 120-1 and the side surface of the first planar gate 130-1. Afterwards, the dielectric layer is etched to form a trench gate cap layer 182 and a planar gate spacer 184, wherein the trench gate cap layer 182 covers the top surface of the first trench gate 120-1, and the planar gate spacer 184 covers two opposite sides of the first planar gate 130-1. By providing the trench gate cap layer 182, the top surface of the first trench gate 120-1 can be protected in subsequent processes to prevent the first trench gate 120-1 from being electrically connected to the conductive compound, such as the conductive compound (not shown) on the first field plate 110-1, through its top surface.

[0102] Next, as shown in step 310 , a body doping region 140 and a source doping region 150 are formed on the upper portion of the epitaxial layer 107 . The source doping region 150 laterally (eg, on the XY plane) separates the first trench gate 120 - 1 and the first planar gate 130 - 1 .

[0103] Next, refer to Fig. 9 In step 312, a metal layer (not shown) is formed on the entire upper surface of the semiconductor device 100, that is, covering the first field plate 110-1, the first trench gate 120-1, the first planar gate 130-1, the trench gate cap layer 182, the planar gate spacer 184, and the source doping region 150. Afterwards, a heat treatment is performed to react the metal layer with the first field plate 110-1, the first planar gate 130-1, and the source doping region 150 to generate conductive compounds 160, such as the first conductive compound 160-1, the second conductive compound 160-2, and the third conductive compound 160-3. Since the metal layer only reacts with the semiconductor material and does not react with the dielectric layer (such as the trench gate cap layer 182 and the planar gate spacer 184), the conductive compound 160 can be formed in a self-aligned manner, and therefore can be called a self-aligned conductive compound. Further, the first conductive compound 160-1 covers the first field plate 110-1, the second conductive compound 160-2 covers the first planar gate 130-1, and the third conductive compound 160-3 covers the source doping region 150. The first conductive compound 160-1, the second conductive compound 160-2, and the third conductive compound 160-3 are laterally separated from each other.

[0104] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: an epitaxial layer having a first conductivity type; a first trench, disposed in the epitaxial layer and extending along a first direction; a first field plate, disposed in the first trench and extending along the first direction; a first trench gate, disposed in the first trench and extending along the first direction, wherein the first trench gate is laterally separated from the first field plate, and a top surface of the first field plate is higher than a top surface of the first trench gate; a first planar gate, disposed on the first field plate and the first trench gate, and extending along a second direction, wherein the second direction is not parallel to the first direction; as well as A first conductive connection portion is disposed in the first trench and located between the first trench gate and the first planar gate. The first trench gate is electrically connected to the first planar gate through the first conductive connection portion.

2. The semiconductor device according to claim 1, wherein The invention also includes a first conductive compound covering the top surface of the first field plate and extending along the first direction.

3. The semiconductor device according to claim 1, wherein: The first trench gate, the first planar gate, and the first conductive connecting portion are made of the same material.

4. The semiconductor device according to claim 1, wherein: Also includes: A trench gate capping layer is disposed in the first trench, wherein the trench gate capping layer covers a top surface of the first trench gate and a side surface of the first conductive connecting portion.

5. The semiconductor device according to claim 4, wherein: Also includes: A planar gate spacer is disposed on the first trench and extends along the second direction, wherein the planar gate spacer and the trench gate cap layer are made of the same material.

6. The semiconductor device according to claim 4, wherein: The trench gate cap layer includes a recessed top surface.

7. The semiconductor device according to claim 1, wherein Also includes: A second conductive compound covers the top surface of the first planar gate and extends along the second direction.

8. The semiconductor device according to claim 1, wherein Also includes: a source doping region, disposed on an upper portion of the epitaxial layer and adjacent to the first trench, the source doping region having the first conductivity type; as well as A third conductive compound covers the top surface of the source doped region and laterally separates the first trench gate and the first conductive compound.

9. The semiconductor device according to claim 8, wherein: Also includes: A substrate doping region is arranged below the source doping region, wherein a portion of the substrate doping region covers the side surface of the first trench gate in the second direction, and another portion of the substrate doping region is covered by the first planar gate in a vertical direction.

10. The semiconductor device according to claim 1, wherein Also includes: a trench dielectric layer disposed in the first trench and between an inner surface of the first trench and the first field plate; as well as a first recess, disposed in the first trench and located above the trench dielectric layer, Wherein, the first trench gate is arranged in the first groove.

11. The semiconductor device according to claim 1, wherein Also includes: a second trench disposed in the epitaxial layer and extending along the first direction; a second field plate, disposed in the second trench and extending along the first direction; a second trench gate, disposed in the second trench and extending along the first direction, wherein the second trench gate is laterally separated from the second field plate, and a top surface of the second field plate is higher than a top surface of the second trench gate; a second conductive connection portion, disposed in the second trench and located on the second trench gate; and a first conductive compound covering the top surface of the second field plate and extending along the first direction, wherein: The first planar gate is further disposed on the second field plate and the second trench gate.

12. The semiconductor device according to claim 1, wherein The first trench includes two first trench gates, and the first trench gates are respectively arranged on both sides of the first field plate.

13. The semiconductor device according to claim 1, wherein: Also includes: a second planar gate, disposed above the first field plate and the first trench gate and parallel to the first planar gate; a substrate doping region, disposed below the first planar gate and the second planar gate, wherein a portion of the substrate doping region overlaps with the first planar gate, another portion of the substrate doping region overlaps with the second planar gate, and the substrate doping region has a second conductivity type, which is opposite to the first conductivity type; as well as Two source doping regions are arranged in the base doping region and adjacent to the first trench, the source doping regions are separated from each other along the first direction, and the source doping regions have the first conductivity type, wherein one of the source doping regions is adjacent to the first planar gate, and the other of the source doping regions is adjacent to the second planar gate.

14. The semiconductor device according to claim 13, wherein: The invention also comprises a single conductive compound covering the source doping regions separated from each other.

15. The semiconductor device according to claim 13, wherein: It also includes two conductive contact structures, which are separated from each other and respectively arranged on the corresponding source doping regions.

16. A method for manufacturing a semiconductor device, characterized in that: include: A first trench structure is provided, wherein the first trench structure is located in an epitaxial layer and extends along a first direction, and the first trench structure includes: a first groove; a first field plate disposed in the first trench; and a trench dielectric layer disposed between the first trench and the first field plate; Etching the trench dielectric layer to form a first groove, wherein the first groove extends along the first direction; forming a conductive layer to fill the first groove, wherein the conductive layer covers the first field plate and the epitaxial layer; and The conductive layer is etched to form a first trench gate, a first planar gate, and a first conductive connection portion, wherein: The first trench gate extends along the first direction and laterally separates the first field plate. The first planar gate extends along a second direction which is not parallel to the first direction, wherein the first planar gate is arranged above the first field plate and the first trench gate, and the first conductive connection portion is arranged in the first groove and between the first trench gate and the first planar gate.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: The first trench gate is electrically connected to the first planar gate through the first conductive connection portion.

18. The method for manufacturing a semiconductor device according to claim 16, wherein: Also includes: Before forming the conductive layer, forming a gate dielectric layer, wherein the gate dielectric layer is disposed along the inner surface of the first groove and the top surface of the first field plate; as well as After forming the conductive layer, a portion of the gate dielectric layer is located between the first field plate and the first planar gate, and another portion of the gate dielectric layer is located between the trench dielectric layer and the first trench gate.

19. The method for manufacturing a semiconductor device according to claim 16, wherein: After etching the conductive layer, the method further comprises: forming a dielectric layer to fill the first groove, wherein the dielectric layer covers the top surface of the first trench gate and the side surface of the first planar gate; and The dielectric layer is etched to form a trench gate cap layer and a planar gate spacer, wherein the trench gate cap layer covers the top surface of the first trench gate, and the planar gate spacer covers the side surface of the first planar gate.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: After forming the trench gate cap layer and the planar gate spacer, the method further comprises: forming a metal layer to cover the first field plate, the first trench gate, the first planar gate, the trench gate cap layer, and the planar gate spacer; and A heat treatment is performed to react the metal layer with the first field plate and the first planar gate to generate a first conductive compound and a second conductive compound, wherein the first conductive compound covers the first field plate, the second conductive compound covers the first planar gate, and the first conductive compound and the second conductive compound are laterally separated from each other.

21. The method for manufacturing a semiconductor device according to claim 19, wherein: Also includes: After forming the trench gate cap layer and the planar gate spacer, forming a source doping region on the upper portion of the epitaxial layer, the source doping region laterally separating the first trench gate and the first planar gate; When forming the metal layer, the metal layer further covers the source doping region; as well as When the heat treatment is performed, the metal layer further reacts with the source doping region to generate a third conductive compound, wherein the third conductive compound, the second conductive compound, and the first conductive compound are laterally separated from each other.

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